Datasheet AD8220 Datasheet (ANALOG DEVICES)

JFET Input Instrumentation Amplifier with

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Rail-to-Rail Output in MSOP Package

FEATURES

Low input currents

10 pA maximum input bias current (B Grade)

0.6 pA maximum input offset current (B Grade)

High CMRR

100 dB CMRR (minimum), G = 10 (B Grade) 80 dB CMRR (minimum) to 5 kHz, G = 1 (B Grade)

Excellent ac specifications and low power

1.5 MHz bandwidth (G = 1) 14 nV/√Hz input noise (1 kHz) Slew rate: 2 V/μs 750 μA quiescent supply current (maximum)

Versa tile

MSOP package Rail-to-rail output Input voltage range to below negative supply rail 4 kV ESD protection

4.5 V to 36 V single supply ±2.25 V to ±18 V dual supply Gain set with single resistor (G = 1 to 1000)

APPLICATIONS

Medical instrumentation Precision data acquisition Transducer interfaces

GENERAL DESCRIPTION

The AD8220 is the first single-supply, JFET input instrumentation amplifier available in an MSOP package. Designed to meet the needs of high performance, portable instrumentation, the AD8220 has a minimum common-mode rejection ratio (CMRR) of 86 dB at dc and a minimum CMRR of 80 dB at 5 kHz for G = 1. Maximum input bias current is 10 pA and typically remains below 300 pA over the entire industrial temperature range. Despite the JFET inputs, the AD8220 typically has a noise corner of only 10 Hz.

With the proliferation of mixed-signal processing, the number o

f power supplies required in each system has grown. The AD8220 is designed to alleviate this problem. The AD8220 can operate on a ±18 V dual supply, as well as on a single +5 V supply. Its rail-to-rail output stage maximizes dynamic range on the low voltage supplies common in portable applications. Its ability to run on a single 5 V supply eliminates the need to use higher voltage, dual supplies. The AD8220 draws a maximum of 750 μA of quiescent current, making it ideal for battery powered devices.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD8220

PIN CONFIGURATION

AD8220

1

–IN

2

R

G

3

R

G

4

+IN

TOP VIEW

(Not to Scale)

Figure 1.

10n

1n

100p

10p

1p

INPUT BIAS CURRE NT (A)

0.1p

–25 0 25 50 75 100 125

–50 150

TEMPERATURE (°C)

Figure 2. Input Bias Current and Offset Current vs. Temperature

Gain is set from 1 to 1000 with a single resistor. Increasing the ga

in increases the common-mode rejection. Measurements that need higher CMRR when reading small signals benefit when the AD8220 is set for large gains.

A reference pin allows the user to offset the output voltage. This fe

ature is useful when interfacing with analog-to-digital converters.

The AD8220 is available in an MSOP that takes roughly half the b

oard area of an SOIC. Performance is specified over the industrial

temperature range of −40°C to +85°C.

8

7

6

5

I

BIAS

+V

V

REF

–V

OUT

S

03579-005

I

OS

03579-059

AD8220

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REVISION HISTORY

5/07—Rev. 0 to Rev. A

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 5

Changes to Table 3............................................................................ 8

Changes to Figure 6 and Figure 7................................................. 10

Changes to Figure 23 and Figure 24............................................. 13

Changes to Theory of Operation.................................................. 19

Changes to Layout.......................................................................... 20

Changes to Ordering Guide.......................................................... 26

4/06—Revision 0: Initial Version

Rev. A | Page 2 of 28

AD8220

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SPECIFICATIONS

VS+ = 15 V, VS− = −15 V, V

Table 1.

Parameter Test Conditions Min Typ Max Min Typ Max Unit

COMMON-MODE REJECTION RATIO (CMRR)

CMRR DC to 60 Hz with

1 kΩ Source Imbalance G = 1 78 86 dB G = 10 94 100 dB G = 100 94 100 dB G = 1000 94 100 dB

CMRR at 5 kHz VCM = ±10 V

G = 1 74 80 dB G = 10 84 90 dB G = 100 84 90 dB G = 1000 84 90 dB

NOISE

Voltage Noise, 1 kHz Input Voltage Noise, e Output Voltage Noise, e RTI, 0.1 Hz to 10 Hz

G = 1 5 5 μV p-p G = 1000 0.8 0.8 μV p-p

Current Noise f = 1 kHz 1 1 fA/√Hz

VOLTAGE OFFSET VOS = V

Input Offset, V

Average TC T = −40°C to +85°C 10 5 μV/°C

Output Offset, V

Average TC T = −40°C to +85°C 10 5 μV/°C

Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V

G = 1 86 86 dB G = 10 96 100 dB G = 100 96 100 dB G = 1000 96 100 dB

INPUT CURRENT

Input Bias Current 25 10 pA

Over Temperature T = −40°C to +85°C 300 300 pA

Input Offset Current 2 0.6 pA

Over Temperature T = −40°C to +85°C 5 5 pA

DYNAMIC RESPONSE

Small Signal Bandwidth, – 3 dB

G = 1 1500 1500 kHz G = 10 800 800 kHz G = 100 120 120 kHz G = 1000 14 14 kHz

OSI

OSO

= 0 V, TA = 25°C, G = 1, RL = 2 kΩ1, unless otherwise noted.

REF

A Grade B Grade

V

= ±10 V

CM

RTI noise =

2

+ (eno/G)2)

√(e

ni

no

VIN+, VIN− = 0 V 14 14 17 nV/√Hz VIN+, VIN− = 0 V 90 90 100 nV/√Hz

+ V

OSI

OSO

250 125 μV

750 500 μV

/G

Rev. A | Page 3 of 28

AD8220

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Parameter Test Conditions Min Typ Max Min Typ Max Unit

Settling Time 0.01% 10 V step

G = 1 5 5 μs G = 10 4.3 4.3 μs G = 100 8.1 8.1 μs G = 1000 58 58 μs

Settling Time 0.001% 10 V step

G = 1 6 6 μs G = 10 4.6 4.6 μs G = 100 9.6 9.6 μs G = 1000 74 74 μs

Slew Rate

G = 1 to 100 2 2 V/μs

GAIN G = 1 + (49.4 kΩ/RG)

Gain Range 1 1000 1 1000 V/V

Gain Error V

G = 1 0.06 0.04 % G = 10 0.3 0.2 % G = 100 0.3 0.2 % G = 1000 0.3 0.2 %

Gain Nonlinearity V

G = 1 RL = 10 kΩ 10 15 10 15 ppm G = 10 RL = 10 kΩ 5 10 5 10 ppm G = 100 RL = 10 kΩ 30 60 30 60 ppm G = 1000 RL = 10 kΩ 400 500 400 500 ppm G = 1 RL = 2 kΩ 10 15 10 15 ppm G = 10 RL = 2 kΩ 10 15 10 15 ppm G = 100 RL = 2 kΩ 50 75 50 75 ppm

Gain vs. Temperature

G = 1 3 10 2 5 ppm/°C G > 10 −50 −50 ppm/°C

INPUT

Impedance (Pin to Ground)

Input Operating Voltage Range

Over Temperature T = −40°C to +85°C −VS − 0.1 +VS − 2.1 −VS − 0.1 +VS − 2.1 V

OUTPUT

Output Swing RL = 2 kΩ −14.3 +14.3 −14.3 +14.3 V

Over Temperature T = −40°C to +85°C −14.3 +14.1 −14.3 +14.1 V

Output Swing RL = 10 kΩ −14.7 +14.7 −14.7 +14.7 V

Over Temperature T = −40°C to +85°C −14.6 +14.6 −14.6 +14.6 V

Short-Circuit Current 15 15 mA REFERENCE INPUT

R

IN

I

IN

Voltage Range −V

Gain to Output

2

3

= ±10 V

OUT

= −10 V to +10 V

OUT

104||5 104||5 GΩ||pF VS = ±2.25 V to ±18 V

for dual supplies

40 40 kΩ VIN+, VIN− = 0 V 70 70 μA

−V

A Grade B Grade

− 0.1 +VS − 2 −VS − 0.1 +VS − 2 V

S

+V 1 ±

0.0001

S

−V

S

+V 1 ±

0.0001

V/V

S

V

Rev. A | Page 4 of 28

AD8220

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Parameter Test Conditions Min Typ Max Min Typ Max Unit

POWER SUPPLY

Operating Range ±2.25 Quiescent Current 750 750 μA

Over Temperature T = −40°C to +85°C 850 850 μA

TEMPERATURE RANGE

For Specified Performance −40 +85 −40 +85 °C Operational

1

When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ.

2

Differential and common-mode input impedance can be calculated from the pin impedance: Z

3

The AD8220 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum

allowable voltage where the input bias current is within the specification.

4

At this supply voltage, ensure that the input common-mode voltage is within the input voltage range specification.

5

The AD8220 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in this temperature range.

5

−40 +125 −40 +125 °C

V

+ = 5 V, VS− = 0 V, V

S

= 2.5 V, TA = 25°C, G = 1, RL = 2 kΩ1, unless otherwise noted.

REF

Table 2.

A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit

COMMON-MODE REJECTION RATIO (CMRR)

V

CMRR DC to 60 Hz with

= 0 to 2.5 V

CM

1 kΩ Source Imbalance G = 1 78 86 dB G = 10 94 100 dB G = 100 94 100 dB G = 1000 94 100 dB

CMRR at 5 kHz VCM = 0 to 2.5 V

G = 1 74 80 dB G = 10 84 90 dB G = 100 84 90 dB G = 1000 84 90 dB

NOISE

RTI noise =

2

+ (eno/G)2)

√(e

ni

Voltage Noise, 1 kHz VS = ±2.5 V Input Voltage Noise, e Output Voltage Noise, e

ni

no

VIN+, VIN− = 0 V, V VIN+, VIN− = 0 V, V

= 0 V 14 14 17 nV/√Hz

REF

= 0 V 90 90 100 nV/√Hz

REF

RTI, 0.1 Hz to 10 Hz

G = 1 5 5 μV p-p G = 1000 0.8 0.8 μV p-p

Current Noise f = 1 kHz 1 1 fA/√Hz

VOLTAGE OFFSET VOS = V

+ V

OSI

/G

OSO

Input Offset, VOSI 300 200 μV

Average TC T = −40°C to +85°C 10 5 μV/°C

Output Offset, VOSO 800 600 μV

Average TC T = −40°C to +85°C 10 5 μV/°C

Offset RTI vs. Supply (PSR)

G = 1 86 86 dB G = 10 96 100 dB G = 100 96 100 dB G = 1000 96 100 dB

A Grade B Grade

4

±18 ±2.25

= 2(Z

DIFF

); ZCM = Z

/2.

4

±18 V

Rev. A | Page 5 of 28

AD8220

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A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit

INPUT CURRENT

Input Bias Current 25 10 pA

Over Temperature T = −40°C to +85°C 300 300 pA

Input Offset Current 2 0.6 pA

Over Temperature T = −40°C to +85°C 5 5 pA

DYNAMIC RESPONSE

Small Signal Bandwidth, – 3 dB

G = 1 1500 1500 kHz G = 10 G = 100 G = 1000

Settling Time 0.01%

G = 1 3 V step 2.5 2.5 μs G = 10 4 V step 2.5 2.5 μs G = 100 4 V step 7.5 7.5 μs G = 1000 4 V step 30 30 μs

Settling Time 0.001%

G = 1 3 V step 3.5 3.5 μs G = 10 4 V step 3.5 3.5 μs G = 100 4 V step 8.5 8.5 μs G = 1000 4 V step 37 37 μs

Slew Rate

G = 1 to 100

GAIN G = 1 + (49.4 kΩ/RG)

Gain Range

Gain Error

G = 1 0.06 0.04 % G = 10 G = 100 G = 1000

Nonlinearity

G = 1 RL = 10 kΩ 35 50 35 50 ppm G = 10 RL = 10 kΩ 35 50 35 50 ppm G = 100 RL = 10 kΩ 50 75 50 75 ppm G = 1000 RL = 10 kΩ 650 750 650 750 ppm G = 1 G = 10 G = 100

Gain vs. Temperature

G = 1 G > 10

INPUT

Impedance (Pin to Ground)

Input Voltage Range

Over Temperature T = −40°C to +85°C −0.1 +VS − 2.1 −0.1 +VS − 2.1 V

2

3

= 0.3 V to 2.9 V for G = 1,

V

OUT

= 0.3 V to 3.8 V for G > 1

V

OUT

= 0.3 V to 2.9 V for G = 1,

V

OUT

= 0.3 V to 3.8 V for G > 1

V

OUT

R

= 2 kΩ

L

R

= 2 kΩ

L

R

= 2 kΩ

L

104||6 104||6 GΩ||pF

−0.1 +VS − 2 −0.1 +VS − 2 V

800 800 kHz 120 120 kHz 14 14 kHz

2 2 V/μs

1 1000 1 1000 V/V

0.3 0.2 %

35 50 35 50 ppm 35 50 35 50 ppm 50 75 50 75 ppm

3 10 2 5 ppm/°C

−50 −50 ppm/°C

Rev. A | Page 6 of 28

AD8220

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A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit

OUTPUT

Output Swing RL = 2 kΩ 0.25 4.75 0.25 4.75 V

Over Temperature T = −40°C to +85°C 0.3 4.70 0.3 4.70 V

Output Swing RL = 10 kΩ 0.15 4.85 0.15 4.85 V

Over Temperature T = −40°C to +85°C 0.2 4.80 0.2 4.80 V

Short-Circuit Current

REFERENCE INPUT

R

IN

I

IN

Voltage Range Gain to Output

POWER SUPPLY

Operating Range 4.5 36 4.5 36 V Quiescent Current 750 750 μA

Over Temperature T = −40°C to +85°C 850 850 μA

TEMPERATURE RANGE

For Specified Performance −40 +85 −40 +85 °C Operational

1

When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ.

2

Differential and common-mode impedance can be calculated from the pin impedance: Z

3

The AD8220 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum

allowable voltage where the input bias current is within the specification.

4

The AD8220 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in that temperature range.

4

VIN+, VIN− = 0 V

15 15 mA

40 40 kΩ 70 70 μA

−VS +V 1 ±

0.0001

S

−VS +V 1 ±

V/V

0.0001

S

V

−40 +125 −40 +125 °C

= 2(Z

DIFF

); ZCM = Z

/2.

Rev. A | Page 7 of 28

AD8220

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ABSOLUTE MAXIMUM RATINGS

Tabl e 3.

Parameter Rating

Supply Voltage ±18 V Power Dissipation See Figure 3 Output Short-Circuit Current Indefinite

1

Input Voltage (Common Mode) ±Vs Differential Input Voltage ±Vs Storage Temperature Range −65°C to +125°C Operating Temperature Range

2

−40°C to +125°C Lead Temperature (Soldering 10 sec) 300°C Junction Temperature 140°C θJA (4-Layer JEDEC Standard Board) 135°C/W Package Glass Transition Temperature 140°C ESD (Human Body Model) 4 kV ESD (Charge Device Model) 1 kV ESD (Machine Model) 0.4 kV

1

Assumes the load is referenced to midsupply.

2

Temperature for specified performance is −40°C to +85°C. For performance

to 125°C, see the Typical Performance Characteristics section.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 3 shows the maximum safe power dissipation in the p

ackage vs. the ambient temperature for the MSOP on a 4-layer

JEDEC standard board. θ

values are approximations.

JA

2.00

1.75

1.50

1.25

1.00

0.75

0.50

MAXIMUM POW ER DISSIPAT ION (W)

0.25

0

–40 120

–20 0 20 40 60 80 100

AMBIENT T EMPERATURE (°C)

Figure 3. Maximum Power Dissipation vs. Ambient Temperature

03579-045

ESD CAUTION

Rev. A | Page 8 of 28

AD8220

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD8220

1

–IN

2

R

G

3

R

G

4

+IN

TOP VIEW

(Not to Scale)

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 −IN Negative Input Terminal (True Differential Input) 2, 3 R

G

Gain Setting Terminals (Place Resistor Across the RG Pins) 4 +IN Positive Input Terminal (True Differential Input) 5 −V

S

Negative Power Supply Terminal 6 REF Reference Voltage Terminal (Drive This Terminal with a Low Impedance Voltage Source to Level-Shift the Output) 7 V 8 +V

OUT

S

Output Terminal

Positive Power Supply Terminal

8

+V

S

7

V

OUT

6

REF

5

–V

S

03579-005

Rev. A | Page 9 of 28

AD8220

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TYPICAL PERFORMANCE CHARACTERISTICS

1200

1600

1000

800

600

400

NUMBER OF UNIT S

200

0

–40 –20 0 20 40

CMRR (µV/V)

03579-060

Figure 5. Typical Distribution of CMRR (G = 1)

1000

800

600

400

NUMBER OF UNIT S

1400

1200

1000

800

600

NUMBER OF UNIT S

400

200

0

0 1 2 3 4 5

I

(pA)

BIAS

Figure 8. Typical Distribution of Input Bias Current

1200

1000

800

600

400

NUMBER OF UNIT S

03579-063

200

0

–200 –100 0 100 200

V

(µV)

OSI

Figure 6. Typical Distribution of Input Offset Voltage

1000

800

600

400

NUMBER OF UNIT S

200

0

–1000 –500 0 500 1000

V

(µV)

OSO

Figure 7. Typical Distribution of O

utput Offset Voltage

200

03579-061

0

–0.2 –0. 1 0 0.1 0.2

IOS(pA)

03579-064

Figure 9. Typical Distribution of Input Offset Current

1000

Hz)

100

10

VOLTAGE NOISE RTI (nV/

03579-062

1

11

10 100 1k 10k

GAIN = 100 BANDWI DTH ROLL -OFF

GAIN = 1

GAIN = 10

GAIN = 100/G AIN = 1000

GAIN = 1000 BANDWI DTH ROLL -OFF

FREQUENCY (Hz)

03579-042

00k

Figure 10. Voltage Spectral Density vs. Frequency

Rev. A | Page 10 of 28

AD8220

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XX

XXX (X)

XX

XX XX

XXX (X)

Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)

XX

XXX (X)

XX

XX XX

XXX (X)

Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)

1s/DIV5µV/DIV

03579-024

1s/DIV1µV/DIV

03579-025

150

130

GAIN = 100

110

90

70

PSRR (dB)

50

30

10

11

GAIN = 10

10 100 1k 10k 100k

FREQUENCY (Hz)

GAIN = 1000

GAIN = 1

BANDWIDTH

LIMITED

03579-035

M

Figure 14. Positive PSRR vs. Frequency, RTI

150

130

110

90

GAIN = 1

70

PSRR (dB)

50

30

10

11

GAIN = 10

GAIN = 100

10 100 1k 10k 100k

FREQUENCY (Hz)

GAIN = 1000

03579-040

M

Figure 15. Negative PSRR vs. Frequency, RTI

8

7

6

5

(µV)

4

OSI

 V

3

2

1

0

0.1 1k

1 10 100

TIME (s)

Figure 13. Change in Input Offset Voltage vs. Warmup Time

INPUT BIAS CURRENT (pA)

03579-009

INPUT OFFSET

9

CURRENT ±15

7

5

3

1

–1

–16 16

–15.1V

–5.1V

–12 –8 –4 0 4 8 12

COMMON-MO DE VOLT AGE (V)

Figure 16. Input Bias Current and Input Offset Current vs.

Co

Rev. A | Page 11 of 28

INPUT OFFSET

CURRENT ±5

INPUT BIAS

CURRENT ±5

mmon-Mode Voltage

INPUT BIAS

CURRENT ±15

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

INPUT OFFSET CURRENT ( pA)

03579-050

AD8220

www.BDTIC.com/ADI

10n

1n

100p

10p

1p

INPUT BIAS CURRE NT (A)

0.1p

–25 0 25 50 75 100 125

–50 150

TEMPERATURE (°C)

I

BIAS

I

OS

Figure 17. Input Bias Current and Offset Current vs. Temperature,

= ±15 V, V

V

S

10n

1n

100p

10p

CURRENT (A)

1p

0.1p

–25 0 25 50 75 100 125

–50 150

TEMPERATURE (°C)

REF

= 0 V

I

BIAS

I

OS

Figure 18. Input Bias Current and Offset Current vs. Temperature,

= +5 V, V

V

S

= 2.5 V

REF

160

140

GAIN = 1000

120

GAIN = 100

100

CMRR (dB)

80

60

03579-059

40

GAIN = 10

1 100k

10 100 1k 10k

GAIN = 1

FREQUENCY (Hz)

BANDWIDTH

LIMITED

03579-051

Figure 20. CMRR vs. Frequency, 1 kΩ Source Imbalance

10

8

6

4

2

0

–2

 CMRR (V/V)

–4

–6

–8

03579-065

–10

–50 130

–30 –10 10 30 50 70 90 110

TEMPERATURE (°C)

03579-034

Figure 21. Change in CMRR vs. Temperature, G = 1

160

GAIN = 1000

140

GAIN = 100

120

GAIN = 10

100

CMRR (dB)

GAIN = 1

80

60

40

10 100k

100 1k 10k

FREQUENCY (Hz)

Figure 19. CMRR vs. Frequency

BANDWIDTH

LIMITED

03579-023

70

60

GAIN = 1000

50

40

GAIN = 100

30

20

GAIN = 10

10

GAIN (dB)

0

GAIN = 1

–10

–20

–30

–40

100 10M

1k 10k 100k 1M

Figure 22. Gain vs. Frequency

Rev. A | Page 12 of 28

FREQUENCY (Hz)

03579-022

AD8220

www.BDTIC.com/ADI

R

=2k

LOAD

R

=10k

XXX

R

LOAD

= 2k

XXX

LOAD

XXX

NONLINEARI TY (5ppm/ DIV)

VS = ±15V

–8–10 –6 –4 –2 0 2 4 6 8 10

OUTPUT VOLTAGE (V)

R

Figure 23. Gain Nonlinearity, G = 1

R

= 10k

LOAD

NONLINEARI TY (5ppm/ DIV)

VS = ±15V

–8–10 –6 –4 –2 0 2 4 6 8 10

OUTPUT VOLTAGE (V)

Figure 24. Gain Nonlinearity, G = 10

LOAD

= 10k

= 2k

NONLINEARITY (500ppm/DIV)

03579-026

VS= ±15V

–8–10 –6–4–20246810

OUTPUT VOLTAGE (V)

03579-029

Figure 26. Gain Nonlinearity, G = 1000

18

12

±15V SUPPLIES

6

–14.8V, +5.5V

0

–6

–12

INPUT COMMO N-MODE VOL TAGE (V)

03579-027

–18

–16 16

–4.8V, +0.6V

–4.8V, –3.3V

–14.8V, –8.3V

–12 –8 –4 0 4 8 12

OUTPUT VOLTAGE (V)

+13V

+3V

±5V SUPPLIES

–5.3V

–15.3V

+14.9V, +5.5V

+4.95V, +0.6V

+4.95V, –3.3V

+14.9V, –8.3V

03579-037

Figure 27. Input Common-Mode Voltage Range vs. Output Voltage,

G =

4

1, V

REF

= 0 V

3

R

=2k

LOAD

R

= 10k

XXX

NONLINEARITY (50pp m/DIV)

VS= ±15V

–8–10 –6–4–20246810

LOAD

OUTPUT VOLTAGE (V)

03579-028

Figure 25. Gain Nonlinearity, G = 100

2

1

0

INPUT COMMO N-MODE VOL TAGE (V)

–1

–1 6

+0.1V, +1.7V

+0.1V, +0.5V

012345

Figure 28. Input Common-Mode Voltage Range vs. Output Voltage,

G =

Rev. A | Page 13 of 28

+3V

+5VSINGLESUPPLY,

V

= +2.5V

REF

–0.3V

OUTPUT VOLTAGE (V)

1, V

= +5 V, V

S

= 2.5 V

REF

+4.9V, +1.7V

+4.9V, +0.5V

03579-036

AD8220

V

www.BDTIC.com/ADI

18

12

6

0

–6

–12

INPUT COMMO N-MODE VOL TAGE (V)

–18

–16 16

±15V SUPPLIES

–14.9V, +5.4V

–4.9V, + 0.4V

–4.9V, –4.1V

–14.8V, –9V

–12 –8 –4 0 4 8 12

OUTPUT VOLTAGE (V)

+13V

+3V

±5V SUPPLIES

–5.3V

–15.3V

+14.9V, +5.4V

+4.9V, +0.5V

+4.9V, –4.1V

+14.9V, –9V

Figure 29. Input Common-Mode Voltage Range vs. Output Voltage,

100, V

V

REF

+3V

= +2.5V

= 0 V

+4.9V, +1.7V

G =

4

3

2

+0.1V, +1.7V

1

+5V SINGLE SUPPL Y,

+

S

–1

–2

–3

–4

+4

+3

OUTPUT VOLTAGE SWING (V)

+2

REFERRED TO SUPPLY VOL TAGE

+1

03579-039

V

–

S

21

4 6 8 10121416

DUAL SUPPLY VOLTAGE (±V)

+125°C

–40°C

+25°C

+85°C

Figure 32. Output Voltage Swing vs. Supply Voltage, R

= 0 V

V

REF

+

S

–0.2

+125°C

+85°C

–0.4

+25°C

–40°C

+85°C

+125°C

–40°C

+25°C

= 2 kΩ, G = 10,

LOAD

03579-053

8

0

INPUT COMMO N-MODE VOL TAGE (V)

–1

–1 6

+0.1V, –0.5V

012345

–0.3V

OUTPUT VOLTAGE (V)

+4.9V, –0.5V

03579-038

Figure 30. Input Common-Mode Voltage Range vs. Output Voltage,

G =

+

S

–1

–2

NOTES

1. THE AD8220 CAN OPERATE UP TO A V THE NEGATI VE SUPPLY, BUT THE BIAS CURRENT WILL I NCREASE SHARPLY.

+1

INPUT VOLTAGE LIMIT (V)

V

–

S

–1

21

+25°C–40°C

4 6 8 10121416

= +5 V, V

100, V

S

+85°C

SUPPLY VOLTAGE (V)

Figure 31. Input Voltage Limit vs. Supply Voltage, G = 1, V

–40°C

+25°C

+125°C

= 2.5 V

REF

+125°C

+85°C

BELOW

BE

03579-052

8

=0 V

REF

OUTPUT VOLTAGE SWING (V)

+0.4

REFERRED TO SUPPLY VOL TAGE

+125°C

+0.2

V

–

S

21

Figure 33. Output Voltage Swing vs. Supply Voltage, R

15

10

5

0

–5

OUTPUT VOLTAGE SWING (V)

–1

0

–15

100 10k

Figure 34. Output Voltage Swing vs. Load Resistance V

+85°C

4 6 8 10 12 14 16

DUAL SUPPLY VO LTAGE ( ±V)

–40°C

+25°C

–40°C

+25°C

V

REF

+125°C

R

= 0 V

+85°C

1k

LOAD

–40°C

+85°C

()

= 10 kΩ, G = 10,

LOAD

= ±15 V, V

S

03579-054

8

03579-055

= 0 V

REF

Rev. A | Page 14 of 28

AD8220

V

X

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5

–40°C

4

+125°C

3

2

OUTPUT VOLTAGE SWING (V)

+125°C

1

–40°C

0 100 10k

+25°C

+85°C

R

LOAD

1k

()

Figure 35. Output Voltage Swing vs. Load Resistance V

+

S

–1

–2

–3

–4

+125°C +85°C

= +5 V, V

S

+25°C

REF

–40°C

03579-056

= 2.5 V

X

5µs/DIV20mV/DIV

47pF

100pF

XXX (X)

NO LOAD

XXX (X)

XX

XX XX

Figure 38. Small Signal Pulse Response for Various Capacitive Loads,

X

NO LOAD

= ±15 V, V

V

S

47pF

REF

100pF

= 0 V

03579-018

+4

+3

OUTPUT VOLTAGE SWING (V)

+2

REFERRED TO SUPPLY VOLTAGES

+1

V

–

S

01

2 4 6 8 101214

I

(mA)

OUT

+125°C

+85°C

Figure 36. Output Voltage Swing vs. Output Current, V

+

S

–1

+125°C

–2

+2

OUTPUT VOLTAGE SWING (V)

+1

REFERRED TO SUPPLY VOLTAGES

V

–

S

01

2 4 6 8 101214

+125°C

I

OUT

(mA)

+85°C

Figure 37. Output Voltage Swing vs. Output Current, V

+25°C

= ±15 V, V

S

+25°C

= 5 V, V

S

XXX (X)

–40°C

03579-057

6

20mV/DIV 5µs/DIV

XX

XX XX

= 0 V

REF

–40°C

03579-058

6

Figure 39. Small Signal Pulse Response for Various Capacitive Loads,

35

GAIN = 10, 100, 1000

30

GAIN = 1

25

20

15

10

OUTPUT VOLTAGE SWING (V p-p)

5

0

100 10M

= 2.5 V

REF

Figure 40. Output Voltage Swing vs. Large Signal Frequency Response

XXX (X)

= 5 V, V

V

S

1k 10k 100k 1M

= 2.5 V

REF

FREQUENCY (Hz)

03579-019

03579-021

Rev. A | Page 15 of 28

AD8220

X

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XX

5V/DIV

XXX (X)

5µs TO 0.01%

0.002%/DIV

XX

XX XX

6µs TO 0.001%

XXX (X)

Figure 41. Large Signal Pulse Response and Settle Time, G = 1,

XX

5V/DIV

= 10 kΩ, VS = ±15 V, V

R

LOAD

REF

= 0 V

20µs/DIV

X

5V/DIV

XXX (X)

0.002%/DIV

03579-046

XX

XX XX

58sTO0.01% 74sTO0.001%

XXX (X)

200µs/DIV

03579-049

Figure 44. Large Signal Pulse Response and Settle Time, G = 1000,

= 10 kΩ, VS = ±15 V, V

R

LOAD

REF

= 0 V

XXX (X)

0.002%/DIV

XX

XX XX

4.3sTO0.01%

4.6sTO0.001%

XXX (X)

20µs/DIV

Figure 42. Large Signal Pulse Response and Settle Time, G = 10,

= 10 kΩ, VS = ±15 V, V

R

LOAD

XX

5V/DIV

XXX (X)

0.002%/DIV

XX

XX XX

8.1s TO 0.01%

9.6s TO 0.001%

XXX (X)

REF

= 0 V

20µs/DIV

Figure 43. Large Signal Pulse Response and Settle Time, G = 100,

= 10 kΩ, VS = ±15 V, V

R

LOAD

REF

= 0 V

XXX

20mV/DIV

03579-047

Figure 45. Small Signal Pulse Response, G = 1, R

= ±15 V, V

V

S

XXX

20mV/DIV

03579-048

Figure 46. Small Signal Pulse Response, G = 10, R

= ±15 V, V

V

S

XXX

REF

XXX

REF

= 0 V

LOAD

= 2 kΩ, C

LOAD

4µs/DIV

= 100 pF,

4µs/DIV

= 100 pF,

03579-016

03579-014

Rev. A | Page 16 of 28

AD8220

www.BDTIC.com/ADI

XXX

20mV/DIV

XXX

Figure 47 Small Signal Pulse Response, G = 100, R

XXX

20mV/DIV

= ±15 V, V

V

S

XXX

REF

=0 V

Figure 48. Small Signal Pulse Response, G = 1000, R

= 100 pF, VS = ±15 V, V

C

LOAD

REF

= 2 kΩ, C

= 0 V

LOAD

4µs/DIV

= 100 pF,

LOAD

40µs/DIV

= 2 kΩ,

XXX

20mV/DIV

03579-012

= 5 V, V

XXX

= 2.5 V

REF

XXX

= 2.5 V

REF

LOAD

= 2 kΩ, C

LOAD

Figure 50. Small Signal Pulse Response, G = 10, R

V

S

XXX

20mV/DIV

03579-010

Figure 51. Small Signal Pulse Response, G = 100, R

V

S

4µs/DIV

= 100 pF,

4µs/DIV

= 100 pF,

LOAD

03579-015

03579-013

XXX

20mV/DIV

XXX

Figure 49. Small Signal Pulse Response, G = 1, R

= 5 V, V

V

S

= 2.5 V

REF

LOAD

= 2 kΩ, C

4µs/DIV

= 100 pF,

LOAD

03579-017

XXX

20mV/DIV

Figure 52. Small Signal Pulse Response, G = 1000, R

= 100 pF, VS = 5 V, V

C

LOAD

Rev. A | Page 17 of 28

XXX

= 2.5 V

REF

LOAD

40µs/DIV

= 2 kΩ,

03579-011

AD8220

www.BDTIC.com/ADI

15

10

SETTL ED TO 0.001%

5

SETTLING TIME (µs)

0

02

510

OUTPUT VOLTAGE STEP SIZE (V)

Figure 53. Settling Time vs. Output Voltage St

SETTLED TO 0.01%

15

ep Size (G = 1) ±15 V, V

100

SETTLED TO 0.001%

10

SETTLED TO 0.01%

SETTLING TIME (µs)

03579-043

0

= 0 V Figure 54. Settling Time vs. Gain for a 10 V Step, VS = ±15 V, V

REF

1

1 1000

10 100

GAIN (V/V)

REF

03579-041

= 0 V

Rev. A | Page 18 of 28

AD8220

+

V

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THEORY OF OPERATION

+

S

+V

S

IN

–V

J1

Q1

C1

V

S

PINCH

I I

+

S

NODE A

R1

24.7k

–V

S

NODE C NODE D

A1 A2

The AD8220 is a JFET input, monolithic instrumentation amplifier

ased on the classic 3-op amp topology (see Figure 55). Input

b T

ransistor J1 and Input Transistor J2 are biased at a fixed current so that any input signal forces the output voltages of A1 and A2 to change accordingly; the input signal creates a current through R that flows in R1 and R2 such that the outputs of A1 and A2 provide the correct, gained signal. Topologically, J1, A1, and R1 and J2, A2, and R2 can be viewed as precision current feedback amplifiers that have a gain bandwidth of 1.5 MHz. The common-mode voltage and amplified differential signal from A1 and A2 are applied to a difference amplifier that rejects the common-mode voltage but amplifies the differential signal. The difference amplifier employs 20 kΩ laser-trimmed resistors that result in an in-amp with gain error less than 0.04%. New trim techniques were developed to ensure that CMRR exceeds 86 dB (G = 1).

Using JFET transistors, the AD8220 offers an extremely high

put impedance, extremely low bias currents of 10 pA

in maximum, a low offset current of 0.6 pA maximum, and no input bias current noise. In addition, input offset is less than 125 μV and drift is less than 5 μV/°C. Ease of use and robustness were considered. A common problem for instrumentation amplifiers is that at high gains, when the input is overdriven, an excessive milliampere input bias current can result and the output can undergo phase reversal. The AD8220 has none of these problems; its input bias current is limited to less than 10 μA, and the output does not phase reverse under overdrive fault conditions.

1

Overdriving the input at high gains refers to when the input signal is within the supply voltages but the amplifier cannot output the gained signal. For example, at a gain of 100, driving the amplifier with 10 V on ±15 V constitutes overdriving the inputs since the amplifier cannot output 100 V.

+

S

R

G

–V

NODE B

–V

S

VB

S

Figure 55. Simplified Schematic

G

1

R2

24.7k

+

S

20k

NODE F

20k

+V

S

Q2

V

J2

PINCH

C2

–IN

–V

S

A3

NODE E

20k

+V

S

OUTPUT

–V

+V

–V

S

REF

S

The AD8220 has extremely low load-induced nonlinearity. All amplifiers that comprise the AD8220 have rail-to-rail output capability for enhanced dynamic range. The input of the AD8220 can amplify signals with wide common-mode voltages even slightly lower than the negative supply rail. The AD8220 operates over a wide supply voltage range. It can operate from either a single +4.5 V to +36 V supply or a dual ±2.25 V to ±18 V. The transfer function of the AD8220 is

G

1+=

kΩ49.4

R

G

Users can easily and accurately set the gain using a single, s

tandard resistor. Because the input amplifiers employ a current feedback architecture, the AD8220 gain-bandwidth product increases with gain, resulting in a system that does not suffer as much bandwidth loss as voltage feedback architectures at higher gains. A unique pinout enables the AD8220 to meet a CMRR specification of 80 dB through 5 kHz (G = 1). The balanced pinout, shown in

fect CMRR performance. In addition, the new pinout

af

Figure 56, reduces parasitics that adversely

simplifies board layout because associated traces are grouped together. For example, the gain setting resistor pins are adjacent to the inputs, and the reference pin is next to the output.

AD8220

1

–IN

2

R

G

3

R

G

4

+IN

TOP VIEW

(Not to Scale)

Figure 56. Pin Configuration

8

+V

S

7

V

OUT

6

REF

5

–V

S

03579-005

03579-006

Rev. A | Page 19 of 28

AD8220

www.BDTIC.com/ADI

GAIN SELECTION

Placing a resistor across the RG terminals sets the AD8220 gain, which can be calculated by referring to Table 5 or by using the

in equation

ga

G

R

Table 5. Gains Achieved Using 1% Resistors

1% Standard Table Value of RG (Ω) Calculated Gain

49.9 k 1.990

12.4 k 4.984

5.49 k 9.998

2.61 k 19.93

1.00 k 50.40 499 100.0 249 199.4 100 495.0

49.9 991.0

The AD8220 defaults to G = 1 when no gain resistor is used. Gain accuracy is determined by the absolute tolerance of R The TC of the external gain resistor increases the gain drift of the instrumentation amplifier. Gain error and gain drift are kept to a minimum when the gain resistor is not used.

kΩ4.49

1

−=G

.

G

LAYOUT

Careful board layout maximizes system performance. In applications that need to take advantage of the low input bias current of the AD8220, avoid placing metal under the input path to minimize leakage current. To maintain high CMRR over frequency, lay out the input traces symmetrically and lay out the traces of the R maintain resistive and capacitive balance; this holds for additional PCB metal layers under the input and R

resistor symmetrically. Ensure that the traces

G

pins. Traces from the

G

gain setting resistor to the R possible to minimize parasitic inductance. An example layout is shown in Figure 57 and Figure 58. To ensure the most accurate

utput, the trace from the REF pin should either be connected to

o the AD8220 local ground (see Figure 59) or connected to a

oltage that is referenced to the AD8220 local ground.

v

Common-Mode Rejection Ratio (CMRR)

The AD8220 has high CMRR over frequency giving it greater immunity to disturbances, such as line noise and its associated harmonics, in contrast to typical in-amps whose CMRR falls off around 200 Hz. These in-amps often need common-mode filters at the inputs to compensate for this shortcoming. The AD8220 is able to reject CMRR over a greater frequency range, reducing the need for input common-mode filtering.

A well-implemented layout helps to maintain the high CMRR

ver frequency of the AD8220. Input source impedance and

o capacitance should be closely matched. In addition, source resistance and capacitance should be placed as close to the inputs as possible.

Grounding

The output voltage of the AD8220 is developed with respect to the potential on the reference terminal. Care should be taken to tie REF to the appropriate local ground (see Figure 59).

In mixed-signal environments, low level analog signals need to

e isolated from the noisy digital environment. Many ADCs

b have separate analog and digital ground pins. Although it is convenient to tie both grounds to a single ground plane, the current traveling through the ground wires and PC board can cause a large error. Therefore, separate analog and digital ground returns should be used to minimize the current flow from sensitive points to the system ground.

pins should be kept as short as

G

03579-101

Figure 57. Example Layout—Top Layer of the AD8220 Evaluation Board

Rev. A | Page 20 of 28

Figure 58. Example Layout—Bottom Layer of the AD8220 Evaluation Board

03579-102

AD8220

f

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REFERENCE TERMINAL

The reference terminal, REF, is at one end of a 20 kΩ resistor (see Figure 55). The output of the instrumentation amplifier is re

ferenced to the voltage on the REF terminal; this is useful when the output signal needs to be offset to voltages other than common. For example, a voltage source can be tied to the REF pin to level-shift the output so that the AD8220 can interface with an ADC. The allowable reference voltage range is a function of the gain, common-mode input, and supply voltages. The REF pin should not exceed either +V

or −VS by more than 0.5 V.

S

For best performance, especially in cases where the output is

ot measured with respect to the REF terminal, source impedance

n to the REF terminal should be kept low, because parasitic resistance can adversely affect CMRR and gain accuracy.

POWER SUPPLY REGULATION AND BYPASSING

The AD8220 has high PSRR. However, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. As in all linear circuits, bypass capacitors must be used to decouple the amplifier.

A 0.1 μF capacitor should be placed close to each supply pin. A 10 μF ta part (see p

recision integrated circuits.

ntalum capacitor can be used further away from the

Figure 59). In most cases, it can be shared by other

+V

S

INPUT BIAS CURRENT RETURN PATH

The AD8220 input bias current is extremely small at less than 10 pA. Nonetheless, the input bias current must have a return path to common. When the source, such as a transformer, cannot provide a return current path, one should be created

Figure 60).

(see

+V

S

AD8220

REF

–V

S

TRANSFORMER

+V

S

C

HIGH- PASS

=

1

2RC

R

AD8220

C

R

REF

0.1µF

+IN

AD8220

–IN

0.1µF 10µF

–V

S

Figure 59. Supply Decoupling, REF a

10µF

V

OUT

REF

nd Output Referred to Ground

LOAD

3579-001

–V

S

AC-COUPLED

Figure 60. Creating an I

BIAS

Path

03579-002

INPUT PROTECTION

All terminals of the AD8220 are protected against ESD. (ESD protection is guaranteed to 4 kV, human body model.) In addition, the input structure allows for dc overload conditions a diode drop above the positive supply and a diode drop below the negative supply. Voltages beyond a diode drop of the supplies cause the ESD diodes to conduct and enable current to flow through the diode. Therefore, an external resistor should be used in series with each of the inputs to limit current for voltages above +Vs. In either scenario, the AD8220 safely handles a continuous 6 mA current at room temperature.

For applications where the AD8220 encounters extreme o

verload voltages, as in cardiac defibrillators, external series resistors and low leakage diode clamps, such as BAV199Ls, FJH1100s, or SP720s, should be used.

Rev. A | Page 21 of 28

AD8220

V

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RF INTERFERENCE

RF rectification is often a problem in applications where there are large RF signals. The problem appears as a small dc offset voltage. The AD8220 by its nature has a 5 pF gate capacitance, C inputs. Matched series resistors form a natural low-pass filter that reduces rectification at high frequency (see Figure 61). The

elationship between external, matched series resistors and the

r internal gate capacitance is expressed as follows:

FilterFreq

DIFF

CM

Figure 61. RFI Filtering Without External Capacitors

1

=

RC

π2

G

1

=

RC

π2

G

0.1µF 10µF

+IN

R

–V

R

–IN

0.1µF 10µF

+15

C

S

C –V

–15V

G

AD8220

G

S

REF

To eliminate high frequency common-mode signals while using smal

ler source resistors, a low-pass RC network can be placed at

the input of the instrumentation amplifier (see Figure 62). The

ilter limits the input signal bandwidth according to the following

f relationship:

FilterFreq++=

FilterFreq

Mismatched C

DIFF

=

CM

capacitors result in mismatched low-pass filters.

C

1

)2(π2

CD

CCCR

G

1

)(π2

C

CCR

+

G

The imbalance causes the AD8220 to treat what would have been a common-mode signal as a differential signal. To reduce the effect of mismatched external C

greater than 10 times CC. This sets the differential filter

C

D

capacitors, select a value of

C

frequency lower than the common-mode frequency.

, at its

G

V

OUT

03579-030

+15

R

4.02k

R

4.02k

0.1µF

C

1nF

C

+IN

C

10nF

D

1nF

C

AD8220

–IN

0.1µF

–15V

REF

10µF

V

OUT

03579-003

Figure 62. RFI Suppression

COMMON-MODE INPUT VOLTAGE RANGE

The common-mode input voltage range is a function of the input range and the outputs of Internal Amplifier A1, Internal Amplifier A2, and Internal Amplifier A3, the reference voltage, and the gain. Figure 27 to Figure 30 show common-mode

oltage ranges for various supply voltages and gains.

v

DRIVING AN ADC

An instrumentation amplifier is often used in front of an ADC to provide CMRR and additional conditioning, such as a voltage level shift and gain (see Figure 63). In this example, a 2.7 nF

pacitor and a 1 kΩ resistor create an antialiasing filter for the

ca

AD7685. The 2.7 nF capacitor also serves to store and deliver

he necessary charge to the switched capacitor input of the

t ADC. The 1 kΩ series resistor reduces the burden of the 2.7 nF load from the amplifier. However, large source impedance in front of the ADC can degrade THD.

The example shown in Figure 63 is for sub-60 kHz applications. F

or higher bandwidth applications where THD is important, the series resistor needs to be small. At worst, a small series resistor can load the AD8220, potentially causing the output to overshoot or ring. In such cases, a buffer amplifier, such as the

AD8615, should be used after the AD8220 to drive the ADC.

+5

±50mV

0.1µF10µF

+IN

REF

1k

2.7nF

+2.5V

1.07k

AD8220

–IN

Figure 63. Driving an ADC in a Low Frequency Application

AD7685

ADR435

+5V

4.7µF

3579-033

Rev. A | Page 22 of 28

AD8220

V

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APPLICATIONS

AC-COUPLED INSTRUMENTATION AMPLIFIER

Measuring small signals that are in the noise or offset of the amplifier can be a challenge. Figure 64 shows a circuit that c

an improve the resolution of small ac signals. The large gain reduces the referred input noise of the amplifier to 14 nV/√Hz. Therefore, smaller signals can be measured because the noise floor is lower. DC offsets that would have been gained by 100 are eliminated from the AD8220 output by the integrator feedback network.

At low frequencies, the OP1177 forces the AD8220 output to 0 V

. Once a signal exceeds f

amplified input signal.

+

S

0.1µF

+IN

R

–IN

0.1µF

AD8220

–V

S

499

REF

, the AD8220 outputs the

HIGH-PASS

f

HIGH-PASS

1µF

0.1µF

C

=

+V

S

OP1177

1

2RC

15.8k

R

DIFFERENTIAL OUTPUT

In certain applications, it is necessary to create a differential signal. New high resolution ADCs often require a differential input. In other cases, transmission over a long distance can require differential processing for better immunity to interference.

Figure 65 shows how to configure the AD8220 to output a dif

ferential signal. An OP1177 op amp is used to create a

dif

ferential voltage. Errors from the op amp are common to both outputs and are thus common mode. Likewise, errors from using mismatched resistors cause a common-mode dc offset error. Such errors are rejected in differential signal processing by differential input ADCs or instrumentation amplifiers.

When using this circuit to drive a differential ADC, V set using a resistor divider from the reference of the ADC to make the output ratiometric with the ADC as shown in Figure 66.

can be

REF

–V

+V

S

10µF10µF

Figure 64. AC-Coupled Circuit

0.1µF

V

–V

S

REF

03579-004

Rev. A | Page 23 of 28

AD8220

V

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+15

+5V

–5V

AMPLITUDE

TIME

±5V

10µF

0.1µF

+5V

+IN

–IN

AD8220

–15V

REF

4.99k

–15V

0.1µF

OP1177

0.1µF

V

+15V

V

OUT

A=+VIN+V

2

AMPLITUDE

V

REF

2.5V

B=–VIN+V

2

REF

+5.0V +2.5V +0V

REF

TIME

03579-008

Figure 65. Differential Output with Level Shift

+15

0.1µF

TIME

±5V

+IN

AD8220

REF

4.99k

OP1177

4.99k

0.1µF

10µF

0.1µF

–IN

+5V

–15V

Figure 66. Configuring the AD8220 to Output A Ra

V

A=+VIN+V

OUT

+5V FROM REFERENCE

V

REF

2.5V

+15V–15V

0.1µF

V

B=–VIN+V

OUT

REF

2

TO 0V TO +5V ADC

4.99k

2

10nF

TO 0V TO +5V ADC

REF

tiometric, Differential Signal

+5V FROM REFERENCE

REF

+AIN

–AIN

3579-031

Rev. A | Page 24 of 28

AD8220

A

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ELECTROCARDIOGRAM SIGNAL CONDITIONING

The AD8220 makes an excellent input amplifier for next generation ECGs. Its small size, high CMRR over frequency, rail-to-rail output, and JFET inputs are well suited for this application. Potentials measured on the skin range from 0.2 mV to 2 mV. The AD8220 solves many of the typical challenges of measuring these body surface potentials. The high CMRR of the AD8220 helps reject common-mode signals that come in the form of line noise or high frequency EMI from equipment in the operating room. Its rail-to-rail output offers a wide dynamic range allowing for higher gains than would be possible using other instrumentation amplifiers. JFET inputs offer a large input capacitance of 5 pF. A natural RC filter is formed reducing high frequency noise when series input resistors are used in front of the AD8220 (see the

2.2pF

10k

10pF

10k

2.2pF

AB

C

15k

RF Interference section).

INSTRUMENTATION

AMPLIFIER

+5V

–5V

+5V

–5V

24.9k

AD8220

4.12k

OP2177

499k

G=+14

HIGH-PASS FI LTER 0.033Hz

+5V

–5V

OP AMPS

68pF

866k

+5V

–5V

2.5V

+5V

4.7µF

–5V

220pF

12.7k

OP2177

Figure 67. Example ECG Schematic

In addition, the AD8220 JFET inputs have ultralow input b

ias current and no current noise, making it useful for ECG applications where there are often large impedances. The MSOP and the optimal pinout of the AD8220 allow smaller footprints and more efficient layout, paving the way for next-generation portable ECGs.

Figure 67 shows an example ECG schematic. Following the AD8220 is a 0.0

33 Hz high-pass filter, formed by the 4.7 μF capacitor and the 1 MΩ resistor, which removes the dc offset that develops between the electrodes. An additional gain of 50, provided by the ra

nge of the ADC. An active, fifth-order, low-pass Bessel filter

AD8618, makes use of the 0 V to 5 V input

removes signals greater than approximately 160 Hz. An OP2177

uffers, inverts, and gains the common-mode voltage taken at

b the midpoint of the AD8220 gain setting resistors. This rightleg drive circuit helps cancel common-mode signals by inverting the common-mode signal and driving it back into the body. A 499 kΩ series resistor at the output of the limi

ts the current driven into the body.

G=+50

14k57.6k1.18k

+5V

AD8618

1M

SS FIF TH ORDER FILTER AT 157Hz

LOW-P

14k

47nF

+5V

19.3k 14.5k

AD8618

33nF

2.5V2.5V2.5V

33nF

AD8618

1.15k

4.99k

+5V

68nF

14.5k19.3k

AD8618

+5V

500

2.7nF

22nF

2.5V

OP2177

AD7685

ADC

REF

+5V

4.7µF

REFERENCE ADR435

03579-032

Rev. A | Page 25 of 28

AD8220

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OUTLINE DIMENSIONS

3.20

3.00

2.80

8

5

4

SEATING PLANE

5.15

4.90

4.65

1.10 MAX

0.23

0.08

8° 0°

0.80

0.60

0.40

3.20

3.00

2.80

PIN 1

0.95

0.85

0.75

0.15

0.00

COPLANARITY

1

0.65 BSC

0.38

0.22

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 68. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dim

ensions shown in millimeters

ORDERING GUIDE

Model Temperature Range

AD8220ARMZ AD8220ARMZ-RL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 H01 AD8220ARMZ-R7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 H01 AD8220BRMZ −40°C to +85°C 8-Lead MSOP RM-8 H0P AD8220BRMZ-RL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 H0P AD8220BRMZ-R7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 H0P AD8220-EVALZ Evaluation Board

1

See the Typical Performance Characteristics section for expected operation from 85°C to 125°C.

2

Z = RoHS Compliant Part.

2

−40°C to +85°C 8-Lead MSOP RM-8 H01

1

Package Description Package Option Branding

Rev. A | Page 26 of 28

AD8220

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NOTES

Rev. A | Page 27 of 28

AD8220

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NOTES

Rev. A | Page 28 of 28

Datasheet AD8220 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

PIN CONFIGURATION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

GAIN SELECTION

LAYOUT

Common-Mode Rejection Ratio (CMRR)

Grounding

REFERENCE TERMINAL

POWER SUPPLY REGULATION AND BYPASSING

INPUT BIAS CURRENT RETURN PATH

INPUT PROTECTION

RF INTERFERENCE

COMMON-MODE INPUT VOLTAGE RANGE

DRIVING AN ADC

APPLICATIONS

AC-COUPLED INSTRUMENTATION AMPLIFIER

DIFFERENTIAL OUTPUT

ELECTROCARDIOGRAM SIGNAL CONDITIONING

OUTLINE DIMENSIONS

ORDERING GUIDE