Page 1
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD820
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
Single Supply, Rail to Rail
Low Power FET-Input Op Amp
FUNCTIONAL BLOCK DIAGRAM
FEATURES
True Single Supply Operation
Output Swings Rail-to-Rail
Input Voltage Range Extends Below Ground
Single Supply Capability from 5 V to 36 V
Dual Supply Capability from 2.5 V to 18 V
Excellent Load Drive
Capacitive Load Drive Up to 350 pF
Minimum Output Current of 15 mA
Excellent AC Performance for Low Power
800 A Max Quiescent Current
Unity Gain Bandwidth: 1.8 MHz
Slew Rate of 3.0 V/s
Excellent DC Performance
800 V Max Input Offset Voltage
1 V/C Typ Offset Voltage Drift
25 pA Max Input Bias Current
Low Noise
13 nV/√Hz @ 10 kHz
APPLICATIONS
Battery-Powered Precision Instrumentation
Photodiode Preamps
Active Filters
12- to 14-Bit Data Acquisition Systems
Medical Instrumentation
Low Power References and Regulators
PRODUCT DESCRIPTION
The AD820 is a precision, low power FET input op amp that
can operate from a single supply of 5.0 V to 36 V, or dual supplies of ±2.5 V to ±18 V. It has true single supply capability
with an input voltage range extending below the negative rail,
50
0
10
15
5
1
10
0
30
20
25
35
40
45
98765432
INPUT BIAS CURRENT – pA
NUMBER OF UNITS
Figure 1. Typical Distribution of Input Bias Current
allowing the AD820 to accommodate input signals below ground
in the single supply mode. Output voltage swing extends to within
10 mV of each rail providing the maximum output dynamic range.
Offset voltage of 800 µV max, offset voltage drift of 1 µV/°C,
typical input bias currents below 25 pA and low input voltage noise
provide dc precision with source impedances up to a Gigaohm.
1.8 MHz unity gain bandwidth, –93 dB THD at 10 kHz and
3 V/µs slew rate are provided for a low supply current of 800 µA.
The AD820 drives up to 350 pF of direct capacitive load and
provides a minimum output current of 15 mA. This allows the
amplifier to handle a wide range of load conditions. This combination of ac and dc performance, plus the outstanding load drive
capability, results in an exceptionally versatile amplifier for the
single supply user.
The AD820 is available in two performance grades. The A and
B grades are rated over the industrial temperature range of
–40°C to +85°C.
The AD820 is offered in two varieties of 8-lead package: plastic
DIP, and surface mount (SOIC).
Figure 2. Gain of 2 Amplifier; VS = 5, 0,
V
IN
= 2.5V Sine Centered at 1.25 Volts
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
AD820
NULL
–IN
+IN
–V
S
NC
+V
S
V
OUT
NULL
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
AD820
NC
–IN
+IN
–V
S
NC
+V
S
V
OUT
NC
NC = NO CONNECT
Page 2
REV. C
–2–
AD820–SPECIFICATIONS
AD820A AD820B
Parameter Conditions Min Typ Max Min Typ Max Unit
DC PERFORMANCE
Initial Offset 0.1 0.8 0.1 0.4 mV
Max Offset over Temperature 0.5 1.2 0.5 0.9 mV
Offset Drift 2 2 µV/°C
Input Bias Current V
O
= 0 V to 4 V 2 25 2 10 pA
at T
MAX
0.5 5 0.5 2.5 nA
Input Offset Current 2 20 2 10 pA
at T
MAX
0.5 0.5 nA
Open-Loop Gain V
O
= 0.2 V to 4 V
T
MIN
to T
MAX
RL = 100 kΩ 400 1000 500 1000 V/mV
400 400 V/mV
T
MIN
to T
MAX
RL = 10 kΩ 80 150 80 150 V/mV
80 80 V/mV
T
MIN
to T
MAX
RL = 1 kΩ 15 30 15 30 V/mV
10 10 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz 2 2 µV p-p
f = 10 Hz 25 25 nV/√Hz
f = 100 Hz 21 21 nV/√Hz
f = 1 kHz 16 16 nV/√Hz
f = 10 kHz 13 13 nV/√Hz
Input Current Noise
0.1 Hz to 10 Hz 18 18 fA p-p
f = 1 kHz 0.8 0.8 fA/√Hz
Harmonic Distortion R
L
= 10 kΩ to 2.5 V
f = 10 kHz VO = 0.25 V to 4.75 V –93 –93 dB
DYNAMIC PERFORMANCE
Unity Gain Frequency 1.8 1.8 MHz
Full Power Response V
O
p-p = 4.5 V 210 210 kHz
Slew Rate 3 3 V/µs
Settling Time
to 0.1% V
O
= 0.2 V to 4.5 V 1.4 1.4 µs
to 0.01% 1.8 1.8 µs
INPUT CHARACTERISTICS
Common-Mode Voltage Range
1
–0.2 +4 –0.2 +4 V
T
MIN
to T
MAX
–0.2 +4 –0.2 +4 V
CMRR V
CM
= 0 V to 2 V 66 80 72 80 dB
T
MIN
to T
MAX
66 66 dB
Input Impedance
Differential 10
13
储0.5 1013储0.5 Ω储pF
Common Mode 1013储2.8 1013储2.8 Ω储pF
OUTPUT CHARACTERISTICS
Output Saturation Voltage
2
VOL–V
EE
I
SINK
= 20 µA 5 7 57mV
T
MIN
to T
MAX
10 10 mV
VCC–V
OH
I
SOURCE
= 20 µA 10 14 1014mV
T
MIN
to T
MAX
20 20 mV
V
OL–VEE
I
SINK
= 2 mA 40 55 40 55 mV
T
MIN
to T
MAX
80 80 mV
V
CC–VOH
I
SOURCE
= 2 mA 80 110 80 110 mV
T
MIN
to T
MAX
160 160 mV
VOL–V
EE
I
SINK
= 15 mA 300 500 300 500 mV
T
MIN
to T
MAX
1000 1000 mV
V
CC–VOH
I
SOURCE
= 15 mA 800 1500 800 1500 mV
T
MIN
to T
MAX
1900 1900 mV
Operating Output Current 15 15 mA
T
MIN
to T
MAX
12 12 mA
Short-Circuit Current 25 25 mA
Capacitive Load Drive 350 350 pF
POWER SUPPLY
Quiescent Current T
MIN
to T
MAX
620 800 620 800 µA
Power Supply Rejection VS+ = 5 V to 15 V 70 80 66 80 dB
T
MIN
to T
MAX
70 66 dB
(VS = 0, 5 V @ TA = 25C, VCM = 0 V, V
OUT
= 0.2 V unless otherwise noted.)
Page 3
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–3–
AD820
SPECIFICATIONS
AD820A AD820B
Parameter Conditions Min Typ Max Min Typ Max Unit
DC PERFORMANCE
Initial Offset 0.1 0.8 0.3 0.4 mV
Max Offset over Temperature 0.5 1.5 0.5 1 mV
Offset Drift 2 2 µV/°C
Input Bias Current V
O
= –5 V to 4 V 2 25 2 10 pA
at T
MAX
0.5 5 0.5 2.5 nA
Input Offset Current 2 20 2 10 pA
at T
MAX
0.5 0.5 nA
Open-Loop Gain V
O
= 4 V to –4 V
R
L
= 100 kΩ 400 1000 400 1000 V/mV
T
MIN
to T
MAX
400 400 V/mV
R
L
= 10 kΩ 80 150 80 150 V/mV
T
MIN
to T
MAX
80 80 V/mV
R
L
= 1 kΩ 20 30 20 30 V/mV
T
MIN
to T
MAX
10 10 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz 2 2 µV p-p
f = 10 Hz 25 25 nV/√Hz
f = 100 Hz 21 21 nV/√Hz
f = 1 kHz 16 16 nV/√Hz
f = 10 kHz 13 13 nV/√ Hz
Input Current Noise
0.1 Hz to 10 Hz 18 18 fA p-p
f = 1 kHz 0.8 0.8 fA/√Hz
Harmonic Distortion R
L
= 10 kΩ
f = 10 kHz VO = ±4.5 V –93 –93 dB
DYNAMIC PERFORMANCE
Unity Gain Frequency 1.9 1.8 MHz
Full Power Response V
O
p-p = 9 V 105 105 kHz
Slew Rate 3 3 V/µs
Settling Time
to 0.1% V
O
= 0 V to ±4.5 V 1.4 1.4 µs
to 0.01% 1.8 1.8 µs
INPUT CHARACTERISTICS
Common-Mode Voltage Range
1
–5.2 +4 –5.2 +4 V
T
MIN
to T
MAX
–5.2 +4 –5.2 +4 V
CMRR V
CM
= –5 V to +2 V 66 80 72 80 dB
T
MIN
to T
MAX
66 66 dB
Input Impedance
Differential 10
13
储0.5 1013储0.5 Ω储pF
Common Mode 1013储2.8 1013储2.8 Ω储pF
OUTPUT CHARACTERISTICS
Output Saturation Voltage
2
VOL–V
EE
I
SINK
= 20 µA 5 7 57mV
T
MIN
to T
MAX
10 10 mV
V
CC–VOH
I
SOURCE
= 20 µA 10 14 1014mV
T
MIN
to T
MAX
20 20 mV
V
OL–VEE
I
SINK
= 2 mA 40 55 40 55 mV
T
MIN
to T
MAX
80 80 mV
VCC–V
OH
I
SOURCE
= 2 mA 80 110 80 110 mV
T
MIN
to T
MAX
160 160 mV
V
OL–VEE
I
SINK
= 15 mA 300 500 300 500 mV
T
MIN
to T
MAX
1000 1000 mV
V
CC–VOH
I
SOURCE
= 15 mA 800 1500 800 1500 mV
T
MIN
to T
MAX
1900 1900 mV
Operating Output Current 15 15 mA
T
MIN
to T
MAX
12 12 mA
Short-Circuit Current 30 30 mA
Capacitive Load Drive 350 350 pF
POWER SUPPLY
Quiescent Current T
MIN
to T
MAX
650 800 620 800 µA
Power Supply Rejection V
S
+ = 5 V to 15 V 70 80 70 80 dB
T
MIN
to T
MAX
70 70 dB
(VS = 0, 5 V @ TA = 25C, VCM = 0 V, V
OUT
= 0.2 V unless otherwise noted.)
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–4–
AD820–SPECIFICATIONS
AD820A AD820B
Parameter Conditions Min Typ Max Min Typ Max Unit
DC PERFORMANCE
Initial Offset 0.4 2 0.3 1.0 mV
Max Offset over Temperature 0.5 3 0.5 2 mV
Offset Drift 2 2 µV/°C
Input Bias Current V
CM
= 0 V 2 25 2 10 pA
V
CM
= –10 V 40 40 pA
at T
MAX
VCM = 0 V 0.5 5 0.5 2.5 nA
Input Offset Current 2 20 2 10 pA
at T
MAX
0.5 0.5 nA
Open-Loop Gain V
O
= +10 V to –10 V
R
L
= 100 kΩ 500 2000 500 2000 V/mV
T
MIN
to T
MAX
500 500 V/mV
R
L
= 10 kΩ 100 500 100 500 V/mV
T
MIN
to T
MAX
100 100 V/mV
R
L
= 1 kΩ 30 45 30 45 V/mV
T
MIN
to T
MAX
20 20 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz 2 2 µV p-p
f = 10 Hz 25 25 nV/√Hz
f = 100 Hz 21 21 nV/√Hz
f = 1 kHz 16 16 nV/√Hz
f = 10 kHz 13 13 nV/√ Hz
Input Current Noise
0.1 Hz to 10 Hz 18 18 fA p-p
f = 1 kHz 0.8 0.8 fA/√Hz
Harmonic Distortion R
L
= 10 kΩ
f = 10 kHz VO = ±10 V –85 –85 dB
DYNAMIC PERFORMANCE
Unity Gain Frequency 1.9 1.9 MHz
Full Power Response V
O
p-p = 20 V 45 45 kHz
Slew Rate 3 3 V/µs
Settling Time
to 0.1% V
O
= 0 V to ±10 V 4.1 4.1 µs
to 0.01% 4.5 4.5 µs
INPUT CHARACTERISTICS
Common-Mode Voltage Range
1
–15.2 +14 –15.2 +14 V
T
MIN
to T
MAX
–15.2 +14 –15.2 +14 V
CMRR V
CM
= –15 V to 12 V 70 80 74 90 dB
T
MIN
to T
MAX
70 74 dB
Input Impedance
Differential 1013储0.5 1013储0.5 Ω储pF
Common Mode 1013储2.8 1013储2.8 Ω储pF
OUTPUT CHARACTERISTICS
Output Saturation Voltage
2
VOL–V
EE
I
SINK
= 20 µA 5 7 57mV
T
MIN
to T
MAX
10 10 mV
V
CC–VOH
I
SOURCE
= 20 µA 10 14 1014mV
T
MIN
to T
MAX
20 20 mV
V
OL–VEE
I
SINK
= 2 mA 40 55 40 55 mV
T
MIN
to T
MAX
80 80 mV
V
CC–VOH
I
SOURCE
= 2 mA 80 110 80 110 mV
T
MIN
to T
MAX
160 160 mV
V
OL–VEE
I
SINK
= 15 mA 300 500 300 500 mV
T
MIN
to T
MAX
1000 1000 mV
V
CC–VOH
I
SOURCE
= 15 mA 800 1500 800 1500 mV
T
MIN
to T
MAX
1900 1900 mV
Operating Output Current 20 20 mA
T
MIN
to T
MAX
15 15 mA
Short-Circuit Current 45 45 mA
Capacitive Load Drive 350 350
POWER SUPPLY
Quiescent Current T
MIN
to T
MAX
700 900 700 900 µA
Power Supply Rejection V
S
+ = 5 V to 15 V 70 80 70 80 dB
T
MIN
to T
MAX
70 70 dB
(VS = 15 V @ TA = 25C, VCM = 0 V, V
OUT
= 0 V unless otherwise noted.)
Page 5
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–5–
AD820
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD820 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
NOTES
1
This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+ VS – 1 V) to +VS.
Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 volt below the positive supply.
2
VOL–VEE is defined as the difference between the lowest possible output voltage (VOL) and the minus voltage supply rail (VEE).
VCC–VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation
2
Plastic DIP (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 W
SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W
Input Voltage . . . . . . . . . . . . . . (+V
S
+ 0.2 V) to – (20 V + VS)
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Storage Temperature Range (N) . . . . . . . . . –65°C to +125°C
Storage Temperature Range (R) . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD820A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range
(Soldering 60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
8-Lead Plastic DIP Package: θJA = 90°C/W
8-Lead SOIC Package: θJA = 160°C/W
ORDERING GUIDE
Temperature Package Package
Model Range Description Options
AD820AN –40°C to +85°C 8-Lead Plastic Mini-DIP N-8
AD820BN* –40°C to +85°C 8-Lead Plastic Mini-DIP N-8
AD820AR –40°C to +85°C 8-Lead SOIC R-8
AD820BR –40°C to +85°C 8-Lead SOIC R-8
WARNING!
ESD SENSITIVE DEVICE
*Not for new design, obsolete April 2002.
Page 6
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AD820
0.5
50
0
0
30
10
–0.4
20
–0.5
40
0.40.30.20.1–0.1–0.2–0.3
OFFSET VOLTAGE – mV
NUMBER OF UNITS
VS = 0V, 5V
TPC 1. Typical Distribution of Offset Voltage
(248 Units)
VS = 5V
V
S
= 15V
OFFSET VOLTAGE DRIFT – V/C
48
0
10
24
8
–8
16
–10
40
32
84206–2–4–6
% IN BIN
TPC 2. Typical Distribution of Offset Voltage
Drift (120 Units)
50
0
10
15
5
1
10
0
30
20
25
35
40
45
98765432
INPUT BIAS CURRENT – pA
NUMBER OF UNITS
TPC 3. Typical Distribution of Input Bias
Current (213 Units)
INPUT BIAS CURRENT – pA
5
0
–5
–5 –4543210–1–2–3
COMMON-MODE VOLTAGE – V
VS = 5V
VS = 0V, +5V AND 5V
TPC 4. Input Bias Current vs. Common-Mode
Voltage; V
S
= +5 V, 0 V and VS = ±5 V
INPUT BIAS CURRENT – pA
COMMON-MODE VOLTAGE – V
1k
10
0.1
–16 –12 1612840–4–8
100
1
TPC 5. Input Bias Current vs. Common-Mode
Voltage; V
S
= ±15 V
100k
100
0.1
20 40 1401201008060
1k
10k
1
10
TEMPERATURE – C
INPUT BIAS CURRENT – pA
TPC 6. Input Bias Current vs. Temperature;
V
S
= 5 V, VCM = 0
–Typical Performance Characteristics
Page 7
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–7–
AD820
VS = 15V
10M
100k
10k
100 1k 100k10k
1M
LOAD RESISTANCE –
OPEN-LOOP GAIN –V/V
VS = 0V, 5V
TPC 7. Open-Loop Gain vs. Load Resistance
RL = 10k
RL = 100k
140
10M
100k
10k
1M
–60 –40 120100806040200–20
TEMPERATURE – C
OPEN-LOOP GAIN – V/V
RL = 600
VS = 0V, 5V
VS = 0V, 5V
VS = 0V, 5V
VS = 15V
VS = 15V
VS = 15V
TPC 8. Open-Loop Gain vs. Temperature
RL = 100k
RL = 600
300
–300
16
0
–200
–12
–100
–16
200
100
1240–48–8
OUTPUT VOLTAGE – V
INPUT VOLTAGE – V
RL = 10k
TPC 9. Input Error Voltage vs. Output Voltage
for Resistive Loads
NEG RAIL
POS RAIL
RL = 2k
RL = 20k
POS
RAIL
RL = 100k
40
–40
0 300
20
–20
60
0
180 240120
OUTPUT VOLTAGE FROM VOLTAGE RAILS – mV
INPUT VOLTAGE – V
NEG RAIL
NEG RAIL
POS RAIL
TPC 10. Input Error Voltage with Output Voltage
within 300 mV of Either Supply Rail for Various
Resistive Loads; VS = ±5 V
1k
100
1
10 10k1k100
1
FREQUENCY – Hz
10
INPUT VOLTAGE NOISE – nV/ Hz
TPC 11. Input Voltage Noise vs. Frequency
RL = 10k
A
CL
= –1
VS = 0V, 5V; V
OUT
= 4.5V p-p
VS = 5V; V
OUT
= 9V p-p
–40
–90
–110
100 1k 100k10k
–60
–100
–80
–70
–50
FREQUENCY – Hz
THD – dB
VS = 15V; V
OUT
= 20V p-p
TPC 12. Total Harmonic Distortion vs. Frequency
Page 8
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AD820
100
40
–20
10 100 10M1M100k10k1k
60
80
0
20
FREQUENCY – Hz
OPEN-LOOP GAIN – dB
100
40
–20
60
80
0
20
PHASE MARGIN IN DEGREES
GAIN
PHASE
RL = 2k
C
L
= 100pF
TPC 13. Open-Loop Gain and Phase Margin
vs. Frequency
ACL = +1
V
S
= 15V
1k
100
0.01
100 1k 10M1M100k10k
10
1
0.1
FREQUENCY – Hz
OUTPUT IMPEDANCE –
TPC 14. Output Impedance vs. Frequency
1%
1%
ERROR
0.01%0.1%
16
–16
5.0
–8
–12
1.00.0
0
–4
4
8
12
4.03.02.0
SETTLING TIME –
s
OUTPUT SWING FROM 0 TO Volts
TPC 15. Output Swing and Error vs. Settling Time
100
50
0
10 100 10M1M100k10k1k
60
70
80
90
10
20
30
40
FREQUENCY – Hz
COMMON-MODE REJECTION – dB
VS = 0V, 5V
VS = 15V
TPC 16. Common-Mode Rejection vs. Frequency
POSITIVE
RAIL
+125C
+125C
+25C
NEGATIVE
RAIL
–55
C
COMMON-MODE VOLTAGE FROM SUPPLY RAILS – V
COMMON-MODE ERROR VOLTAGE – mV
5
0
3
3
1
2
–1
4
210
–55C
TPC 17. Absolute Common-Mode Error vs.
Common-Mode Voltage from Supply Rails
(VS – VCM)
VOL– V
S
1000
100
0
0.001 0.01 1001010.1
10
LOAD CURRENT – mA
OUTPUT SATURATION VOLTAGE – mV
VS – V
OH
TPC 18. Output Saturation Voltage vs. Load Current
Page 9
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AD820
I
SOURCE
= 10mA
I
SINK
= 10mA
I
SOURCE
= 1mA
I
SINK
= 1mA
I
SOURCE
= 10A
I
SINK
= 10A
1000
100
1
–60 –40 140120100806040200–20
10
TEMPERATURE – C
OUTPUT SATURATION VOLTAGE – mV
TPC 19. Output Saturation Voltage vs.
Temperature
–OUT
VS = 15V
VS = 15V
VS = 0V, 5V
TEMPERATURE – C
SHORT CIRCUIT CURRENT LIMIT – mA
80
0
140
20
10
–40–60
40
30
50
60
70
120100806040200–20
+
–
+
VS = 0V, 5V
TPC 20. Short Circuit Current Limit vs.
Temperature
T = +125C
T = +25C
T = –55C
TOTAL SUPPLY VOLTAGE – V
QUIESCENT CURRENT – A
800
0
36
200
100
40
400
300
500
600
700
3028242016128
TPC 21. Quiescent Current vs. Supply
Voltage vs. Temperature
FREQUENCY – Hz
POWER SUPPLY REJECTION – dB
120
60
0
10 100 10M1M100k10k1k
30
90
80
20
50
110
70
10
40
100
–PSRR
+PSRR
TPC 22. Power Supply Rejection vs. Frequency
R1 = 2k
FREQUENCY – Hz
OUTPUT VOLTAGE – V
30
15
0
10k 100k 10M1M
10
5
20
25
VS = 15V
VS = 0V, 5V
TPC 23. Large Signal Frequency Response
Page 10
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AD820
Figure 6. Large Signal Response Unity Gain
Follower; V
S
= ±15 V, RL = 10 k
Ω
Figure 7. Small Signal Response Unity Gain
Follower; V
S
= ±15 V, RL = 10 k
Ω
GND
Figure 8. VS = 5 V, 0 V; Unity Gain Follower
Response to 0 V to 5 V Step
AD820
RL100pF
V
OUT
0.01F
+V
S
V
IN
0.01F
–V
S
3
2
4
7
6
Figure 3. Unity Gain Follower
Figure 4. 20 V, 25 kHz Sine Input; Unity Gain
Follower; R
L
= 600 Ω, VS = ±15 V
GND
Figure 5. VS = 5 V, 0 V; Unity Gain Follower
Response to 0 V to 4 V Step
Page 11
REV. C
–11–
AD820
GND
Figure 12. VS = 5 V, 0 V; Unity Gain Follower
Response to 40 mV Step Centered 40 mV
above Ground
100
GND
Figure 13. VS = 5 V, 0 V; Gain-of-Two Inverter
Response to 20 mV Step, Centered 20 mV
below Ground
AD820
R
L
100pF
V
OUT
0.01F
+V
S
V
IN
3
2
4
7
6
Figure 9. Unity Gain Follower
10k 20k
V
IN
AD820
R
L
100pF
V
OUT
0.01F
+V
S
3
2
4
7
6
Figure 10. Gain of Two Inverter
GND
Figure 11. VS = 5 V, 0 V; Gain-of-Two Inverter
Response to 2.5 V Step Centered –1.25 V
below Ground
Page 12
REV. C
–12–
AD820
APPLICATION NOTES
Input Characteristics
In the AD820, n-channel JFETs are used to provide a low offset,
low noise, high impedance input stage. Minimum input commonmode voltage extends from 0.2 V below –V
S
to 1 V less than +VS.
Driving the input voltage closer to the positive rail will cause a
loss of amplifier bandwidth (as can be seen by comparing the
large signal responses shown in Figures 5 and 8) and increased
common-mode voltage error as illustrated in TPC 11.
The AD820 does not exhibit phase reversal for input voltages
up to and including +VS. Figure 14a shows the response of an
AD820 voltage follower to a 0 V to 5 V (+V
S
) square wave
input. The input and output are superimposed. The output
polarity tracks the input polarity up to +V
S
—no phase reversal.
The reduced bandwidth above a 4 V input causes the rounding
of the output wave form. For input voltages greater than +V
S
, a
resistor in series with the AD820’s plus input will prevent phase
reversal, at the expense of greater input voltage noise. This is
illustrated in Figure 14b.
Since the input stage uses n-channel JFETs, input current during
normal operation is negative; the current flows out from the input
terminals. If the input voltage is driven more positive than +V
S
– 0.4 V, the input current will reverse direction as internal device
junctions become forward biased. This is illustrated in TPC 4.
R
P
AD820
V
OUT
V
IN
+5V
GND
(a)
+V
S
GND
(b)
Figure 14. (a) Response with RP = 0; VIN from 0 to +V
S
Figure 36. (b) VIN = 0 to +VS + 200 mV
V
OUT
= 0 to +V
S
RP = 49.9 k
Ω
A current limiting resistor should be used in series with the
input of the AD820 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV, or if an
input voltage will be applied to the AD820 when ±V
S
= 0. The
amplifier will be damaged if left in that condition for more than
10 seconds. A 1 kΩ resistor allows the amplifier to withstand up
to 10 volts of continuous overvoltage, and increases the input
voltage noise by a negligible amount.
Input voltages less than –V
S
are a completely different story.
The amplifier can safely withstand input voltages 20 V below the
minus supply voltage as long as the total voltage from the positive
supply to the input terminal is less than 36 V. In addition, the
input stage typically maintains picoamp level input currents across
that input voltage range.
The AD820 is designed for 13 nV/√Hz wideband input voltage
noise and maintains low noise performance to low frequencies
(refer to TPC 11). This noise performance, along with the AD820’s
low input current and current noise means that the AD820
contributes negligible noise for applications with source resistances
greater than 10 kΩ and signal bandwidths greater than 1 kHz.
This is illustrated in Figure 15.
AMPLIFIER-GENERATED
NOISE
RESISTOR JOHNSON
NOISE
WHENEVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR APPLICATION.
100k
0.1
10G
100
1
100k
10
10k
10k
1k
1G100M10M1M
SOURCE IMPEDANCE –
INPUT VOLTAGE NOISE – V
RMS
1kHz
10Hz
Figure 15. Total Noise vs. Source Impedance
Output Characteristics
The AD820’s unique bipolar rail-to-rail output stage swings within
5 mV of the minus supply and 10 mV of the positive supply with
no external resistive load. The AD820’s approximate output
saturation resistance is 40 Ω sourcing and 20 Ω sinking. This can
be used to estimate output saturation voltage when driving heavier
current loads. For instance, when sourcing 5 mA, the saturation
voltage to the positive supply rail will be 200 mV, when sinking
5 mA, the saturation voltage to the minus rail will be 100 mV.
The amplifier’s open-loop gain characteristic will change as a
function of resistive load, as shown in TPCs 7 through 10. For
load resistances over 20 kΩ, the AD820’s input error voltage is
virtually unchanged until the output voltage is driven to 180 mV
of either supply.
If the AD820’s output is driven hard against the output saturation voltage, it will recover within 2 µs of the input returning to
the amplifier’s linear operating region.
Page 13
REV. C
–13–
AD820
Direct capacitive load will interact with the amplifier’s effective
output impedance to form an additional pole in the amplifier’s
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is used
as a unity gain follower. Figure 16 shows the AD820’s pulse response
as a unity gain follower driving 350 pF. This amount of overshoot
indicates approximately 20 degrees of phase margin—the system
is stable, but is nearing the edge. Configurations with less loop
gain, and as a result less loop bandwidth, will be much less sensitive to capacitance load effects. Figure 17 is a plot of capacitive
load that will result in a 20 degree phase margin versus noise gain
for the AD820. Noise gain is the inverse of the feedback attenu–
ation factor provided by the feedback network in use.
Figure 16. Small Signal Response of AD820 as Unity Gain
Follower Driving 350 pF Capacitive Load
R
I
R
F
CAPACITIVE LOAD FOR 20 PHASE MARGIN – pF
5
4
1
300
NOISE GAIN – 1+
R
F
R
I
3
2
1k 3k 10k 30k
Figure 17. Capacitive Load Tolerance vs. Noise Gain
Figure 18 shows a possible configuration for extending capacitance load drive capability for a unity gain follower. With these
component values, the circuit will drive 5,000 pF with a 10%
overshoot.
100
20k
AD820
V
OUT
0.01F
+V
S
V
IN
0.01F
–V
S
3
2
4
7
6
20pF
Figure 18. Extending Unity Gain Follower Capacitive Load
Capability Beyond 350 pF
OFFSET VOLTAGE ADJUSTMENT
The AD820’s offset voltage is low, so external offset voltage nulling is not usually required. Figure 19 shows the recommended
technique for AD820’s packaged in plastic DIPs. Adjusting offset
voltage in this manner will change the offset voltage temperature
drift by 4 µV/°C for every millivolt of induced offset. The null pins
are not functional for AD820s in the SO-8 “R” package.
20k
1
AD820
+V
S
–V
S
3
2
4
7
6
5
Figure 19. Offset Null
APPLICATIONS
Single Supply Half-Wave and Full-Wave Rectifiers
An AD820 configured as a unity gain follower and operated with
a single supply can be used as a simple half-wave rectifier. The
AD820’s inputs maintain picoamp level input currents even when
driven well below the minus supply. The rectifier puts that behavior to good use, maintaining an input impedance of over 10
11
Ω
for input voltages from 1 volt from the positive supply to 20 volts
below the negative supply.
The full and half-wave rectifier shown in Figure 20 operates as
follows: when V
IN
is above ground, R1 is bootstrapped through
the unity gain follower A1 and the loop of amplifier A2. This forces
the inputs of A2 to be equal, thus no current flows through R1 or R2,
and the circuit output tracks the input. When V
IN
is below ground,
the output of A1 is forced to ground. The noninverting input of
amplifier A2 sees the ground level output of A1, therefore, A2 operates as a unity gain inverter. The output at node C is then a full-wave
rectified version of the input. Node B is a buffered half-wave
rectified version of the input. Input voltages up to ±18 volts can
be rectified, depending on the voltage supply used.
Page 14
REV. C
–14–
AD820
R1
100k
AD820
2
3
6
FULL-WAVE
RECTIFIED OUTPUT
HALF-WAVE
RECTIFIED OUTPUT
R2
100k
A
C
B
AD820
0.01F
+V
S
V
IN
3
2
4
7
6
A1
A2
0.01F
+V
S
7
4
A
B
C
Figure 20. Single Supply Half- and Full-Wave
Rectifier
4.5 V Low Dropout, Low Power Reference
The rail-to-rail performance of the AD820 can be used to provide
low dropout performance for low power reference circuits powered
with a single low voltage supply. Figure 21 shows a 4.5 V reference
using the AD820 and the AD680, a low power 2.5 V bandgap
reference. R2 and R3 set up the required gain of 1.8 to develop
the 4.5 V output. R1 and C2 form a low-pass RC filter to reduce
the noise contribution of the AD680.
2
3
4
R2
80k
(20k)
U1
AD680
REF
COMMON
4.5V
OUTPUT
2.5V
OUTPUT
R3
100k
(25k)
C3
10F/25V
3
6
7
2
C1
0.1F
C2
0.1F FILM
U2
AD820
5V
2.5V 10mV
6
R1
100k
4
Figure 21. Single Supply 4.5 V Low Dropout
Reference
With a 1 mA load, this reference maintains the 4.5 V output
with a supply voltage down to 4.7 V. The amplitude of the
recovery transient for a 1 mA to 10 mA step change in load
current is under 20 mV, and settles out in a few microseconds.
Output voltage noise is less than 10 µV rms in a 25 kHz noise
bandwidth.
Low Power Three-Pole Sallen Key Low-Pass Filter
The AD820’s high input impedance makes it a good selection
for active filters. High value resistors can be used to construct
low frequency filters with capacitors much less than 1 µF. The
AD820’s picoamp level input currents contribute minimal dc errors.
Figure 22 shows an example, a 10 Hz three-pole Sallen Key
Filter. The high value used for R1 minimizes interaction with
signal source resistance. Pole placement in this version of the
filter minimizes the Q associated with the two-pole section of
the filter. This eliminates any peaking of the noise contribution
of resistors R1, R2, and R3, thus minimizing the inherent output voltage noise of the filter.
FREQUENCY – Hz
0.1
FILTER GAIN RESPONSE – dB
0
–10
–100
–20
–30
–40
–50
–60
–70
–80
–90
1 10 100 1k
C2
0.022F
V
OUT
0.01F
+V
S
V
IN
0.01F
–V
S
3
2
4
7
6
AD820
R1
243k
C3
0.022F
C1
0.022F
R2
243kR3243k
Figure 22. 10 Hz Sallen Key Low-Pass Filter
Page 15
REV. C
–15–
AD820
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Mini-DIP Package
(N-8)
SEATING
PLANE
0.125 (3.18)
MIN
0.035 0.01
(0.89 0.25)
0.033
(0.84)
NOM
0.018 0.003
(0.46 0.08)
0.165 0.01
(4.19 0.25)
0.18 0.03
(4.57 0.75)
8
14
5
PIN 1
0.10 (2.54)
BSC
0.39 (9.91)
MAX
0.25
(6.35)
0.31
(7.87)
0.011 0.003
(0.28 0.08)
15
0
0.30 (7.62)
REF
SOIC Package
(R-8)
10
0
0.030 (0.76)
0.018 (0.46)
0.020 (0.051) 45
CHAMF
0.098 (0.2482)
0.075 (0.1905)
8
0
0.190 (4.82)
0.170 (4.32)
0.090
(2.29)
0.244 (6.20)
0.228 (5.79)
85
41
PIN 1
0.157 (3.99)
0.150 (3.81)
0.150 (3.81)
0.102 (2.59)
0.094 (2.39)
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0.019 (0.48)
0.014 (0.36)
0.197 (5.01)
0.189 (4.80)
0.050
(1.27)
BSC
Page 16
–16–
C00873–0–1/02(C)
PRINTED IN U.S.A.
Revision History
Location Page
Data Sheet changed from REV. B to REV. C.
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Delete SPECIFICATIONS for AD820A-3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Edits to TYPICAL PERFORMANCE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AD820
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