Datasheet AD8209 Datasheet (ANALOG DEVICES)

High Voltage,

V

FEATURES

±8000 V HBM ESD
AEC-Q100 qualified
EMI filters included
High common-mode voltage range

−2 V to +45 V operating

−24 V to +80 V survival
Buffered output voltage
Gain = 14 V/V
Low-pass filter (single-pole or two-pole)
Wide operating temperature range

8-lead MSOP: −40°C to +125°C

Excellent ac and dc performance

±1 mV voltage offset

−5 ppm/°C typical gain drift

80 dB CMRR minimum dc to 10 kHz

APPLICATIONS

High-side current sensing

Motor controls
Solenoid controls

Power management
Low-side current sensing
Diagnostic protection

Precision Difference Amplifier

AD8209

FUNCTIONAL BLOCK DIAGRAM

A1 A2

S

EMI

FILTER

IN+

IN–

EMI

FILTER

EMI

FILTER

+
–

GND

Figure 1.

+

G = 2G = 7

–

AD8209

OUT

08461-001

GENERAL DESCRIPTION

The AD8209 is a single-supply difference amplifier ideal for
amplifying and low-pass filtering small differential voltages in the
presence of a large common-mode voltage. The input common­mode voltage range extends from −2 V to +45 V at a single +5 V
supply. The AD8209 is qualified per AEC-Q100 specifications. The
amplifier offers enhanced input overvoltage and ESD protection,
and includes EMI filtering.

Automotive applications demand robust, precision components for
improved system control. The AD8209 provides excellent ac and dc

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

performance, minimizing errors in the application. Typical offset
and gain drift in the MSOP package are less than 5 µV/°C and
10 ppm/°C, respectively. The device also delivers a minimum
CMRR of 80 dB from dc to 10 kHz.

The AD8209 features an externally accessible 100 kΩ resistor at
the output of the preamplifier (A1), which can be used for low­pass filtering and for establishing gains other than 14.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

AD8209

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 4

ESD Caution .................................................................................. 4

Pin Configuration and Function Descriptions ............................. 5

Typical Performance Characteristics ............................................. 6

Theory of Operation ...................................................................... 10

REVISION HISTORY

10/09—Revision 0: Initial Version

Applications Information .............................................................. 11

High-Side Current Sensing with a Low-Side Switch ............. 11

High-Rail Current Sensing ....................................................... 11

Low-Side Current Sensing ........................................................ 11

Gain Adjustment ........................................................................ 12

Gain Trim .................................................................................... 12

Low-Pass Filtering ...................................................................... 13

High Line Current Sensing with LPF and Gain Adjustment ...... 14

Outline Dimensions ....................................................................... 15

Ordering Guide .......................................................................... 15

Rev. 0 | Page 2 of 16

AD8209

SPECIFICATIONS

T

= −40°C to +125°C, TA = 25°C, VS = 5 V, RL = 25 k (RL is the output load resistor), unless otherwise noted.

OPR

Table 1.

1

Parameter Test Conditions

SYSTEM GAIN

Initial 14 V/V

Error vs. Temperature 0.075 V ≤ V

Gain Drift T

OPR

VOLTAGE OFFSET

Initial Input Offset (Referred to Input [RTI]) VCM = 0.15 V, TA ±2 mV

Input Offset (RTI) Over Temperature VCM = 0 V, T

Voltage Offset vs. Temperature VCM = 0 V, T

INPUT

Input Impedance

Differential 360 400 440 kΩ
Common Mode 180 200 220 kΩ

VCM (Continuous) −2 +45 V

2

CMRR

V

= −2 V to +45 V, dc 80 100 dB

CM

f = dc to 10 kHz,3 T

PREAMPLIFIER (A1)

Gain 7 V/V

Gain Error 0.05 V ≤ V

Output Voltage Range 0.05 VS − 0.1 V

Output Resistance 97 100 103 kΩ

OUTPUT BUFFER (A2)

Gain 2 V/V

Gain Error 0.075 V ≤ V

Output Voltage Range

Input Bias Current T

4

R

= 25 kΩ, differential Input (V) = 0 V, T

L

50 nA

OPR

Output Resistance RL = 1 kΩ, frequency = dc 2 Ω

DYNAMIC RESPONSE

System Bandwidth VIN = 0.01 V p-p, V

Slew Rate VIN = 0.28 V, V

NOISE

0.1 Hz to 10 Hz 20 μV p-p

Spectral Density, 1 kHz (RTI) 500 nV/√Hz

POWER SUPPLY

Operating Range 4.5 5.5 V

Quiescent Current Typical, TA 1.6 mA

Quiescent Current vs. Temperature V

= 0.1 V dc, VS = 5 V, T

OUT

PSRR VS = 4.5 V to 5.5 V, T

TEMPERATURE RANGE

For Specified Performance at T

1

VCM = input common-mode voltage.

2

Source imbalance < 2 Ω.

3

The AD8209 preamplifier exceeds 80 dB CMRR at 10 kHz. However, because the output is available only by way of the 100 kΩ resistor, even a small amount of pin-to-

pin capacitance between the IN pins and the A1 and A2 pins might couple an input common-mode signal larger than the greatly attenuated preamplifier output. The
effect of pin-to-pin coupling can be neglected in all applications by using a filter capacitor from Pin 3 to GND.

4

The output voltage range of the AD8209 varies depending on the load resistance and temperature. For additional information on this specification, refer to

and .

Figure 13

OPR

≤ (VS − 0.1 V), dc, T

OUT

±0.3 %

OPR

Min Typ Max Unit

0 −20 ppm/°C

±4 mV

OPR

−20 +20 μV/°C

OPR

80 dB

OPR

≤ (VS − 0.1 V), dc, T

OUT

≤ (VS − 0.1 V), dc, T

OUT

= 0.14 V p-p 80 kHz

OUT

= 4 V step 1 V/μs

OUT

OPR

66 80 dB

OPR

−0.3 +0.3 %

OPR

−0.3 +0.3 %

OPR

0.075 VS − 0.1 V

OPR

2.7 mA

−40 +125 °C

Figure 12

Rev. 0 | Page 3 of 16

AD8209

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage 12 V
Continuous Input Voltage (Common Mode) −24 V to +80 V
Differential Input Voltage ±12 V
Reversed Supply Voltage Protection 0.3 V
ESD Human Body Model ±8000 V
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Output Short-Circuit Duration Indefinite
Lead Temperature Range (Soldering 10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 4 of 16

AD8209

G

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

–IN

1

AD8209

2

ND

TOP VIEW

A1

3

(Not to Scale)

A2

4

NC = NO CONNECT

+IN

8
7

V

S

NC

6

OUT

5

08461-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Coordinates
Pin No. Mnemonic X Y Description

1 −IN −322 +563 Inverting Input
2 GND −321 +208 Ground
3 A1 −321 −51 Preamplifier (A1) Output
4 A2 −321 −214 Buffer (A2) Input
5 OUT +321 −388 Buffer (A2) Output
6 NC No Connect
7 VS +322 +363 Supply
8 +IN +322 +561 Noninverting Input

1

2

3

4

8

7

5

08461-003

Figure 3. Metallization Photograph

Rev. 0 | Page 5 of 16

AD8209

–

TYPICAL PERFORMANCE CHARACTERISTICS

T

= −40°C to +125°C, TA = 25°C, VS = 5 V, RL = 25 k (RL is the output load resistor), unless otherwise noted.

OPR

0.70

0.55

0.40

0.25

0.10

(mV)

–0.05

OSI

V

–0.20

–0.35

–0.50

–0.65

–0.80

–40–30 –20–10 0 10 20 30 40 50 60 70 80 90 100110120

TEMPERATURE (°C)

Figure 4. Typical Offset Drift vs. Temperature

8461-004

1500

1250

1000

750

500

250

0

GAIN ERROR (ppm)

–250

–500

–750

–1000

–40–30 –20–10 0 10 20 30 40 50 60 70 80 90 100 110120

TEMPERATURE (°C)

Figure 7. Typical Gain Error vs. Temperature

08461-005

30

25

20

15

10

5

0

GAIN (dB)

–5

–10

–15

–20

1k 10k 100k

FREQUENCY (Hz)

Figure 5. Typical Small-Signal Bandwidth

140
130

+125°C

120

+25°C

110

–40°C

100

90
80

CMRR (dB)

70
60
50
40
30

10 100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 6. Typical CMRR vs. Frequency

1M

0.47

0.42

0.37

0.32

0.27

0.22

0.17

0.12

0.07

TOTAL INPUT BIAS CURRENT (mA)

0.02

–0.03

–2 0 2 4 6 8 1012 1416 18 20 22 24 26 28 30 32 34 36 38 4042 44

08461-022

INPUT COMMON-MODE (V)

08461-006

Figure 8. Total Input Bias Current vs. Common-Mode Voltage,

with +IN and –IN Pins Connected (Shorted)

35

–30

–

4

0

°

C

–25

–20

A2 INPUT BIAS CURRENT (nA)

–15

–10

0

0

0

0

.

08461-012

2

0

.

4

1

.

6

.

8

.

0

U

I

P

N

2

A

2

+

5

°

C

1

+

2

°

5

C

1

1

1

.

2

L

O

T

V

1

.

4

G

A

T

2

.

6

)

(

V

E

2

.

8

2

.

0

.

2

.

4

08461-007

Figure 9. Input Bias Current of A2 vs. Input Voltage and Temperature

Rev. 0 | Page 6 of 16

AD8209

12.0

11.5

11.0

10.5

10.0

9.5

9.0

8.5

8.0

7.5

7.0

6.5

6.0

MAXIMUM OUT PUT SINK CURRENT (mA)

5.5

5.0
–40–200 20406080100120140

TEMPERATURE (°C)

Figure 10. Maximum Output Sink Current vs. Temperature

6.5

6.3

6.0

5.8

5.5

5.3

5.0

4.8

4.5

4.3

MAXIMUM OUT PUT SOURCE CURRENT ( mA)

4.1
–40 –20 0 20 40 60 80 100 120 140

TEMPERATURE (°C)

Figure 11. Maximum Output Source Current vs. Temperature

08461-008

08461-009

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

OUTPUT VOLTAGE RANGE (V)

0.4

0.2

0

0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

0.5

1.5

2.5

3.5

OUTPUT SI NK CURRE NT (mA)

4.5

5.5

6.5

7.5

8.5

9.0

Figure 13. Output Voltage Range from GND vs. Output Sink Current

100mV/DIV

1

500mV/DIV

2

TIME (2µs/DIV)

INPUT

OUTPUT

08461-018

Figure 14. Rise Time

08461-011

5.0

4.6

4.2

3.8

3.4

3.0

2.6

2.2

OUTPUT VOLTAGE RANGE (V)

1.8

1.4

1.0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

OUTPUT SOURCE CURRENT (mA)

Figure 12. Output Voltage Range of A2 vs. Output Source Current

08461-010

Rev. 0 | Page 7 of 16

1

2

100mV/DIV

500mV/DIV

TIME (2µs/DIV)

Figure 15. Fall Time

INPUT

OUTPUT

08461-017

AD8209

INPUT

3

2

OUTPUT

TIME (2µs/DIV)

Figure 16. Differential Overload Recovery, Rising

200mV/DIV

3

2V/DIV

2

200mV/DIV

2V/DIV

INPUT

OUTPUT

2

3

08461-014

TIME (20µs/DIV)

2V/DIV

0.01%/DIV

08461-016

Figure 19. Settling Time, Falling

500

+125°C
+25°C
–40°C

400

300

COUNT

200

100

TIME (2µs/DIV)

Figure 17. Differential Overload Recovery, Falling

2V/DIV

2

0.01%/DIV

3

TIME (20µ s/ DI V )

Figure 18. Settling Time, Rising

08461-013

0

–4 –3 –2 –1 0 1 2 3 4

VOS (mV)

08461-019

Figure 20. Offset Distribution

180

150

120

90

COUNT

60

30

08461-015

0

–20 –15 –10 –5 5 10 15 200

OFFSET DRIFT (µV/°C)

08461-020

Figure 21. Offset Drift Distribution

Rev. 0 | Page 8 of 16

AD8209

1400

1200

1000

800

600

COUNT

400

200

0

–20 –15 –10 –5 0

GAIN DRIFT (ppm/°C)

5 101520

8461-021

Figure 22. Gain Drift Distribution

Rev. 0 | Page 9 of 16

AD8209

V

THEORY OF OPERATION

The AD8209 is a single-supply difference amplifier typically used
to amplify a small differential voltage in the presence of rapidly
changing, high common-mode voltages.

The AD8209 consists of two amplifiers (A1 and A2), a resistor
network, a small voltage reference, and a bias circuit (not shown);
see Figure 23.

The set of input attenuators preceding A1 consist of R
R

, which feature a combined series resistance of approximately

C

, RB, and

A

400 k ± 20%. The purpose of these resistors is to attenuate the
input voltage to match the input voltage range of A1. This balanced
resistor network attenuates the common-mode signal by a ratio
of 1/14. The A1 amplifier inputs are held within the power supply
range, even as Pin 1 and Pin 8 exceed the supply or fall below the
common (ground). A reference voltage of 350 mV biases the
attenuator above ground, allowing Amplifier A1 to operate in
the presence of negative common-mode voltages.

The input resistor network also attenuates normal (differential)
mode voltages. Therefore, A1 features a gain of 97 V/V to provide
a total system gain, from ±IN to the output of A1, equal to 7 V/V,
as shown in the following equation:

Gain (A1) = 1/14 (V/V) × 97 (V/V) = 7 V/V

A precision trimmed, 100 k resistor is placed in series with the
output of Amplifier A1. The user has access to this resistor via
an external pin (A1). A low-pass filter can be easily implemented

by connecting A1 to A2 and placing a capacitor to ground (see
Figure 32).

The value of R

and RF2 is 10 k, providing a gain of 2 V/V for

F1

Amplifier A2. When connecting Pin A1 and Pin A2 together, the
AD8209 provides a total system gain equal to

Total Gain of (A1 + A2) (V/V) = 7 (V/V) × 2 (V/V) = 14 V/V

at the output of A2 (the OUT pin).

The ratios of R

, RB, RC, and RF are trimmed to a high level of

A

precision, allowing a typical CMRR value that exceeds 80 dB. This
performance is accomplished by laser trimming the resistor ratio
matching to better than 0.01%.

–IN

+IN

S

R

R

A

A

+

A1

R

B

R

G

R

CRF

350mV

GND

–

R

B

R

C

R

Figure 23. Simplified Schematic

A1 A2

R

FILTER

F

+

A2

–

R

M

OUT

R

F1

R

F2

08461-025

Rev. 0 | Page 10 of 16

AD8209

V

V

APPLICATIONS INFORMATION

HIGH-SIDE CURRENT SENSING WITH A LOW-SIDE SWITCH

In load control configurations for high-side current sensing with a
low-side switch, the PWM-controlled switch is ground referenced.
An inductive load (solenoid) connects to a power supply/battery.
A resistive shunt is placed between the switch and the load (see
Figure 24). An advantage of placing the shunt on the high side
is that the entire current, including the recirculation current, is
monitored because the shunt remains in the loop when the switch
is off. In addition, shorts to ground can be detected with the shunt
on the high side, enhancing the diagnostics of the control loop. In
this circuit configuration, when the switch is closed, the common­mode voltage moves down to near the negative rail. When the
switch is opened, the voltage reversal across the inductive load
causes the common-mode voltage to be held one diode drop
above the battery by the clamp diode.

5

CLAMP

DIODE

BATTERY

NC = NO CONNECT

+
–

In cases where a high-side switch is used for PWM control of the
load current in an application, the AD8209 can be used as shown
in Figure 25. The recirculation current through the freewheeling
diode (clamp diode) is monitored through the shunt resistor. In
this configuration, the common-mode voltage in the application
drops below GND when the FET is switched off. The AD8209
operates down to −2 V, providing an accurate current measurement.

BATTERY

+
–

CLAMP

DIODE

INDUCTIVE

LOAD

SHUNT

SWITCH

+INA1+V

AD8209

GND

–IN

Figure 24. Low-Side Switch

5

SWITCH

+INA1+V

SHUNT

INDUCTIVE

LOAD

–IN

AD8209

GND

OUTPUT

OUT

NC

S

A2

C

F

OUTPUT

NC

OUT

S

A2

C

F

08461-026

HIGH-RAIL CURRENT SENSING

In the high-rail current-sensing configuration, the shunt resistor is
referenced to the battery. High voltage is present at the inputs of
the current-sense amplifier. When the shunt is battery referenced,
the AD8209 produces a linear ground-referenced analog output.
Additionally, the AD8214 can be used to provide an overcurrent
detection signal in as little as 100 ns (see Figure 26). This feature is
useful in high current systems where fast shutdown in overcurrent
conditions is essential.

OVERCURRENT

DETECTI ON (<100ns)

8765

REG

–INNCGND

+INV

V

S

1234

CLAMP

DIODE

SHUNT

+IN

8

V

S

7

NC

6

OUT

5

INDUCTIVE

5V

LOAD

SWITCH

+

BATTERY

–

OUT

AD8214

NC

–IN

1

GND

2

AD8209

A1

3

A2

C

4

F

Figure 26. Battery-Referenced Shunt Resistor

LOW-SIDE CURRENT SENSING

In systems where low-side current sensing is preferable, the
AD8209 provides a simple, high accuracy, integrated solution. In
this configuration, the AD8209 rejects ground noise and offers high
input to output linearity, regardless of the differential input voltage.

INDUCTIVE

CLAMP
DIODE

SWITCH

BATTERY

NC = NO CONNECT

Figure 27. Ground-Referenced Shunt Resistor

LOAD

SHUNT

+INA1+V

AD8209

–IN

5V

GND

OUTPUT

NC

OUT

S

A2

C

F

08461-029

8461-028

NC = NO CONNECT

08461-027

Figure 25. High-Side Switch

Rev. 0 | Page 11 of 16

AD8209

V

V

V

V

4 mA to 20 mA Current Loop Receiver

The AD8209 can also be used in low current-sensing applica­tions, such as the 4 mA to 20 mA current loop receiver shown
in Figure 28. In such applications, the relatively large shunt
resistor may degrade the common-mode rejection. Adding a
resistor of equal value on the low impedance side of the input
corrects this error.

5

10Ω

+

BATTERY

–

10Ω

1%

1%

+INA1+V

AD8209

–IN

GND

NC

S

OUTPUT

OUT

A2

used should be equal to 100 kΩ minus the parallel sum of R
and 100 kΩ. For example, with R

= 100 kΩ (yielding a composite

EXT

gain of 7 V/V), the optional offset nulling resistor is 50 kΩ.

Gains Greater than 14

Connecting a resistor from the output of the buffer amplifier to
its noninverting input, as shown in Figure 30, increases the gain.
The gain is now multiplied by the factor

/(R

R

EXT

For example, it is doubled for R

− 100 kΩ)

EXT

= 200 kΩ. Overall gains as

EXT

high as 50 are achievable in this way. Note that the accuracy of
the gain becomes critically dependent on the resistor value at
high gains. In addition, the effective input offset voltage at Pin 1
and Pin 8 (which is about six times the actual offset of A1) limits
the use of the part in high gain, dc-coupled applications.

5

EXT

C

F

NC = NO CONNECT

08461-030

Figure 28. 4 mA to 20 mA Current Loop Receiver

GAIN ADJUSTMENT

The default gain of the preamplifier and buffer are 7 V/V and
2 V/V, respectively, resulting in a composite gain of 14 V/V. With
the addition of external resistor(s) or trimmer(s), the gain can
be lowered, raised, or finely calibrated.

Gains Less than 14

Because the preamplifier has an output resistance of 100 kΩ, an
external resistor connected from Pin 3 and Pin 4 to GND decreases
the gain by the following factor (see Figure 29):

/(100 kΩ + R

R

EXT

V

DIFF

V

CM

+
–

+
–

EXT

+INA1+V

AD8209

GND

–IN

)

5

OUTPUT

NC

OUT

S

GAIN =

R

A2

R

EXT

EXT

R

EXT

= 100kΩ

14R

+ 100kΩ

EXT

GAIN

14 – GAIN

OUTPUT

+INA1+V

+

V

DIFF

–

–IN

+

V

CM

–

NC = NO CONNECT

Figure 30. Adjusting for Gains Greater than 14

AD8209

GND

OUT

NC

S

GAIN =

R

EXT

R

A2

EXT

14R

R

EXT

= 100kΩ

EXT

– 100kΩ

GAIN

GAIN – 14

08461-032

GAIN TRIM

Figure 31 shows a method for incremental gain trimming by
using a trim potentiometer and an external resistor, R

The following approximation is useful for small gain ranges:

G ≈ (10 MΩ ÷ R

EXT

)%

For example, using this equation, the adjustment range is ±2%
for R

= 5 MΩ and ±10% for R

EXT

+INA1+V

+

V

DIFF

–

AD8209

5

S

= 1 MΩ.

EXT

OUT

NC

OUTPUT

EXT

.

NC = NO CONNECT

08461-031

Figure 29. Adjusting for Gains Less than 14

The overall bandwidth is unaffected by changes in gain by using
this method, although there may be a small offset voltage due to

+

V

CM

–

GND

–IN

A2

GAIN TRIM
20kΩ MIN

R

EXT

the imbalance in source resistances at the input to the buffer. In
many cases, this can be ignored, but if desired, the offset voltage can
be nulled by inserting a resistor in series with Pin 4. The resistor

NC = NO CONNECT

Figure 31. Incremental Gain Trimming

Rev. 0 | Page 12 of 16

08461-033

AD8209

V

V

Internal Signal Overload Considerations

When configuring the gain for values other than 14, the maximum
input voltage with respect to the supply voltage and ground must
be considered because either the preamplifier or the output buffer
reaches its full-scale output (V
input voltages. The input of the AD8209 is limited to (V

− 0.1 V) with large differential

S

− 0.1) ÷

S

7 for overall gains of ≤7 because the preamplifier, with its fixed
gain of 7 V/V, reaches its full-scale output before the output
buffer. For gains greater than 7, the swing at the buffer output
reaches its full scale first and then limits the AD8209 input to
(V

− 0.1) ÷ G, where G is the overall gain.

S

LOW-PASS FILTERING

In many transducer applications, it is necessary to filter the signal
to remove spurious high frequency components, including noise,
or to extract the mean value of a fluctuating signal with a peak­to-average ratio (PAR) greater than unity. For example, a full-wave
rectified sinusoid has a PAR of 1.57, a raised cosine has a PAR
of 2, and a half-wave sinusoid has a PAR of 3.14. Signals with
large spikes may have PARs of 10 or more.

When implementing a filter, the PAR should be considered so
that the output of the AD8209 preamplifier (A1) does not clip
before A2; otherwise, the nonlinearity would be averaged and
appear as an error at the output. To avoid this error, both amplifiers
should clip at the same time. This condition is achieved when the
PAR is no greater than the gain of the second amplifier (2 for
the default configuration). For example, if a PAR of 5 is expected,
the gain of A2 should be increased to 5.

Low-pass filters can be implemented in several ways by using
the features provided by the AD8209. In the simplest case, a
single-pole filter (20 dB/decade) is formed when the output
of A1 is connected to the input of A2 via the internal 100 kΩ
resistor by tying Pin 3 to Pin 4 and adding a capacitor from this
node to ground, as shown in Figure 32. If a resistor is added
across the capacitor to lower the gain, the corner frequency
increases; therefore, gain should be calculated using the parallel
sum of the resistor and 100 kΩ.

5

OUTPUT

+INA1+V

+

V

DIFF

–

+

V

CM

–

AD8209

–IN

GND

OUT

NC

S

1

f

=

2πC10

5

A2

C

C

C IN FARADS

F

If the gain is raised using a resistor, as shown in Figure 30, the
corner frequency is lowered by the same factor as the gain is raised.
Therefore, using a resistor of 200 kΩ (for which the gain would
be doubled), results in a corner frequency scaled to 0.796 Hz µF
(0.039 µF for a 20 Hz corner frequency).

5

OUTPUT

+INA1+V

+

V

DIFF

–

+

V

CM

–

NC = NO CONNECT

AD8209

–IN

255kΩ

Figure 33. Two-Pole, Low-Pass Filter

GND

OUT

NC

S

C

f

(Hz) = 1/C(µF)

A2

C

C

08461-035

A two-pole filter with a roll-off of 40 dB/decade can be
implemented using the connections shown in Figure 33. This
configuration is a Sallen-Key form based on a ×2 amplifier. It is
useful to remember that a two-pole filter with a corner frequency
of f

and a single-pole filter with a corner frequency of f1 have

2

the same attenuation, that is, 40 log (f

), as shown in Figure 34.

2/f1

Using the standard resistor value shown in Figure 33 and capacitors
of equal values, the corner frequency is conveniently scaled to
1 Hz µF (0.05 µF for a 20 Hz corner frequency). A maximal flat
response occurs when the resistor is lowered to 196 kΩ, scaling
the corner frequency to 1.145 Hz µF. The output offset is raised
by approximately 5 mV (equivalent to 250 µV at the input pins).

FREQUENCY

40dB/DECADE

20dB/DECADE

ATTENUATION

40log (f2/f1)

A 1-POLE FILTER, CORNER f1, AND
A 2-POLE FILTER, CORNER f
THE SAME ATTENUATION –40log (f
AT FREQUENCY f

2

f

1

Figure 34. Comparative Responses of Single-Pole and Two-Pole Low-Pass Filters

, HAVE

2

)

2

/f

1

2/f1

2

f

f

2

/f

2

1

08461-036

NC = NO CONNECT

08461-034

Figure 32. Single-Pole, Low-Pass Filter Using the Internal 100 kΩ Resistor

Rev. 0 | Page 13 of 16

AD8209

V

HIGH LINE CURRENT SENSING WITH LPF AND GAIN ADJUSTMENT

The circuit shown in Figure 35 is similar to Figure 24, but
includes gain adjustment and low-pass filtering.

5V

CLAMP

BATTERY

NC = NO CONNECT

+
–

A power device that is either on or off controls the current in
the load. The average current is proportional to the duty cycle
of the input pulse and is sensed by a small-value resistor. The
average differential voltage across the shunt is typically 100 mV,
although its peak value is higher by an amount that depends on the
inductance of the load and the control frequency. The common­mode voltage, on the other hand, extends from roughly 1 V above
ground for the on condition to about 1.5 V above the battery
voltage in the off condition. The conduction of the clamping

INDUCTIVE

DIODE

LOAD

SHUNT

SWITCH

+INA1+V

AD8209

–IN

GND

OUT

NC

S

A2

V
NULL

C

Figure 35. High Line Current-Sensor Interface;

Gain = 40 V/V, Single-Pole, Low-Pass Filter

OUTPUT
4V/AMP

133kΩ

20kΩ

OS/IB

5% CALIBRATION RANGE

f

(Hz) = 0.767Hz/C(µ F )

C

(0.22µF FOR

f

= 3.6Hz)

C

08461-037

diode regulates the common-mode potential applied to the device.
For example, a battery spike of 20 V may result in an applied
common-mode potential of 21.5 V to the input of the devices.

To produce a full-scale output of 4 V, a gain of 40 V/V is used,
adjustable by ±5% to absorb the tolerance in the shunt. There is
sufficient headroom to allow 10% overrange (to 4.4 V). The
roughly triangular voltage across the sense resistor is averaged
by a single-pole, low-pass filter that is set with a corner frequency
of 3.6 Hz, which provides about 30 dB of attenuation at 100 Hz.
A higher rate of attenuation can be obtained by using a two-pole
filter with a corner frequency of 20 Hz, as shown in Figure 36.
Although this circuit uses two separate capacitors, the total capaci­tance is less than half of what is needed for the single-pole filter.

5

CLAMP

BATTERY

NC = NO CONNE CT

+
–

INDUCTIVE

DIODE

LOAD

SHUNT

SWITCH

Figure 36. Two-Pole Low-Pass Filter

+INA1+V

AD8209

–IN

GND

OUTPUT

NC

OUT

S

A2

93kΩ

f

C

(0.05µF FOR

C

(Hz) =1/C(µF)

C

432kΩ

50kΩ

f

C

= 20Hz)

08461-038

Rev. 0 | Page 14 of 16

AD8209

OUTLINE DIMENSIONS

3.20

3.00

2.80

8

5

3.20

3.00

2.80

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

1

0.65 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 37. 8-Lead Mini Small Outline Package [MSOP]

5.15

4.90

4.65

4

15° MAX

6°
0°

0.23

0.09

0.40

0.25

1.10 MAX

(RM-8)

Dimensions shown in millimeters

0.80

0.55

0.40

100709-B

ORDERING GUIDE

Model Temperature Package Package Description Package Option Branding

AD8209WBRMZ1 −40°C to +125°C 8-Lead Mini Small Outline Package (MSOP) RM-8 Y26
AD8209WBRMZ-R71 −40°C to +125°C 8-Lead Mini Small Outline Package (MSOP) RM-8 Y26
AD8209WBRMZ-RL1 −40°C to +125°C 8-Lead Mini Small Outline Package (MSOP) RM-8 Y26

1

Z = RoHS Compliant Part.

Rev. 0 | Page 15 of 16

AD8209

NOTES

©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08461-0-10/09(0)

Rev. 0 | Page 16 of 16