Page 1
High Common-Mode Voltage,
FEATURES
High common-mode voltage range
−6 V to +30 V at a 5 V supply voltage
Operating temperature range: −40°C to +125°C
Supply voltage range: 3.5 V to 12 V
Low-pass filter (1-pole or 2-pole)
Excellent ac and dc performance
±1 mV voltage offset (8-lead SOIC)
±1 ppm/°C typical gain drift
80 dB CMRR minimum dc to 10 kHz
APPLICATIONS
Transmission control
Diesel injection control
Engine management
Adaptive suspension control
Vehicle dynamics control
GENERAL DESCRIPTION
The AD8203 is a single-supply difference amplifier for amplifying and low-pass filtering small differential voltages in the
presence of a large common-mode voltage (CMV). The input
CMV range extends from −6 V to +30 V at a typical supply
voltage of 5 V.
Single-Supply Difference Amplifier
AD8203
FUNCTIONAL BLOCK DIAGRAMS
+V
A2
3
INDUCTIVE
LOAD
+INA1+V
–IN
746
G = ×2
+IN
A2
–IN
5V
NC
S
AD8203
GND
S
AD8203
5
OUT
10kΩ
10kΩ
2
GND
OUT
A2
05013-001
OUTPUT
8
+IN
1
–IN
BATTERY
NC A1
200kΩ200kΩ
NC = NO CONNECT
Figure 1. Functional Block Diagram
CLAMP
DIODE
14V
G = ×7
+IN
A1
–IN
4-TERM
SHUNT
POWER
DEVICE
100kΩ
The AD8203 is available in die and packaged form. The MSOP
and SOIC packages are specified over a wide temperature range,
from −40°C to +125°C, while the die is specified over a wider
temperature range, from −40°C to +150°C, making the AD8203
well-suited for use in many automotive platforms.
Automotive platforms demand precision components for better
system control. The AD8203 provides excellent ac and dc
performance keeping errors to a minimum in the user’s system.
Typical offset and gain drift in the SOIC package are 0.3 µV/°C and
1 ppm/°C, respectively. Typical offset and gain drift in the MSOP
package are 2 V/°C and 1 ppm/°C, respectively. The device also
delivers a minimum CMRR of 80 dB from dc to 10 kHz.
The AD8203 features an externally accessible 100 kΩ resistor at
the output of the Preamp A1, which can be used for low-pass
filter applications and for establishing gains other than 14.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
COMMON
NC = NO CONNECT
Figure 2. High Line Current Sensor
POWER
BATTERY
DEVICE
14V
CLAMP
DIODE
COMMON NC = NO CONNECT
4-TERM
SHUNT
INDUCTIVE
LOAD
+INA1+V
AD8203
–IN
5V
GND
OUT
NC
S
A2
Figure 3. Low Line Current Sensor
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
OUTPUT
05013-002
05013-003
Page 2
AD8203
TABLE OF CONTENTS
Features .............................................................................................. 1
Current Sensing .......................................................................... 14
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
Specifications..................................................................................... 3
Single Supply ................................................................................. 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 12
Applications..................................................................................... 14
REVISION HISTORY
10/05—Rev. A to Rev. B
Added SOIC Package.........................................................Universal
Replaced Figure 23 ........................................................................... 8
Added Figure 24 to Figure 29.......................................................... 9
Changes to Theory of Operation Section ................................... 12
Added Figure 41.............................................................................. 12
Updated Outline Dimensions....................................................... 17
Changes to Ordering Guide.......................................................... 17
Gain Adjustment........................................................................ 14
Gain Trim.................................................................................... 15
Low-Pass Filtering ...................................................................... 15
High Line Current Sensing with LPF and
Gain Adjustment........................................................................ 16
Driving Charge Redistribution ADCs..................................... 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
2/05—Rev. 0 to Rev. A
Changes to Specifications Table...................................................... 3
Changes to Caption on Figure 6 and Figure 8.............................. 6
Changes to Figure 12........................................................................ 7
Added Figure 14 to Figure 23.......................................................... 7
Changes to Figure 26 and Figure 27............................................. 10
Changes to Figure 29...................................................................... 11
Changes to Figure 32 and Figure 33............................................. 12
Changes to Ordering Guide.......................................................... 13
10/04—Revision 0: Initial Version
Rev. B | Page 2 of 20
Page 3
AD8203
SPECIFICATIONS
SINGLE SUPPLY
TA = operating temperature range, VS = 5 V, unless otherwise noted.
Table 1.
AD8203 SOIC AD8203 MSOP AD8203 Die
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit
SYSTEM GAIN
Initial 14 14 14 V/V
Error 0.02 ≤ V
vs. Temperature 1 20 1 25 1 30 ppm/°C
VOLTAGE OFFSET
Input Offset (RTI) VCM = 0.15 V; 25°C −1 +1 −2 +2 −1 +1 mV
vs. Temperature −40°C to +125°C −10 +0.3 +10 −20 +2 +20 −10 +0.3 +10 μV/°C
−40°C to +150°C −15 +5 +15 μV/°C
INPUT
Input Impedance
Differential 260 320 380 260 320 380 260 320 380 kΩ
Common Mode 130 160 190 130 160 190 130 160 190 kΩ
CMV Continuous −6 +30 −6 +30 −6 +30 V
1
CMRR
VCM = −6 V to +30 V
f = dc 82 82 82 dB
f = 1 kHz 82 82 82 dB
f = 10 kHz
PREAMPLIFIER
Gain 7 7 7 V/V
Gain Error −0.3 +0.3 −0.3 +0.3 −0.3 +0.3 %
Output Voltage Range 0.02 4.8 0.02 4.8 0.02 4.8 V
Output Resistance 97 100 103 97 100 103 97 100 103 kΩ
OUTPUT BUFFER
Gain 2 2 2 V/V
Gain Error 0.02 ≤ V
Output Voltage Range 0.02 4.8 0.02 4.8 0.02 4.8 V
Input Bias Current 40 40 40 nA
Output Resistance 2 2 2 Ω
DYNAMIC RESPONSE
System Bandwidth VIN = 0.01 V p-p, V
Slew Rate VIN = 0.28 V, V
NOISE
0.1 Hz to 10 Hz 10 10 10 μV p-p
Spectral Density, 1 kHz (RTI) 300 300 300 nV/√Hz
POWER SUPPLY
Operating Range 3.5 12 3.5 12 3.5 12 V
Quiescent Current vs.
VO = 0.1 V dc 0.25 1.0 0.25 1.0 0.25 1.0 mA
Temperature
PSRR VS = 3.5 V to 12 V 75 83 75 83 75 83 dB
TEMPERATURE RANGE
For Specified Performance −40 +125 −40 +125 −40 +150 °C
1
Source imbalance <2 Ω.
2
The AD8203 preamplifier exceeds 80 dB CMRR at 10 kHz. However, since the signal is available only by way of a 100 kΩ resistor, even the small amount of pin-to-pin
capacitance between Pin 1, Pin 8 and Pin 3, Pin 4 may couple an input common-mode signal larger than the greatly attenuated preamplifier output. The effect of pinto-pin coupling may be neglected in all applications by using filter capacitors at Node 3.
≤ 4.8 V dc @ 25°C −0.3 +0.3 −0.3 +0.3 −0.3 +0.3 %
OUT
2
≤ 4.8 V dc −0.3 +0.3 −0.3 +0.3 −0.3 +0.3 %
OUT
= 0.14 V p-p 40 60 40 60 40 60 kHz
OUT
= 4 V step 0.33 0.33 0.33 V/μs
OUT
80 80 80 dB
Rev. B | Page 3 of 20
Page 4
AD8203
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage 12.5 V
Transient Input Voltage (400 ms) 44 V
Continuous Input Voltage (Common Mode) 35 V
Reversed Supply Voltage Protection 0.3 V
Operating Temperature Range
Die −40°C to +150°C
SOIC −40°C to +125°C
MSOP −40°C to +125°C
Storage Temperature −65°C to +150°C
Output Short-Circuit Duration Indefinite
Lead Temperature Range (Soldering 10 sec) 300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 4 of 20
Page 5
AD8203
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
–IN
GND
AD8203
2
A1
3
TOP VIEW
(Not to Scale)
A2
4
NC = NO CONNECT
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic X Y
1 −IN −205.2
−409.0
2 GND −244.6 −413.0
3 A1 +229.4 −413.0
4 A2 +410.0 −308.6
5 OUT +410.0 +272.4
6 NC NA NA
7 +V +121.0 S+417.0
8 +IN −409.0 +205.2
8
7
6
5
1048μm
+IN
+V
NC
OUT
S
+IN
–IN
05013-004
1036μm
+V
S
OUT
A2
A1GND
Figure 5. Metallization Photograph
05013-005
Rev. B | Page 5 of 20
Page 6
AD8203
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, V = 5 V, V = 0 V, R
A S CM L
90
80
70
60
50
40
PSRR (dB)
30
20
10
0
10 100 1k 10k 100k
Figure 6. Power Supply Rejection Ratio vs. Frequency
for Common-Mode Range −6 V to +30 V
= 10 kΩ, unless otherwise noted.
FREQUENCY (Hz)
05013-006
0
–5
–10
–15
–20
COMMON-MODE VOLTAGE (V)
–25
–30
354876 9 10 11 12
POWER SUPPLY (V)
–55°C
–40°C
+25°C
+125°C
+150°C
Figure 9. Negative Common-Mode Voltage vs. Voltage Supply
05013-009
25
20
15
10
OUTPUT (dB)
5
0
100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 7. Bandwidth
100
95
90
85
80
75
CMRR (dB)
70
65
60
55
50
10 100 1k 10k 100k
FREQUENCY (Hz)
Figure 8. Common-Mode Rejection Ratio vs. Frequency
for Common-Mode Range −6 V to +30 V
05013-007
05013-008
40
35
+25°C
30
–55°C
25
+150°C
20
COMMON-MODE VOLTAGE (V)
15
+125°C
–40°C
10
354876 9 10 11 12
POWER SUPPLY (V)
Figure 10. Positive Common-Mode Voltage vs. Voltage Supply
5.0
4.0
3.0
2.0
OUTPUT VOLTAGE (dB)
1.0
0
10 100 1k 10k
LOAD RESISTANCE (Ω)
Figure 11. Output Swing vs. Load Resistance
05013-010
05013-011
Rev. B | Page 6 of 20
Page 7
AD8203
0
–10
–20
–30
–40
–50
OUTPUT MINUS SUPPLY (mV)
–60
–70
354876 9 10 11 1312
NO LOAD
10kΩ LOAD
SUPPLY VOLTAGE (V)
05013-012
40
35
30
25
20
HITS
15
10
–6V TO +30V COMMON MODE
TEMPERATURE = 25°C
5
0
–80
–72
–64
–56
–48
–40
–32
–8
–24
–16
CMRR (μV/V)
0
8
162432404856647280
05013-051
Figure 12. Swing Minus Supply vs. Supply Voltage
OUTPUT
4
3
CH3 100mVΩ 1.0VΩ M 20μs 2.5MS/s 400NS/PT
CH4
INPUT
A CH3 260mV
Figure 13. Pulse Response
1000
800
600
400
200
(μV)
0
OS
V
–200
–400
–600
–800
–1000
–10 0–5 15105202530
Figure 14. V
–40°C
COMMON-MODE VOLTAGE (V)
vs. Common-Mode Voltage
OS
+25°C
+85°C
+125°C
05013-013
05013-052
35
Figure 15. CMRR Distribution, Temperature = 25°C
7
6
5
4
HITS
3
2
1
0
–30
–28
–26
–24
–22
–20
–18
–16
–8
–14
–10
–12
VOS DRIFT (μV/°C)
V
SUPPLY
TEMPERATURE RANGE =
+25°C TO –40°C
2
6
0
4
–6
–2
–4
8
1014182226
Figure 16. Offset Drift Distribution, MSOP,
Temperature Range = +25°C to −40°C
8
V
= 5V
SUPPLY
TEMPERATURE RANGE =
7
25°C TO 85°C
6
5
4
HITS
3
2
1
0
–30
–26
–22
–18
–14
–20
–16
–10
–12
VOS DRIFT (μV/°C)
–28
–24
2
6
0
8
4
–6
–2
–8
–4
1014182226
Figure 17. Offset Drift Distribution, MSOP,
Temperature Range = 25°C to 85°C
= 5V
12
12
05013-025
30
28
24
20
16
05013-026
30
28
24
20
16
Rev. B | Page 7 of 20
Page 8
AD8203
9
8
7
6
5
HITS
4
3
2
1
0
–30
Figure 18. V
V
= 5V
SUPPLY
TEMPERATURE RANGE =
25°C TO 125°C
2
6
0
8
4
–6
–26
–22
–18
–28
–24
–20
–16
Distribution, MSOP, Temperature Range = 25°C to 125°C Distribution, MSOP, Temperature = −40°C
OS OS
–14
–10
–12
VOS DRIFT (μV/°C)
–4
–2
–8
1014182226
20
16
12
05013-027
30
28
24
8
7
6
5
4
HITS
3
2
1
0
–2200
Figure 21. V
–2000
–1800
–1600
–1400
–1200
–1000
–800
PACKAGE = MSOP @–40°C
0
200
–200
VOS (μV)
400
–600
–400
600
800
1000
1200
1400
1600
1800
2000
05013-030
2200
10
9
8
7
6
5
HITS
4
3
2
1
0
14
12
10
8
HITS
6
–2200
–2000
PACKAGE = MSOP @ 25°C
0
200
400
–400
–800
–600
–1600
–1800
–1000
–1400
–1200
Distribution, MSOP, Temperature = 25°C
OS
–200
VOS (μV)
600
PACKAGE = MSOP @ 125°C
800
1000
1200
1400
1600
1800
2000
2200
05013-028
8
7
6
5
4
HITS
3
2
1
0
7
6
5
4
HITS
3
TEMPERATURE = 25°C
0
0.02
0.06
0.10
0.14
0.18
0.22
0.04
0.08
0.12
0.16
ERROR (%)
0.20
0.24
0.26
0.28
05013-031
0.30
Figure 22. MSOP Gain Accuracy, Temperature = 25°C Figure 19. V
TEMPERATURE = 125°C
4
2
0
–2200
–2000
Figure 20. V
0
200
800
400
–400
–800
–600
–1600
–1800
–1000
–1400
–1200
Distribution, MSOP, Temperature = 125°C
OS
–200
VOS (μV)
600
1000
1200
1400
1600
1800
2000
05013-029
2200
Rev. B | Page 8 of 20
2
1
0
0
0.02
0.06
0.10
0.14
0.18
0.04
0.08
0.12
ERROR (%)
0.16
0.20
0.22
0.24
Figure 23. MSOP Gain Accuracy, Temperature = 125°C
0.26
0.28
05013-032
0.30
Page 9
AD8203
7
6
5
4
HITS
3
2
1
0
0
0.04
0.06
0.08
0.10
0.02
TEMPERATURE = –40°C
0.12
0.16
0.14
ERROR (%)
0.18
0.20
0.22
Figure 24. MSOP Gain Accuracy, Temperature = −40°C
12
10
HITS
8
6
4
PACKAGE = MSOP
V
= 5V
SUPPLY
TEMPERATURE RANGE = +25°C TO –40°C
0.24
0.26
0.28
05013-033
0.30
18
PACKAGE = MSOP
V
= 5V
SUPPLY
16
TEMPERATURE RANGE =
25°C TO 125°C
14
12
10
HITS
8
6
4
2
0
–9
–8–7–6–5–4–3–2
Figure 27. Gain Drift Distribution, MSOP,
Temperature Range = 25°C to 125°C
14
PACKAGE = SOIC @ 25°C
12
10
8
HITS
6
4
012345678
–1
GAIN DRIFT (ppm/°C)
9
05013-038
2
0
–9
–8–7–6–5–4–3–2
Figure 25. Gain Drift Distribution,
Temperature Range = +25°C to −40°C
12
PACKAGE = MSOP
V
= 5V
SUPPLY
TEMPERATURE RANGE =
10
25°C TO 85°C
8
6
HITS
4
2
0
–9
–8–7–6–5–4–3–2
Figure 26. Gain Drift Distribution, MSOP,
Temperature Range = 25°C to 85°C
012345678
–1
GAIN DRIFT (ppm/°C)
012345678
–1
GAIN DRIFT (ppm/°C)
2
1600
1600
1800
1800
05013-039
2000
05013-040
2000
05013-036
9
05013-037
9
0
–2000
–1800
–1600
–1400
–1200
Figure 28. V
9
PACKAGE = SOIC @ 125°C
8
7
6
5
HITS
4
3
2
1
0
–2000
Figure 29. V
–1800
–1600
–1400
–1200
OS
OS
0
200
400
600
–1000
–800
–600
–400
–200
VOS (μV)
800
1000
1200
1400
Distribution, SOIC, Temperature = 25°C
0
200
400
600
–1000
–800
–600
–400
–200
VOS (μV)
800
1000
1200
1400
Distribution, SOIC, Temperature = 125°C
Rev. B | Page 9 of 20
Page 10
AD8203
14
PACKAGE = SOIC @ –40°C
12
6
PACKAGE = SOIC
V
= 5V
SUPPLY
TEMPERATURE RANGE = 25°C TO 125°C
5
10
8
HITS
6
4
2
1600
05013-041
1800
2000
0
–2000
–1800
–1600
Figure 30. V Figure 33. Offset Drift Distribution, SOIC,
–800
–1400
–1200
–1000
Distribution, SOIC, Temperature = −40°C
OS
–600
–400
–200
VOS (μV)
0
200
400
600
800
1000
1200
1400
HITS
4
3
2
1
0
–9.0
–7.5
–10.5
–6.0
VOS DRIFT (mV/°C)
–15.0
–13.5
–12.0
0
1.5
3.0
–4.5
–3.0
–1.5
4.5
Temperature Range = +25°C to 125°C
6
PACKAGE = SOIC
V
= 5V
SUPPLY
TEMPERATURE RANGE = +25°C TO –40°C
5
4
3
HITS
2
1
0
–9.0
–7.5
–6.0
–4.5
–3.0
–15.0
–13.5
–12.0
–10.5
–1.5
VOS DRIFT (μV/°C)
Figure 31. Offset Drift Distribution, SOIC,
0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
13.5
05013-042
15.0
9
TEMPERATURE = 25°C
8
7
6
5
HITS
4
3
2
1
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
0.11
0.12
0.13
ERROR (%)
0.14
0.15
0.16
0.17
0.18
0.19
Figure 34. Gain Accuracy, SOIC, Temperature = 25°C
Temperature Range = +25°C to −40°C
6
PACKAGE = SOIC
V
= 5V
SUPPLY
TEMPERATURE RANGE = 25°C TO 85°C
5
4
3
HITS
2
1
0
–9.0
–7.5
–6.0
–4.5
–15.0
–13.5
–12.0
–10.5
–3.0
VOS DRIFT (μV/°C)
Figure 32. Offset Drift Distribution, SOIC,
0
1.5
3.0
4.5
6.0
7.5
–1.5
9.0
10.5
12.0
13.5
05013-043
15.0
9
TEMPERATURE = 125°C
8
7
6
5
HITS
4
3
2
1
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
0.11
0.12
0.13
ERROR (%)
0.14
0.15
0.16
0.17
0.18
0.19
Figure 35. Gain Accuracy, SOIC, Temperature = 125°C
Temperature Range = 25°C to 85°C
0.20
0.20
6.0
0.21
0.21
7.5
0.22
0.22
0.23
0.23
9.0
0.24
0.24
10.5
0.25
0.25
0.26
0.26
12.0
0.27
0.27
13.5
0.28
0.28
0.29
0.29
05013-044
15.0
05013-045
0.30
05013-046
0.30
Rev. B | Page 10 of 20
Page 11
AD8203
12
TEMPERATURE = –40°C
10
8
6
HITS
4
2
0.26
05013-047
0.30
0.27
0.28
0.29
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
0.11
0.12
0.13
0.14
ERROR (%)
0.15
0.16
0.17
0.18
0.19
0.20
0.21
0.22
0.23
0.24
0.25
Figure 36. Gain Accuracy, SOIC, Temperature = −40°C Figure 38. Gain Drift Distribution, SOIC,
10
PACKAGE = SOIC
9
V
= 5V
SUPPLY
TEMPERATURE RANGE =
+25°C to –40°C
8
7
6
5
HITS
4
3
2
1
0
–16
–14
–8–6–4
–12
–10
GAIN DRIFT (ppm/°C)
02468
–2
101214
05013-048
16
Figure 37. Gain Drift Distribution, SOIC,
Temperature Range = +25°C to −40°C
10
PACKAGE = SOIC
V
= 5V
SUPPLY
TEMPERATURE RANGE =
25°C TO 85°C
–16
–14
–12
–10
HITS
9
8
7
6
5
4
3
2
1
0
Temperature Range = 25°C to 85°C
10
PACKAGE = SOIC
V
= 5V
SUPPLY
TEMPERATURE RANGE =
25°C TO 125°C
–9–8–7–6–5–4–3–2–1
–12
–11
–10
HITS
9
8
7
6
5
4
3
2
1
0
Figure 39. Gain Drift Distribution, SOIC,
Temperature Range = 25°C to 125°C
–8–6–4
–2
GAIN DRIFT (ppm/°C)
GAIN DRIFT (ppm/°C)
02468
012345678
101214
9
10
05013-049
16
05013-050
12
11
Rev. B | Page 11 of 20
Page 12
AD8203
THEORY OF OPERATION
The AD8203 consists of a preamp and buffer, arranged as
shown in
The preamp incorporates a dynamic bridge (subtractor) circuit.
Identical networks (within the shaded areas) consisting of R
R
B
Pin 8. Note that when equal amplitude signals are asserted at
Input 1 and Input 8, and the output of A1 is equal to the
common potential (that is, 0), the two attenuators form a
balanced-bridge network. When the bridge is balanced, the
differential input voltage at A1, and thus its output, is 0.
Any common-mode voltage applied to both inputs keeps the
bridge balanced and the A1 output at 0. Because the resistor
networks are carefully matched, the common-mode signal
rejection approaches this ideal state.
However, if the signals applied to the inputs differ, the result is a
difference at the input to A1. A1 responds by adjusting its output
to drive R
input until it matches the voltage at its noninverting input.
By attenuating voltages at Pin 1 and Pin 8, the amplifier inputs
are held within the power supply range, even if Pin 1 and Pin 8
input levels exceed the supply or fall below common (ground).
The input network also attenuates normal (differential) mode
voltages. R
forcing large output signals to balance relatively small differential inputs. The resistor ratios establish the preamp gain at 7.
Because the differential input signal is attenuated and then
amplified to yield an overall gain of 7, Amplifier A1 operates at
a higher noise gain, multiplying deficiencies such as input offset
voltage and noise with respect to Pin 1 and Pin 8.
R
G
Figure 40. Like-named resistors have equal values.
, RBC, and RG, attenuate input signals applied to Pin 1 and
, by way of RB
B
and RG form an attenuator that scales A1 feedback,
C
+IN
8
R
R
R
–IN
R
A
A
R
B
B
R
C
C
, to adjust the voltage at its inverting
G
1
A1
R
R
CM
CM
A3
R
G
100kΩ
(TRIMMED)
AD8203
4
3
A2
R
R
,
A
5
F
F
A3 amplifier detects the common-mode signal applied to A1
and adjusts the voltage on the matched R
resistors to reduce
CM
the common-mode voltage range at the A1 inputs. By adjusting
the common voltage of these resistors, the common-mode input
range is extended while, at the same time, the normal mode
signal attenuation is reduced, leading to better performance
referred to input.
The output of the dynamic bridge taken from A1 is connected
to Pin 3 by way of a 100 kΩ series resistor, provided for lowpass filtering and gain adjustment. The resistors in the input
networks of the preamp and the buffer feedback resistors are
ratio-trimmed for high accuracy.
The output of the preamp drives a gain-of-2 buffer amplifier,
A2, implemented with carefully matched feedback resistors R
.
F
The 2-stage system architecture of the AD8203 enables the user
to incorporate a low-pass filter prior to the output buffer. By
separating the gain into two stages, a full-scale, rail-to-rail
signal from the preamp can be filtered at Pin 3, and a half-scale
signal, resulting from filtering, can be restored to full scale by
the output buffer amp. The source resistance seen by the
inverting input of A2 is approximately 100 kΩ to minimize the
effects of the input bias current of A2. However, this current is
quite small, and errors resulting from applications that
mismatch the resistance are correspondingly small.
The A2 input bias current has a typical value of 40 nA, however,
this can increase under certain conditions. For example, if the
input signal to the A2 amplifier is V
go to V
due to the gain of 2. However, the output saturates
CC
/2, the output attempts to
CC
because the maximum specified voltage for correct operation is
200 mV below V
current increases (see
–140
–120
–100
–80
–60
. Under these conditions the total input bias
CC
Figure 41 for more information).
2
COM
Figure 40. Simplified Schematic
To minimize these errors while extending the common-mode
range, a dedicated feedback loop is used to reduce the range of
common-mode voltage applied to A1 for a given overall range
at the inputs. By offsetting the range of voltage applied to the
compensator, the input common-mode range is also offset to
include voltages more negative than the power supply. The
Rev. B | Page 12 of 20
05013-014
–40
A2 INPUT BIAS CURRENT (nA)
–20
0
0.50 1.0 1.5 2.0 2.5
DIFFERENTIAL MODE VOLTAGE (V)
Figure 41. A2 Input Bias Current vs. Input Voltage and Temperature. The
Shaded Area Is the Bias Current from −40°C to +125°C.
An increase in the A2 bias current, in addition to the output
saturation voltage of A1, directly affects the output voltage of
05013-035
Page 13
AD8203
the AD8203 system (Pin 3 and Pin 4 shorted). An example of
how to calculate the correct output voltage swing of the
AD8203, by taking all variables into account, follows:
• Amplifier A1 output saturation potential can go as low as
20 mV at its output.
• A2 typical input bias current of 40 nA multiplied by the
100 kΩ preamplifier output resistor produces
40 nA × 100 kΩ = 4 mV at the A2 input
• Total voltage at the A2 input equals the output saturation
voltage of A1 combined with the voltage error generated
by the input bias current
20 mV + 4 mV = 24 mV
• The total error at the input of A2, 24 mV, multiplied by the
buffer gain generates a resulting error of 48 mV at the
output of the buffer. This is the AD8203 system output low
saturation potential.
• The high output voltage range of the AD8203 is specified
as 4.8 V. Therefore, assuming a typical A2 input bias
current, the output voltage range for the AD8203 is 48 mV
to 4.8 V.
For an example of the effect of changes in A2 input bias current
vs. applied input potentials, see
current causes a change in error voltage at the input of the
buffer amplifier. This results in a change in overall error
potential at the output of the buffer amplifier.
Figure 41. The change in bias
Rev. B | Page 13 of 20
Page 14
AD8203
+
APPLICATIONS
The AD8203 difference amplifier is intended for applications
that require extracting a small differential signal in the presence
of large common-mode voltages. The input resistance is nominally
320 kΩ, and the device can tolerate common-mode voltages
higher than the supply voltage and lower than ground.
The open collector output stage sources current to within
20 mV of ground and to within 200 mV of V
CURRENT SENSING
High Line, High Current Sensing
Basic automotive applications making use of the large commonmode range are shown in
Figure 2 and Figure 3. The capability
of the device to operate as an amplifier in primary battery supply circuits is shown in
Figure 2. Figure 3 illustrates the ability
of the device to withstand voltages below system ground.
Low Current Sensing
The AD8203 is also used in low current sensing applications,
such as the 4 to 20 mA current loop shown in
applications, the relatively large shunt resistor can degrade the
common-mode rejection. Adding a resistor of equal value on the
low impedance side of the input corrects this error.
10Ω
1%
10Ω
1%
Figure 42. 4 to 20 mA Current Loop Receiver
+INA1+V
–IN
5V
AD8203
GND
GAIN ADJUSTMENT
The default gain of the preamplifier and buffer are ×7 and ×2,
respectively, resulting in a composite gain of ×14. With the
addition of external resistor(s) or trimmer(s), the gain can be
lowered, raised, or finely calibrated.
Gains Less Than 14
Since the preamplifier has an output resistance of 100 kΩ, an
external resistor connected from Pin 3 and Pin 4 to GND
decreases the gain by a factor R
in
Figure 43.
/(100 kΩ + R
EXT
.
S
Figure 42. In such
OUT
NC
S
A2
NC = NO CONNECT
EXT
OUTPUT
05013-015
), as shown
+V
S
OUT+V
NC+IN
S
V
DIFF
2
V
V
CM
DIFF
2
NC = NO CONNECT
AD8203
100kΩ
10kΩ10kΩ
OUT
14R
R
EXT
= 100kΩ
EXT
+ 100kΩ
GAIN
14 – GAIN
GAIN =
R
EXT
A2A1GND–IN
R
EXT
Figure 43. Adjusting for Gains < 14
The overall bandwidth is unaffected by changes in gain by using
this method, although there may be a small offset voltage due to
the imbalance in source resistances at the input to the buffer.
This can often be ignored, but if desired, it can be nulled by
inserting a resistor equal to 100 kΩ minus the parallel sum of
R
and 100 kΩ, in series with Pin 4. For example, with
EXT
R
= 100 kΩ (yielding a composite gain of ×7), the optional
EXT
offset nulling resistor is 50 kΩ.
Gains Greater Than 14
Connecting a resistor from the output of the buffer amplifier to
its noninverting input, as shown in
gain. The gain is now multiplied by the factor R
100 kΩ); for example, the gain is doubled for R
Figure 44, increases the
/(R
EXT EXT
EXT
−
= 200 kΩ.
Overall gains as high as 50 are achievable this way. Note that the
accuracy of the gain becomes critically dependent on the
resistor value at high gains. Also, the effective input offset
voltage at Pin 1 and Pin 8 (about six times the actual offset of
A1) limits the part’s use in high gain, dc-coupled applications.
+V
S
OUT+V
NC+IN
S
V
DIFF
2
V
V
CM
DIFF
2
NC = NO CONNECT
AD8203
10kΩ10kΩ
R
100kΩ
A2A1GND–IN
Figure 44. Adjusting for Gains > 14
EXT
OUT
GAIN =
R
EXT
R
EXT
= 100kΩ
14R
– 100kΩ
GAIN – 14
EXT
GAIN
05013-016
05013-017
Rev. B | Page 14 of 20
Page 15
AD8203
GAIN TRIM
Figure 45 shows a method for incremental gain trimming by
using a trim potentiometer and external resistor R
The following approximation is useful for small gain ranges:
G ≈ (10 MΩ/R
Thus, the adjustment range is ±2% for R
R
= 1 MΩ, and so on.
EXT
V
DIFF
V
V
CM
DIFF
)%
EXT
= 5 MΩ; ±10% for
EXT
5V
+INA1+V
2
NC
OUT
S
AD8203
2
GND
–IN
A2
R
EXT
.
EXT
OUT
GAIN TRIM
20kΩ MIN
Low-pass filters can be implemented in several ways by using
the features provided by the AD8203. In the simplest case, a
single-pole filter (20 dB/decade) is formed when the output of
A1 is connected to the input of A2 via the internal 100 kΩ
resistor by strapping Pin 3, Pin 4, and a capacitor added from
this node to ground, as shown in
Figure 46. If a resistor is added
across the capacitor to lower the gain, the corner frequency
increases; it should be calculated using the parallel sum of the
resistor and 100 kΩ.
5V
V
DIFF
2
V
V
CM
DIFF
2
+INA1+V
–IN
NC
S
AD8203
GND
OUT
A2
fC=
C IN FARADS
C
OUTPUT
2πC10
1
5
NC = NO CONNECT
05013-018
Figure 45. Incremental Gain Trim
Internal Signal Overload Considerations
When configuring gain for values other than 14, the maximum
input voltage with respect to the supply voltage and ground
must be considered, since either the preamplifier or the output
buffer reaches its full-scale output (approximately V
− 0.2 V)
S
with large differential input voltages. The input of the AD8203
is limited to (V
− 0.2)/7 for overall gains ≤ 7, since the pre-
S
amplifier, with its fixed gain of ×7, reaches its full-scale output
before the output buffer. For gains greater than 7, the swing at
the buffer output reaches its full scale first and limits the
AD8203 input to (V
− 0.2)/G, where G is the overall gain.
S
LOW-PASS FILTERING
In many transducer applications, it is necessary to filter the
signal to remove spurious high frequency components, including noise, or to extract the mean value of a fluctuating signal
with a peak-to-average ratio (PAR) greater than unity. For
example, a full-wave rectified sinusoid has a PAR of 1.57, a
raised cosine has a PAR of 2, and a half-wave sinusoid has a
PAR of 3.14. Signals having large spikes can have PARs of
10 or more.
When implementing a filter, the PAR should be considered so
that the output of the AD8203 preamplifier (A1) does not clip
before A2, since this nonlinearity would be averaged and appear
as an error at the output. To avoid this error, both amplifiers
should be made to clip at the same time. This condition is
achieved when the PAR is no greater than the gain of the second amplifier (2 for the default configuration). For example, if a
PAR of 5 is expected, the gain of A2 should be increased to 5.
NC = NO CONNECT
05013-019
Figure 46. Single-Pole, Low-Pass Filter Using the Internal 100 kΩ Resistor
If the gain is raised using a resistor, as shown in Figure 44, the
corner frequency is lowered by the same factor as the gain is
raised. Thus, using a resistor of 200 kΩ (for which the gain
would be doubled), the corner frequency is now 0.796 Hz µF
(0.039 µF for a 20 Hz corner frequency).
5V
V
DIFF
2
V
V
CM
DIFF
2
NC = NO CONNECT
+INA1+V
–IN
AD8203
GND
OUT
NC
S
A2
255kΩ
C
Figure 47. 2-Pole, Low-Pass Filter
C
f
(Hz) = 1/C(μF)
C
OUT
005013-020
A 2-pole filter (with a roll-off of 40 dB/decade) can be implemented
using the connections shown in
Figure 47. This is a Sallen-Key
form based on a ×2 amplifier. It is useful to remember that a 2-pole
filter with a corner frequency f
have the same attenuation at the frequency (f
at that frequency is 40 log (f
and a 1-pole filter with a corner at f1
2
), which is illustrated in Figure 48.
2/f1
2
/f1). The attenuation
2
Using the standard resistor value shown and equal capacitors (see
Figure 47), the corner frequency is conveniently scaled at 1 Hz µF
(0.05 µF for a 20 Hz corner). A maximally flat response occurs
when the resistor is lowered to 196 kΩ and the scaling is then
1.145 Hz µF. The output offset is raised by approximately 5 mV
(equivalent to 250 µV at the input pins).
Rev. B | Page 15 of 20
Page 16
AD8203
Y
FREQUENCY
40dB/DECADE
20dB/DECADE
ATTENUATION
40log (f2/f1)
A 1-POLE FILTER, CORNER f1, AND
A 2-POLE FILTER, CORNER f
THE SAME ATTENUATION –40log (f
AT FREQUENCY f
2
2
f
1
, HAVE
2
)
/f
1
2/f1
2
f
f
2
/f
2
1
05013-021
Figure 48. Comparative Responses of 1-Pole and 2-Pole Low-Pass Filters
HIGH LINE CURRENT SENSING WITH LPF AND GAIN ADJUSTMENT
Figure 49 is another refinement of Figure 2, including gain
adjustment and low-pass filtering.
INDUCTIVE
5V
LOAD
+INA1+V
AD8203
–IN
NC
OUT
S
GND
A2
V
NULL
C
5% CALIBRATION RANGE
(Hz) = 0.767Hz/C(μF)
f
C
(0.22μF FOR f
OS/IB
BATTER
CLAMP
DIODE
14V
NC = NO CONNECT COMMON
4-TERM
SHUNT
POWER
DEVICE
Figure 49. High Line Current Sensor Interface;
Gain = ×40, Single-Pole Low-Pass Filter
A power device that is either on or off controls the current in
the load. The average current is proportional to the duty cycle
of the input pulse and is sensed by a small value resistor. The
average differential voltage across the shunt is typically 100 mV,
although its peak value is higher by an amount that depends on
the inductance of the load and the control frequency. The
common-mode voltage, conversely, extends from roughly 1 V
above ground for the on condition to about 1.5 V above the
battery voltage for the off condition. The conduction of the
clamping diode regulates the common-mode potential applied
to the device. For example, a battery spike of 20 V may result in
an applied common-mode potential of 21.5 V to the input of
the devices.
133kΩ
20kΩ
= 3.6Hz)
C
OUT
4V/AMP
by a 1-pole low-pass filter, shown in
Figure 49
, set with a corner
frequency of 3.6 Hz, which provides about 30 dB of attenuation
at 100 Hz. A higher rate of attenuation can be obtained using a
2-pole filter with f
= 20 Hz, as shown in Figure 50. Although
C
this circuit uses two separate capacitors, the total capacitance is
less than half that needed for the 1-pole filter.
INDUCTIVE
CLAMP
DIODE
BATTERY
14V
NC = NO CONNECT COMMON
4-TERM
SHUNT
POWER
DEVICE
LOAD
Figure 50. 2-Pole Low-Pass Filter
+INA1+V
AD8203
–IN
5V
S
GND
NC
OUT
A2
93kΩ
C
fC(Hz) = 1/C(μF)
(0.05μF FOR f
C
301kΩ
50kΩ
= 20Hz)
C
OUTPUT
05013-023
DRIVING CHARGE REDISTRIBUTION ADCS
When driving CMOS ADCs, such as those embedded in popular microcontrollers, the charge injection (Q) can cause a
significant deflection in the output voltage of the AD8203.
Though generally of short duration, this deflection may persist
until after the sample period of the ADC has expired due to the
relatively high open-loop output impedance (21 kΩ) of the
AD8203. Including an R-C network in the output can significantly reduce the effect. The capacitor helps to absorb the
transient charge, effectively lowering the high frequency output
impedance of the AD8203. For these applications, the output
05013-022
signal should be taken from the midpoint of the
R
to C
LAG
combination, as shown in Figure 51.
LAG
Since the perturbations from the analog-to-digital converter are
small, the output impedance of the AD8203 appears to be low. The
transient response, therefore, has a time constant governed by the
product of the two LAG components, C
shown in
Figure 51, this time constant is programmed at approxi-
LAG
× R
LAG
. For the values
mately 10 µs. Therefore, if samples are taken at several tens of
microseconds or more, there is negligible charge stack-up.
5V
4 7
+IN
–IN
AD8203
A2
10kΩ
R
LAG
1kΩ
5
C
0.01μF
LAG
MICROPROCESSOR
A/D
To produce a full-scale output of 4 V, a gain ×40 is used, adjustable by ±5% to absorb the tolerance in the shunt. There is
sufficient headroom to allow 10% overrange (to 4.4 V). The
roughly triangular voltage across the sense resistor is averaged
Rev. B | Page 16 of 20
10kΩ
2
Figure 51. Recommended Circuit for Driving CMOS A/D
05013-024
Page 17
AD8203
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
5
4
SEATING
PLANE
5.15
4.90
4.65
1.10 MAX
0.23
0.08
8°
0°
3.20
3.00
1
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
0.15
0.38
0.00
0.22
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 52. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
0.80
0.60
0.40
4.00 (0.1574)
3.80 (0.1497)
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 53. 8-Lead Standard Small Outline Package [SOIC_N]
5.00 (0.1968)
4.80 (0.1890)
85
1.27 (0.0500)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
BSC
6.20 (0.2440)
5.80 (0.2284)
41
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
8°
1.27 (0.0500)
0°
0.40 (0.0157)
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
× 45°
ORDERING GUIDE
Model Temperature Package Package Description Package Outline Branding
AD8203YRMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 JXA
AD8203YRMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 JXA
AD8203YRZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8203YRZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8203YCSURF Die
1
Z = Pb-free part.
1
1
1
1
1
1
RM-8 AD8203YRMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] JXA
R-8 AD8203YRZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N]
Rev. B | Page 17 of 20
Page 18
AD8203
NOTES
Rev. B | Page 18 of 20
Page 19
AD8203
NOTES
Rev. B | Page 19 of 20
Page 20
AD8203
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05013-0-10/05(B)
Rev. B | Page 20 of 20
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