Datasheet AD818AR-REEL, AD818AR, AD818AN, AD818AR-REEL7 Datasheet (Analog Devices)

Page 1
Low Cost, Low Power
a
FEATURES Low Cost Excellent Video Performance
55 MHz 0.1 dB Bandwidth (Gain = +2)
0.01% & 0.05 Differential Gain & Phase Errors
High Speed
130 MHz Bandwidth (3 dB, G = +2) 100 MHz Bandwidth (3 dB, G+ = –1) 500 V/s Slew Rate 80 ns Settling Time to 0.01% (V
High Output Drive Capability
50 mA Minimum Output Current Ideal for Driving Back Terminated Cables
Flexible Power Supply
Specified for Single (+5 V) and Dual (ⴞ5 V to ⴞ15 V) Power Supplies Low Power: 7.5 mA max Supply Current
Available in 8-Lead SOIC and 8-Lead Plastic Mini-DIP

PRODUCT DESCRIPTION

The AD818 is a low cost, video op amp optimized for use in video applications which require gains equal to or greater than +2 or –1. The AD818 low differential gain and phase errors, single supply functionality, low power and high output drive make it ideal for cable driving applications such as video cam­eras and professional video equipment.
With video specs like 0.1 dB flatness to 55 MHz and low differ­ential gain and phase errors of 0.01% and 0.05°, along with 50 mA of output current, the AD818 is an excellent choice for any video application. The 130 MHz 3 dB bandwidth (G = +2)
+15V
0.01µF
V
IN
3
AD818
2
7
6
4
0.1µF
O
2.2µF
2.2µF
= 10 V Step)
Rbt
75
75
Rt 75
Video Op Amp
CONNECTION DIAGRAMS
8-Lead Plastic Mini-DIP (N), and
SOIC (R) Packages
NULL
NULL
1
AD818
–IN
2
+IN
3
–V
4
S
TOP VIEW
NC = NO CONNECT
and 500 V/µs slew rate make the AD818 useful in many high speed applications including: video monitors, CATV, color copiers, image scanners and fax machines.
The AD818 is fully specified for operation with a single +5 V power supply and with dual supplies from ±5 V to ±15 V. This power supply flexibility, coupled with a very low supply current of 7.5 mA and excellent ac characteristics under all power supply conditions, make the AD818 the ideal choice for many demanding yet power sensitive applications.
The AD818 is a voltage feedback op amp and excels as a gain stage in high speed and video systems (gain = >2 or –1). It achieves a settling time of 45 ns to 0.1%, with a low input offset voltage of 2 mV max.
The AD818 is available in low cost, small 8-lead plastic mini­DIP and SOIC packages.
0.06
0.05
DIFF PHASE
8
+V
7
S
OUTPUT
6
5
NC
DIFF GAIN
0.02
0.01
0.00
DIFFERENTIAL GAIN – Percent
1k
–15V
1k

AD818 Video Line Driver

REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
0.04
0.03
DIFFERENTIAL PHASE – Degrees
510
SUPPLY VOLTAGE – ±Volts
15
AD818 Differential Gain and Phase vs. Supply
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000
Page 2
AD818–SPECIFICATIONS
(@ TA = +25C, unless otherwise noted)
Parameter Conditions V
S
Min Typ Max Units
DYNAMIC PERFORMANCE
–3 dB Bandwidth Gain = +2 ±5 V 70 95 MHz
±15 V 100 130 MHz 0, +5 V 40 55 MHz
Gain = –1 ±5 V 50 70 MHz
±15 V 70 100 MHz 0, +5 V 30 50 MHz
Bandwidth for 0.1 dB Flatness Gain = +2 ±5 V 20 43 MHz
AD818A
= 2 pF ± 15 V 40 55 MHz
C
C
0, +5 V 10 18 MHz
Gain = –1 ±5 V 18 34 MHz
= 2 pF ± 15 V 40 72 MHz
C
Full Power Bandwidth
1
Slew Rate R
C
V
= 5 V p-p
OUT
= 500 Ω±5 V 25.5 MHz
R
LOAD
V
= 20 V p-p
OUT
= 1 kΩ±15 V 8.0 MHz
R
LOAD
= 1 kΩ±5 V 350 400 V/µs
LOAD
0, +5 V 10 19 MHz
Gain = –1 ±15 V 450 500 V/µs
0, +5 V 250 300 V/µs
Settling Time to 0.1% –2.5 V to +2.5 V ±5 V 45 ns
0 V–10 V Step, A
= –1 ±15 V 45 ns
V
to 0.01% –2.5 V to +2.5 V ±5 V 80 ns
0 V–10 V Step, A
= –1 ±15 V 80 ns
V
Total Harmonic Distortion FC = 1 MHz ±15 V 63 dB Differential Gain Error NTSC ±15 V 0.005 0.01 %
= 150 ) Gain = +2 ±5 V 0.01 0.02 %
(R
L
0, +5 V 0.08 %
Differential Phase Error NTSC ± 15 V 0.045 0.09 Degrees
= 150 ) Gain = +2 ±5 V 0.06 0.09 Degrees
(R
L
0, +5 V 0.1 Degrees
Cap Load Drive 10 pF
INPUT OFFSET VOLTAGE ±5 V to ± 15 V 0.5 2 mV
T
MIN
to T
MAX
3mV
Offset Drift 10 µV/°C
INPUT BIAS CURRENT ±5 V, ± 15 V 3.3 6.6 nA
T T
MIN
MAX
10 nA
4.4 nA/°C
INPUT OFFSET CURRENT ±5 V, ± 15 V 25 300 nA
to T
T
MIN
MAX
500 nA
Offset Current Drift 0.3 nA/°C
OPEN-LOOP GAIN V
= ±2.5 V ±5 V
OUT
= 500 3 5 V/mV
R
LOAD
to T
T R V R T V R
MIN
LOAD
OUT
LOAD
MIN
OUT
LOAD
MAX
= 150 2 4 V/mV
= ±10 V ±15 V
= 1 k 6 9 V/mV
to T
MAX
= ±7.5 V ±15 V
= 150
2 V/mV
3 V/mV
(50 mA Output) 3 5 V/mV
COMMON-MODE REJECTION V
POWER SUPPLY REJECTION V
= ±2.5 V ± 5 V 82 100 dB
CM
= ±12 V ±15 V 86 120 dB
V
CM
T
to T
MIN
S
T
MIN
MAX
= ±5 V to ± 15 V 80 90 dB
to T
MAX
±15 V 84 100 dB
80 dB
INPUT VOLTAGE NOISE f = 10 kHz ± 5 V, ± 15 V 10 nV/Hz
INPUT CURRENT NOISE f = 10 kHz ± 5 V, ±15 V 1.5 pA/Hz
–2–
REV. B
Page 3
AD818A
Parameter Conditions V
S
Min Typ Max Units
INPUT COMMON-MODE VOLTAGE RANGE ±5 V +3.8 +4.3 V
–2.7 –3.4 V
±15 V +13 +14.3 V
–12 –13.4 V
0, +5 V +3.8 +4.3 V
+1.2 +0.9 V
AD818
OUTPUT VOLTAGE SWING R
= 500 Ω±5 V 3.3 3.8 ±V
LOAD
= 150 Ω±5 V 3.2 3.6 ±V
R
LOAD
R
= 1 kΩ±15 V 13.3 13.7 ± V
LOAD
= 500 Ω±15 V 12.8 13.4 ± V
R
LOAD
= 500 0, +5 V +1.5,
R
LOAD
+3.5 V
Output Current ±15 V 50 mA
±5 V 50 mA 0, +5 V 30 mA
Short-Circuit Current ±15 V 90 mA
INPUT RESISTANCE 300 k
INPUT CAPACITANCE 1.5 pF
OUTPUT RESISTANCE Open Loop 8
POWER SUPPLY
Operating Range Dual Supply ±2.5 ± 18 V
Single Supply +5 +36 V
Quiescent Current ±5 V 7.0 7.5 mA
to T
T
MIN
MAX
±5 V 7.5 mA ±15 V 7.5 mA
T
to T
MIN
NOTE
1
Full power bandwidth = slew rate/2 π V
Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation
2
PEAK
.
1
MAX
±15 V 7.0 7.5 mA
2.0
8-LEAD MINI-DIP PACKAGE
1.5
TJ = 150°C
Plastic (N) . . . . . . . . . . . . . . . . . . . . . . See Derating Curves
Small Outline (R) . . . . . . . . . . . . . . . . . See Derating Curves
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± V
S
1.0
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Output Short Circuit Duration . . . . . . . . See Derating Curves
Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 seconds) . . . . +300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
Specification is for device in free air: 8-lead plastic package, θJA = 90°C/W; 8-lead SOIC package, θJA = 155°C/W.

ORDERING GUIDE

Temperature Package Package
Model Range Description Option
AD818AN –40°C to +85°C 8-Lead N-8
Plastic DIP
AD818AR –40°C to +85°C 8-Lead SO-8
Plastic SOIC
Maximum Power Dissipation vs. Temperature for Differ­ent Package Types

ESD SUSCEPTIBILITY

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 volts, which readily accumulate on the human body and on test equipment, can discharge without de­tection. Although the AD818 features proprietary ESD protec­tion circuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic dis­charges. Therefore, proper ESD precautions are recommended to avoid any performance degradation or loss of functionality.
0.5
MAXIMUM POWER DISSIPATION – Watts
0
50 +90
30
AMBIENT TEMPERATURE – °C
8-LEAD SOIC PACKAGE
+50 +70+30+10–10
AD818AR-REEL –40°C to +85°C 13" Tape & Reel SO-8 AD818AR-REEL7 –40°C to +85°C 7" Tape & Reel SO-8
+80–40 +40 +60+200–20
REV. B
–3–
Page 4
AD818
0
–Typical Characteristics

METALIZATION PHOTOGRAPH

Dimensions shown in inches and (mm).
20
15
+V
CM
10
–V
CM
5
INPUT COMMON-MODE RANGE – ± Volts
0
020
5
SUPPLY VOLTAGE – ±Volts
10
15
Figure 1. Common-Mode Voltage Range vs. Supply
30
25
20
15
VS = ±15V
600
500
400
SLEW RATE – V/µs
300
200
020
Figure 3. Slew Rate vs. Supply Voltage
20
15
10
5
SUPPLY VOLTAGE – ±Volts
10
RL = 500
15
10
5
OUTPUT VOLTAGE SWING – Volts p-p
0
10
100
LOAD RESISTANCE –
VS = ±5V
1k
10k
Figure 2. Output Voltage Swing vs. Load Resistance
–4–
= 150
R
L
5
OUTPUT VOLTAGE SWING – ±Volts
0
0
5
SUPPLY VOLTAGE – ±Volts
10
15
Figure 4. Output Voltage Swing vs. Supply
2
REV. B
Page 5
AD818
k
130
30
140
90
50
–40
70
–60
110
12010080604020
0
–20
TEMPERATURE – °C
SHORT CIRCUIT CURRENT – mA
SOURCE CURRENT
SINK CURRENT
0
8.0
7.5
QUIESCENT SUPPLY CURRENT – mA
7.0
6.5
6.0
+85°C
-40°C
0
5
SUPPLY VOLTAGE – ±Volts
10
+25°C
15
2
Figure 5. Quiescent Supply Current vs. Supply Voltage
100
10
1
70
PHASE MARGIN
60
50
GAIN/BANDWIDTH
40
PHASE MARGIN – Degrees
30
60 140
40
TEMPERATURE – °C
100 120806040200–20
Figure 8. –3 dB Bandwidth and Phase Margin vs. Temperature. Gain = +2
9
8
7
6
±15V
±5V
95
85
75
–3dB BANDWIDTH – MHz
65
55
5
OPEN-LOOP GAIN – V/mV
0.1
CLOSED-LOOP OUTPUT IMPEDANCE – Ohms
0.01 1k 10k 100M10M1M100k
FREQUENCY – Hz
Figure 6. Closed-Loop Output Impedance vs. Frequency
7
6
5
4
3
INPUT BIAS CURRENT – µA
2
1
40
60
Figure 7. Input Bias Current vs. Temperature
0
–20
TEMPERATURE – °C
140
120806040 10020
4
3
100 1k 10
LOAD RESISTANCE – Ohms
Figure 9. Open-Loop Gain vs. Load Resistance
Figure 10. Short Circuit Current vs. Temperature
REV. B
–5–
Page 6
0
AD818–Typical Characteristics
OPEN-LOOP GAIN – dB
100
–20
80
60
40
20
0
10k
1k
±15V SUPPLIES R
±5V SUPPLIES
R
= 1k
L
FREQUENCY – Hz
L
= 1k
PHASE ±5V OR ±15V SUPPLIES
100M10M1M100k
Figure 11. Open-Loop Gain and Phase Margin vs. Frequency
100
90
80
70
60
50
PSR – dB
40
30
20
10
–SUPPLY
1k100
+SUPPLY
10M1M100k10k
FREQUENCY – Hz
1G
100M
+100
+80
+60
+40
+20
0
PHASE MARGIN – Degrees
10
8
6
4
1%
1%
0.1%
0.1%
20
2
0
2
4
OUTPUT SWING FROM 0 TO ±V
6
8
10
0
0.01%
0.01%
SETTLING TIME – ns
16
140120100806040
Figure 14. Output Swing and Error vs. Settling Time
50
40
30
20
10
INPUT VOLTAGE NOISE – nV/ Hz
0
10
1
FREQUENCY – Hz
10M
1M100k10k1k100
Figure 12. Power Supply Rejection vs. Frequency
120
100
80
CMR – dB
60
40
1k 10M
10k
100k
FREQUENCY – Hz
1M
Figure 13. Common-Mode Rejection vs. Frequency
Figure 15. Input Voltage Noise Spectral Density vs. Frequency
30
R = 1k
L
20
R = 150LΩ
10
OUTPUT VOLTAGE – Volts p-p
0 100k 1M 100M10M
FREQUENCY – Hz
Figure 16. Output Voltage vs. Frequency
–6–
REV. B
Page 7
AD818
10
0
–10
1M 10M 100M
2
4
6
8
2
4
6
8
GAIN – dB
±15V
±5V
+5V
FREQUENCY – Hz
1k
150
2pF
1k
V
IN
V
OUT
AD818
VS 0.1dB FLATNESS
±15V 72 MHz
±5V 34 MHz
+5V 19 MHz
1G
–40
RL = 150
2V p-p
2nd HARMONIC
1k
3rd HARMONIC
1M100k10k
FREQUENCY – Hz
HARMONIC DISTORTION – dB
50
60
70
80
90
100
100
Figure 17. Harmonic Distortion vs. Frequency
650
550
450
10M
C
10
VS CC 0.1dB Flatness
9
15V 2pF 55 MHz5V 1pF 43 MHz
8
+5V 1pF 18 MHz
7
6
GAIN – dB
5
4
3
2
1
1M 10M 100M
5V
+5V
FREQUENCY – Hz
1k
V
IN
1k
AD818
C
150
15V
V
OUT
1G
Figure 20. Closed-Loop Gain vs. Frequency (G = +2)
SLEW RATE – V/µs
350
250
60 140
40
Figure 18. Slew Rate vs. Temperature
0.06
0.05
0.04
DIFFERENTIAL PHASE – Degrees
0.03
Figure 19. Differential Gain and Phase vs. Supply Voltage
REV. B
510
–20
0
TEMPERATURE – °C
100 12080604020
Figure 21. Closed-Loop Gain vs. Frequency (G = –1)
0.02
DIFF GAIN
DIFF PHASE
SUPPLY VOLTAGE – ±Volts
0.01
0.00
DIFFERENTIAL GAIN – Percent
15
–7–
Page 8
A
A
AD818–Typical Characteristics
C
F
1k
+V
3.3µF
S
0.01µF
HP PULSE (LS) OR FUNCTION (SS) GENERATOR
V
1k
IN
50
2
3
7
AD818
4
–V
S
3.3µF
6
V
OUT
0.01µF
TEKTRONIX
P6201 FET
PROBE
R
L
TEKTRONIX
7A24
PREAMP
100
5V
90
10
0%
50ns
5V
Figure 22. Inverting Amplifier Connection
2V
50ns
100
90
10
0%
2V
Figure 23. Inverter Large Signal Pulse Response ±5 VS,
= 1 pF, RL = 1 k
C
F
100
90
200mV
10ns
Figure 25. Inverter Large Signal Pulse Response ±15 VS,
= 1 pF, RL = 1 k
C
F
100
90
10
0%
200mV
200mV
10ns
Figure 26. Inverter Small Signal Pulse Response ±15 VS,
= 1 pF, RL = 150
C
F
100
90
200mV
10ns
10
0%
200mV
Figure 24. Inverter Small Signal Pulse Response ±5 VS,
= 1 pF, RL = 150
C
F
10
0%
200mV
Figure 27. Inverter Small Signal Pulse Response ±5 VS,
= 0 pF, RL = 150
C
F
REV. B–8–
Page 9
HP
A
PULSE (LS) OR FUNCTION (SS) GENERATOR
AD818
C
F
1k
V
100
IN
50
2
3
1k
+V
S
7
AD818
4
–V
S
3.3µF
3.3µF
0.01µF
6
V
OUT
0.01µF
TEKTRONIX
P6201 FET
PROBE
R
L
TEKTRONIX
7A24
PREAMP
100
5V
90
10
0%
50ns
5V
Figure 28. Noninverting Amplifier Connection
2V
100
90
10
0%
2V
50ns
Figure 29. Noninverting Large Signal Pulse Response
±
5 V, CF = 1 pF, RL = 1 k
100mV
100
90
10ns
Figure 31. Noninverting Large Signal Pulse Response
±
15 V, CF = 1 pF, RL = 1 k
100mV
100
90
10
0%
10ns
200mV
Figure 32. Noninverting Small Signal Pulse Response
±
15 V, CF = 1 pF, RL = 150
100mV
100
90
10ns
10
0%
200mV
Figure 30. Noninverting Small Signal Pulse Response
±
5 V, CF = 1 pF, RL = 150
REV. B
10
0%
200mV
Figure 33. Noninverting Small Signal Pulse Response
±
5 V, CF = 0 pF, RL = 150
–9–
Page 10
AD818
+V
S
OUTPUT
–IN
+IN
–V
S
NULL 1 NULL 8
Figure 34. AD818 Simplified Schematic
THEORY OF OPERATION
The AD818 is a low cost, video operational amplifier designed to excel in high performance, high output current video applications.
The AD818 (Figure 34) consists of a degenerated NPN differ­ential pair driving matched PNPs in a folded-cascode gain stage. The output buffer stage employs emitter followers in a class AB amplifier which delivers the necessary current to the load, while maintaining low levels of distortion.
The AD818 will drive terminated cables and capacitive loads of 10 pF or less. As the closed-loop gain is increased, the AD818 will drive heavier cap loads without oscillating.

INPUT CONSIDERATIONS

An input protection resistor (RIN in Figure 28) is required in circuits where the input to the AD818 will be subjected to tran­sient of continuous overload voltages exceeding the ±6 V maxi­mum differential limit. This resistor provides protection for the input transistors by limiting their maximum base current.
For high performance circuits, it is recommended that a “bal­ancing” resistor be used to reduce the offset errors caused by bias current flowing through the input and feedback resistors. The balancing resistor equals the parallel combination of R
IN
and RF and thus provides a matched impedance at each input terminal. The offset voltage error will then be reduced by more than an order of magnitude.
may result in peaking. A small capacitance (1–5 pF) may be used in parallel with the feedback resistor to neutralize this effect.
Power supply leads should be bypassed to ground as close as possible to the amplifier pins. Ceramic disc capacitors of
0.1 µF are recommended.
+V
S
7
2
1
6
8
10k
VOS ADJUST
3
AD818
4
–V
S
Figure 35. Offset Null Configuration

OFFSET NULLING

The input offset voltage of the AD818 is inherently very low. However, if additional nulling is required, the circuit shown in Figure 35 can be used. The null range of the AD818 in this configuration is ±10 mV.

SINGLE SUPPLY OPERATION

Another exciting feature of the AD818 is its ability to perform well in a single supply configuration. The AD818 is ideally suited for applications that require low power dissipation and high output current.
Referring to Figure 36, careful consideration should be given to the proper selection of component values. The choices for this particular circuit are: R1 + R3R2 combine with C1 to form a low frequency corner of approximately 10 kHz. C4 was inserted in series with R4 to maintain amplifier stability at high frequency.
Combining R3 with C2 forms a low pass filter with a corner frequency of approximately 500 Hz. This is needed to maintain amplifier PSRR, since the supply is connected to V
through
IN
the input divider. The values for R2 and C2 were chosen to demonstrate the AD818’s exceptional output drive capability. In this configuration, the output is centered around 2.5 V. In order to eliminate the static dc current associated with this level, C3 was inserted in series with R
.
L
+V
S

GROUNDING AND BYPASSING

When designing high frequency circuits, some special precau­tions are in order. Circuits must be built with short interconnect leads. When wiring components, care should be taken to pro­vide a low resistance, low inductance path to ground. Sockets should be avoided, since their increased interlead capacitance can degrade circuit bandwidth.
Feedback resistors should be of low enough value (1 k) to assure that the time constant formed with the inherent stray capacitance at the amplifier’s summing junction will not limit performance. This parasitic capacitance, along with the parallel resistance of RF/RIN, form a pole in the loop transmission which
–10–
R3
3.3␮F
V
IN
100
C2
C1
0.01␮F
1k
0.001␮F
R1
3.3k
R2
3.3k
R4
C4
1k
2
AD818
3
7
4
SELECT C1, R1, R2 FOR DESIRED LOW
3.3␮F FREQUENCY CORNER.
0.01␮F
6
V
OUT
Figure 36. Single Supply Amplifier Configuration
R
L
150
C3
0.1␮F
REV. B
Page 11
ERROR
SIGNAL
OUTPUT
ERROR AMPLIFIER V
OUTPUT × 10
ERROR
2× HP2835
3
AD829
2
AD818
15pF
2×
5
7
HP2835
6
4
0.47µF
1M
SHORT, DIRECT
100
CONNECTION TO TEKTRONIX TYPE 11402 OSCILLOSCOPE PREAMP INPUT SECTION
0 TO ±10V
POWER
SUPPLY
TTL LEVEL
SIGNAL
GENERATOR
50Hz
OUTPUT
DIGITAL
GROUND
ANALOG
GROUND
EI&S DL1A05GM MERCURY RELAY
7, 8
2
13
1, 14
50
COAX
CABLE
2.2µF
500
50
ADJUST
1k
NULL
0.01µF
100
2
3
AD818
FALSE SUMMING NODE
500
7
+V
S
5–18pF
4
2.2µF
–V
S
1k
DEVICE UNDER TEST
6
0.01µF
Figure 37. Settling Time Test Circuit

AD818 SETTLING TIME

Settling time is comprised primarily of two regions. The first is the slew time in which the amplifier is overdriven, where the output voltage rate of change is at its maximum. The second is the linear time period required for the amplifier to settle to within a specified percent of the final value.
Measuring the rapid settling time of AD818 (45 ns to 0.1% and 80 ns to 0.01%—10 V step) requires applying an input pulse with a very fast edge and an extremely flat top. With the AD818 configured in a gain of –1, a clamped false summing junction responds when the output error is within the sum of two diode voltages (approximately 1 volt). The signal is then amplified 20 times by a clamped amplifier whose output is connected directly to a sampling oscilloscope.
A High Performance Video Line Driver
The buffer circuit shown in Figure 38 will drive a back-termi­nated 75 video line to standard video levels (1 V p-p) with
0.1 dB gain flatness to 55 MHz with only 0.05° and 0.01% differential phase and gain at the 3.58 MHz NTSC subcarrier frequency. This level of performance, which meets the require­ments for high-definition video displays and test equipment, is achieved using only 7 mA quiescent current.
+15V
0.01µF
V
IN
Rt
75
1k
2
AD818
3
1k
7
4
0.01µF
–15V
2.2µF
Rbt
75
2.2µF
75
Rt 75
6
0.01µF
100
0.47µF
+V
1.9k
NOTE: USE CIRCUIT BOARD WITH GROUND PLANE
10pF SCOPE PROBE CAPACITANCE
0.01µF
–V
S
S
TEKTRONIX P6201 FET PROBE TO TEKTRONIX TYPE 11402 OSCILLOSCOPE PREAMP INPUT SECTION
SETTLING OUTPUT

DIFFERENTIAL LINE RECEIVER

The differential receiver circuit of Figure 39 is useful for many applications from audio to video. It allows extraction of a low level signal in the presence of common-mode noise. As shown in Figure 40, the AD818 provides this function with only 10 nV/Hz noise at the output.
2pF
1k 1k
+5V
2.2␮F
6
V
OUT
2.2␮F
OUTPUT
DIFFERENTIAL
INPUT
1k
2
AD818
3
2pF
0.01␮F
7
4
0.01␮F
–5V
1k
Figure 39. Differential Line Receiver
100
200
V
1V
90
2V
10
0%
10n
s
20ns
REV. B
Figure 38. Video Line Driver
200m V
Figure 40. Performance of Line Receiver, RL = 150 Ω, G = +2
–11–
Page 12
AD818

A HIGH SPEED, THREE OP AMP IN AMP

The circuit of Figure 41 uses three high speed op amps: two AD818s and an AD817. This high speed circuit lends itself well to CCD imaging and other video speed applications. It has the optional flexibility of both dc and ac trims for common-mode rejection, plus the ability to adjust for minimum settling time.
EACH
+15V
10µF
COMMON
10µF
15V
V
IN
A1
0.1µF
0.1µF
AD818
1k
1k
1k
3pF
2pF
5pF
R
G
5pF
1k
A2
R
G
1k 222 20
AD818
CADJ (pF)
2-8 2-8 2-8
SMALL SIGNAL BANDWIDTH
14.7 MHz
4.5 MHz 960 kHz
+V
IN
BANDWIDTH, SETTLING TIME, & TOTAL HARMONIC DISTORTION VS. GAIN
GAIN
3 10 100
+V
S
–V
S
AMPLIFIER
1µF
1µF
2-8 pF
970
50 D.C. CMR ADJUST
SETTLING TIME TO 0.1%
200ns 370ns
2.5µs
PIN 7 EACH AMPLIFIER
0.1µF
0.1µF
PIN 4 EACH AMPLIFIER
SETTLING TIME A.C. CMR ADJUST
1k
A3
AD817
THD + NOISE BELOW INPUT LEVEL @ 10kHz
82 dB 81 dB 71 dB
V
OUT
R
L
2k
0.165±0.01 (4.19±0.25)
0.125
(3.18)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0098 (0.25)
0.0040 (0.10)
SEATING
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic Mini-DIP (N) Package
PIN 1
MIN
0.018±0.003 (0.46±0.08)
8
1
0.39 (9.91) MAX
0.10
(2.54)
BSC
4
0.033 (0.84) NOM
5
0.25
(6.35)
0.035±0.01 (0.89±0.25)
0.18±0.03 (4.57±0.76)
SEATING PLANE
0.31
(7.87)
0.30 (7.62) REF
0.011±0.003 (0.28±0.08)
15°
0°
8-Lead SOIC (R) Package
0.1968 (5.00)
0.1890 (4.80)
85
0.0500 (1.27)
PLANE
41
BSC
0.0192 (0.49)
0.0138 (0.35)
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0075 (0.19)
0.0196 (0.50)
0.0099 (0.25)
8
0.0500 (1.27)
0
0.0160 (0.41)
C1738–0–5/00 (rev. B) 00872
45
Figure 41. High Speed 3 Op Amp In Amp
–12–
PRINTED IN U.S.A.
REV. B
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