Page 1
700 MHz, 5 mA
a
FEATURES
Single and Dual 2-to-1 Also Available (AD8180 and AD8182)
Fully Buffered Inputs and Outputs
Fast Channel Switching: 10 ns
High Speed
> 700 MHz Bandwidth (–3 dB)
> 750 V/ms Slew Rate
Fast Settling Time of 15 ns to 0.1%
Excellent Video Specifications (R
Gain Flatness of 0.1 dB of 75 MHz
0.01% Differential Gain Error, R
0.018 Differential Phase Error, RL = 10 kV
Low Power: 4.4 mA
Low Glitch: < 25 mV
Low All-Hostile Crosstalk of –95 dB @ 5 MHz
High “OFF” Isolation of –115 dB @ 5 MHz
Low Cost
Fast Output Disable Feature for Connecting Multiple Devices
APPLICATIONS
Pin Compatible with HA4314* and GX4314*
Video Switchers and Routers
Pixel Switching for “Picture-In-Picture”
Switching in LCD and Plasma Displays
> 2 kV)
L
= 10 kV
L
4-to-1 Video Multiplexer
AD8184
FUNCTIONAL BLOCK DIAGRAM
IN0
GND
IN1
GND
IN2
GND
IN3
+1
1
2
3
+1
DECODER
4
+1
5
6
7
+1
AD8184
NC = NO CONNECT
Table I. Truth Table
ENABLE A1 A0 OUTPUT
0 0 0 IN0
0 0 1 IN1
0 1 0 IN2
0 1 1 IN3
1 X X High Z
14
13
12
11
10
9
8
+V
S
A0
A1
ENABLE
OUT
NC
–V
S
PRODUCT DESCRIPTION
The AD8184 is a high speed 4-to-1 multiplexer. It offers –3 dB
signal bandwidth of 700 MHz along with a slew rate of 750 V/µs.
With 95 dB of crosstalk and 115 dB isolation, it is useful in
many high speed applications. The differential gain and differential phase error of 0.01% and 0.01°, along with 0.1 dB flatness
of 75 MHz, make AD8184 ideal for professional video multiplexing. It offers 10 ns switching time, making it an excellent
choice for pixel switching (picture-in-picture) while consuming
less than 4.5 mA on ±5 V supply voltage.
The AD8184 offers a high speed disable feature allowing the
output to be put into a high impedance state. This allows multiple outputs to be connected together for cascading stages while
the “OFF” channels do not load the output bus. It operates on
voltage supplies of ±5 V and is offered in 14-lead PDIP and
SOIC packages.
*All trademarks are the property of their respective holders.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
5
VIN = 50mVrms
4
R
= 5kΩ
L
3
2
1
0
–1
–2
NORMALIZED OUTPUT – dB
–3
–4
–5
1M
10M 100M 1G
FREQUENCY – Hz
Figure 1. Small Signal Frequency Response
One T echnology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1997
Page 2
AD8184–SPECIFICA TIONS
(@ TA = +258C, VS = 65 V, RL = 2 kV unless otherwise noted)
Parameter Conditions Min Typ Max Units
AD8184A
SWITCHING CHARACTERISTICS
Channel Switching Time
1
Channel-to-Channel
50% Logic to 10% Output Settling IN0 = +1 V, IN1 = –1 V 5 ns
50% Logic to 90% Output Settling 10 ns
50% Logic to 99.9% Output Settling 15 ns
ENABLE to Channel ON Time
50% Logic to 90% Output Settling IN0 = +1 V, –1 V or IN1 = –1 V, +1 V 12 ns
ENABLE to Channel OFF Time
50% Logic to 90% Output Settling IN1 = +1 V, –1 V or IN1 = –1 V, +1 V 22 ns
Channel Switching Transient (Glitch)
2
2
3
A0, A1 = 0 or 1
A0, A1 = 0 or 1
All Inputs Are Grounded ±25 mV
DIGITAL INPUTS
Logic “1” Voltage A0, A1 and ENABLE Inputs 2.0 V
Logic “0” Voltage A0, A1 and ENABLE Inputs 0.8 V
Logic “1” Input Current A0, A1, ENABLE = +4 V 10 200 nA
Logic “0” Input Current A0, A1, ENABLE = +0.4 V 2 3 µA
DYNAMIC PERFORMANCE
–3 dB Bandwidth (Small Signal)4AD8184AR VIN = 50 mV rms, RL = 5 kΩ 550 700 MHz
–3 dB Bandwidth (Large Signal) AD8184AR VIN = 1 V rms, RL = 5 kΩ 105 135 MHz
0.1 dB Bandwidth
4, 5
AD8184AR VIN = 50 mV rms, RL = 5 kΩ 60 75 MHz
Slew Rate 2 V Step 600 750 V/µs
Settling Time to 0.1% 2 V Step 15 ns
DISTORTION/NOISE PERFORMANCE
Differential Gain ƒ = 3.58 MHz, RL = 2 kΩ 0.2 %
f = 3.58 MHz, RL = 10 kΩ 0.01 0.02 %
Differential Phase f = 3.58 MHz, RL = 2 kΩ 0.2 Degrees
All Hostile Crosstalk
OFF Isolation
7
6
AD8184AR ƒ = 5 MHz –95 dB
AD8184AR ƒ = 5 MHz, RL = 30 Ω –115 dB
f = 3.58 MHz, RL = 10 kΩ 0.01 0.02 Degrees
ƒ = 30 MHz –78 dB
Voltage Noise ƒ = 30 MHz 4.5 nV/√Hz
Total Harmonic Distortion ƒC = 10 MHz, VO = 2 V p-p, RL = 1 kΩ –74 dBc
DC/TRANSFER CHARACTERISTICS
Voltage Gain
8
VIN = ±1 V 0.982 V/V
Input Offset Voltage 28 mV
T
to T
MIN
Input Offset Voltage Drift 5 µV/°C
MAX
15 mV
Input Offset Voltage Matching Channel-to-Channel 0.6 3 mV
Input Bias Current 2.5 7.5 µA
T
to T
MIN
Input Bias Current Drift 5 nA/°C
MAX
9.5 µA
INPUT CHARACTERISTICS
Input Resistance 1.0 2.4 MΩ
Input Capacitance Channel Enabled (R Package) 1.6 pF
Channel Disabled (R Package) 1.6 pF
Input Voltage Range ±3.3 V
OUTPUT CHARACTERISTICS
Output Voltage Swing VIN = ±4 V, RL = 2 kΩ
9
±3.15 ±3.2 V
Short Circuit Current 30 mA
Output Resistance Enabled 28 33 Ω
Disabled 10 MΩ
Output Capacitance Disabled (R Package) 3.2 pF
POWER SUPPLY
Operating Range ± 4 ±6V
Power Supply Rejection Ratio +PSRR +VS = +4.5 V to +5.5 V, –VS = –5 V 5 4 57 dB
Power Supply Rejection Ratio –PSRR –VS = –4.5 V to –5.5 V, +VS = +5 V 51 54 dB
Quiescent Current Enabled 4.4 5.2 mA
T
to T
MIN
MIN
to T
MAX
MAX
Disabled 2.1 2.9 mA
T
5.7 mA
2.9 mA
OPERATING TEMPERATURE RANGE –40 +85 °C
–2–
REV. 0
Page 3
AD8184
WARNING!
ESD SENSITIVE DEVICE
NOTES
1
ENABLE pin is grounded. IN0 and IN2 = +1 V dc, IN1 and IN3 = –1 V dc. A0 is driven with a 0 V to +5 V pulse, A1 is grounded. Measure transition time from 50% of the A0
input value (+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 channel voltage (+1 V) to IN1 (–1 V), or vice versa. All inputs are measured in a similar
manner using A0 and A1 to select the channels.
2
ENABLE pin is driven with 0 V to +5 V pulse (with 3 ns edges). The state of the A0 and A1 pins determines which input is activate d (refer to Table I). Set IN0 and IN2 = +1 V dc,
IN1 and IN3 = –1 V dc, and measure transition time from 50% of
is the enable time.
3
All inputs are grounded. A0 input is driven with 0 V to +5 V pulse, A1 is grounded. The output is monitored. Speeding the edges of the A0 pulse increases the glitch magnitude
due to coupling via the ground plane. Removing the A0 and A1 terminations will lower the glitch, as does increasing R
4
Decreasing RL slightly lowers the bandwidth. Increasing CL significantly lowers the bandwidth (see Figure 18).
5
A resistor (RS) placed in series with the multiplexer inputs serves to optimize 0.1 dB flatness, but is not required (see Figure 19.)
6
Select an input that is not being driven (i.e., A0 and A1 are logic 0, IN0 is selected); drive all other inputs with VIN = 0.707 V rms and monitor the output at ƒ = 5 and 30 MHz.
= 2 kΩ (see Figure 12).
R
L
7
Multiplexer is disabled (i.e., ENABLE = logic 1) and all inputs are driven simultaneously with VIN = 0.446 V rms. Output is monitored at ƒ = 5 and 30 MHz. RL = 30 Ω to simu-
of one enabled multiplexer within a system (see Figure 13). In this mode the output impedance is very high (typ 10 MΩ), and the signal couples across the package; the
late R
ON
load impedance determines the crosstalk.
8
Voltage gain decreases for lower values of RL. The resistive divider formed by the multiplexers enables output resistance (28 Ω) and RL causes a gain that increases as R
decreases (i.e., the voltage gain is approximately 0.97 V/V [3% gain error] for RL = 1 kΩ).
9
Larger values of RL provide wider output voltage swings, as well as better gain accuracy. See Note 8.
Specifications subject to change without notice.
ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 4, ∆t
.
L
is the disable time, ∆t
OFF
ON
L-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.6 V
Internal Power Dissipation
2
1
AD8184 14-Lead Plastic (N) . . . . . . . . . . . . . . . . 1.6 Watts
AD8184 14-Lead Small Outline (R) . . . . . . . . . . 1.0 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±V
S
Output Short Circuit Duration . . Observe Power Derating Curves
Storage Temperature Range
N & R Package . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . +300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air: 14-pin plastic package: θJA = 75°C/Watt
14-pin SOIC package: θJA = 120°C/Watt, where PD = (TJ–TA)/θJA.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD8184AN –40°C to +85°C 14-Lead Plastic DIP N-14
AD8184AR –40°C to +85°C 14-Lead Narrow SOIC R-14
AD8184AR-REEL –40°C to +85°C Reel 14-Lead SOIC R-14
AD8184-EB Evaluation Board For AD8184R
While the AD8184 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction temperature (+150°C) is not exceeded under all conditions. To ensure
proper operation, it is necessary to observe the maximum power
derating curves shown in Figure 2.
2.5
TJ = +150°C
2.0
14-PIN DIP PACKAGE
1.5
1.0
MAXIMUM POWER DISSIPATION – Watts
0.5
14-PIN SOIC
–30 –20 –10 0 10 20 30 40 50 60 80
–50 90–40
AMBIENT TEMPERATURE – °C
70
Figure 2. Maximum Power Dissipation vs. Temperature
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8184
is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is
determined by the glass transition temperature of the plastic,
approximately +150°C. Exceeding this limit temporarily may
cause a shift in parametric performance due to a change in the
stresses exerted on the die by the package. Exceeding a junction
temperature of +175°C for an extended period can result in
device failure.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8184 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
Page 4
AD8184–T ypical Performance Curves
DUT OUT
500mV/DIV
A0 PULSE
0 TO 5V
1V
–1V
OUTPUT
5ns/DIV
5
V
= 50mVrms
IN
4
R
= 5kΩ
L
= 0Ω
R
3
S
2
1
0
–1
–2
NORMALIZED OUTPUT – dB
–3
–4
–5
1M
10M 100M 1G
FREQUENCY – Hz
Figure 3 Channel Switching Characteristics
PULSE
0 TO 5V
t
OFF
10ns/DIV
t
ON
+1V
DUT OUT
800mV/DIV
–1V
+1V
–1V
Figure 4. Enable and Disable Switching Characteristics
OUTPUT
SWITCHING A0
25mV/DIV
OUTPUT
SWITCHING A1
A0 and A1 PULSE
0 TO +5V
25ns/DIV
Figure 6. Small Signal Frequency Response
0.5
VIN = 50mVrms
0.4
= 5kΩ
R
L
= 0Ω
R
S
0.3
0.2
0.1
0.0
–0.1
–0.2
NORMALIZED FLATNESS – dB
–0.3
–0.4
–0.5
1M 10M 100M 1G
FREQUENCY – Hz
Figure 7. Gain Flatness vs. Frequency
3
RL = 5kΩ
0
–3
–6
–9
–12
–15
OUTPUT – dBV
–18
–21
–24
–27
1M 10M 100M 1G
VIN = 1.0Vrms
VIN = 0.5Vrms
VIN = 0.25Vrms
VIN = 125mVrms
VIN = 62.5mVrms
FREQUENCY – Hz
Figure 5. Channel Switching Transient (Glitch)
–4–
Figure 8. Large Signal Frequency Response
REV. 0
Page 5
AD8184
OUTPUT @ 50mV
OUTPUT @ 100mV
50mV/DIV
INPUT
5ns/DIV
Figure 9. Small Signal Transient Response
INPUT
+
–
+
–
10ns/DIV
OUTPUT = 2V
2V/DIV
OUTPUT = 1V
–10
–20
–30
–40
–50
–60
50Ω
1
3
50Ω
5
V
IN
50Ω
10
7
AD8184
OUTPUT
2kΩ
VIN = 0.707Vrms
R
= 2kΩ
L
–70
CROSSTALK – dB
–80
–90
–100
–110
100k
1G1M 10M 100M
FREQUENCY – Hz
Figure 12. All-Hostile Crosstalk vs. Frequency
–30
VIN = 0.446 Vrms
= 30Ω
R
–40
L
–50
–60
–70
V
IN
–80
–90
OFF ISOLATION – dB
–100
–110
–120
–130
100k
1
3
50Ω
5
50Ω
7
AD8184
1M 10M 100M
FREQUENCY – Hz
= LOGIC 1
OUTPUT
10
30Ω
1G
Figure 10. Large Signal Transient Response
0.05
0.04
0.03
0.02
0.01
0.00
–0.01
–0.02
–0.03
–0.04
DIFFERENTIAL GAIN – %DIFFERENTIAL PHASE – Deg
–0.05
1234567891011
0.05
0.04
0.03
0.02
0.01
0.00
–0.01
–0.02
–0.03
–0.04
–0.05
1234567891011
RL = 2kΩ
NTSC
Figure 11. Differential Gain and Phase Error
Figure 13. “OFF” Isolation vs. Frequency
100
10
VOLTAGE NOISE – nV/ Hz
1
10 1M100 1k 10k 100k 10M
FREQUENCY – Hz
Figure 14. Voltage Noise vs. Frequency
30M
REV. 0
–5–
Page 6
AD8184–Typical Performance Curves
0
V
= 2V p-p
OUT
–10
R
= 1kΩ
L
–20
–30
–40
–50
–60
–70
–80
HARMONIC DISTORTION – dBc
–90
–100
100k 1M 10M 100M
2ND HARMONIC
3RD HARMONIC
FREQUENCY – Hz
Figure 15. Harmonic Distortion vs. Frequency
100M
10M
1M
100k
Z
10k
1k
100
INPUT AND DISABLED OUTPUT IMPEDANCE
10
100 1G1k
(DISABLED)
OUT
Z
(ENABLED)
OUT
10k 100k 1M 10M 100M
FREQUENCY – Hz
Z
IN
150
140
130
120
110
100
0.8
0.7
V
= 50mVrms
0.6
IN
= 5kΩ
R
L
0.5
R
= 0Ω
S
0.4
0.3
0.2
0.1
NORMALIZED FLATNESS – dB
0.0
–0.1
–0.2
1M 10M 100M 1G
100pF
100pF
33pF
FREQUENCY – Hz
33pF
10pF
0pF
1
0
–1
–2
–3
–4
–5
–6
NORMALIZED OUTPUT – dB
–7
–8
–9
Figure 18. Frequency Response vs. Capacitive Load
0.8
0.7
VIN = 50mVrms
0.6
= 5kΩ
R
L
0.5
90
80
70
60
50
40
ENABLED OUTPUT IMPEDANCE – Ω
30
20
10
0.4
0.3
0.2
0.1
0
NORMALIZED FLATNESS – dB
–0.1
–0.2
1M
10M 100M
RS = 150Ω
RS = 75Ω
RS = 0Ω
RS = 75Ω
RS = 150Ω
FREQUENCY – Hz
RS = 0Ω
1
0
–1
–2
–3
–4
–5
–6
NORMALIZED OUTPUT – dB
–7
–8
–9
1G
Figure 16. Output & Input Impedance vs. Frequency
0
–10
–20
–30
–40
PSSR – dB
–50
–60
–70
–80
0.03M 0.01M 10M 500M
+PSRR
–PSRR
1M 100M
FREQUENCY – Hz
Figure 17. Power Supply Rejection vs. Frequency
Figure 19. Frequency Response vs. Input Series Resistance
5
4
3
2
1
0
–1
–2
OUTPUT VOLTAGE – Volts
–3
–4
–5
–5 5–4 –3 –2 –1 0 1 2 3 4
Figure 20. Output Voltage vs. Input Voltage, RL = 2 k
INPUT VOLTAGE – Volts
Ω
–6–
REV. 0
Page 7
AD8184
THEORY OF OPERATION
The AD8184 video multiplexer is designed for fast switching
(10 ns) and wide bandwidth (> 700 MHz). This performance is
attained with low power dissipation (4.4 mA, enabled) through
the use of proprietary circuit techniques and a dielectricallyisolated complementary bipolar process. This device has a fast
disable function that allows the outputs of several muxes to be
wired in parallel to form a larger mux with little degradation in
switching time. The low disabled output capacitance (3.2 pF)
helps to preserve the system bandwidth in larger matrices. Unlike earlier CMOS switches, the switched open-loop buffer architecture of the AD8184 provides a unidirectional signal path
with minimal switching glitches and constant, low input capacitance. Since the input impedance of these muxes is nearly independent of the load impedance and the state of the mux, the
frequency response of the ON channels in a large switch matrix
is not affected by fanout.
Figure 21 shows a block diagram and simplified schematic of the
AD8184, which contains four switched buffers (S0–S3) that
share a common output. The decoder logic translates TTLcompatible logic inputs (A0, A1 and ENABLE) to internal, differential ECL levels for fast, low-glitch switching. The A0 (LSB)
and A1 (MSB) control inputs constitute a two-bit binary word
that determines which of the four buffers is enabled, unless the
ENABLE input is HIGH, in which case all buffers are disabled
and the output is switched to a high impedance state.
Each open-loop buffer is implemented as a complementary
emitter follower that provides high input impedance, symmetric
slew rate and load drive, and high output-to-input isolation due
2
to its β
current gain. The selected buffer is biased ON by fast
switched current sources that allow the buffer to turn on quickly.
Dedicated flatness circuits, combined with the open-loop architecture of the AD8184, keep peaking low (typically < 0.5 dB)
when driving high capacitive loads, without the need for external
series resistors at the input or output. If better flatness response
is desired, an input series resistance (R
) may be used (refer to
S
Figure 19), although this will increase crosstalk. The dc gain of
the AD8184 is almost independent of load for R
> 10 kΩ. For
L
heavier loads, the dc gain is approximately that of the voltage
divider formed by the output impedance of the mux (typically
28 Ω and R
).
L
High speed disable clamp circuits (not shown) at the bases of
Q3 and Q4 allow the buffers to turn off quickly and cleanly
without dissipating much power once off. Moreover, these
clamps shunt displacement currents flowing through the junction capacitances of Q1 and Q2 away from the bases of Q3 and
Q4 and to ac ground through low impedances. The two-pole
high-pass frequency response of the T switch formed by these
clamps is a significant improvement over the one-pole high pass
response of a simple series CMOS switch. As a result, board
and package parasitics, especially stray capacitance between
inputs and outputs, may limit the achievable crosstalk and off
isolation.
LAYOUT CONSIDERATIONS:
Realizing the high speed performance attainable with the
AD8184 requires careful attention to board layout and component selection. Proper RF design techniques and low parasitic
component selection are mandatory.
Wire wrap boards, prototype boards and sockets are not recommended because of their high parasitic inductance and capacitance. Instead, surface-mount components should be directly
soldered to a printed circuit board (PCB). The PCB should
have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path.
To reduce stray capacitance the ground plane should be removed
from the area near input and output pins.
REV. 0
AD8184
DECODER
14
V
CC
13
A0
12
A1
11
OUT
10
NC
9
V
8
EE
IN0
GND
IN1
GND
IN2
GND
IN3
I1
1
2
3
4
5
6
7
Q3
Q2
Q4
I2
Q1
S0
I1
Q3
Q2
Q4
I2
Q1
S1
I1
Q3
Q2
Q4
I2
Q1
S2
I1
Q3
Q2
Q4
I2
Q1
S3
NC = NO CONNECT
Figure 21. Block Diagram and Simplified Schematic of the AD8184 Multiplexer
–7–
Page 8
AD8184
Chip capacitors should be used for supply bypassing. One end
of the capacitor should be connected to the ground plane and
the other within 1/4 inch of each power pin. An additional large
(4.7 µF–10 µF) tantalum capacitor should be connected in par-
allel with each of the smaller capacitors for low impedance supply bypassing over a broad range of frequencies.
Signal traces should be as short as possible. Stripline or
microstrip techniques should be used for long (longer than
about 1 inch) signal traces. These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly ter-
minated at each end using surface mount components.
Careful layout is imperative to minimize crosstalk. Guards
(ground or supply traces) must be run between all signal traces
to limit direct capacitive coupling. Input and output signal lines
should fan out away from the mux as much as possible. If multiple signal layers are available, a buried stripline structure having ground plane above, below and between signal traces will
have the best crosstalk performance.
Return currents flowing through termination resistors can also
increase crosstalk if these currents flow in sections of the finiteimpedance ground circuit shared between more than one input
or output. Minimizing the inductance and resistance of the ground
plane can reduce this effect, but further care should be taken in positioning the terminations. Terminating cables directly at the connectors will minimize the return current flowing on the board, but
the signal trace between the connector and the mux will look like
an open stub and will degrade the frequency response. Moving the
termination resistors close to the input pins will improve the frequency response, but the terminations from neighboring inputs
should not have a common ground return.
APPLICATIONS
A Buffered 4-to-1 Multiplexer
In applications where the output of a multiplexer must drive a
back-terminated 75 Ω line (R
= 75 Ω + 75 Ω), it is necessary
L
to buffer the output of the AD8184. In the example in Figure
22, this is accomplished using the AD8009 high speed current
feedback op amp. The amplifier is configured with a gain of 2 to
compensate for the signal halving due to termination at the multiplexer input. This gives the overall circuit a gain of unity.
If lower speed can be tolerated, a number of other amplifiers
can replace the AD8009 op amp in the above circuit. In general
there is a trade-off between bandwidth and power consumption.
Table II summarizes the bandwidth and power consumption
characteristics of these op amps.
Table II. Amplifier Options for Multiplexer Buffering
Op Amp Comments
AD8009 Highest Bandwidth, (G = +2) = 700 MHz, I
SY
=
14 mA
AD8001 Lower Power Consumption, Bandwidth (G = +2) =
440 MHz, I
= 5 mA
SY
AD8011 Lower Power Consumption, Bandwidth (G = +2) =
210 MHz, I
= 1 mA
SY
AD8079 Fixed Gain Dual Amplifier (2 or 2.2), Bandwidth =
260 MHz, I
= 5 mA Per Amp
SY
AD8005 Lowest Power Consumption, Bandwidth (G = +2) =
170 MHz, ISY = 400 µA
A0 A1
IN0
IN1
IN2
IN3
75Ω
75Ω
75Ω
75Ω
10µF
1
2
3
4
5
6
7
AD8184
+1
GND
+1
GND
+1
GND
+1
DECODER
+V
14
S
13
12
11
10
9
NC
–V
8
S
0.1µF
0.1µF
10µF
+V
S
–V
S
Figure 22. A Buffered 4-to-1 Multiplexer
681Ω
+V
S
AD8009
–V
S
681Ω
10µF
0.1µF
0.1µF
10µF
75Ω
V
OUT
–8–
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AD8184
Color Document Scanner
Figure 23 shows a block diagram of a Color Document Scanner.
Charge Coupled Devices (CCDs) find widespread use in scanner applications. A monochrome CCD delivers a serial stream
of voltages levels, each level being proportional to the light shining on that cell. In the case of the color image scanner shown,
there are three output streams, representing red, green and blue.
Interlaced with the stream of voltage levels is a voltage representing the reset level (or black level) of each cell. A Correlated
Double Sampler (CDS) subtracts these two voltages from each
other in order to eliminate the relatively large offsets common
with CCDs.
CONTROL & TIMING
A0
A1
CCD
R
CDS
G
CDS
B
CDS
REFERENCE
ENABLE
AD8184
OUT
10µF
0.1µF
AD9220
10/12-BIT
10MSPS
A/D
CONVERTER
VINA
VINB
V
REF
SENSE
Figure 23. Color Document Scanner
The next step in the data acquisition process involves digitizing
the three signal streams. Assuming that the analog-to-digital
converter chosen has a fast enough sample rate, multiplexing
the three streams into a single ADC is generally more economical than using one ADC per channel. In the example shown, we
use the AD8184 as the multiplexer.
Because of its high bandwidth, the AD8184 is capable of driving
the switched capacitor input stage of the AD9220 without additional buffering. In addition to having the required bandwidth,
it is necessary to consider the settling time of the multiplexer. In
this case, the ADC has a sample rate of 10 MHz, which corresponds to a sampling period of 100 ns. Typically, one phase of
the sampling clock is used for conversion (i.e., all levels are held
steady) and the other is used for switching and settling to the
next channel. Assuming a 50% duty cycle, the signal chain must
settle within 50 ns. With a settling time to 0.1% of 15 ns, the
multiplexer easily satisfies this criterion.
In the example shown, the fourth (spare) channel of the
AD8184 is used to measure a reference voltage. This voltage
would probably be measured less frequently than the R, G and
B signals. Multiplexing a reference voltage offers the advantage
that any temperature drift effects caused by the multiplexer will
equally impact the reference voltage and the to-be-measured signals. If the fourth channel is unused, it is good design practice
to permanently tie it to ground.
A 4 3 4 Crosspoint Switch
While large crosspoint arrays are best constructed using highly
integrated devices such as the AD8116, 16 × 16 crosspoint
switch, smaller or irregular sized arrays can be constructed using
4-to-1 multiplexers such as the AD8184. The circuit below
shows a 4 × 4 array, constructed using the AD8184 and buffered using the AD8079, a dual, fixed gain of 2 or 2.2, video
amplifier.
IN0-3
AD8184
4
IN0-IN3
4
IN0-IN3
4
4
IN0-IN3
4
IN0-IN3
OUT
AD8184
OUT
AD8184
OUT
AD8184
OUT
*AD8079 IS A DUAL, FIXED GAIN OF 2 AMPLIFIER
1/2 AD8079*
OUT0
750Ω750Ω
1/2 AD8079*
OUT1
750Ω750Ω
1/2 AD8079*
OUT2
750Ω750Ω
1/2 AD8079*
OUT3
750Ω750Ω
Figure 24. 4 × 4 Crosspoint Switch
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Page 10
AD8184
IN0
IN1
IN2
IN3
R3
49.9Ω
R1
49.9Ω
R4
49.9Ω
R2
49.9Ω
10µF
C4
1
2
3
4
5
6
7
AD8184
+1
GND
+1
GND
+1
GND
+1
+V
DECODER
NC
–V
C3
14
S
13
12
11
10
9
8
S
0.1µF
49.9Ω
49.9Ω
49.9Ω
4.99kΩ
0.1µF
C2
10µF
C1
Figure 25. AD8184AR Evaluation Board
+V
S
A0
R5
A1
R6
R7
OUT
(SCOPE PROBE ADAPTER)
R8
–V
S
EVALUATION BOARD
An evaluation board is available for the AD8184. It has been
carefully laid out and tested to demonstrate the specified high
speed performance of the devices. Figure 25 shows the schematic of the evaluation board. For ordering information,
please refer to the Ordering Guide.
Figure 26 shows the silkscreen of the component side and Figure 28 shows the silkscreen of the solder side. Figures 27 and 29
show the layout of the component side and solder side respectively.
The evaluation board is provided with 49.9 Ω termination resistors on all inputs. This is to allow the performance to be evaluated at very high frequencies where 50 Ω termination is most
popular. To use the evaluation board in video applications, the
termination resistors should be replaced with 75 Ω resistors.
The FR4 board type has the following stripline dimensions:
60-mil width, 12-mil gap between center conductor and outside
ground plane “island” and 62-mil board thickness.
The multiplexer output is loaded with a 4.99 kΩ resistor. For
connection to external instruments, an oscilloscope probe
adapter is provided. This allows direct connection of an FET
probe to the board. For verification of data sheet specifications,
use of an FET probe is recommended because of its low input
capacitance. The probe adapter used on the board has the same
footprint as SMA, SMB and SMC type connectors, allowing
easy replacement if necessary.
The side-launched SMA connectors on the analog and digital
inputs can also be replaced by top-mount SMA, SMB or SMC
type connectors. When using top-mount connectors, the
stripline on the outside 1/8" of the board edge should be removed with an X-acto blade as this unused stripline acts as an
open stub, which could degrade the small-signal frequency response of the multiplexer.
Input termination resistor placement on the evaluation board is
critical to reducing crosstalk. Each termination resistor is oriented so that the ground return currents flow counterclockwise
to the ground plane “island.” Although the direction of this
ground current flow is arbitrary, it is important that no two input or output termination resistors share a connection to the
same ground “island.”
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AD8184
Figure 26. Component Side Silkscreen
Figure 28. Solder Side Silkscreen
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Figure 27. Board Layout (Component Side)
Figure 29. Board Layout (Solder Side)
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Page 12
AD8184
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Plastic DIP
(N-14)
0.795 (20.19)
0.725 (18.42)
14
17
PIN 1
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
8
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
SEATING
PLANE
14-Lead SOIC
(R-14)
0.3444 (8.75)
0.3367 (8.55)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
C3036–10–4/97
0.1574 (4.00)
0.1497 (3.80)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
14 8
PIN 1
0.0500
0.0192 (0.49)
(1.27)
0.0138 (0.35)
BSC
0.2440 (6.20)
71
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0099 (0.25)
0.0075 (0.19)
0.0196 (0.50)
0.0099 (0.25)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
x 45°
–12–
–12–
PRINTED IN U.S.A.
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