Datasheet AD8158 Datasheet (ANALOG DEVICES)

O

O

6.5 Gbps

FEATURES

Quad 2:1 mux/1:2 demux
Optimized for dc to 6.5 Gbps NRZ data
Per-lane P/N pair inversion for routing ease
Programmable input equalization
Compensates up to 40 inches of FR4
Loss-of-signal detection
Programmable output pre-emphasis up to 12 dB
Programmable output levels with squelch and disable
Accepts ac-coupled or dc-coupled differential CML inputs
50 Ω on-chip termination
1:2 demux supports unicast or bicast operation
Port-level loopback
Port or single lane switching

1.8 V to 3.3 V flexible core supply
User-settable I/O supply from V
Low power, typically 2.0 W in basic configuration
100-lead LFCSP

−40°C to +85°C operating temperature range

APPLICATIONS

Low cost redundancy switch
SONET OC48/SDH16 and lower data rates
XAUI/GbE/FC/Infiniband over backplane
OIF CEI 6.25 Gbps over backplane
Serial data-level shift
4-/8-/12-lane equalizers or redrivers

to 1.2 V

CC

Ix_A[3:0]

Ix_B[3:0]

x_A[3:0]

x_B[3:0]

I2C_A0
I2C_A1
I2C_A2

SCL
SDA

Quad Buffer Mux/Demux

AD8158

FUNCTIONAL BLOCK DIAGRAM

TRANSMIT

RECEIVE

EQUALIZATION

EQ

EQ

TRANSMIT

PRE-

EMPHASIS

I2C

CONTROL

LOGIC

AD8158

2:1

1:2

QUAD

2:1

MULTIPLEXER/

1:2

DEMULTIPLEXER

Figure 1.

PRE-

EMPHASIS

EQ

RECEIVE

EQUALIZATION

TOGGLE

CONTROL

LOGIC

Ox_C[3:0]

Ix_C[3:0]

LB_A
LB_B
LB_C
PE_A
PE_B
PE_C
EQ_A[1:0]
EQ_B[1:0]
EQ_C[1:0]
SEL[3:0]
BICAST
SEL4G
RESETb
LOS_INT

06646-001

GENERAL DESCRIPTION

The AD8158 is an asynchronous, protocol-agnostic, quad-lane
2:1 switch with a total of 12 differential CML inputs and
12 differential CML outputs. The signal path supports NRZ
signaling with data rates up to 6.5 Gbps per lane. Each lane
offers programmable receive equalization, programmable
output pre-emphasis, programmable output levels, and loss-of­signal detection.

The nonblocking switch-core of the AD8158 implements a
2:1 multiplexer and 1:2 demultiplexer per lane and supports
independent lane switching through the four select pins,
SEL[3:0]. Each port is a four-lane link. Every lane implements
an asynchronous path supporting dc to 6.5 Gbps NRZ data,
fully independent of other lanes. The AD8158 has low latency
and very low lane-to-lane skew.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The main application of the AD8158 is to support redundancy
on both the backplane and the line interface sides of a serial
link. The demultiplexing path implements unicast and bicast
capability, allowing the part to support either 1 + 1 or 1:1
redundancy.

The AD8158 is also suited for testing high speed serial links
because of its ability to duplicate incoming data. In a port­monitoring application, the AD8158 can maintain link­connectivity with a pass-through connection from Port C to
Port A while sending a duplicate copy of the data to test
equipment on Port B.

The rich feature set of the AD8158 can be controlled either
through external toggle pins or by setting on-chip control
registers through the I

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008–2009 Analog Devices, Inc. All rights reserved.

2

C interface.

AD8158

TABLE OF CONTENTS

Features .............................................................................................. 1

AD8158 Power Consumption .................................................. 23

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

I2C Timing Specifications ............................................................ 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 16

The Switch (Mux/Demux/Unicast/Bicast/Loopback) ........... 17

Receivers ...................................................................................... 19

Loss of Signal (LOS) ................................................................... 21

Transmitters ................................................................................ 22

I2C Control Interface ...................................................................... 25

Serial Interface General Functionality..................................... 25

I2C Interface Data Transfers: Data Write ................................ 25

I2C Interface Data Transfers: Data Read ................................. 26

Applications Information .............................................................. 27

Output Compliance ................................................................... 28

Signal Levels and Common-Mode Shift for AC-Coupled and

DC-Coupled Outputs ................................................................ 29

Supply Sequencing ..................................................................... 31

Reset ............................................................................................. 31

Single Supply vs. Multiple Supply Operation ......................... 31

Printed Circuit Board (PCB) Layout Guidelines ................... 32

Register Map ................................................................................... 34

Outline Dimensions ....................................................................... 36

Ordering Guide .......................................................................... 36

REVISION HISTORY

12/09—Rev. A: Rev. B

Changes to LOS to Output Squelch Parameter (Table 1) ............ 3

Added Endnote 1 to Table 2 ............................................................ 5

Added Speed Select (SEL4G) to Table 6 ...................................... 17

Changes to Loss of Signal (LOS) section ..................................... 21

Deleted Table 15 .............................................................................. 21

Changes to Serial Interface General Functionality Section ...... 25

Added Reset Section ....................................................................... 31

Changes to Table 22 ........................................................................ 34

9/09—Rev. 0: Rev. A

Reorganized Layout ............................................................ Universal

Changes to Specifications Section .................................................. 3

Changes to Table 2 ............................................................................ 5

Changes to Table 3 ............................................................................ 6

Changes to Table 4 ............................................................................ 7

Changes to Theory of Operation Section .................................... 16

Added Table 15; Renumbered Sequentially ................................ 21

Changes to Applications Information Section ............................ 27

Changes to Table 23 ........................................................................ 34

6/08—Revision 0: Initial Version

Rev. B | Page 2 of 36

AD8158

SPECIFICATIONS

VCC = V
inputs and outputs, differential input swing = 800 mV p-p, T

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Data Rate/Channel (NRZ) DC 6.5 Gbps
Deterministic Jitter (No

Random Jitter (No Channel) RMS, data rate = 6.5 Gbps 1 ps
Residual Deterministic Jitter

Residual Deterministic Jitter

Propagation Delay 50% input to 50% output (maximum EQ) 700 ps
Lane-to-Lane Skew

Switching Time 50% logic switching to 50% output data 150 ns
Output Rise/Fall Time 20% to 80% (PE = lowest setting) 62 ps

INPUT CHARACTERISTICS

Differential Input Voltage

Input Voltage Range Single-ended absolute voltage level, VL minimum VEE + 0.6 V
Single-ended absolute voltage level, VH maximum VCC + 0.3 V

OUTPUT CHARACTERISTICS

Output Voltage Swing Differential, PE = 0, default output level, @ dc 590 725 820

Output Voltage Range, Single-

TX_HEADROOM = 0, VH maximum VCC + 0.6 V
TX_HEADROOM = 1, VL minimum VCC − 1.3 V
TX_HEADROOM = 1, VH maximum VCC + 0.6 V
Output Current Port A/B/C, PE_A/B/C = minimum 16 mA
Port A/B/C, PE_A/B/C = 6 dB, VOD = 800 mV p-p 32 mA

TERMINATION CHARACTERISTICS

Resistance Differential, VCC = V

LOS CHARACTERISTICS

DC Assert Level 50

DC Deassert Level 300

LOS to Output Squelch

LOS to Output Enable

POWER SUPPLY

Operating Range

= V

TTI

= 1.8 V, DVCC = 3.3 V, VEE = 0 V, RL = 50 Ω, basic configuration1, data rate = 6.5 Gbps, data pattern = PRBS7, ac-coupled

TTO

= 25°C, unless otherwise noted.

A

Data rate = 6.5 Gbps, EQ setting = 0 22 ps p-p

Channel)

Data rate 6.5 Gbps, 20 inch FR4 30 ps p-p

with Receive Equalization

Data rate 6.5 Gbps, 40 inch FR4 40 ps p-p
Data rate 6.5 Gbps, 10 inch FR4 35 ps p-p

with Transmit Preemphasis

Data rate 6.5 Gbps, 30 inch FR4 42 ps p-p

Signal path and switch architecture is balanced

90 ps

and symmetric (maximum EQ)

Swing

2

V

= VCC − 0.6 V, VCC = V

ICM

MIN

LOS control register = 0x05

TX_HEADROOM = 0, V

minimum VCC − 1.1 V

L

to V

MAX

, TA = T

MIN

to T

200 2000

,

MAX

Ended Absolute Voltage Level

to V

MAX

, TA = T

LOS_FILT = 0, V
V

= 1.8 V

CC

MIN

= 0 to 50% OP/ON settling,

ID

LOS_FILT = 0, data present to first valid transition,

= 1.8 V

V

CC

V

CC

VEE = 0 V, TX_HEADROOM = 0 1.6 1.8 to 3.3 3.6 V
VEE = 0 V, TX_HEADROOM = 1 2.2 3.3 3.6 V

MIN

to T

90 100 110 Ω

MAX

21 ns

67 ns

DVCC DVCC ≥ VCC, VEE = 0 V 1.6 1.8 to 3.3 3.6 V
V

1.2 VCC + 0.3 V

TTI

V

1.2 VCC + 0.3 V

TTO

mV p-p
diff

mV p-p
diff

mV p-p
diff

mV p-p
diff

Rev. B | Page 3 of 36

AD8158

Parameter Conditions Min Typ Max Unit

Supply Current

ICC

VCC = 1.8 V LB_x = 0, PE = 0 dB on all ports, default 370 450 mA
LB_x = 1, PE = 6 dB on all ports, default 730 850 mA
VCC = 3.3 V LB_x = 0, PE = 0 dB on all ports, default 400 460 mA
LB_x = 1, PE = 6 dB on all ports, default 780 860 mA

I

TTO

V

= 1.8 V LB_x = 0, PE = 0 dB on all ports, default 128 150 mA

TTO

LB_x = 1, PE = 6 dB on all ports, default 367 420 mA
V

= 3.3 V LB_x = 0, PE = 0 dB on all ports, default 134 152 mA

TTO

LB_x = 1, PE = 6 dB on all ports, default 388 422 mA

I

10 20 mA

TTI

I

2 4 mA

DVCC

THERMAL CHARACTERISTICS

Operating Temperature Range −40 +85 °C
θJA

θJC Still air; thermal resistance through exposed pad 1.4 °C/W
Maximum Junction Temperature 125 °C

LOGIC CHARACTERISTICS3 I

Input High (VIH) DV
Input Low (VIL) DV
Input High (VIH) DV
Input Low (VIL) DV
Output High (VOH) 2 kΩ pull-up resistor to DVCC DVCC V
Output Low (VOL) IOL = +3 mA VEE 0.4 V

1

Bicast is off, loopback is off on all ports, preemphasis is set to minimum on all ports, and equalization is set to minimum on all ports.

2

V

is the input common-mode voltage.

ICM

3

EQ control pins (EQ_A[1:0], EQ_B[1:0], EQ_C[1:0]) require 5 kΩ in series when DVCC > VCC.

Still air; JEDEC 4-layer test board, exposed pad

22.2 °C/W

soldered

2

C, SDA, SCL, control pins

= 3.3 V 0.7 × DVCC DVCC V

CC

= 3.3 V VEE 0.3 × DVCC V

CC

= 1.8 V 0.8 × DVCC DVCC V

CC

= 1.8 V VEE 0.2 × DVCC V

CC

Rev. B | Page 4 of 36

AD8158

A

I2C TIMING SPECIFICATIONS

SD

t

t

F

SCL

NOTES

1. S = START CONDITION.

2. Sr = REPEAT START.

3. P = ST OP.

t

LOW

t

HD;STA

S Sr

t

R

t

HD;DAT

t

SU;DAT

t

HIGH

F

t

SU;STA

Figure 2. I

2

C Timing Diagram

t

HD;STA

Table 2. I2C Timing Parameters

Parameter Symbol Min Max Unit

SCL Clock Frequency f
Hold Time for a Start Condition t
Setup Time for a Repeated Start Condition t
Low Period of the SCL Clock t
High Period of the SCL Clock t
Data Hold Time t
Data Setup Time t
Rise Time for Both SDA and SCL t
Fall Time for Both SDA and SCL t
Setup Time for Stop Condition t
Bus Free Time Between a Stop and a Start Condition t

0 400+ kHz

SCL

HD;STA

SU;STA

LOW

HIGH

HD;DAT

SU;DAT

R

F

SU;STO

BUF

Bus Free Time After a Reset 1 μs
Reset Pulse Width1 10 ns

1

Reset pulse width is defined as the time RESETB is held below the logic low threshold (VIL) listed in Table 1 while the DVCC supply is within the operating range in Table 1.

t

SU;STO

t

R

t

BUF

SP

0.6 μs

0.6 μs

1.3 μs

0.6 μs
0 μs
10 ns
1 300 ns
1 300 ns

0.6 μs
1 μs

06646-102

Rev. B | Page 5 of 36

AD8158

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating
VCC to VEE 3.7 V
DVCC to VEE 3.7 V
V

Lower of (VCC + 0.6 V) or 3.6 V

TTI

V

Lower of (VCC + 0.6 V) or 3.6 V

TTO

VCC to DVCC 0.6 V
Internal Power Dissipation
Differential Input Voltage 2.0 V
Logic Input Voltage VEE − 0.3 V < VIN < VCC + 0.6 V
Storage Temperature Range

Junction Temperature

4.26 W

−65°C to +125°C
125°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 6 of 36

AD8158

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CC

TTI

IP_C1

IN_C1

V

IP_C2

IN_C2

VCCIP_C3

IN_C3

PE_A

PE_B

PE_C

LOS_INT

LB_A

LB_B

IP_C0

IN_C0

V

9392919089888786858483828180797877

94 VEE95 SEL3

96 SEL2

97 SEL1

98 SEL0

99 BICAST

100 SEL4G

V

EE

ON_A3
OP_A3

V

CC

ON_A2
OP_A2

V

TTO

ON_A1
OP_A1

10

V

CC

11

ON_A0

12

OP_A0

13

V

EE

14

IN_A3

15

IP_A3

16

V

CC

17IN_A2
18IP_A2
19V

TTI

20IN_A1
21IP_A1
22V

CC

23IN_A0
24IP_A0
25V

EE

NOTES

1. THE ePAD O N THE BOTTOM OF T HE P ACKAG E MUST BE EL E CTRICALLY CONNECTED TO V

CONTROL PORT C INPUTS

1
2
3
4
5
6
7
8
9

PIN 1
INDICATOR

PORT A OU TP UTSPORT A INPUTS

DIE IS PACKAGE D DIE UP

I2C PORT B OUTPUTS CONTROL

262728293031323334353637383941

CC

SCL

SDA

DV

I2C_A0

I2C_A1

I2C_A2

OP_B3

ON_B3

RESETb

AD8158

TOP VIEW

(Not to S cale)

CC

TTO

V

V

OP_B2

ON_B2

ON_B1

CONTROL

40OP_B1

43OP_B0

44V

42

45EQ_A0

EE

CC

V

ON_B0

Figure 3. Pin Configuration

LB_C
76

75 V

EE

74 OP_C0
73 ON_C0
72 V

CC

71 OP_C1
70 ON_C1
69 V

TTO

OP_C2

68

PORT C OU TP UTSPORT B INPUTS

67

ON_C2

66

V

CC

65

OP_C3

64

ON_C3

63

V

CC

62

IP_B0

61

IN_B0

60

V

CC

59

IP_B1

58

IN_B1

57

V

TTI

56

IP_B2

55

IN_B2

54

V

CC

53

IP_B3

52

IN_B3

51

V

EE

46EQ_A1

47EQ_B0

48EQ_B1

49EQ_C0

50EQ_C1

.

06646-002

EE

Table 4. Pin Function Descriptions

Pin No. Mnemonic Type Description

1, 13, 25, 44, 51, 75, 94, ePAD VEE Power Negative Supply
2 ON_A3 Output High Speed Output Complement
3 OP_A3 Output High Speed Output
4, 10, 16, 22, 35, 41, 54, 60, 63, 66, 72, 85, 91 VCC Power Positive Supply
5 ON_A2 Output High Speed Output Complement
6 OP_A2 Output High Speed Output
7, 38, 69 V

Power Port A, Port B, and Port C Output Termination Supply

TTO

8 ON_A1 Output High Speed Output Complement
9 OP_A1 Output High Speed Output
11 ON_A0 Output High Speed Output Complement
12 OP_A0 Output High Speed Output
14 IN_A3 Input High Speed Input Complement
15 IP_A3 Input High Speed Input
17 IN_A2 Input High Speed Input Complement
18 IP_A2 Input High Speed Input
19, 57, 88 V

Power Port A, Port B, and Port C Input Termination Supply

TTI

20 IN_A1 Input High Speed Input Complement
21 IP_A1 Input High Speed Input
23 IN_A0 Input High Speed Input Complement
24 IP_A0 Input High Speed Input
26 DVCC Power Digital Power Supply

Rev. B | Page 7 of 36

AD8158

Pin No. Mnemonic Type Description

27 SCL I2C I2C Clock Pin
28 SDA I2C I2C Data Pin
29 I2C_A0 I2C I2C Address Pin (LSB)
30 I2C_A1 I2C I2C Address Pin
31 I2C_A2 I2C I2C Address Pin (MSB)
32 RESETb Control1 Chip Reset. Active Low
33 ON_B3 Output High Speed Output Complement
34 OP_B3 Output High Speed Output
36 ON_B2 Output High Speed Output Complement
37 OP_B2 Output High Speed Output
39 ON_B1 Output High Speed Output Complement
40 OP_B1 Output High Speed Output
42 ON_B0 Output High Speed Output Complement
43 OP_B0 Output High Speed Output
45 EQ_A02 Control1 Port A Equalizer Control Bit 0 (LSB)
46 EQ_A12 Control1 Port A Equalizer Control Bit 1 (MSB)
47 EQ_B02 Control1 Port B Equalizer Control Bit 0 (LSB)
48 EQ_B12 Control1 Port B Equalizer Control Bit 1 (MSB)
49 EQ_C02 Control1 Port C Equalizer Control Bit 0 (LSB)
50 EQ_C12 Control1 Port C Equalizer Control Bit 1 (MSB)
52 IN_B3 Input High Speed Input Complement
53 IP_B3 Input High Speed Input
55 IN_B2 Input High Speed Input Complement
56 IP_B2 Input High Speed Input
58 IN_B1 Input High Speed Input Complement
59 IP_B1 Input High Speed Input
61 IN_B0 Input High Speed Input Complement
62 IP_B0 Input High Speed Input
64 ON_C3 Output High Speed Output Complement
65 OP_C3 Output High Speed Output
67 ON_C2 Output High Speed Output Complement
68 OP_C2 Output High Speed Output
70 ON_C1 Output High Speed Output Complement
71 OP_C1 Output High Speed Output
73 ON_C0 Output High Speed Output Complement
74 OP_C0 Output High Speed Output
76 LB_C Control1 Loopback Enable for Port C, Active High
77 LB_B Control1 Loopback Enable for Port B, Active High
78 LB_A Control1 Loopback Enable for Port A, Active High
79 LOS_INT Interrupt1 Loss of Signal Interrupt, Active High
80 PE_C Control1 Pre-Emphasis Control for Port C, Active High
81 PE_B Control1 Pre-Emphasis Control for Port B, Active High
82 PE_A Control1 Pre-Emphasis Control for Port A, Active High
83 IN_C3 Input High Speed Input Complement
84 IP_C3 Input High Speed Input
86 IN_C2 Input High Speed Input Complement
87 IP_C2 Input High Speed Input
89 IN_C1 Input High Speed Input Complement
90 IP_C1 Input High Speed Input
92 IN_C0 Input High Speed Input Complement
93 IP_C0 Input High Speed Input

Rev. B | Page 8 of 36

AD8158

Pin No. Mnemonic Type Description

95 SEL3 Control1 Lane 3 A/B Switch Control
96 SEL2 Control1 Lane 2 A/B Switch Control
97 SEL1 Control1 Lane 1 A/B Switch Control
98 SEL0 Control1 Lane 0 A/B Switch Control
99 BICAST Control1

100 SEL4G Control1 Set Transmitter for Low Speed PE, Active High

1

Logic level of control pins referred to DVCC.

2

EQ control pins (EQ_A[1:0], EQ_B[1:0], EQ_C[1:0]) require 5 kΩ in series when DVCC > VCC.

Enable Bicast Mode for Port A and Port B Outputs, Active
High

Rev. B | Page 9 of 36

AD8158

V

V

TYPICAL PERFORMANCE CHARACTERISTICS

50Ω CABLES

DATA OUT

PATTERN

GENERATOR

2 2

INPUT
PIN

OUTPUT

AD8158

AC-COUPLED
EVALUATION

BOARD

Figure 4. Standard Test Circuit (No Channel)

50Ω CABLES

2 2

PIN

50Ω

TP2TP1

OSCILLOSCOPE

HIGH SPEED

SAMPLING

06646-004

200mV/DI

25ps/DIV

Figure 5. 6.5 Gbps Input Eye (TP1 from Figure 4)

06646-005

200mV/DI

25ps/DIV

Figure 6. 6.5 Gbps Output Eye, No Channel (TP2 from Figure 4)

06646-006

Rev. B | Page 10 of 36

AD8158

V

V

V

V

V

200mV/DI

25ps/DIV

REFERENCE EYE DIAGRAM AT TP1

DATA OUT

PATTERN

GENERATOR

50Ω CABLES

2 2

FR4 TEST BACKP LANE

DIFFERENTIAL
STRIPLI NE TRACES

TP1

8mils WI DE, 8mils S P ACE ,
8mils DIEL ECTRIC HEI GHT

TRACE LENGT H S = 20 INCHES,
40 INCHES

Figure 7. Input Equalization Test Circuit

50Ω CABLES

2 2

TP2

INPUT

OUTPUT

PIN

AD8158

AC-COUPLED

EVALUATION

BOARD

50Ω CABLES

2 2

PIN

50Ω

TP3

SAMPLING

OSCILLOSCOPE

HIGH

SPEED

06646-007

200mV/DI

25ps/DIV

06646-008

Figure 8. 6.5 Gbps Input Eye, 20 Inch FR4 Input Channel (TP2 from Figure 7)

200mV/DI

25ps/DIV

06646-009

Figure 9. 6.5 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 7)

200mV/DI

25ps/DIV

06646-010

Figure 10. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel (TP3 from Figure 7)

200mV/DI

25ps/DIV

06646-011

Figure 11. 6.5 Gbps Output Eye, 40 Inch FR4 Input Channel (TP3 from Figure 7)

Rev. B | Page 11 of 36

AD8158

V

V

V

V

V

200mV/DI

25ps/DIV

REFERENCE EYE DIAGRAM AT TP1

DATA OUT

PATTERN

GENERATOR

50Ω CABLES

2 2

TP1

INPUT

OUTPUT

PIN

AD8158

AC-COUPLED
EVALUATION

BOARD

50Ω CABLES

2 2

PIN

Figure 12. Output Pre-emphasis Test Circuit

FR4 TEST BACKP LANE

DIFFERENTIAL
STRIPLI NE TRACES

TP2

8mils WI DE , 8mils SP ACE,
8mils DIELECTRIC HEIGHT

TRACE LENGTHS = 20 INCHES,
30 INCHES

50Ω CABLES

2 2

TP3

50Ω

HIGH

SPEED

SAMPLING

OSCILLOSCOPE

06646-012

200mV/DI

25ps/DIV

Figure 13. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel, PE = 0

(TP3 from Figure 12)

200mV/DI

25ps/DIV

Figure 14. 6.5 Gbps Output Eye, 30 Inch FR4 Input Channel, PE = 0

(TP3 from Figure 12)

200mV/DI

06646-013

25ps/DIV

06646-015

Figure 15. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel, PE = Best Setting,

Default Output Level (TP3 from Figure 12)

100mV/DI

06646-014

25ps/DIV

06646-016

Figure 16. 6.5 Gbps Output Eye, 30 Inch FR4 Input Channel, PE = Best Setting,

200 mV Output Level (TP3 from Figure 12)

Rev. B | Page 12 of 36

AD8158

100

80

80

70

60

60

40

DETERMINI S TIC JITT ER (ps)

20

0

02468

DATA RATE (GHz )

Figure 17. Deterministic Jitter vs. Data Rate

100

80

60

40

DETERMINI S TIC JITT ER (ps)

20

0

01.00.5 1.5 2.0 2.5
DIFFERENTIAL INPUT SWING (V p-p)

Figure 18. Deterministic Jitter vs. Input Swing

50

40

30

20

DETERMINI S TIC JITT ER (ps)

10

0

044.03.53.02.52.01.51.00.5

06646-034

VCC = 3.3V

V

= 1.8V

CC

INPUT COMMON-MODE (V)

.5

06646-037

Figure 20. Deterministic Jitter vs. Input Common Mode

100

80

60

40

DETERMINISTIC JITTER (ps)

20

0

1.0 4.03.53.02.52.01.5

06646-035

VCC (V)

06646-038

Figure 21. Deterministic Jitter vs. VCC

DETERMINI S TIC JITT ER (ps)

100

80

60

40

20

0

–60 100806040200–20–40

TEMPERATURE ( °C)

Figure 19. Deterministic Jitter vs. Temperature

06646-036

Rev. B | Page 13 of 36

100

90

80

70

60

50

(V

CC

40

MIN OUTPUT SWING

30

DETERMINISTIC JITTER (ps)

20

(VCC = 1.8V)

10

DEFAULT OUT P UT SW I NG

0

1.0 4.03.53.02.52.01.5

= 1.8V)

(V

= 3.3V)

CC

MIN OUTPUT SWING

(V
DEFAULT O UT P UT SWING

V

VOLTAGE (V)

TTO

CC

= 3.3V)

Figure 22. Deterministic Jitter vs. Output Termination Voltage (V

TTO

06646-039

)

AD8158

V

100

90

80

= 3.3V)

70

60

50

(VCC = 1.8V)

40

DEFAULT OUTPUT SWING

30

DETERMINISTIC JITTER (ps)

20

= 1.8V)

(V

CC

10

200mV OUTPUT VOLTAGE

0

0.5 3.53.02.52.01.51.0
V

Figure 23. Deterministic Jitter vs. Output Common-Mode Voltage (V

(V

CC

DEFAULT OUTPUT SWING

(V

CC

200mV OUTPUT V OLTAGE

VOLTAGE (V)

OCM

= 3.3V)

OCM

1.0

0.9

0.8

0.7

0.6

AMPLITUDE (V p-p DIFF)

0.5

0.4

1.4 1.9 2.4 2.9 3.4

06646-040

)

Figure 26. Output Amplitude (Default Setting) vs. VCC

1.0

0.9

0.8

CORE VOLTAGE (V)

06646-043

200kSAMPLES/DI

Rj

2ps/DIV

Figure 24. Random Jitter Histogram

100

90

80

(ps)

F

/t

R

t

70

60

50

–60 –40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

Figure 25. tR/tF vs. Temperature

0.7

0.6

AMPLITUDE (V p-p DIFF)

0.5

06646-144

0.4
012345 76

RATE (Gbps)

06646-044

Figure 27. Output Amplitude vs. Rate

1000

950

900

850

800

750

700

DELAY (ps)

650

600

550

500

06646-042

1.6 2.1 2.6 3.1 3.6
CORE SUPPLY VOLTAGE (V)

06646-045

Figure 28. Propagation Delay vs. Core Supply

Rev. B | Page 14 of 36

AD8158

1000

950

900

850

800

750

700

DELAY (ps)

650

600

550

500

–60 –40 –20 0 20 40 60 80 100

TEMPERATURE ( °C)

Figure 29. Propagation Delay vs. Temperature

06646-046

90

80

70

60

50

40

30

DETERMINISTIC JITTER (ps)

20

10

0

01234567

0" DEFAULT OUTPUT SWING
10" DEFAULT OUTPUT SWING
20" DEFAULT OUTPUT SWING
30" DEFAULT OUTPUT SWING
30" 200mV OUTPUT LEVEL

PE SETTING

Figure 32. Deterministic Jitter vs. PE Setting

06646-049

140

120

100

80

60

40

DETERMINI STIC JIT TER (ps)

20

0

NO

0123456789

DUT

EQ SETTING

Figure 30. Deterministic Jitter vs. EQ Setting

10

9

8

7

6

5

4

3

RANDOM JITT ER (ps)

2

1

0

012345678910

EQ SETTING

Figure 31. Random Jitter vs. EQ Setting vs. Trace

0"
10"
20"
30"
40"

0"
10"
20"
30"
40"

10

9

8

7

6

5

4

3

RANDOM JITT ER (ps)

2

1

06646-047

0

0123456 87

0" DEFAULT OUTPUT SWI NG
10" DEFAULT OUTPUT SWING
20" DEFAULT OUTPUT SWING
30" DEFAULT OUTPUT SWING
30" MINIMUM OUTPUT SWING

PE SETTING

06646-050

Figure 33. Random Jitter vs. PE Setting

0

–2

–4

–6

–8

–10

LOSS (dB)

–12

–14

–16

–18

06646-048

–20

6"
10"
20"
30"
40"

FREQUENCY (Hz)

1G100M10M1M100k

06646-051

Figure 34. S21 Test Traces

Rev. B | Page 15 of 36

AD8158

THEORY OF OPERATION

The AD8158 is a buffered, asynchronous, three-port transceiver
that allows 2:1 multiplexing and 1:2 demultiplexing among its
ports. The 1:2 demux path supports bicast operation, allowing
the AD8158 to operate as a port replicator as well as a redundancy
switch. The AD8158 offers loopback on each lane, allowing
the part to be configured as a twelve-lane equalizer or redriver
with FFE.

MUX

RXA

RXB

DEMUX

TXA

TXB

Figure 35. Mux/Demux Paths, Port A to Port C

The part offers extensively programmable transmit output levels
and preemphasis settings as well as squelch or full disable. The
receivers integrate a programmable, multizero transfer function
for aggressive equalization and a programmable loss-of-signal
feature. The AD8158 provides a balanced, high speed switch
core that maintains low lane-to-lane skew while preserving
edge rates.

TXC

RXC

6646-023

The I/O on-chip termination resistors are tied to user-settable
supplies for increased flexibility. The AD8158 supports a wide
primary supply range; V

can be set from 1.8 V to 3.3 V. These

CC

features, together with programmable transmitter output levels,
allow for a wide range of dc- and ac-coupled I/O configurations.

The AD8158 supports several control and configuration modes,
shown in Tab l e 5. The pin control mode offers access to a subset
of the total feature list but allows for a much simplified control
scheme. Table 6 compares the features in all control modes.

The primary advantage of using the serial control interface is
that it allows finer resolution in setting receive equalization,
transmitter preemphasis, loss-of-signal (LOS) behavior, and
output levels.

By default, the AD8158 starts in the pin control mode. Strobing
the RESETb pin sets all on-chip registers to their default values
and uses pins to configure switch connectivity, PE, and EQ
levels. In mixed mode, switch connectivity is still controlled
through the SEL[3:0], LB_[A:C], and BICAST pins. The user
can override PE and EQ settings in mixed mode. In serial
mode, all functions are accessed through registers and the
control pin inputs are ignored, except RESETb.

The AD8158 register set is controlled through a 2-wire I

2

interface. The AD8158 acts only as an I
slave address for the AD8158 I

C slave device. The 7-bit

2

C interface contains the static

2

C

value b1010 for the upper four bits. The lower three bits are
controlled by the input pins, I2C_A[2:0].

Table 5. Control Interface Mode Register

Address Default Register Name Bit Bit Name Functionality Description

0x0F 0x00

Control
interface mode

7:2 Reserved Set to 0.
1:0 Mode[1:0] 00: toggle pin control. Asynchronous control through toggle pins only.

10: mixed control. Switch configuration via toggle pins, register-based
control through the I

2

C serial interface.

11: serial control. Register-based control through the I2C serial interface.

Rev. B | Page 16 of 36

AD8158

Table 6. Features Available Through Toggle Pin or Serial Control

Feature Pin Control Serial Control

Switch Features

BICAST One pin One bit
A/B Lane Select Two pins Two bits
Loopback Three pins Three bits
Speed Select (SEL4G) One pin One bit

Rx Features

EQ Levels Four settings 10 settings
N/P Swap Not available Available
Squelch Enabled Three bits

Tx Features

Programmable Output Levels ±400 mV diff fixed1 ±200 mV diff/±300 mV diff/±400 mV diff/±600 mV diff
PE Levels Two settings >7 settings

1

±400 mV diff indicates a 400 mV amplitude signal measured between two differential nodes. The voltage swing at differential I/O pins is described in this data sheet

both in terms of the differentially measured voltage range (±400 mV diff, for example) and in terms of peak-to-peak differential swing, denoted as mV p-p diff. An
output level setting of ±400 mV diff delivers a differential peak-to-peak output voltage of 800 mV p-p diff.

THE SWITCH (MUX/DEMUX/UNICAST/BICAST/LOOPBACK)

The mux and demux functions of the AD8158 can be controlled
either with the toggle pins or through the register map. The
multiplexer path switches received data from Input Port A or
Input Port B to Output Port C. The SEL[3:0] pins allow switching
lanes independently. The demultiplexer path switches received
data from Input Port C to Output Port A, Output Port B, or (if
bicast mode is enabled) to both Output Port A and Output Port B.

Table 7. Port Selection and Configuration with All
Loopbacks Disabled

Output

BICAST SELx

0 0 Ix_C[3:0] Idle Ix_A[3:0]
0 1 Idle Ix_C[3:0] Ix_B[3:0]
1 0 Ix_C[3:0] Ix_C[3:0] Ix_A[3:0]
1 1 Ix_C[3:0] Ix_C[3:0] Ix_B[3:0]

Port A

When the device is in unicast mode, the output lanes on either
Port A or Port B are in an idle state. In the idle state, the
transmitter output current is set to 0, and the P and N sides of
the lane are pulled up to the output termination voltage through
the on-chip termination resistors. To save power, the unused
receiver automatically disables.

The AD8158 supports port-level loopback, illustrated in Figure 36.
The loopback control pins override the lane select (SEL[3:0])
and bicast control (BICAST) pin settings at the port level. In serial
control mode, Bits [6:4] of Register 0x01 control loopback and
are equivalent to asserting Pin LB_A, Pin LB_B, and Pin LB_C.
Tabl e 8 summarizes the different loopback configurations.

Output
Port B

Output
Port C

The loopback feature is useful for system debug, self-test, and
initialization, allowing system ASICs to compare Tx and Rx
data sent over a single bidirectional link. Loopback can also be
used to configure the device as a four- to 12-lane receive
equalizer or backplane redriver.

Rev. B | Page 17 of 36

AD8158

Ix_C[3:0]

PORT C LO OPBACK

Ox_C[3:0]

X4

X4

1:2 DEMUX

2:1 MUX

Figure 36. Port-Level Loopback

X4

X4

X4

X4

Ox_A[3:0]

Ox_B[3:0]

PORT A LO OPBACK
PORT B LO OPBACK

Ix_A[3:0]

Ix_B[3:0]

6646-024

Table 8. Switch Connectivity vs. Loopback, BICAST, and Port Select Settings

LB_A LB_B LB_C BICAST SEL[3:0] Output Port A Output Port B Output Port C

0 0 0 0 0000 Ix_C[3:0] Idle Ix_A[3:0]
0 0 0 0 1111 Idle Ix_C[3:0] Ix_B[3:0]
0 0 0 1 0000 Ix_C[3:0] Ix_C[3:0] Ix_A[3:0]
0 0 0 1 1111 Ix_C[3:0] Ix_C[3:0] Ix_B[3:0]
0 0 1 0 0000 Ix_C[3:0] Idle Ix_C[3:0]
0 0 1 0 1111 Idle Ix_C[3:0] Ix_C[3:0]
0 0 1 1 0000 Ix_C[3:0] Ix_C[3:0] Ix_C[3:0]
0 0 1 1 1111 Ix_C[3:0] Ix_C[3:0] Ix_C[3:0]
0 1 0 0 0000 Ix_C[3:0] Ix_B[3:0] Ix_A[3:0]
0 1 0 0 1111 Idle Ix_B[3:0] Ix_B[3:0]
0 1 0 1 0000 Ix_C[3:0] Ix_B[3:0] Ix_A[3:0]
0 1 0 1 1111 Ix_C[3:0] Ix_B[3:0] Ix_B[3:0]
0 1 1 0 0000 Ix_C[3:0] Ix_B[3:0] Ix_C[3:0]
0 1 1 0 1111 Idle Ix_B[3:0] Ix_C[3:0]
0 1 1 1 0000 Ix_C[3:0] Ix_B[3:0] Ix_C[3:0]
0 1 1 1 1111 Ix_C[3:0] Ix_B[3:0] Ix_C[3:0]
1 0 0 0 0000 Ix_A[3:0] Idle Ix_A[3:0]
1 0 0 0 1111 Ix_A[3:0] Ix_C[3:0] Ix_B[3:0]
1 0 0 1 0000 Ix_A[3:0] Ix_C[3:0] Ix_A[3:0]
1 0 0 1 1111 Ix_A[3:0] Ix_C[3:0] Ix_B[3:0]
1 0 1 0 0000 Ix_A[3:0] Idle Ix_C[3:0]
1 0 1 0 1111 Ix_A[3:0] Ix_C[3:0] Ix_C[3:0]
1 0 1 1 0000 Ix_A[3:0] Ix_C[3:0] Ix_C[3:0]
1 0 1 1 1111 Ix_A[3:0] Ix_C[3:0] Ix_C[3:0]
1 1 0 0 0000 Ix_A[3:0] Ix_B[3:0] Ix_A[3:0]
1 1 0 0 1111 Ix_A[3:0] Ix_B[3:0] Ix_B[3:0]
1 1 0 1 0000 Ix_A[3:0] Ix_B[3:0] Ix_A[3:0]
1 1 0 1 1111 Ix_A[3:0] Ix_B[3:0] Ix_B[3:0]
1 1 1 0 0000 Ix_A[3:0] Ix_B[3:0] Ix_C[3:0]
1 1 1 0 1111 Ix_A[3:0] Ix_B[3:0] Ix_C[3:0]
1 1 1 1 0000 Ix_A[3:0] Ix_B[3:0] Ix_C[3:0]
1 1 1 1 1111 Ix_A[3:0] Ix_B[3:0] Ix_C[3:0]

Rev. B | Page 18 of 36

AD8158

RECEIVERS

The AD8158 receivers incorporate 50 Ω on-chip termination,
ESD protection, and a multizero equalization function capable
of delivering up to 18 dB of boost at 4.25 GHz. The AD8158 can
compensate signal degradation at 6.5 Gbps from over 40 inches
of FR4 backplane trace. The receive path also incorporates a
loss-of-signal (LOS) function that squelches the associated
transmitter when the midband differential voltage falls below a
specified threshold value. Finally, the receivers implement a sign­swapping option (P/N swap), which allows the user to invert the
sign of the input signal path and eliminates the need for board­level crossovers in the receive channels.

Input Structure and Allowed Input Levels

The AD8158 tolerates an input common-mode range (meas­ured with zero differential input) of

V

+ 0.6 V < V

EE

< VCC + 0.3 V

ICM

Equalizer Settings

Every input lane offers a low power, asynchronous, programma­ble receive equalizer for NRZ data up to 6.5 Gbps. The pin control
interface allows two levels of receive equalization. Register-based
control allows the user 10 equalizer settings. Register and pin
control boost settings are listed in Tabl e 10 . Equalization capa­bility and resulting jitter performance are illustrated in Figure 30,
Figure 31, and Figure 34. Figure 34 shows the loss characteristic
of various reference channels, and Figure 30 and Figure 31 show
resulting DJ and RJ performance vs. equalizer setting against these
channels.

The four LSBs of Register 0x41, Register 0x81, and Register 0xC1
allow programming of all the equalizers in a port simultane­ously (see Ta ble 13). The 0x42, 0x82, and 0xC2 registers allow
per-lane programming of the equalizers (see Table 2 2). Be
aware that writing to the port-level equalizer registers updates
and overwrites per-lane settings.

Typical supply configurations include, but are not limited to,
those listed in Tab l e 9.

Table 9. Typical Input Supply Configurations

Configuration DVCC V

Low V

, AC-Coupled Input 3.3 V − 1.8 V 1.8 V 1.6 V

TTI

V

CC

TTI

Single 1.8 V Supply 3.3 V − 1.8 V 1.8 V 1.8 V

3.3 V Core 3.3 V 3.3 V 1.8 V
Single 3.3 V Supply 3.3 V 3.3 V 3.3 V

When dc-coupling with LVDS, CML, or ECL signals, it can
be advantageous to operate with split or negative supplies
(see the Applications Information section). In these appli­cations, it is necessary to observe the maximum voltage ratings
between V
V

in the range of V

TTI

and VEE and to select supply voltages for V

CC

to VEE to avoid activating the ESD

CC

TTO

and

protection devices.

V

CC

V

IP_xx

IN_xx

V

TTI

RP

52Ω

EE

RN
52Ω

750Ω

750Ω

RLN

RL

R1

R3
1kΩ

R2

Figure 37. Simplified Receiver Input Structure

Q1

RLP
RL

Q2

I1

Table 10. Equalizer Settings

Equalization
Boost (dB) EQ Register Setting EQ[1:0] Pins

0 0 00
2 1 N/A
4 2 01
6 3 N/A
8 4 10
10 5 N/A
12 6 N/A
14 7 N/A
16 8 N/A
18 9 11

V

CC

V

TTI

IP_xx

IN_xx

V

EE

Figure 38. Functional Diagram of the AD8158 Receiver

06646-138

R

ON-CHIP TERMINATIONESD

TERM

RP

RN
R

TERM

EQUALIZER

V

THRESH

LOSS

OF

SIGNAL

DETECT

EQ OUT

SIG

06646-137

Rev. B | Page 19 of 36

AD8158

Lane Disables

By default, the receivers and transmitters enable in an on-demand
fashion according to the state of the SEL[3:0], LB_[A:C], and
BICAST pins or to the state of the equivalent registers in serial
control mode. Register 0x40, Register 0x80, and Register 0xC0
implement per-lane disables for the receivers, and Register 0x48,
Register 0x88, and Register 0xC8 implement per-lane transmit­ter disables. These disables override the default settings. Each
bit in the register is named for the lane and function it disables.
For example, RXDIS B0 disables the receiver on Lane 0 of Port B
whereas TXDIS C1 disables the Lane 1 transmitter of Port C
(see Tabl e 11 ).

Table 11. Per-Lane Disables

Address Port Default Register Name Bit Bit Name Functionality Description

0x40 Port A 0x00 RX[A/B/C] disable 7:4 Reserved Set to 0
0x80 Port B 0x00 3 RXDIS [A/B/C]3 0: RX Port [A/B/C], Lane 3, enabled

0xC0 Port C 0x00 2 RXDIS [A/B/C]2 0: RX Port [A/B/C], Lane 2, enabled

1 RXDIS [A/B/C]1 0: RX Port [A/B/C], Lane 1, enabled

0 RXDIS [A/B/C]0 0: RX Port [A/B/C], Lane 0, enabled

0x48 Port A 0x00 TX[A/B/C] disable 7:4 Reserved Set to 0
0x88 Port B 0x00 3 TXDIS [A/B/C]3 0: TX Port [A/B/C], Lane 3 enabled

0xC8 Port C 0x00 2 TXDIS [A/B/C]2 0: TX Port [A/B/C], Lane 2 enabled

1 TXDIS [A/B/C]1 0: TX Port [A/B/C], Lane 1, enabled

0 TXDIS [A/B/C]0 0: TX Port [A/B/C], Lane 0, enabled

Lane Inversion: P/N Swap

The receiver P/N swap function is a convenience intended to
allow the user to implement the equivalent of a board-level
routing crossover in a much smaller area while eliminating vias
(impedance discontinuities) that compromise the high frequency
integrity of the signal path. Using this feature to correct an
inversion downstream of the receiver may require the user to be
aware of the sign of the data when switching connectivity (the
mux/demux path). The feature is available on a per-lane setting
through Register 0x44, Register 0x84, and Register 0xC4.
Setting the bit true flips the sign sense of the P and N inputs for
the associated lane. The default setting is 0 (no inversion).

1: RX Port [A/B/C], Lane 3, disabled

1: RX Port [A/B/C], Lane 2, disabled

1: RX Port [A/B/C], Lane 1, disabled

1: RX Port [A/B/C], Lane 0, disabled

1: TX Port [A/B/C], Lane 3 disabled

1: TX Port [A/B/C], Lane 2 disabled

1: TX Port [A/B/C], Lane 1, disabled

1: TX Port [A/B/C], Lane 0, disabled

Table 12. Lane Inversion

Address Port Default Register Name Bit Bit Name Functionality Description

0x44 Port A 0x00 RX[A/B/C] P/N swap 7:4 Reserved Set to 0
0x84 Port B 0x00 3 PN[A/B/C]3 0: Lane 3 noninverted

1: Lane 3 inverted

0xC4 Port C 0x00 2 PN[A/B/C]2 0: Lane 2 noninverted

1: Lane 2 inverted

1 PN[A/B/C]1 0: Lane 1, noninverted

0 PN[A/B/C]0 0: Lane 0, noninverted

1: Lane 1, inverted

1: Lane 0, inverted

Table 13. Port-Level EQ Setting

Address Port Default Register Name Bit Bit Name Functionality Description

0x41 Port A 0x00 RX[A/B/C] EQ setting 7:4 Reserved Set to 0
0x81 Port B 0x00 3:0 [A/B/C]EQ[3:0]
0xC1 Port C 0x00

Rev. B | Page 20 of 36

AD8158

LOSS OF SIGNAL (LOS)

The serial control interface allows access to the AD8158 loss-of­signal features (LOS is not available in pin control mode). Each
receiver includes a low power, loss-of-signal detector. The loss-of­signal circuit monitors the received data stream and generates
a system interrupt when the received signal power falls below a
fixed threshold. The threshold is 50 mV p-p diff, referred to the
input pins. The LOS circuit monitors the equalized receive wave­form and integrates the rms power of the equalized waveform over
a selectable interval of either 2 ns or 10 ns. The detectors are
enabled on a per-port basis with Bit 0 of the RXA/B/C LOS control
registers (0x51, 0x91, 0xD1).

The squelch feature can be disabled with Bit 3 of the global
squelch control register (0x04).

The LOS_INT pin evaluates a logical OR of all LOS status
register bits for all enabled receivers (LOS status registers are
located at 0x45, 0x85, and 0xC5). The upper two bits in the
RXA, RXB, and RXC LOS status registers are sticky, whereas
the two LSBs are continuously updated to indicate the instantan­eous status of LOS for an enabled receiver. The sticky bits are
cleared by writing 0 to the RXA, RXB, and RXC LOS status
registers. The LOS_INT pin remains high after an LOS event
until all sticky registers are cleared and all active status registers
(for example, Bits[3:0]) read 0.

By default, when the receiver detects an LOS event, it squelches
its associated transmitter, lowering the output current to
submicroamps. This prevents the high gain, wide bandwidth
signal path from turning low level system noise on an undriven
input pair into a source of hostile crosstalk at the transmitter.

The LOS_INT pin can be used to generate an interrupt for the
system control software. In a standard implementation, when
LOS_INT goes high, the system software registers the interrupt
and polls the RXA, RXB, and RXC LOS status registers to
determine which input lost signal and whether the signal has
been restored.

Table 14. Global Loss-of-Signal Squelch Control Register

Address Default Register Name Bit Bit Name Functionality Description

0x04 0x0F Global Squelch Ctrl 7:4 Reserved Set to 0
3 GSQLCH_ENB 0: LOS auto squelch disabled
1: LOS auto squelch enabled
2:0 Reserved Set to 1

Table 15. Port-Level Loss-of-Signal Control Registers

Address Port Default Register Name Bit Bit Name Functionality Description

0x51 Port A 0x05
0x91 Port B 0x05 2 LOS_FILT 0: LOS filter time constant = 2 ns
0xD1 Port C 0x05 1: LOS filter time constant = 10 ns
1 Reserved Set to 0
0 LOS_ENB 0: LOS disabled

RX[A/B/C] LOS
control

7:3 Reserved Set to 0

1: LOS enabled

Table 16. Port-Level Loss-of-Signal Status Registers

Address Port Default Register Name Bit Bit Name Functionality Description

0x45
0x85

0xC5

3:0

Port A
Port B
Port C

Read only
Write 0 to clear

RX[A/B/C] LOS
status

7:4

LOS[A/B/C][3:0]
sticky

LOS[A/B/C][3:0]
active

0000: LOS event has not occurred.
0001: LOS event has occurred on Lane 0.
0010: LOS event has occurred on Lane 1.
0100: LOS event has occurred on Lane 2.
1000: LOS event has occurred on Lane 3.
1111: LOS event has occurred on all lanes.

0000: active signals on all lanes.
0001: inactive signal on Lane 0.
0010: inactive signal on Lane 1.
0100: inactive signal on Lane 2.
1000: inactive signal on Lane 3.
1111: inactive signals on all lanes.

Rev. B | Page 21 of 36

AD8158

TRANSMITTERS

The AD8158 transmitter offers programmable preemphasis,
programmable output levels, output disable, and transmit
squelch. The SEL4G pin lets the user lower the transmitter
frequency of maximum boost from 3.25 GHz to 2.0 GHz,
allowing the AD8158 to offer exceptional transmit channel
compensation for legacy applications (4.5 Gbps and slower).

V

ON-CHIP TERMINATION ESD

V3
VC

V2

VP

V1
VN

Figure 39. Simplified Transmitter Structure

R

I

DC

RP

TERM

+ I

RN
R

TERM

Q1

Q2

IT

PE

Output Level Programming and Output Structure

The output level of the transmitter of each lane is independently
programmable. In pin control mode, a default output amplitude
of 800 mV p-p diff (±400 mV diff) is delivered (see Ta b le 1 7 ).
Register-based control allows the user to set the transmitter
output levels on a per-port or per-lane basis to four predefined
levels. Port-level programming overwrites lane-level configuration.
The ALEV, BLEV, and CLEV bits in Register 0x49, Register 0x89,
and Register 0xC9, respectively, are used to set the output levels
for all transmitters. The A[3:0]OLEV[1:0], B[3:0]OLEV[1:0],
and C[3:0]OLEV[1:0] bits in Register 0x4C, Register 0x8C, and
Register 0xCC allow per-lane settings (see Tabl e 22).

Table 17. Predefined Output Levels

[A/B/C][3:0]OLEV[1] [A/B/C][3:0]OLEV[0] Output Level

0 0 ±200 mV diff
0 1 ±300 mV diff
1 0

±400 mV diff
(default)

1 1 ± 600 mV diff

Note that the choice of output level influences the output
common-mode level. A 600 mV diff output level with a full PE
range requires a supply and output termination voltage of 2.5 V
or higher (V

, VCC ≥ 2.5 V).

TTO

Preemphasis

Transmitter preemphasis levels can be set by pin control or
through the control registers. Pin control allows two settings of
PE, 0 dB and 6 dB. The control registers provide seven levels of
PE. Note that a larger range of boost settings is available for lower
output levels. Note that toggle pin control of PE is limited to the
400 mV diff output level settings. Tab l e 1 8 lists the available
preemphasis settings for each output level.

CC

V

TTO

OP_xx
ON_xx

V

EE

06646-139

Preemphasis can be programmed per port or per lane. Register
0x49, Register 0x89, and Register 0xC9 set all outputs in a port
at once. Registers 0x4A, 0x8A, and 0xCA allow setting PE on a
per-lane basis. The following equation sets preemphasis boost:

Table 18. Setting Transmitter Preemphasis

Output Level
(mV diff)

200 N/A 000 0 0
200 N/A 001 50 3.52
200 N/A 010 100 6.02
200 N/A 011 150 7.96
200 N/A 100 200 9.54
200 N/A 101 250 10.88
200 N/A 110 300 12.04
300 N/A 000 0 0
300 N/A 001 33 2.5
300 N/A 010 67 4.44
300 N/A 011 100 6.02
300 N/A 100 133 7.36
300 N/A 101 167 8.52
300 N/A 110 200 9.54
400 0 000 0 0
400 N/A 001 25 1.94
400 N/A 010 50 3.52
400 N/A 011 75 4.86
400 1 100 100 6.02
400 N/A 101 125 7.04
400 N/A 110 150 7.96
600 N/A 000 0 0
600 N/A 001 17 1.34
600 N/A 010 33 2.5
600 N/A 011 50 3.52
600 N/A 100 67 4.44
600 N/A 101 83 5.26
600 N/A 110 100 6.02

Squelch and Disable

Each transmitter is equipped with disable and squelch controls.
Disable is a full power-down state: the transmitter current is
reduced to zero and the output pins pull up to V
is a delay of approximately 1 μs associated with reenabling
the transmitter. Squelch keeps the output current enabled such
that both output pins are at the output common-mode voltage.
The transmitter recovers from squelch in less than 64 ns.

Speed Select

The SEL4G pin lets the user lower the transmitter frequency of
maximum boost from 3.25 GHz to 2.0 GHz, allowing the
AD8158 to offer exceptional transmit channel compensation for
legacy applications (4.5 Gbps and slower). SEL4G = 1 lowers the

dBGain

10

Pin
PE_[A/B/C]

+×=

−

V

−

Bit
PE[2:0]

VV

DCSW

−−

DCSWPESW

(1)

)1(log20][

PE Boost
(%)

, but there

TTO

PE Boost
(dB)

Rev. B | Page 22 of 36

AD8158

A

V

frequency of maximum boost without sacrificing the amount of
boost delivered.

AD8158 POWER CONSUMPTION

There are several sections of the AD8158 that draw varying
power depending on the supply voltages, the type of I/O coupling
used, and the status of the AD8158 operation. Figure 40 shows a
block diagram of these sections.

The first section consists of the input termination resistors. The
power dissipated in the termination resistors is due to the input
differential swing and any common-mode current resulting
from dc-coupling the input.

In the next section (the receiver section), each input is powered
only when it is selected, and the disable bits are set to 0. If a
receiver is not selected, it is powered down. Thus, the total
number of active inputs affects the total power consumption.
Furthermore, the loss-of-signal detection circuits can be
disabled independent of the receiver for even greater power
savings.

The core of the device performs the multiplexer and demulti­plexer switching functions. It draws a fixed quiescent current of
2 mA whenever the AD8158 is powered from V
switch draws an additional 8 × 4.6 mA in normal mux/demux
operation and an additional 12 × 4.6 mA with all ports in loop­back or with bicast selected. The switch core can be disabled to
save power.

An output predriver section draws a current, I
related to the programmed output current, I
current always flows from V

to VEE. It is treated separately

CC

from the output current, which flows from V
the same voltage as V

.

CC

to VEE. The

CC

, that is

PRED

. The predriver

TTO

and may not be

TTO

separate paths. One is the on-chip termination resistor, and the
other is the transmission line and the destination termination
resistor. The nominal parallel impedance of these two paths is
25 Ω. The sum of these two currents flows through the switches
and the current source of the AD8158 output circuit and out
through V

. The power dissipated in the transmission line and the

EE

destination resistor is not dissipated in the AD8158 but must be
supplied from the power supply and is a factor in overall system
power. The current in the on-chip termination resistors and the
output current source dissipate power in the AD8158 itself.

Outputs

The output current is set by a combination of output level and
preemphasis settings (see Tab le 19). For the two logic switch
states, this current flows through an on-chip termination
resistor and a parallel path to the destination device and its
termination resistor. The power in this parallel path is not
dissipated by the AD8158. With preemphasis enabled, some
current always flows in both the P and N termination resistors.
This preemphasis current gives rise to an output common­mode shift, which varies with ac-coupling or dc-coupling and
which is calculated for both cases in Ta b l e 1 9 .

Perhaps the most direct method for calculating power dissi­pated in the output is to calculate the power that would be
dissipated if all of I

were to flow on-die from V

TTO

TTO

to VEE
and to subtract from this the power dissipated off die in the
destination device termination resistors and the channel.
For this purpose, the destination device and channel can be
modeled as 50 Ω load resistors, R

, in parallel with the AD8158

L

termination resistors.

The final section is the outputs section. For an individual
output, the programmed output current flows through two

DV

CC

DIGITAL

OUTPUT

CONTROL

REFERENCES/

BIAS CIRCUITRY

EE

V

50Ω 50Ω

PREDRIVERS

TTO

OUTPUT
TERMINATIONS

P = × 50Ω

OPTIONAL CO UP L I NG
CAPACITORS

P = (V

I

OUT

V

VTT

I

OUT

2

) (I

OL

OUT

= V

– (I

OL

TTO

)

OUT

× 25Ω)

50Ω50Ω

06646-141

IP_xx

IN_xx

C-COUPLING CAPS

(OPTIONAL)

INPUT

TERMINATION

(V

IN_DIFF_RMS

P =

V

100Ω

TTI

EQUALIZER

LOSS OF

SIGNAL

2

)

RECEIVER SWITCH

CC

V

Figure 40. AD8158 Power Distribution Block Diagram

Rev. B | Page 23 of 36

AD8158

Power Saving Considerations

Whereas the AD8158 power consumption is very low compared
to similar devices, careful control of its operating conditions can
yield further power savings. Significant power reduction can be
realized by operating the part at a lower voltage. Compared to

3.3 V operation, a supply voltage of 1.8 V can result in power
savings of ~45%. There is no performance penalty when oper­ting at lower voltage.

A second measure is to disable transmitters when they are not
being used. This can be done on a static basis if the output is
not used or on a dynamic basis if the output does not have a
constant stream of traffic. On transmit disable (Register 0x48,
Register 0x88, Register 0xC8), both the predriver and output
switch currents are disabled. The LOS-activated squelch
disables only the output switch current, I
saving is achieved by using the TX and RX disable registers to

. Superior power

TTO

turn off an unused lane as opposed to relying on the AD8158
transmit squelch feature.

Because the majority of the power dissipated is in the output
stage, some of its flexibility can be used to lower the power
consumption. First, the output current and output preemphasis
settings can be programmed to the smallest amount required to
maintain BER performance. If an output circuit always has a
short length and the receiver has good sensitivity, then a lower
output current can be used.

It is also possible to lower the voltage on V
power dissipation. The amount that V
dependent on the lowest of all the output’s V

to lower the

TTO

can be lowered is

TTO

and VCC. This

OL

is determined by the output that is operating at the highest
programmed output current. Ta b le 1 and Tab l e 19 list minimum
output levels.

Rev. B | Page 24 of 36

AD8158

I2C CONTROL INTERFACE

SERIAL INTERFACE GENERAL FUNCTIONALITY

The AD8158 register set is controlled through a 2-wire I2C
interface. The AD8158 acts only as an I
7-bit slave address for the AD8158 I2C interface contains the
static value b1010 for the upper four bits. The lower three bits
are controlled by the input pins, I2C_A[2:0].

Therefore, the I

2

C bus in the system must include an I2C master
to configure the AD8158 and other I
the bus. Data transfers are controlled through the use of the two

2

I

C wires: the SCL input clock pin and the SDA bidirectional

data pin.

2

The AD8158 I

C interface can be run in the standard (100 kHz)
and fast (400 kHz) modes. The SDA line changes value only
when the SCL pin is low, with two exceptions. To indicate the
beginning or continuation of a transfer, the SDA pin is driven
low while the SCL pin is high, and to indicate the end of a
transfer, the SDA line is driven high while the SCL line is high.
Therefore, it is important to control the SCL clock to toggle
only when the SDA line is stable unless indicating a start,
repeated start, or stop condition.

2

C slave device. The

2

C devices that may be on

I2C INTERFACE DATA TRANSFERS: DATA WRITE

To write data to the AD8158 register set, a microcontroller or
any other I
to the AD8158 slave device. The following steps must be taken,
where the signals are controlled by the I
wise specified. For a diagram of the procedure, see Figure 41.

1. Send a start condition (while holding the SCL line high,

2. Send the AD8158 part address (seven bits) whose upper

3. Send the write indicator bit (0).

4. Wait for the AD8158 to acknowledge the request.

5. Send the register address (eight bits) to which data is to be

2

C master must send the appropriate control signals

2

C master, unless other-

pull the SDA line low).

four bits are the static value b1010 and whose lower three
bits are controlled by the I2C_A[2:0] input pins. This
transfer should be MSB first.

written. This transfer should be MSB first.

6. Wait for the AD8158 to acknowledge the request.

7. Send the data (eight bits) to be written to the register whose

address was set in Step 5. This transfer should be MSB first.

8. Wait for the AD8158 to acknowledge the request.

9. Do one or more of the following:
a. Send a stop condition (while holding the SCL line

high, pull the SDA line high) and release control of
the bus.

b. Send a repeated start condition (while holding the

SCL line high, pull the SDA line low) and continue
with Step 2 in this procedure to perform another write.

c. Send a repeated start condition (while holding the

SCL line high, pull the SDA line low) and continue
with Step 2 of the read procedure (in the I

2

C Interface
Data Transfers: Data Read section) to perform a read
from another address.

d. Send a repeated start condition (while holding the

SCL line high, pull the SDA line low) and continue
with Step 8 of the read procedure (in the I

2

C Interface
Data Transfers: Data Read section) to perform a read
from the same address set in Step 5.

In Figure 41, the AD8158 write process is shown. The SCL
signal is shown along with a general write operation and a
specific example. In this example, the value 0x92 is written to
Address 0x6D of an AD8158 device with a part address of 0x53.
The part address is seven bits wide and is composed of the
AD8158 static upper four bits (b1010) and the pin-programmable
lower three bits (I2C_A[2:0]). The address pins are set to b011.
In Figure 41, the corresponding step number is visible in the
circle under the waveform. The SCL line is driven by the I

2

C
master and never by the AD8158 slave. As for the SDA line, the
data in the shaded polygons is driven by the AD8158, whereas
the data in the nonshaded polygons is driven by the I

2

C master.

The end phase case shown is that of Step 9a.

It is important to note that the SDA line changes only when the
SCL line is low, except for the case of sending a start, stop, or
repeated start condition (Step 1 and Step 9 in this case).

SCL

START R/W ACK ACK ACK STOPDATA

SDA

SDA

1 2 2 3 4 5 6 7 8 9a

b1010 REGISTER ADDR

ADDR

[2:0]

Figure 41. I

2

C Write Diagram

06646-142

Rev. B | Page 25 of 36

AD8158

ASDA

I2C INTERFACE DATA TRANSFERS: DATA READ

To read data from the AD8158 register set, a microcontroller or
any other I
to the AD8158 slave device. The following steps must be taken,
where the signals are controlled by the I
wise specified. For a diagram of the procedure, see Figure 42.

1. Send a start condition (while holding the SCL line high,

2. Send the AD8158 part address (seven bits) whose upper

3. Send the write indicator bit (0).

4. Wait for the AD8158 to acknowledge the request.

5. Send the register address (eight bits) from which data is to

6. Wait for the AD8158 to acknowledge the request.

7. Send a repeated start condition (while holding the SCL line

8. Send the AD8158 part address (seven bits) whose upper

9. Send the read indicator bit (1).

10. Wait for the AD8158 to acknowledge the request.

11. The AD8158 then serially transfers the data (eight bits)

12. Acknowledge the data.

13. Do one or more of the following:

2

C master must send the appropriate control signals

2

C master, unless other-

pull the SDA line low).

four bits are the static value b1010 and whose lower three
bits are controlled by the I2C_A[2:0] input pins. This
transfer should be MSB first.

be read. This transfer should be MSB first. The register
address is kept in memory in the AD8158 until the part is
reset or the register address is written over with the same
procedure (Step 1 to Step 6).

high, pull the SDA line low).

four bits are the static value b1010 and whose lower three
bits are controlled by the I2C_A[2:0] input pins. This
transfer should be MSB first.

held in the register indicated by the address set in Step 5.

a. Send a stop condition (while holding the SCL line high,

pull the SDA line high) and release control of the bus.

b. Send a repeated start condition (while holding the

SCL line high, pull the SDA line low) and continue
with Step 2 of the write procedure (see the I

2

C
Interface Data Transfers: Data Write section) to
perform a write.

c. Send a repeated start condition (while holding the

SCL line high, pull the SDA line low) and continue
with Step 2 of this procedure to perform a read from
another address.

d. Send a repeated start condition (while holding the

SCL line high, pull the SDA line low) and continue
with Step 8 of this procedure to perform a read from
the same address.

In Figure 42, the AD8158 read process is shown. The SCL signal is
shown along with a general read operation and a specific example.
In this example, the value 0x49 is read from Address 0x6D of
an AD8158 device with a 0x53 part address. The part address
is seven bits wide and is composed of the AD8158 static upper
four bits (b1010) and the pin-programmable lower three bits
(I2C_A[2:0]). The address pins are set to b011. In Figure 42, the
corresponding step number is visible in the circle under the
waveform. The SCL line is driven by the I

2

C master and never
by the AD8158 slave. As for the SDA line, the data in the shaded
polygons is driven by the AD8158, whereas the data in the
nonshaded polygons is driven by the I

2

C master. The end phase

case shown is that of Step 13a.

It is important to note that the SDA line changes only when
the SCL line is low, except for the case of sending a start, stop,
or repeated start condition, as in Step 1, Step 7, and Step 13.
In Figure 42, A is the same as ACK. Equally, Sr represents a
repeated start where the SDA line is brought high before SCL
is raised. SDA is then dropped while SCL is still high.

SCL

SD

ADDR

b1010 A A Sr DATA A STOPREGISTER ADDRSTART

1 2 2 3 4 5 6 7 8 8 9 10 11 12 13a

[2:0]

R/
W

Figure 42. I

2

b1010

C Read Diagram

ADDR

[2:0]

R/

A

W

06646-143

Rev. B | Page 26 of 36

AD8158

APPLICATIONS INFORMATION

The main application of the AD8158 is to support redundancy
on both the backplane side and the line interface side of a
serial link. Each port consists of four lanes to support standards
such as XAUI. Figure 43 illustrates redundancy in an XAUI
backplane system. Each line card is connected to two switch
fabrics (primary and redundant). The device can be configured

to support either 1 + 1 or 1:1 redundancy. Also, the AD8158 can
enable module redundancy, as shown in Figure 44, and can be
used as a four-, eight- or 12-lane signal conditioning device to
enable high speed serial communication over long copper links.

PHYSICAL

INTERFACE

PHYSICAL

INTERFACE

MACs

FRAMERS

MACs

FRAMERS

PRIMARY

MODULE

REDUNDANT

MODULE

FABRIC INTERFACE

TRAFFIC MANAG E RS

NETWORK PRO CE S S OR

AD8158

LINE CARDS

FABRIC INTERFACE

TRAFFIC MANAG E RS

NETWORK PRO CE S S OR

Figure 43. Using the AD8158 for Switch Redundancy

MACs

FRAMERS

AD8158

LINE CARD

Figure 44. Using the AD8158 for Module Redundancy

Z

0

IN 1

Z

0

EQ PE

OUT 1

BACKPLANE

FABRIC INTERF ACE

TRAFFIC M ANAG E RS

NETWORK PROCESSOR

Z

0

Z

0

PRIMARY

SWITCH
FABRIC

FABRIC CARDS

REDUNDANT

SWITCH
FABRIC

06646-146

06646-145

Z

0

Z

0

Z

0

Z

0

Z

0

Z

0

LOSSY CHANNE LLOSSY CHANNE L

ASIC 2

06646-147

ASIC 1

Z

0

IN 4

Z

0

Z

0

OUT 5

Z

0

Z

0

OUT 8

Z

0

EQ

PE EQ

PE EQ

PE

OUT 4

IN 5

IN 8

Figure 45. Using the AD8158 for Signal Conditioning

Rev. B | Page 27 of 36

AD8158

OUTPUT COMPLIANCE

In low voltage applications, users must pay careful attention
to both the differential and common-mode signal levels. The
choice of output voltage swing, preemphasis setting, supply
voltages (V
peak and settled single-ended voltage swings and the common­mode shift measured across the output termination resistors.
These choices also affect output current and, consequently,
power consumption. For certain combinations of supply voltage
and output coupling, output voltage swing and preemphasis
settings may violate the single-ended absolute output low
voltage, as specified in Tabl e 1. Under these conditions, the
performance is degraded; therefore, these settings are not
recommended. Tabl e 19 includes annotations that identify
these settings.

Tabl e 19 shows the change in output common mode (ΔV

− V

V

CC

Tabl e 19 also shows the minimum and maximum peak single­ended output levels (V
ended output levels are calculated for V
and 1.8 V for both ac- and dc-coupled outputs to illustrate
the practical challenges of reducing the supply voltage.

TX_HEADROOM

For output levels greater than 400 mV diff (800 mV p-p diff),
setting the TX_HEADROOM bit to 1 allows the transmitter
an extra 200 mV of output compliance range. When the TX_
HEADROOM bit is enabled, a core supply voltage, V
is required. Enabling TX_HEADROOM increases the core
supply current. TX_HEADROOM can be enabled on a per-port
basis through Bits[6:4] in Register 0x05. A value of 0 disables the
headroom-generating circuitry; a value of 1 enables it.

Example 1: 1.8 V, PE Disabled

Consider a typical application using pin control mode. In this
case, the default output level of 400 mV diff (800 mV p-p diff)
is selected, and the user can choose preemphasis settings of

and V

CC

) with output level (VSW) and preemphasis setting.

OCM

), and output coupling (ac or dc) affect

TTO

L-PE

and V

, respectively). The single-

H-PE

supplies of 3.3 V

TTO

OCM

≥ 2.5 V,

CC

=

0 dB or 6 dB. Table 19 shows that with preemphasis disabled,
a dc-coupled transmitter causes a 200 mV common-mode shift
across the termination resistors, whereas an ac-coupled transmitter
causes twice the common-mode shift. Notice that with V

powered from a 1.8 V supply, the single-ended output voltage

V

TTO

CC

and

swings between 1.8 V and 1.4 V when dc-coupled and between

1.6 V and 1.2 V when ac-coupled. In both cases, these levels are
greater than the minimum V
the minimum V

limit of 1.8 V with the TX_HEADROOM bit

CC

limit of 725 mV, and VCC satisfies

L

set to 0. Note that setting TX_HEADROOM = 1 violates the
minimum V

limit of 2.5 V.

CC

Example 2: 1.8 V, PE = 6 dB

With a PE setting of 6.02 dB, the ac-coupled transmitter has
single-ended swings from 1.4 V to 0.6 V, whereas the dc­coupled transmitter outputs swing between 1.8 V and 1 V. The
peak minimum single-ended swing (V
transmitter, in this case, exceeds the minimum V

) of the ac-coupled

L-PE

limit of

L

725 mV by 125 mV. While theoretically in violation of the
specification, in practice, this setting is viable, especially at high
data rates. The transmitter theoretical peak voltage is rarely
achieved in practice because the high frequency characteristic
of the preemphasis is attenuated at the output pins by the low­pass nature of the PC board environment and the channel. For

6.5 Gbps PE (SEL4G = 0), a 30% reduction of overshoot as
measured at the PC board is possible. For an output level of
400 mV diff and a PE setting of 6 dB, the user can calculate a
maximum overshoot of 400 mV diff but can measure only a
270 mV overshoot. With the preemphasis configured for

4.25 Gbps operation (SEL4G = 1), the measured overshoot
more closely matches the theoretical maximum. In this case, the
peak minimum voltage limit should be more closely observed.

Rev. B | Page 28 of 36

AD8158

SIGNAL LEVELS AND COMMON-MODE SHIFT FOR AC-COUPLED AND DC-COUPLED OUTPUTS

Table 19. Output Voltage Range and Output Common-Mode Shift vs. Output Level and PE Setting

AC-Coupled Transmitter DC-Coupled Transmitter

Output Levels and PE Boost

V

SW-DC

(mV)

1

V
(mV)

SW-PE

PE

1

Boost
(%)

PE (dB)

Setting

TX[A/B/C]
Level/PE
Control

200 200 0.00 0.00 0x00 8 200 3.2 3 1.7 1.5 100 3.3 3.1 1.8 1.6
200 300 50.00 3.52 0x01 12 300 3.15 2.85 1.65 1.35 150 3.3 3 1.8 1.5
200 400 100.00 6.02 0x02 16 400 3.1 2.7 1.6 1.2 200 3.3 2.9 1.8 1.4
200 500 150.00 7.96 0x03 20 500 3.05 2.55 1.55 1.05 250 3.3 2.8 1.8 1.3
200 600 200.00 9.54 0x04 24 600 3 2.4 1.5 0.9 300 3.3 2.7 1.8 1.2
200 700 250.00 10.88 0x05 28 700 2.95 2.25 1.45 0.75 350 3.3 2.6 1.8 1.1
200 800 300.00 12.04 0x06 32 800 2.9 2.1 1.4 0.6 400 3.3 2.5 1.8 1
300 300 0.00 0.00 0x10 12 300 3.15 2.85 1.65 1.35 150 3.3 3 1.8 1.5
300 400 33.33 2.50 0x11 16 400 3.1 2.7 1.6 1.2 200 3.3 2.9 1.8 1.4
300 500 66.67 4.44 0x12 20 500 3.05 2.55 1.55 1.05 250 3.3 2.8 1.8 1.3
300 600 100.00 6.02 0x13 24 600 3 2.4 1.5 0.9 300 3.3 2.7 1.8 1.2
300 700 133.33 7.36 0x14 28 700 2.95 2.25 1.45 0.75 350 3.3 2.6 1.8 1.1
300 800 166.67 8.52 0x15 32 800 2.9 2.1 1.4 0.6 400 3.3 2.5 1.8 1
300 900 200.00 9.54 0x16 36 900 2.85 1.95 1.35 0.45 450 3.3 2.4 1.8 0.9
400 400 0.00 0.00 0x20 16 400 3.1 2.7 1.6 1.2 200 3.3 2.9 1.8 1.4
400 500 25.00 1.94 0x21 20 500 3.05 2.55 1.55 1.05 250 3.3 2.8 1.8 1.3
400 600 50.00 3.52 0x22 24 600 3 2.4 1.5 0.9 300 3.3 2.7 1.8 1.2
400 700 75.00 4.86 0x23 28 700 2.95 2.25 1.45 0.75 350 3.3 2.6 1.8 1.1
400 800 100.00 6.02 0x24 32 800 2.9 2.13 1.4 0.6 400 3.3 2.5 1.8 1
400 900 125.00 7.04 0x25 36 900 2.85 1.954 1.35 0.45 450 3.3 2.4 1.8 0.9
400 1000 150.00 7.96 0x26 40 1000 2.8 1.84 1.3 0.3 500 3.3 2.3 1.8 0.8
600 600 0.00 0.00 0x30 24 600 3 2.4 1.5 0.9 300 3.3 2.7 1.8 1.2
600 700 16.67 1.34 0x31 28 700 2.95 2.25 1.45 0.75 350 3.3 2.6 1.8 1.1
600 800 33.33 2.50 0x32 32 800 2.9 2.13 1.4 0.65 400 3.3 2.5 1.8 1
600 900 50.00 3.52 0x33 36 900 2.85 1.954 1.35 0.454 450 3.3 2.4 1.8 0.9
600 1000 66.67 4.44 0x34 40 1000 2.8 1.84 1.3 0.34 500 3.3 2.3 1.8 0.8
600 1100 83.33 5.26 0x35 44 1100 2.75 1.654 1.25 0.154 550 3.3 2.2 1.8 0.7
600 1200 100.00 6.02 0x36 48 1200 2.7 1.54 1.2 04 600 3.3 2.13 1.8 0.65

Register

1

Symbol definitions are shown in Ta . ble 20

2

TX[A/B/C] level/PE control registers are port level control registers at Address 0x49, Address 0x89, and Address 0xC9. Per-lane level and PE control are in separate

registers.

3

This setting requires TX_HEADROOM = 1 to ensure adequate output compliance.

4

This setting is not recommended for ac-coupled outputs because the theoretical output low level is below the minimum output voltage limit listed in . Table 1

5

This setting is not recommended because the output level is below the minimum output voltage limit listed in . Use VCC = 2.5 V and TX_HEADROOM = 1.

2

Output
Current

1

(mA)

I

TTO

V

ΔV
(mV)

OCM

= V

CC

TTO

1

1

V

H-PE

(V)

= 3.3 V VCC = V

1

V

V

L-PE

(V)

H-PE

(V)

= 1.8 V VCC = V

TTO

1

1

V

ΔV

L-PE

(V)

OCM

(mV)

Table 1

= 3.3 V VCC = V

TTO

1

1

V

H-PE

(V)

V
(V)

L-PE

1

V
(V)

H-PE

1

= 1.8 V

TTO

V
(V)

L-PE

1

Rev. B | Page 29 of 36

AD8158

V

Table 20. Symbol Definitions

Symbol Formula Definition

IDC Programmable Output current that sets output level
IPE Programmable Output current for PE delayed tap
I

I

TTO

V

25 Ω × I

DPP-DC

V

25 Ω × I

DPP-PE

V

V

SW-DC

V

V

SW-PE

∆V

OCM_DC-COUPLED

∆V

OCM_AC-COUPLED

V

V

OCM

V

V

H-DC

V

V

L-DC

V

V

H-PE

V

V

L-PE

25 Ω × I
50 Ω × I

+ IPE Total transmitter output current

DC

× 2

DC

Peak-to-peak differential voltage swing of
nonpreemphasized waveform

TTO

× 2

Peak-to-peak differential voltage swing of preemphasized
waveform

DPP-DC

DPP-PE

− ∆V

TTO

− ∆V

TTO

− ∆V

TTO

− ∆V

TTO

− ∆V

TTO

/2 = V

/2 = V

– V

H-DC

H-PE

/2 Output common-mode shift, dc-coupled outputs

TTO

/2 Output common-mode shift, ac-coupled outputs

TTO

= ( V

OCM

+ V

OCM

− V

OCM

+ V

OCM

− V

OCM

DC single-ended voltage swing

L-DC

– V

Preemphasized single-ended voltage swing

L-PE

+ V

H-DC

DPP-DC

DPP-DC

DPP-PE

DPP-PE

TTO

)/2 Output common-mode voltage

L-DC

/2 DC single-ended output high voltage

/2 DC single-ended output low voltage
/2 Maximum single-ended output voltage
/2 Minimum single-ended output voltage

V

H-PE

V

H-DC

V

OCM

t

PE

Figure 46. V

, VL, and V

H

OCM

V

SW-DC

V

L-DC

V

SW-PE

V

L-PE

6646-140

Rev. B | Page 30 of 36

AD8158

V

SUPPLY SEQUENCING

Ideally, all power supplies should be brought up to the appropri­ate levels simultaneously (power supply requirements are set by
the supply limits in Ta b le 1 and the absolute maximum ratings
listed in Table 3 ). In the event that the power supplies to the
AD8158 are brought up separately, the supply power-up sequence
is as follows: DV
V

and V

TTI

and V

V

being powered off first.

TTO

and V

TTI

is powered first, followed by VCC, and lastly

CC

. The power-down sequence is reversed, with V

TTO

contain ESD protection diodes to the VCC power

TTO

TTI

domain (see Figure 38 and Figure 39). To avoid a sustained high
current condition in these devices (I
and V
be powered off before V

supplies should be powered on after VCC and should

TTO

.

CC

SUSTAINED

< 64 mA), the V

TTI

If the system power supplies have a high impedance in the
powered off state, then supply sequencing is not required
provided the following limits are observed:

• Peak current from V

TTI

or V

• Sustained current from V

to VCC < 200 mA

TTO

TTI

or V

to VCC < 64 mA

TTO

RESET

On initial power up or at any point during operation the
AD8158 register set can be restored to the default values by
pulling the RESETB pin low. Reset pulse width is defined as the
time RESETB is held below the logic low threshold (V
in Tab l e 1 while the DV

supply is within the operating range

CC

) listed

IL

in Tab l e 1. During normal operation the RESETB pin must be
pulled up to DV

. A software reset is available by writing value

CC

0x01 to the Reset register at address 0x00. This register
is write only.

SINGLE SUPPLY vs. MULTIPLE SUPPLY OPERATION

The AD8158 supports a flexible supply voltage of 1.8 V to 3.3 V.
For some dc-coupled links, 1.2 V or ground-referenced signaling
may be desired. In these cases, the AD8158 can be run with a
split supply configuration. An example is shown in Figure 47.

0

CML

V
DV

V

TTI

TX

+

–

= 0mV

V

OH

V

OL

= –400mV

MCU_V

MCU_V

Z

0

Z

0

MCU

DD

SS

50Ω 50Ω 50Ω50Ω

VEE = –3.3V (OR – 1.8V)

ADuM1250

CC

CC

AD8158

DV

V

CC

EE

V

2

C_SCL

I

2

I

C_SDA

TTO

Z

0

Z

0

TO AD8158

RX

06646-148

Figure 47. Multiple Supply Operation

Table 21. Alternate Supply Configuration Examples

Signal Level VCC, V

, V

VEE

TTI

TTO

1.2 V CML 1.2 V −2.1 V ≤VEE ≤ −0.6 V
GND − 400 mV diff GND −3.3 V ≤VEE ≤ −1.8 V

The AD8158 control signals are always referenced between

and VEE and, when using a split supply configuration,

DV

CC

logic level-shift circuits should be used. The evaluation board
design shows the use of the Analog Devices, Inc., ADUM1250

2

I

C isolator and a level shifter to level-shift the SCL and SDA
signals (for information about the evaluation board, see the
Ordering Guide).

Evaluation of DC-Coupled Links

When evaluating the AD8158 dc-coupled, note that most lab
equipment is ground referenced whereas the AD8158 high
speed I/O are connected by 50 Ω on-die termination resistors to
V

and V

TTI

. To interface the AD8158 to ground-referenced,

TTO

high speed instrumentation (for example, the 50 Ω inputs of a
high speed oscilloscope), it is necessary to level-shift the outputs by
either using a dc-blocking network or powering the AD8158
between ground and a negative supply.

For example, to evaluate 1.8 V dc-coupled transmitter perfor­mance with a 50 Ω ground-referenced oscilloscope, use the
following supply configuration:

V

= V

= V

CC

V

= −1.8 V

EE

TTO

= Ground

TTI

Ground < DVCC < 1.5 V

Rev. B | Page 31 of 36

AD8158

PRINTED CIRCUIT BOARD (PCB) LAYOUT GUIDELINES

The high speed differential inputs and outputs should be routed
with 100 Ω controlled impedance differential transmission
lines. The transmission lines, either microstrip or stripline,
should be referenced to a solid low impedance reference plane.
An example of a PCB cross-section is shown in Figure 48. The
trace width (W), differential spacing (S), height above reference
plane (H), and dielectric constant of the PCB material determine
the characteristic impedance. Adjacent channels should be kept
apart by a distance greater than 3 W to minimize crosstalk.

WSW

SOLDERMASK

SIGNAL (M ICROSTRIP)

PCB DIELECTRI C

REFERENCE PLANE

PCB DIELECTRI C

SIGNAL (STRIPLINE)

PCB DIELECTRI C

REFERENCE PLANE

PCB DIELECTRI C

WSW

Figure 48. Example of a PCB Cross-Section

Thermal Paddle Design

The LFCSP is designed with an exposed thermal paddle to
conduct heat away from the package and into the PCB. By
incorporating thermal vias into the PCB thermal paddle,
heat is dissipated more effectively into the inner metal layers
of the PCB. To ensure device performance at elevated
temperatures, it is important to have a sufficient number of
thermal vias incorporated into the design. An insufficient
number of thermal vias results in a θ

value larger than

JA

specified in Tabl e 1. Additional PCB footprint and assembly
guidelines are described in the AN-772 Application Note, A

Design and Manufacturing Guide for the Lead Frame Chip Scale
Package (LFCSP).

H

6646-149

It is recommended that a via array of 4 × 4 or 5 × 5 with a
diameter of 0.3 mm to 0.33 mm be used to set a pitch between

1.0 mm and 1.2 mm. A representative of these arrays is shown
in Figure 49.

THERMAL
VIA

THERMAL
PADDLE

06646-150

Figure 49. PCB Thermal Paddle and Via

Stencil Design for the Thermal Paddle

To effectively remove heat from the package and to enhance
electrical performance, the thermal paddle must be soldered
(bonded) to the PCB thermal paddle, preferably with minimum
voids. However, eliminating voids may not be possible because
of the presence of thermal vias and the large size of the thermal
paddle for larger size packages. Also, outgassing during the
reflow process may cause defects (splatter, solder balling) if the
solder paste coverage is too big. It is recommended that smaller
multiple openings in the stencil be used instead of one big
opening for printing solder paste on the thermal paddle region.
This typically results in 50% to 80% solder paste coverage.
Figure 50 shows how to achieve these levels of coverage.

Voids within solder joints under the exposed paddle can have
an adverse affect on high speed and RF applications, as well as
on thermal performance. Because the LFCSP package incor­porates a large center paddle, controlling solder voiding within
this region can be difficult. Voids within this ground plane can
increase the current path of the circuit. The maximum size for
a void should be less than via pitch within the plane. This
assures that any one via is not rendered ineffectual when any
void increases the current path beyond the distance to the next
available via.

Rev. B | Page 32 of 36

AD8158

R

COPPE
PLATING

1.35mm × 1.35mm S QUARES
AT 1.65 mm PIT CH

COVERAGE: 68%

SOLDER
MASK

VIA

06646-151

Figure 50. Typical Thermal Paddle Stencil Design

Large voids in the thermal paddle area should be avoided. To
control voids in the thermal paddle area, solder masking may
be required for thermal vias to prevent solder wicking inside
the via during reflow, thus displacing the solder away from the
interface between the package thermal paddle and thermal
paddle land on the PCB. There are several methods employed
for this purpose, such as via tenting (top or bottom side), using
dry film solder mask; via plugging with liquid photo-imagible
(LPI) solder mask from the bottom side; or via encroaching.
These options are depicted in Figure 51. In case of via tenting,
the solder mask diameter should be 100 microns larger than
the via diameter.

(A) (B) (D)(C)

Figure 51. Solder Mask Options for Thermal Vias: (A) Via Tenting from the

Top; (B) Via Tenting from the Bottom; (C)Via Plugging, Bottom; and (D) Via

Encroaching, Bottom

6646-152

A stencil thickness of 0.125 mm is recommended for 0.4 mm and

0.5 mm pitch parts. The stencil thickness can be increased to

0.15 mm to 0.2 mm for coarser pitch parts. A laser-cut, stainless
steel stencil is recommended with electropolished trapezoidal
walls to improve the paste release. Because not enough space is
available underneath the part after reflow, it is recommended
that no clean Type 3 paste be used for mounting the LFCSP.
Inert atmosphere is also recommended during reflow.

Rev. B | Page 33 of 36

AD8158

REGISTER MAP

All registers are port-level and global registers, unless otherwise noted.

Table 22. Register Definitions

Mnemonic Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default

Reset 0x00 RESET
Switch

Control 1
Switch

Control 2
Global

Squelch Ctrl
Switch Core/

Headroom
Mode 0x0F MODE[1] MODE[0] 0x00
RXA Disable 0x40 RXDIS A3 RXDIS A2 RXDIS A1 RXDIS A0 0x00
RXA Setting 0x41 AEQ[3] AEQ[2] AEQ[1] AEQ[0] 0x00
RXA LOS

Control
RXA Lane 1/

RXA Lane 0
Setting

RXA Lane 3/
RXA Lane 2
Setting

RXA P/N
Swap

RXA LOS
Status

TXA Disable 0x48 TXDIS A3 TXDIS A2 TXDIS A1 TXDIS A0 0x00
TXA Level/PE

Control
TXA Lane1/

TXA Lane 0
PE Setting

TXA Lane2/3
PE Setting

TXA Per-Lane
Level Setting

RXB Disable 0x80 RXDIS B3 RXDIS B2 RXDIS B1 RXDIS B0 0x00
RXB Setting 0x81 BEQ[3] BEQ[2] BEQ[1] BEQ[0] 0x00
RXB LOS Ctrl 0x91 Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 LOS_FILT Set to 0 LOS_ENB 0x05
RXB Lane 1/

RXB Lane 0
Setting

RXB Lane 3/
RXB Lane 2
Setting

RXB P/N
Swap

RXB LOS
Status

TXB Disable 0x88 TXDIS B3 TXDIS B2 TXDIS B1 TXDIS B0 0x00
TXB Level/PE

Control
TXB Lane1/

TXB Lane 0
PE Setting

TXB Lane2/
TXB Lane 3
PE Setting

TXB Per-Lane
Level Setting

0x01 LBC LBB LBA SELAb/B[3] SELAb/B[2] SELAb/B[1] SELAb/B[0] 0x00

0x02 SEL4G BICAST 0x00

0x04 GSQLCH_ENB 0x0F

0x05 TX_HEAD

0x51 Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 LOS_FILT Set to 0 LOS_ENB 0x05

0x421 A1EQ[3] A1EQ[2] A1EQ[1] A1EQ[0] A0EQ[3] A0EQ[2] A0EQ[1] A0EQ[0] 0x00

0x431 A3EQ[3] A3EQ[2] A3EQ[1] A3EQ[0] A2EQ[3] A2EQ[2] A2EQ[1] A2EQ[0] 0x00

0x441 PNA3 PNA2 PNA1 PNA0 0x00

0x451 LOSA3

Sticky

0x49 ALEV[1] ALEV[0] APE[2] APE[1] APE[0] 0x20

1

0x4A

A1PE[2] A1PE[1] A1PE[0] A0PE[2] A0PE[1] A0PE[0] 0x00

0x4B1 A3PE[2] A3PE[1] A3PE[0] A2PE[2] A2PE[1] A2PE[0] 0x00

0x4C1 A3OLEV[1] A3OLEV[0] A2OLEV[1] A2OLEV[0] A1OLEV[1] A1OLEV[0] A0OLEV[1] A0OLEV[0] 0xAA

B1EQ[3] B1EQ[2] B1EQ[1] B1EQ[0] B0EQ[3] B0EQ[2] B0EQ[1] B0EQ[0] 0x00

0x8

21

0x831 B3EQ[3] B3EQ[2] B3EQ[1] B3EQ[0] B2EQ[3] B2EQ[2] B2EQ[1] B2EQ[0] 0x00

0x841 PNB3 PNB2 PNB1 PNB0 0x00

0x851 LOSB3

Sticky

0x89 BLEV[1] BLEV[0] BPE[2] BPE[1] BPE[0] 0x20

0x8A1 B1PE[2] B1PE[1] B1PE[0] B0PE[2] B0PE[1] B0PE[0] 0x00

0x8B1 B3PE[2] B3PE[1] B3PE[0] B2PE[2] B2PE[1] B2PE[0] 0x00

0x8C1 B3OLEV[1] B3OLEV[0] B2OLEV[1] B2OLEV[0] B1OLEV[1] B1OLEV[0] B0OLEV[1] B0OLEV[0] 0xAA

ROOM_C

LOSA2
Sticky

LOSB2
Sticky

TX_HEAD
ROOM_B

LOSA1
Sticky

LOSB1
Sticky

TX_HEAD
ROOM_A

LOSA0
Sticky

LOSB0
Sticky

XCORE_ENB 0x01

LOSA3 Active LOSA2

Active

LOSB3 Active LOSB2

Active

LOSA1
Active

LOSB1
Active

LOSA0
Active

LOSB0
Active

Rev. B | Page 34 of 36

AD8158

Mnemonic Addr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default

RXC Disable 0xC0 RXDIS C3 RXDIS C2 RXDIS C1 RXDIS C0 0x00
RXC Setting 0xC1 CEQ[3] CEQ[2] CEQ[1] CEQ[0] 0x00
RXC LOS Ctrl 0xD1 Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 LOS_FILT Set to 0 LOS_ENB 0x05
RXC Lane 1/

RXC Lane 0
Setting

RXC Lane 3/
RXC Lane 2
Setting

RXC P/N
Swap

RXC LOS
Status

TXC Disable 0xC8 TXDIS C3 TXDIS C2 TXDIS C1 TXDIS C0 0x00
TXC Level/PE

Control
TXC Lane1/

TXC Lane 0
PE Setting

TXC Lane2/
TXC Lane 3
PE Setting

TXC Per-Lane
Level Setting

1

Per-lane registers.

0xC21 C1EQ[3] C1EQ[2] C1EQ[1] C1EQ[0] C0EQ[3] C0EQ[2] C0EQ[1] C0EQ[0] 0x00

0xC31 C3EQ[3] C3EQ[2] C3EQ[1] C3EQ[0] C2EQ[3] C2EQ[2] C2EQ[1] C2EQ[0] 0x00

0xC41 PNC3 PNC2 PNC1 PNC0 0x00

0xC51 LOSC3

0xC9 CLEV[1] CLEV[0] CPE[2] CPE[1] CPE[0] 0x20

0xCA1 C1PE[2] C1PE[1] C1PE[0] C0PE[2] C0PE[1] C0PE[0] 0x00

0xCB

0xCC1 C3OLEV[1] C3OLEV[0] C2OLEV[1] C2OLEV[0] C1OLEV[1] C1OLEV[0] C0OLEV[1] C0OLEV[0] 0xAA

Sticky

1

C3PE[2] C3PE[1] C3PE[0] C2PE[2] C2PE[1] C2PE[0] 0x00

LOSC2
Sticky

LOSC1
Sticky

LOSC0
Sticky

LOSC3 Active LOSC2

Active

LOSC1
Active

LOSC0
Active

Rev. B | Page 35 of 36

AD8158

OUTLINE DIMENSIONS

PIN 1

INDICATOR

12.00

BSC SQ

11.75

BSC SQ

0.60 MAX

0.40

BSC

0.60 MAX

75

76

EXPOSEDPAD

(BOTTOM VIEW)

0.25

0.20

0.15

100

1

PIN 1
INDICATOR

7.00

6.90 SQ

6.80

26

25

0.20 MIN

061108-B

0.90

0.85

0.80

SEATING

PLANE

12° MAX

TOP VIEW

50

0.50

0.05 MAX

0.01 NOM

0.20 REF

0.40

0.30

0.70

0.65

0.60

COMPLIANT TO JEDEC STANDARDS MO-220-VRRE.

51

9.60 REF

THE EXPOSED METAL PADDLE ON THE
BOTTOM OF THE L FCSP PACKAGE
MUST BE SOLDERED TO PCB GROUND
FOR PROPER HE AT DISSIPATION AND
ALSO FO R NOISE AND MECHANICAL
STRENGTH BENE FITS.

Figure 52. 100-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

12 mm × 12 mm Body, Very Thin Quad

(CP-100-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD8158ACPZ −40°C to +85°C 100-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-100-1
AD8158-EVALZ Evaluation Board

1

Z = RoHS Compliant Part.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06646-0-12/09(B)

Rev. B | Page 36 of 36