Datasheet AD8151 Datasheet (ANALOG DEVICES)

33 × 17, 3.2 Gbps

www.BDTIC.com/ADI

FEATURES

Low cost
33 × 17, fully differential, nonblocking array

3.2 Gbps per port NRZ data rate
Wide power supply range: +3.3 V, –3.3 V
Low power
425 mA (outputs enabled)
35 mA (outputs disabled)
LV PECL- and LV ECL-compatible
CMOS/TTL-level control inputs: 3 V to 5 V
Low jitter
No heat sinks required
Drives a backplane directly
Programmable output current
Optimize termination impedance
User-controlled voltage at the load
Minimize power dissipation
Individual output disable for busing and reducing power
Double row latch
Buffered inputs
184-lead LQFP package

GENERAL DESCRIPTION

Digital Crosspoint Switch

AD8151

APPLICATIONS

High speed serial backplane routing to Sonet OC-48

applications with FEC
Fiber optic network switching
Fiber channel
LVDS

FUNCTIONAL BLOCK DIAGRAM

INP INN

CS

UPDATE

RESET

.

RE

7

D

5

A

WE

OUTPUT

ADDRESS

DECODER

FIRST
RANK

17

7-BIT

LATCH

×

SECOND

RANK

17

×

7-BIT

LATCH

Figure 1.

INPUT

DECODERS

33 33

33×17

DIFFERENTIAL

SWITCH
MATRIX

AD8151

17

OUTP

17

OUTN

02169-001

The AD81511 is a member of the Xstream line of products,
offering a breakthrough in digital switching and a large switch
array (33 × 17) on very little power—typically less than 1.5 W.
It also operates at data rates in excess of 3.2 Gbps per port,
making it suitable for Sonet OC-48 applications with
8/10-bit forward-error correction (FEC). Furthermore, the
price of the AD8151 makes it affordable enough to be used for
lower data rates. The AD8151’s flexible supply voltages allow
the user to operate with either emitter-coupled logic (ECL) or
positive emitter-coupled logic (PECL) data levels, and with 3.3
V for further power reduction. The control interface is CMOS­/TTL-compatible (3 V to 5 V).

Its fully differential signal path reduces jitter and crosstalk,
while al

lowing the use of smaller, single-ended voltage swings.
The AD8151 is offered in a 184-lead LQFP package that
operates over the extended commercial temperature range
of 0°C to 85°C.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

150mV/DIV

70ps/DIV

Figure 2. Eye Pattern, 3.2 Gbps, PRBS 23

1

Patent pending.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

02169-002

AD8151

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

Maximum Power Dissipation..................................................... 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Typical Performance Characteristics ............................................. 9

Control Interface Truth Tables...................................................... 13

Control Interface Timing Diagrams ............................................14

Control Interface Programming Example .............................. 16

Control Interface ............................................................................ 17

Control Pin Description............................................................ 17

Control Interface Translators.................................................... 18

Circuit Description......................................................................... 19

Applications..................................................................................... 23

Input and Output Busing .......................................................... 23

Evaluation Board........................................................................ 23

Power Supplies............................................................................ 24

Configuration Programming.................................................... 25

Software Installation.................................................................. 25

Software Operation.................................................................... 26

Outline Dimensions....................................................................... 38

Ordering Guide .......................................................................... 38

REVISION HISTORY

12/05—Rev. A to Rev. B

Changes to Table 1............................................................................ 3

Changes to Figure 4.......................................................................... 5

Changes to Table 3............................................................................ 6

Changes to Table 4.......................................................................... 13

Changes to Figure 51...................................................................... 35

Changes to Ordering Guide.......................................................... 38

9/05—Rev. 0 to Rev. A

Updated Format..............................................................Universal

hange to Figure 51 ................................................................... 34

C

Change to Ordering Guide........................................................ 37

4/01—Revision 0: Initial Version

Rev. B | Page 2 of 40

AD8151

www.BDTIC.com/ADI

SPECIFICATIONS

@ 25°C, VCC = 3.3 V to 5 V, VEE = 0 V, RL = 50 Ω (see Figure 26), I

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Max Data Rate/Channel (NRZ) 2.5 3.2 Gbps
Channel Jitter Data rate = 3.2 Gbps 52 ps p-p
RMS Channel Jitter 8 ps
Propagation Delay Input to output 650 ps
Propagation Delay Match See Figure 23 ±50 ±100 ps
Output Rise/Fall Time 20% to 80% 100 ps

INPUT CHARACTERISTICS

Input Voltage Swing Single-ended (see Figure 18) 200 1000 mV p-p
Input Bias Current 2 μA
Input Capacitance 2 pF
Input VIN High

Input VIN Low

OUTPUT CHARACTERISTICS

Output Voltage Swing Differential 800 mV p-p
Output Voltage Range (See Figure 19)

Output Current 5 25 mA
Output Capacitance 2 pF
Output V

Output V

POWER SUPPLY

Operating Range

PECL, VCC V
ECL, VEE V
VDD 3 5 V
VSS 0 V

Quiescent Current

VDD 2 mA

VEE All outputs enabled, I
T
All outputs disabled 35 mA
THERMAL CHARACTERISTICS

Operating Temperature Range 0 85 °C

θJA

LOGIC INPUT CHARACTERISTICS VDD = 3 V dc to 5 V dc

Input VIN High 1.9 VDD V
Input VIN Low 0 0.9 V

High

OUT

Low VCC V

OUT

= 0 V 3.0 5.25 V

EE

= 0 V –5.25 –3.0 V

CC

to T

MIN

30 °C/W

450 mA

MAX

= 16 mA, unless otherwise noted.

OUT

VCC − 1.2

VCC − 2.4

VCC − 1.8

VCC − 1.8

= 16 mA 425 mA

OUT

V

V

V

V

CC

VCC − 1.4

V

CC

V

Rev. B | Page 3 of 40

AD8151

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 2.

Parameter Rating

Supply Voltage

VDD − VEE
VCC − VEE

VDD − VSS

VSS − VEE

VSS − VCC

VDD − VCC

Internal Power Dissipation

184-Lead LQFP (ST-184) 4.2 W
Differential Input Voltage 2.0 V
Storage Temperature Range –65°C to +125°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature, θJA

10.5 V

5.5 V

5.5 V

5.5 V

5.5 V

5.5 V

30°C/W

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8151 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit may cause a shift in
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure. To
ensure proper operation, it is necessary to observe the
maximum power derating curves shown in

6

5

4

Figure 3.

TJ = 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress

3

rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

MAXIMUM POWER DISSIPATION (W)

2

1

–10 9080706050403020100

AMBIENT TEMPERATURE (°C)

Figure 3.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

02169-003

Rev. B | Page 4 of 40

AD8151

www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V
IN20P
IN20N

V
IN21P
IN21N

V
IN22P
IN22N

V
IN23P
IN23N

V
IN24P
IN24N

V
IN25P
IN25N

V
IN26P
IN26N

V
IN27P
IN27N

V
IN28P
IN28N

V
IN29P
IN29N

V
IN30P
IN30N

V
IN31P
IN31N

V
IN32P
IN32N

V

V

CC

V

OUT16N

OUT16P

VEEA16

V

EEVEEVEEVEEVEE

IN19N

IN19P

IN18N

IN18P

IN17N

179

178

177

IN17P

176

175

V

184

183

182

181

180

1

EE

2
3
4

EE

5
6
7

EE

8
9

10

EE

11
12
13

EE

14
15
16

EE

17
18
19

EE

20
21
22

EE

23
24
25

EE

26
27
28

EE

29
30
31

EE

32
33
34

EE

35
36
37

EE

38
39
40

EE

41
42

EE

43
44
45
46

EE

PIN 1
INDICATOR

IN16N

174

IN16P

173

CCVDD

V

RESETCSREWEUPDATEA0A1A2A3A4D0D1D2D3D4D5D6

171

170

169

168

167

166

165

164

163

172

162

161

160

AD8151

184L LQFP

TOP VIEW

(Not to Scale)

159

158

157

156

155

154

REF

SSVCCVEEVEEVEEVEE

EE

153

V

152

REF

151

V

150

149

148

IN15N

147

IN15P

146

145

IN14N

144

IN14P

143

142

IN13N

141

IN13P

140

139

138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93

V

EE

IN12N
IN12P
V

EE

IN11N
IN11P
V

EE

IN10N
IN10P
V

EE

IN09N
IN09P
V

EE

IN08N
IN08P
V

EE

IN07N
IN07P
V

EE

IN06N
IN06P
V

EE

IN05N
IN05P
V

EE

IN04N
IN04P
V

EE

IN03N
IN03P
V

EE

IN02N
IN02P
V

EE

IN01N
IN01P
V

EE

IN00N
IN00P
V

EE

V

CC

VEEA0
OUT00P
OUT00N
V

A1

EE

V

EE

4748495051525354555657

EE

V

A15

A14

A13

EE

EE

V

V

OUT13P

OUT13N

OUT15P

OUT15N

EE

V

OUT14P

OUT14N

596061626364656667

58

A12

A11

EE

EE

V

OUT12N

OUT12P

OUT11P

OUT11N

V

OUT10N

OUT10P

A10

EE

V

OUT09N

68

A9
V

OUT09P

697071

EE

OUT08N

A8
V

OUT08P

72

747576777873798081

A7

EE

EE

V

OUT07P

OUT07N

OUT06N

A6
V

OUT06P

EE

OUT05N

A5
V

OUT05P

EE

Figure 4. Pin Configuration

Rev. B | Page 5 of 40

82

OUT04P

OUT04N

A4
V

EE

848586

OUT03P

OUT03N

87838889909192

A3

A2

EE

EE

V

V

OUT02P

OUT02N

OUT01P

OUT01N

EE

V

02169-004

AD8151

www.BDTIC.com/ADI

Table 3. Pin Function Descriptions

Pin No. Mnemonic Type Description

V

1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31,
34, 37, 40, 42, 46, 47, 92, 93, 99,
102, 105, 108, 111, 114, 117, 120,
123, 126, 129, 132, 135, 138, 139,
142, 145, 148, 172, 175, 178, 181,
184

2 IN20P PECL/ECL High Speed Input
3 IN20N PECL/ECL High Speed Input Complement
5 IN21P PECL/ECL High Speed Input
6 IN21N PECL/ECL High Speed Input Complement
8 IN22P PECL/ECL High Speed Input
9 IN22N PECL/ECL High Speed Input Complement
11 IN23P PECL/ECL High Speed Input
12 IN23N PECL/ECL High Speed Input Complement
14 IN24P PECL/ECL High Speed Input
15 IN24N PECL/ECL High Speed Input Complement
17 IN25P PECL/ECL High Speed Input
18 IN25N PECL/ECL High Speed Input Complement
20 IN26P PECL/ECL High Speed Input
21 IN26N PECL/ECL High Speed Input Complement
23 IN27P PECL/ECL High Speed Input
24 IN27N PECL/ECL High Speed Input Complement
26 IN28P PECL/ECL High Speed Input
27 IN28N PECL/ECL High Speed Input Complement
29 IN29P PECL/ECL High Speed Input
30 IN29N PECL/ECL High Speed Input Complement
32 IN30P PECL/ECL High Speed Input
33 IN30N PECL/ECL High Speed Input Complement
35 IN31P PECL/ECL High Speed Input
36 IN31N PECL/ECL High Speed Input Complement
38 IN32P PECL/ECL High Speed Input
39 IN32N PECL/ECL High Speed Input Complement
41, 98, 149, 171 VCC Power Supply Most Positive PECL Supply (Common with Other Points Labeled VCC)
43 OUT16N PECL/ECL High Speed Output Complement
44 OUT16P PECL/ECL High Speed Output
45 VEEA16 Power Supply Most Negative PECL Supply (Unique to this Output)
48 OUT15N PECL/ECL High Speed Output Complement
49 OUT15P PECL/ECL High Speed Output
50 VEEA15 Power Supply Most Negative PECL Supply (Unique to this Output)
51 OUT14N PECL/ECL High Speed Output Complement
52 OUT14P PECL/ECL High Speed Output
53 VEEA14 Power Supply Most Negative PECL Supply (Unique to this Output)
54 OUT13N PECL/ECL High Speed Output Complement
55 OUT13P PECL/ECL High Speed Output
56 VEEA13 Power Supply Most Negative PECL Supply (Unique to this Output)
57 OUT12N PECL/ECL High Speed Output Complement
58 OUT12P PECL/ECL High Speed Output
59 VEEA12 Power Supply Most Negative PECL Supply (Unique to this Output)
60 OUT11N PECL/ECL High speed Output Complement
61 OUT11P PECL/ECL High speed Output
62 VEEA11 Power Supply Most Negative PECL Supply (Unique to this Output)
63 OUT10N PECL/ECL High Speed Output Complement

Power Supply

EE

Most Negative PECL Supply (Common with O

)

V

EE

ther Points Labeled

Rev. B | Page 6 of 40

AD8151

www.BDTIC.com/ADI

Pin No. Mnemonic Type Description

64 OUT10P PECL/ECL High Speed Output
65 VEEA10 Power Supply Most Negative PECL Supply (Unique to this Output)
66 OUT09N PECL/ECL High Speed Output Complement
67 OUT09P PECL/ECL High Speed Output
68 VEEA9 Power Supply Most Negative PECL Supply (Unique to this Output)
69 OUT08N PECL/ECL High speed Output Complement
70 OUT08P PECL/ECL High Speed Output
71 VEEA8 Power Supply Most Negative PECL Supply (Unique to this Output)
72 OUT07N PECL/ECL High Speed Output Complement
73 OUT07P PECL/ECL High Speed Output
74 VEEA7 Power Supply Most Negative PECL Supply (Unique to this Output)
75 OUT06N PECL/ECL High Speed Output Complement
76 OUT06P PECL/ECL High Speed Output
77 VEEA6 Power Supply Most Negative PECL Supply (Unique to this Output)
78 OUT05N PECL/ECL High Speed Output Complement
79 OUT05P PECL/ECL High Speed Output
80 VEEA5 Power Supply Most Negative PECL Supply (Unique to this Output)
81 OUT04N PECL/ECL High Speed Output Complement
82 OUT04P PECL/ECL High Speed Output
83 VEEA4 Power Supply Most Negative PECL Supply (Unique to this Output)
84 OUT03N PECL/ECL High Speed Output Complement
85 OUT03P PECL/ECL High Speed Output
86 VEEA3 Power Supply Most Negative PECL Supply (Unique to this Output)
87 OUT02N PECL/ECL High Speed Output Complement
88 OUT02P PECL/ECL High Speed Output
89 VEEA2 Power Supply Most Negative PECL Supply (Unique to this Output)
90 OUT01N PECL/ECL High Speed Output Complement
91 OUT01 P PECL/ECL High Speed Output
94 VEEA1 Power Supply Most Negative PECL Supply (Unique to this Output)
95 OUT00N PECL/ECL High Speed Output Complement
96 OUT00P PECL/ECL High Speed Output
97 VEEA0 Power Supply Most Negative PECL Supply (Unique to this Output)
100 IN00P PECL/ECL High Speed Input
101 IN00N PECL/ECL High Speed Input Complement
103 IN01P PECL/ECL High Speed Input
104 IN01N PECL/ECL High Speed Input Complement
106 IN02P PECL/ECL High Speed Input
107 IN02N PECL/ECL High Speed Input Complement
109 IN03P PECL/ECL High Speed Input
110 IN03N PECL/ECL High Speed Input Complement
112 IN04P PECL/ECL High Speed Input
113 IN04N PECL/ECL High Speed Input Complement
115 IN05P PECL/ECL High Speed Input
116 IN05N PECL/ECL High Speed Input Complement
118 IN06P PECL/ECL High Speed Input
119 IN06N PECL/ECL High Speed Input Complement
121 IN07P PECL/ECL High Speed Input
122 IN07N PECL/ECL High Speed Input Complement
124 IN08P PECL/ECL High Speed Input
125 IN08N PECL/ECL High Speed Input Complement
127 IN09P PECL/ECL High Speed Input
128 IN09N PECL/ECL High Speed Input Complement

Rev. B | Page 7 of 40

AD8151

www.BDTIC.com/ADI

Pin No. Mnemonic Type Description

130 IN10P PECL/ECL High Speed Input
131 IN10N PECL/ECL High Speed Input Complement
133 IN11P PECL/ECL High Speed Input
134 IN11N PECL/ECL High Speed Input Complement
136 IN12P PECL/ECL High Speed Input
137 IN12N PECL/ECL High Speed Input Complement
140 IN13P PECL/ECL High Speed Input
141 IN13N PECL/ECL High Speed Input Complement
143 IN14P PECL/ECL High Speed Input
144 IN14N PECL/ECL High Speed Input Complement
146 IN15P PECL/ECL High Speed Input
147 IN15N PECL/ECL High Speed Input Complement
150 VEEREF R Program

151 REF R Program Connection Point for Output Logic Pull-Down Programming Resistor
152 VSS Power Supply Most Negative Control Logic Supply
153 D6 TTL

154 D5 TTL Bit 32—MSB Input Select
155 D4 TTL Bit 16
156 D3 TTL Bit 8
157 D2 TTL Bit 4
158 D1 TTL Bit 2
159 D0 TTL Bit 1—LSB Input Select
160 A4 TTL Bit 16—MSB Output Select
161 A3 TTL Bit 8
162 A2 TTL Bit 4
163 A1 TTL Bit 2
164 A0 TTL Bit 1—LSB Output Select
165
166

167
168
169
170 VDD Power Supply Most Positive Control Logic Supply

173 IN16P PECL/ECL High Speed Input
174 IN16N PECL/ECL High Speed Input Complement
176 IN17P PECL/ECL High Speed Input
177 IN17N PECL/ECL High Speed Input Complement
179 IN18P PECL/ECL High Speed Input
180 IN18N PECL/ECL High Speed Input Complement
182 IN19P PECL/ECL High Speed Input
183 IN19N PECL/ECL High Speed Input Complement

UPDATE
WE
RE
CS
RESET

TTL Second Rank Program
TTL First Rank Program
TTL Enable Readback
TTL Enable Chip to Accept Programming
TTL Disable All Outputs (Hi-Z)

Connection Point for Output Logic Pull-Down Programming Resistor

t be Connected to V

(Mus

Enable/Disable

Output

)

EE

Rev. B | Page 8 of 40

AD8151

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

150mV/DIV

p-p = 43ps
STD DEV = 8ps

150mV/DIV

100ps/DIV

Figure 5. Eye Pattern 2.5 Gbps, PRBS 23

20ps/DIV

Figure 6. Jitter @ 2.5 Gbps, PRBS 23

02169-005

02169-006

150mV/DIV

p-p = 53ps
STD DEV = 8ps

150mV/DIV

70ps/DIV

Figure 8. Eye Pattern 3.2 Gbps, PRBS 23

20ps/DIV

Figure 9. Jitter @ 3.2 Gbps, PRBS 23

02169-008

02169-009

100

90

80

70

60

50

40

EYE WIDTH (%)

30

20

10

0

0.5 3.53.02.52.01.51.0

% EYE WIDTH =

(CLOCK PERIOD – JITTER p-p)

CLOCK PERIOD

DATA RATE (Gbps)

Figure 7. Eye Width vs. Data Rate, PRBS 23

×

100

02169-007

100

90

80

70

60

% EYE HEIGHT =

50

40

EYE HEIGHT (%)

30

20

10

0

0.5 3.53.02.52.01.51.0

Figure 10. Eye Height vs. Data Rate, PRBS 23

Rev. B | Page 9 of 40

@ DATA RATE)

(V

OUT

V

@ 0.5Gbps

OUT

DATA RATE (Gbps)

×

100

02169-010

AD8151

www.BDTIC.com/ADI

100

90

80

70

60

50

JITTER (ps)

40

30

20

10

STANDARD DEVIATION

0

1.0 3.53.02.52.01.5

p-p = 38ps
STD DEV = 7.7ps

PEAK-PEAK

JITTER

DATA RATE (Gbps)

Figure 11. Jitter vs. Data Rate, PRBS 23

02169-011

100

JITTER (ps)

90

80

70

60

50

40

30

20

10

0

098070605040302010

3.2Gbps STD DEV

TEMPERATURE (°C)

Figure 14. Jitter vs. Temperature, PRBS 23

3.2Gbps JITTER

2.5Gbps JITTER

2.5Gbps STD DEV

02169-014

0

150mV/DIV

100ps/DIV

Figure 12. Crosstalk, 2.5 Gbps, PRBS 23, Attack Signal Is Off

p-p = 70ps
STD DEV = 8ps

150mV/DIV

100ps/DIV

Figure 13. Crosstalk, 2.5 Gbps, PRBS 23, Attack Signal Is On

02169-012

02169-013

150mV/DIV

p-p = 32ps
STD DEV = 4.7ps

75ps/DIV

Figure 15. Crosstalk, 3.2 Gbps, PRBS 23, Attack Signal Is Off

150mV/DIV

p-p = 70ps
STD DEV = 9ps

75ps/DIV

Figure 16. Crosstalk, 3.2 Gbps, PRBS 23, Attack Signal Is On

02169-015

02169-016

Rev. B | Page 10 of 40

AD8151

www.BDTIC.com/ADI

p-p = 43ps
STD DEV = 8ps

150mV/DIV

1.4ns/DIV

Figure 17. Response, 2.5 Gbps,

3

2-Bit Pattern 1111 1111 0000 0000 0101 0101 0011 0011

100

90

80

70

60

50

40

30

3.2Gbps JITTER

PEAK-TO-PEAK JITTER (ps)

20

10

0

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Figure 18. Jitter vs. Single-Ended I

2.5Gbps JITTER

INPUT AMPLITUDE (V)

nput Amplitude, PRBS 23

02169-017

02169-018

p-p = 43ps
STD DEV = 8ps

150mV/DIV

1.1ns/DIV

Figure 20. Response, 3.2 Gbps,

3

2-Bit Pattern 1111 1111 0000 0000 0101 0101 0011 0011

100

90

80

70

60

50

40

30

PEAK-TO-PEAK JITTER (ps)

20

10

0
–5.0 –4.8 –4.6 –4.4 –4.2 –4.0 –3.8 –3.6 –3.4 –3.2 –3.0

3.2Gbps

2.5Gbps

VEE (V)

Figure 21. Jitter vs. Supply, PRBS 23

02169-020

02169-021

100

90

80

70

60

3.2Gbps

50

40

30

PEAK-TO-PEAK JITTER (ps)

20

10

0
–1.6 –1.4 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6

2.5Gbps

VIH (V)

Figure 19. Jitter vs. VIH, PRBS 23

02169-019

100

90

80

70

3.2Gbps

60

50

2.5Gbps

40

30

PEAK-TO-PEAK JITTER (ps)

20

10

0
–1.4 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2

Figure 22. Jitter vs. V

Rev. B | Page 11 of 40

VOH (V)

, PRBS 23, Output Amplitude = 0.4 V Single-Ended

OH

02169-022

AD8151

www.BDTIC.com/ADI

100

90

80

70

60

50

40

FREQUENCY

30

20

10

0

550 570 590 610 630 650 670 690 710 730

PROPAGATION DELAY (ps)

Figure 23. Variation in Channel-to-Channel Delay, All 561 Points

02169-023

200

150

100

50

0

–50

–100

PROPAGATION DELAY (ps)

–150

–200

–100 –80 –60 –40 –20 0 20 40 60 80 100

NORMALIZED TEMPERATURE (°C)

Figure 25. Propagation Delay, Normalized at 25°C vs. Temperature

02169-025

100

90

80

70

2.5Gbps

60

50

3.2Gbps

40

30

PEAK-TO-PEAK JITTER (ps)

20

10

0

5 1015202

OUTPUT CURRENT (mA)

Figure 24. Jitter vs. I

, PRBS 23

OUT

5

02169-024

PRBS

GENERATOR

DATA OUT

DATA OUT

VCC = 0V, VEE = –3.3V, VTT = –1.6V, VDD = 5V, VSS = 0V

= 1.54kΩ, I

R

SET

= 0.8V p-p EXCEPT AS NOTED

V

IN

V

CCVCCVTT

1.65kΩ

–6dB

–6dB

1.65kΩ

OUT

AD8151

P

P
IN OUT

105Ω

N

N

V

EE

V

EE

= 16mA, VOH = –0.8V, VOL = –1.2V

Figure 26. Test Circuit

49.9Ω

49.9Ω

V

TT

HIGH SPEED

SAMPLING

OSCILLOSCOPE

50Ω

50Ω

02169-026

Rev. B | Page 12 of 40

AD8151

www.BDTIC.com/ADI

CONTROL INTERFACE TRUTH TABLES

Table 4. Basic Control Functions

Control Pins1

RESET

0 X X X X Global Reset. Reset all second rank enable bits to zero (disable all outputs).
1 1 X X X

1 0 0 1 1

1 0 1 0 1

1 0 1 1 0

1 0 0 1 0

1

X means don’t care.

WE RE UPDATE

CS

Table 5. Address/Data Examples

Output Address Pins

MSB–LSB

A4 A3 A2 A1 A0 D6/E D5 D4 D3 D2 D1 D0 Function

0 0 0 0 0 X 0 0 0 0 0 0

1 0 0 0 0 X 1 0 0 0 0 0

Binary Output Number 2 1 Binary Input Number

Binary Output Number
1 0 0 0 1 X Binary Input Number

1 0 0 1 0 X 1 0 0 0 0 1

1

X means don’t care.

2

The binary output number can also be the broadcast connection designator, 10001.

2

Enable

1

Bit

0 X X X X X X Disable Output. Disable Specified Output (D6 = 0).

Functio n

Control Disable. Ignore all logic (but the signal matrix still functions as programmed). D [6:0]

e high impedance.

ar
Single Output Preprogram. Write input configuration data from Data Bus D [6:0] into first rank

tches for the output selected by the Output Address Bus A [4:0].

of la
Single Output Readback. Readback input configuration da

Data Bus D [6:0] for the single output selected by the Output Address Bus A [4:0].
Global Update. Copy input configuration data from all 17 first ra

latches, updating signal matrix connections for all outputs.
Transparent Write and Update. It is possible to write data directly onto rank two. This simplifies

logic wh

Input Address Pins MSB–LSB

en synchronous signal matrix updating is not necessary.

1

Lower Address/Data Range. Connect Output 00

A[4:0] = 00000) to Input 00 (D[5:0] = 000000).

(
Upper Address/Data Range. Connect Output 16

A[4:0] = 10000) to Input 32 (D[5:0] = 100000).

(
Enable Output. Connect Selected Output (A[4:0] = 0 to 16) to

nated Input (D[5:0] = 0 to 32) and Enable Output

Desig
(D6 = 1).

Broadcast Connection. Connect all 17 outputs t
designated input and set all 17 enable bits to D6. Readback is
not possible with the broadcast address.

Reserved. Any address or data code greater or equal to these

e reserved for future expansion or factory testing.

ar

ta from second rank of latches onto

nk latches into second rank of

o same

Rev. B | Page 13 of 40

AD8151

www.BDTIC.com/ADI

CONTROL INTERFACE TIMING DIAGRAMS

CS INPUTS

WE INPUTS

A[4:0] INPUTS

D[6:0] INPUTS

t

CSW

t

ASW

t

WP

t

DSW

Figure 27. First Rank Write Cycle

Table 6. First Rank Write Cycle

Parameter Mnemonic Description Conditions Min Typ Max Unit

Setup Time t
t
t
Hold Time t
t
t
Enable Pulse t

Chip select to write enable TA = 25°C 0 ns

CSW

Address to write enable VDD = 5 V 0 ns

ASW

Data to write enable VCC = 3.3 V 15 ns

DSW

Chip select from write enable 0 ns

CHW

Address from write enable 0 ns

AHW

Data from write enable 0 ns

DHW

Width of write enable pulse 15 ns

WP

t

AHW

t

DHW

t

CHW

02169-027

CS INPUTS

UPDATE INPUTS

ENABLING

OUT[0:16][N:P]

OUTPUTS

TOGGLE

OUT[0:16][N:P]

OUTPUTS

DISABLING

OUT[0:16][N:P]

OUTPUTS

PREVIOUS RANK 2 DATA

DATA FROM RANK 2

t

CSU

t

UOE

t

UOD

t

UOT

DATA FROM RANK 1

t

UW

DATA FROM RANK 1

t

CHU

02169-028

Figure 28. Second Rank Update Cycle

Table 7. Second Rank Update Cycle

Parameter Mnemonic Function Conditions Min Typ Max Unit

Setup Time t
Hold Time t
Output Enable Times t
Output Toggle Times t
Output Disable Times t
Update Pulse t

Chip select to update TA = 25°C 0 ns

CSU

Chip select from update VDD = 5 V ns

CHU

Update to output enable VCC = 3.3 V 25 40 ns

UOE

Update to output reprogram 25 40 ns

UOT

Update to output disabled 25 30 ns

UOD

Width of update pulse 15 ns

UW

Rev. B | Page 14 of 40

AD8151

www.BDTIC.com/ADI

CS INPUTS

UPDATE INPUTS

WE INPUTS

ENABLING

OUT[0:16][N:P]

OUTPUTS

DISABLING

OUT[0:16][N:P]

OUTPUTS

INPUT {DATA 1}INPUT {DATA 0}

t

CSU

t

UOT

t

UOE

t

UW

t

WOT

t

WOD

t

INPUT {DATA 2}INPUT {DATA 1}

WHU

t

CHU

02169-029

Figure 29. First Rank Write Cycle and Second Rank Update Cycle

Table 8. First Rank Write Cycle and Second Rank Update Cycle

Parameter Mnemonic Function Conditions Min Typ Max Unit

Setup Time t
Hold Time t
Output Enable Times t
t
Output Toggle Times t
t
Output Disable Times t
t
Setup Time t
Update Pulse t

1

Not shown.

Chip select to update TA = 25°C 0 ns

CSU

Chip select from update VDD = 5 V 0 ns

CHU

Update to output enable VCC = 3.3 V 25 40 ns

UOE

Write enable to output enable 25 40 ns

WOE

Update to output reprogram 25 30 ns

UOT

Write enable to output reprogram 25 30 ns

WOT

1

D

UOD

Write enable to output disabled 25 30 ns

WOD

Write enable to update 10 ns

WHU

Width of update pulse 15 ns

UW

Update to output disabled 25 30 ns

CS INPUTS

RE INPUTS

A[4:0]

INPUTS

D[6:0]

OUTPUTS

ADDR 1 ADDR 2

DATA

{ADDR 1}

t

CSR

t

RDE

t

DATA

{ADDR 2}

t

AA

t

RHA

t

RDD

CHR

02169-030

Figure 30. Second Rank Readback Cycle

Table 9. Second Rank Readback Cycle

Parameter Mnemonic Function Conditions Min Typ Max Unit

Setup Time t
Hold Time t
Read Enable t
Enable Time t
Access Time t
Release Time t

Chip select to read enable TA = 25°C 0 ns

CSR

Chip select from read enable VDD = 5 V 0 ns

CHR

Address from read enable VCC = 3.3 V 5 ns

RHA

Data from read enable 10 kΩ 15 ns

RDE

Data from address 20 pF on D[6:0] 15 ns

AA

Data from read enable Bus 15 30 ns

RDD

Rev. B | Page 15 of 40

AD8151

www.BDTIC.com/ADI

RESET INPUTS

DISABLING

OUT[0:16][N:P]

OUTPUTS

t

TOD

t

TW

02169-031

Figure 31. Asynchronous Reset

Table 10. Asynchronous Reset

Parameter Mnemonic Function Conditions Min Typ Max Unit

Disable Time t
Width of Reset Pulse tTW VDD = 5 V 15 ns
V

Output disable from reset TA = 25°C 25 30 ns

TOD

= 3.3 V

CC

CONTROL INTERFACE PROGRAMMING EXAMPLE

The following conservative pattern connects all outputs to Input 7, except Output 16, which is connected to Input 32. The vector clock
period t

Table 11. Basic Test Pattern

Vector No.

0 0 1 1 1 1 xxxxx xxxxxxx Disable all outputs
1 1 1 1 1 1 xxxxx xxxxxxx
2 1 0 1 1 1 10001 1000111
3 1 0 0 1 1 10001 1000111
4 1 0 1 1 1 10001 1000111
5 1 0 1 1 1 10000 1100000
6 1 0 0 1 1 10000 1100000
7 1 0 1 1 1 10000 1100000
8 1 0 1 1 0 xxxxx xxxxxxx
9 1 0 1 1 1 xxxxx xxxxxxx
10 1 1 1 1 1 xxxxx xxxxxxx Disable interface

is 15 ns. It is possible to accelerate the execution of this pattern by deleting Vectors 1, 4, 7, and 9.

0

RESET

CS WE

RE UPDATE

A[4:0] D[6:0] Comments

All outputs connected to Input 7
Write to first rank

Connects Output 16 to Input 32
Write to first rank

Transfer to second rank

Rev. B | Page 16 of 40

AD8151

www.BDTIC.com/ADI

CONTROL INTERFACE

7

UPDATE

RESET

D[0:6]

WE

7

7

7

7

1 OF 17 DECODERS

A[0:4]

Figure 32. Control Interface (Simplified Schematic)

7

0

7

1

7

2

7

16

RANK 1

17 ROWS OF 7-BIT

LATCHES

RE

0

1

2

16

RANK 2

7

7

7

7

The AD8151 control interface receives and stores the desired
connection matrix for the 33 input and 17 output signal pairs.
The interface consists of 17 rows of double-rank 7-bit latches,
1 row for each output. The 7-bit data-word stored in each of
these latches indicates to which (if any) of the 33 inputs the
output is connected.

One output at a time can be preprogrammed by addressing the
o

utput and writing the desired connection data into the first
rank of latches. This process can be repeated until each of the
desired output changes has been preprogrammed. All output
connections can then be programmed at once by passing the
data from the first rank of latches into the second rank. The
output connections always reflect the data programmed into the
second rank of latches and do not change until the first rank of
data is passed into the second rank.

If necessary for system verification, the data in the second rank

f latches can be read back from the control interface.

o

At any time, a reset pulse can be applied to the control interface
to

globally reset the appropriate second rank data bits, disabling
all 17 signal output pairs. This feature can be used to avoid
output bus contention on system startup. The contents of the
first rank remain unchanged.

The control interface pins are connected via logic-level trans-

tors. These translators allow programming and readback of

la
the control interface using logic levels different from those in
the signal matrix.

TO 17× 33

SWITCH
MATRIX

33

7

33

7

33

7

33

7

1 OF 33

DECODERS

To facilitate multiple chip address decoding, there is a chip­s

elect pin. All logic signals except the reset pulse are ignored
unless the chip select pin is active. The chip select pin disables
only the control logic interface and does not change the
operation of the signal matrix. The chip select pin does not
power down any of the latches, so any data programmed in the
latches is preserved.

All control pins are level-sensitive, not edge-triggered.

CONTROL PIN DESCRIPTION

A[4:0] Inputs

Output address pins. The binary encoded address applied to
these 5 input pins determines which one of the 17 outputs is
being programmed (or being read back). The most significant
bit (MSB) is A4.

D[6:0] Inputs/Outputs

2169-031

Input configuration data pins. In write mode, the binary
encoded data applied to the D pins [6:0] determines which of
33 inputs is to be connected to the output specified with the
A pins [4:0]. The MSB is D5 and the least significant bit (LSB) is
D0. Bit D6 is the enable bit, setting the specified output signal
pair to an enabled state if D6 is logic high or disabled to a high
impedance state if D6 is logic low. In readback mode, the
D pins [6:0] are low impedance outputs, indicating the data­word stored in the second rank for the output specified with the
A pins [4:0]. The readback drivers are designed to drive high
impedances only, so external drivers connected to the D
pins [6:0] should be disabled during readback mode.

Input

WE

First Rank Write Enable. Forcing this pin to logic low allows the
data on the D pins [6:0] to be stored in the first rank latch for
the output specified by the A pins [4:0]. The

pin must be

WE
returned to a logic high state after a write cycle to avoid
overwriting the first rank data.

UPDATE

Input

Second Rank Write Enable. Forcing this pin to logic low allows
the data stored in all 17 first rank latches to be transferred to the
second rank latches. The signal connection matrix is repro­grammed when the second rank data is changed. This is a
global pin, transferring all 17 rows of data at once. It is not
necessary to program the address pins. It should be noted that
after the initial power-up of the device, the first rank data is
undefined. It may be desirable to preprogram all 17 outputs
before performing the first update cycle.

Rev. B | Page 17 of 40

AD8151

www.BDTIC.com/ADI

Input

RE

Second Rank Read-Enable. Forcing this pin to logic low enables
the output drivers on the bidirectional D pins [6:0], entering
the readback mode of operation. By selecting an output address
with the A pins [4:0] and forcing

data stored in the second rank latch for that output address is
written to the D pins [6:0]. Data should not be written to the
D pins [6:0] externally while in readback mode.

and WE pins are not exclusive, and can be used at the

The

RE
same time, but data should not be written to the D pins [6:0]
from external sources while in readback mode.

Input

CS

Chip-Select. This pin must be forced to logic low to program or
receive data from the logic interface, with the exception of the

pin, described in the next section. This pin has no

RESET
effect on the signal pairs and does not alter any of the stored

control data.

Input

RESET

Global Output Disable Pin. Forcing the

resets the enable bit, D6, in all 17 second rank latches,
regardless of the state of any of the other pins. This has the
effect of immediately disabling the 17 output signal pairs in the
matrix.

to logic low, the 7-bit

RE

pin to logic low

RESET

It is useful to momentarily hold

powering up the AD8151 in a system that has multiple output
signal pairs connected together. Failure to do this can result in
several signal outputs contending after power-up. The

pin is not gated by the state of the chip-select pin,

be noted that the

which contains undefined data after power-up.

pin does not program the first rank,

RESET

at a logic low state when

RESET

RESET

. It should

CS

CONTROL INTERFACE TRANSLATORS

The AD8151 control interface has two supply pins, VDD and VSS.
The potential between the positive logic supply, V
negative logic supply, V
5 V. Regardless of supply, the logic threshold is approximately

1.6 V above V
CMOS and TTL logic drivers. The signal matrix supplies, V
and V

, can be set independently of the voltage on VDD and VSS,

EE

with the constraints that (V
allow operation of the control interface on 3 V or 5 V, while the
signal matrix is operated on 3.3 V or 5 V PECL or –3.3 V or
–5 V ECL.

, allowing the interface to be used with most

SS

, must be at least 3 V and no more than

SS

− VEE) ≤ 10 V. These constraints

DD

, and the

DD

CC

Rev. B | Page 18 of 40

AD8151

V

www.BDTIC.com/ADI

CIRCUIT DESCRIPTION

The AD8151 is a high speed 33 × 17 differential crosspoint

switch designed for data rates up to 3.2 Gbps per channel. The

AD8151 supports PECL-compatible input and output levels

when operated from a 5 V supply (V

= 5 V, VEE = GND), or

CC

ECL-compatible levels when operated from a –5 V supply

(V

= GND, VEE = –5 V). To save power, the AD8151 can run

CC

from a +3.3 V supply to interface with low voltage PECL

circuits or a –3.3 V supply to interface with low voltage ECL

circuits. The AD8151 utilizes differential current-mode outputs

with an individual disable control, which facilitates busing the

outputs of multiple AD8151s together to assemble larger switch

arrays. This feature also reduces system crosstalk and can

greatly reduce power dissipation in a large switch array. A single

external resistor programs the current for all enabled output

stages, allowing user control over output levels with different

output termination schemes and transmission line

characteristic impedances.

High Speed Data Inputs (INxxP, INxxN)

The AD8151 has 33 pairs of differential voltage-mode inputs.

The common-mode input range extends from the positive

supply voltage (V

input levels (V

) down to include standard ECL or PECL

CC

– 2 V). The minimum differential input

CC

voltage is 200 mV. Unused inputs may be connected directly to

any level within the allowed common-mode input range. A

simplified schematic of the input circuit is shown in Figure 33.

V

CC

INxxP

V

EE

INxxN

02169-033

Figure 33. Simplified Input Circuit

To maintain signal fidelity at the high data rates supported by

the AD8151, the input transmission lines should be terminated

as close to the input pins as possible. The preferred input

termination structure depends primarily on the application and

the output circuit of the data source. Standard ECL components

have open emitter outputs that require pull-down resistors.

Three input termination networks suitable for this type of

source are shown in

th

e transmission line is shown as Z
in the Thevenin termination are chosen to synthesize a V
source with an output resistance of Z
output voltage equal to V

Figure 34. The characteristic impedance of

. The resistors, R1 and R2,

O

TT

and an open-circuit

O

– 2 V. The load resistors (RL) in the

CC

differential termination scheme are needed to bias the emitter
followers of the ECL source.

V

CC

Z

ECL SOURCE

O

Z

O

Z

O

VTT = VCC– 2V

INxxN

INxxP

Z

O

(a)

V

CC

R

ECL SOURCE

L

V

EE

Figure 34. AD8151 Input Termination from ECL/PECL Sources: (a) Parallel

Te

rmination Using V

Supply, (b) Thevenin Equivalent Termination,

TT

and (c) Differential Termination

If the AD8151 is driven from a current-mode output stage such
as another AD8151, the input termination should be chosen to
accommodate that type of source, as explained in the following
section.

High speed Data Outputs (OUTyyP, OUTyyN)

The AD8151 has 17 pairs of differential current-mode outputs.
The output circuit, shown in Figure 35, is an open-collector

urrent switch with resistor-programmable tail current

NPN c
and output compliance extending from the positive supply
voltage (V
(V

CC

) down to standard ECL or PECL output levels

CC

− 2 V). The outputs can be disabled individually to permit
outputs from multiple AD8151s to be connected directly. Since
the output currents of multiple enabled output stages sum when
directly connected, care should be taken to ensure that the
output compliance limit is not exceeded at any time by disabling
the active output driver before enabling an inactive driver.

VCC– 2V

DISABLE

V

EE

Figure 35. Simplifie

V

CC

Z

Z

ECL SOURCE

Z

O

2Z

Z

R

L

O

O

(c)

CC

OUTyyP OUTyyN

I

OUT

V

EE

d Output Circuit

VCC– 2V

R1

O

O

R2 R2

V

(b)

INxxN

INxxP

EE

02169-035

R1

INxxN

INxxP

02169-034

Rev. B | Page 19 of 40

AD8151

www.BDTIC.com/ADI

To ensure proper operation, all outputs (including unused
output) must be pulled high using external pull-up networks to
a level within the output compliance range. If outputs from
multiple AD8151s are wired together, a single pull-up network
can be used for each output bus. The pull-up network should be
chosen to keep the output voltage levels within the output
compliance range at all times. Recommended pull-up networks
to produce PECL/ECL 100 kΩ and 10 kΩ compatible outputs
are shown in

ed to provide V

us

AD8151

OUTyyN

Figure 36. Output Pull-Up Networks for PECL/ECL: a) 100 kΩ and b) 10kΩ

Figure 36. Alternatively, a separate supply can be

OUTyyP

, making R

COM

V

CC

R

COM

V

COM

R

L

R

L

and D

COM

AD8151

OUTyyN
OUTyyP

COM

R

L

unnecessary.

V

CC

D

COM

V

COM

R

L

02169-036

The output levels are

= V

V

OH

V

OL

V

SWING

V

COM

V

COM

The common-mode adjustment element (R

COM

= V

– I

COM

= VOH − VOL = I
= VCC – I
= VCC – V(D

OUTRL

OUTRCOM

COM

OUTRL

(100 kΩ mode)

) (10 kΩ mode)

COM

or D

COM

) can be
omitted if the input range of the receiver includes the positive
supply voltage. The bypass capacitors reduce common-mode
perturbations by providing an ac short from the common nodes
(V

) to ground. When busing together the outputs of

COM

multiple AD8151s or when running at high data rates, double
termination of its outputs is recommended to mitigate the
impact of reflections due to open transmission line stubs and
the lumped capacitance of the AD8151 output pins. A possible
connection is shown in

n ac short from the common nodes of the termination resistors

a

Figure 37; the bypass capacitors provide

to ground. To maintain signal fidelity at high data rates, the
stubs connecting the output pins to the output transmission
lines or load resistors should be as short as possible.

V

CC

R

COM

V

O

O

R

L

RECEIVER

COM

R

R

L

Z

O

Z

O

L

02169-037

AD8151

OUTyyN
OUTyyP

AD8151

OUTyyN

OUTyyP

R

L

Z

Z

Figure 37. Double Termination of AD8151 Outputs

In this case, the output levels are

= V

V
V
V

OH

OL

SWING

– (¼)I

COM

= V

– (¾)I

COM

= VOH – VOL = (½)I

OUTRL

OUTRL

OUTRL

Output Current Set Pin (REF)

A simplified schematic of the reference circuit is shown in
Figure 38. A single external resistor connected between the REF

in and V

p

determines the output current for all output stages.

EE

This feature allows a choice of pull-up networks and trans­mission line characteristic impedances while still achieving a
nominal output swing of 800 mV. At low data rates, substantial
power savings can be achieved by using lower output swings
and higher load resistances.

AD8151

1.2V

Figure 38. Simplified Re

I

OUT

/20

V

CC

R

ference Circuit

SET

REF

V

EE

02169-038

The nominal output current is given by the following:

V2.1

⎞

⎛

20

OUTI

=

The minimum set resistor is R

= 25 mA. The maximum set resistor is R

I

OUT, MAX

resulting in I
output swing can be achieved in a 50 Ω load using R
(I

= 16 mA), or in a doubly terminated 75 Ω load using

OUT

= 1.13 kΩ (I

R

SET

⎟

⎜

SETR

⎠

⎝

= 960 Ω resulting in

SET, MIN

= 5 mA. Nominal 800 mV differential

OUT, MIN

= 21.3 mA). To minimize stray capacitance

OUT

SET, MAX

SET

= 4.8 kΩ

= 1.5 kΩ

and avoid the pickup of unwanted signals, the external set
resistor should be located close to the REF pin. Bypassing the
set resistor is not recommended.

Power Supplies

There are several options for the power supply voltages for the
AD8151, as there are two separate sections of the chip that
require power supplies. These are the control logic and the high
speed data paths. Depending on the system architecture, the
voltage levels of these supplies can vary.

Logic Supplies

The control (programming) logic is CMOS and is designed to
interface with any of the standard single-ended logic families
(CMOS or TTL). Its supply voltage pins are V
positive) and V

(Pin 152, logic ground). In all cases the logic

SS

ground should be connected to the system digital ground. V

(Pin 170, logic

DD

DD

should be supplied at between 3.3 V to 5 V to match the supply
voltage of the logic family that is used to drive the logic inputs.
V

should be bypassed to ground with a 0.1 μF ceramic capa-

DD

citor. The absolute maximum voltage from V

to VSS is 5.5 V.

DD

Rev. B | Page 20 of 40

AD8151

www.BDTIC.com/ADI

Data Path Supplies

The data path supplies have more options for their voltage levels.
The choices here affect several other areas, such as power
dissipation, bypassing, and common-mode levels of the inputs
and outputs. The more positive voltage supply for the data paths
is V

(Pin 41, Pin 98, Pin 149, and Pin 171). The more negative

CC

supply is V

, which appears on many pins that are not listed here.

EE

The maximum allowable voltage across these supplies is 5.5 V.
The first choice in the data path power supplies is to decide
whether to run the device as ECL or PECL. For ECL operation,
V

is at ground potential, while VEE is at a negative supply

CC

between –3.3 V to –5 V. This makes the common-mode voltage
of the inputs and outputs a negative voltage (see

+3.3V TO +5V

0.1μF

AD8151

V

CONTROL

LOGIC

DD

GND

DATA

PATHS

V

CC

Figure 39).

POWER DISSIPATION

For analysis, the power dissipation of the AD8151 can be
divided into three separate parts. These are the control logic,
the data path circuits, and the (ECL or PECL) outputs, which
are part of the data path circuits but can be dealt with
separately. The control logic is CMOS technology and does not
dissipate a significant amount of power. This power is, of
course, greater when the logic supply is 5 V rather than 3 V, but
overall it is not a significant amount of power and can be
ignored for thermal analysis.

V

DD

AD8151

CONTROL

LOGIC

I, DATA PATH
LOGIC

V

SS

GND GND

Figure 41. Major Power Consumption Paths

DATA

PATHS

V

EE

V

CC

I

OUT

V

OUT

R

OUT

LOW – V

EE

02169-041

V

EE

–3.3V TO –5V

0.1μF
(ONE FOR EVERY TWO V

EE

PINS)

02169-039

GND

V

SS

Figure 39. Power Supplies and Bypassing for ECL Operation

The proper way to run the device is to dc-couple the data paths
to other ECL logic devices that use ground as the most positive
supply and use a negative voltage for V

. However, if the part is

EE

to be ac-coupled, it is not necessary to have the input/output
common mode at the same level as the other system circuits,
but it is probably more convenient to use the same supply rails
for all devices. For PECL operation, V
and V

is a positive voltage from 3.3 V to 5 V. Thus, the

CC

is at ground potential

EE

common mode of the inputs and outputs is at a positive voltage.
These can then be dc-coupled to other PECL operated devices.
If the data paths are ac-coupled, then the common-mode levels
do not matter (see

0.1μF

AD8151

Figure 40. Power Supplies and Bypassing for PECL Operation

Figure 40).

+3.3V TO +5V

V

DD

CONTROL

LOGIC

V

SS

GND GND

+3.3V TO +5V

V

CC

DATA

PATHS

V

EE

0.1μF
(ONE FOR EACH V
4 REQUIRED)

PIN,

CC

02169-040

The data path circuits operate between the supplies VCC and

. As described in the power supply section, this voltage can

V

EE

range from 3.3 V to 5 V. The current consumed by this section
is constant, so operating at a lower voltage can decrease power
dissipation by about 35 percent. The power dissipated in the
data path outputs is affected by several factors. The first is
whether the outputs are enabled or disabled. The worst case
occurs when all of the outputs are enabled. The current
consumed by the data path logic can be approximated by

= 35 mA + [I

I

CC

This equation states that a minimum I

increases by a factor that is proportional to both the number

I

CC

/20 mA × 3 mA)] × (no. of outputs enabled)

OUT

of 35 mA always flows.

CC

of enabled outputs and the programmed output current.

The power dissipated in this circuit section is simply the voltage

f this section (V

o
worst case, assume that V

– VEE) times the current. To calculate the

CC

– VEE is 5.0 V, all outputs are

CC

enabled, and the programmed output current is 25 mA. The
power dissipated by the data path logic is

P = 5.0 V {35 mA + [4.5 mA + (25 mA/20 mA × 3 mA)] × 17} = 876 mW

The power dissipated by the output current depends on several
factors. These are the programmed output current, the voltage
drop from a logic low output to V

, and the number of enabled

EE

outputs. A simplifying assumption is that one of each (enabled)
differential output pair is low and draws the full output current
(and dissipates most of the power for that output), while the
complementary output of the pair is high and draws insignifi­cant current.

Rev. B | Page 21 of 40

AD8151

www.BDTIC.com/ADI

Thus, the power dissipation of the high output can be ignored and
the output power dissipation for each output can be assumed to
occur in a single static low output that sinks the full output pro­grammed current. The voltage across which this current flows can
also vary, depending on the output circuit design and the supplies
that are used for the data path circuitry. In general, however, there
is a voltage difference between a logic low signal and V
the drop across which the output current flows. For a worst case,
this voltage can be as high as 3.5 V. Thus, for all outputs enabled
and the programmed output current set to 25 mA, the power
dissipated by the outputs is

. This is

EE

There should be no thermal-relief pattern when connecting the
v

ias to the inner layers for these V
parallel and close to the pin leads can provide an even lower
thermal resistive path. If possible, use 2 oz copper foil to
provide better heat removal than 1 oz copper foil. The AD8151
package has a specified thermal impedance θ
is the worst case still-air value that can be expected when the
circuit board does not significantly enhance the heat removal
from the package. By using the concept described earlier or by
using forced-air circulation, the thermal impedance can be
lowered.

pins. Additional vias in

EE

of 30°C/W. This

JA

P = 3.5 V (25 mA) × 17 = 1.49 W

Heat Sinking

Depending on several factors in its operation, the AD8151 can
dissipate upwards of 2 W or more. The part is designed to
operate without the need for an explicit external heat sink.
However, the package design offers enhanced heat removal via
some of the package pins to the PC board traces. The V
on the input sides of the package (Pin 1 to Pin 46 and Pin 93 to
Pin 138) have finger extensions inside the package that connect
to the paddle upon which the IC chip is mounted. These pins
provide a lower thermal resistance from the IC to the V
than other pins that just have a bond wire. As a result, these
pins can be used to enhance the heat removal process from the
IC to the circuit board and ultimately to the ambient. The V
pins described earlier should be connected to a large area of
circuit board trace material to take the most advantage of their
lower thermal resistance. If there is a large area available on an
inner layer that is at V
from the package pin traces to this layer.

potential, then vias can be provided

EE

EE

EE

pins

pins

EE

For an extreme worst case analysis, the junction temperature
in

crease above the ambient can be calculated assuming 2 W of
power dissipation and a θ
the ambient. There are many techniques described earlier that
can mitigate this situation. Most actual circuits do not result in
this high an increase of the junction temperature above the
ambient.

of 30°C/W to yield a 60°C rise above

JA

Rev. B | Page 22 of 40

AD8151

www.BDTIC.com/ADI

APPLICATIONS

INPUT AND OUTPUT BUSING

Although the AD8151 is a digital part, in any application that
runs at high speed, analog design details have to be given very
careful consideration. At high data rates, the design of the signal
channels have a strong influence on data integrity and its
associated jitter and ultimately bit error rate (BER).

While it might be considered very helpful to have a suggested

cuit board layout for any particular system configuration, this

cir
is not something that can be practically realized. Systems come
in all shapes, sizes, speeds, performance criteria, and cost con­straints. Therefore, some general design guidelines are pre­sented that can be used for all systems and judiciously modified
where appropriate.

High speed signals travel best, that is, they maintain their

tegrity when they are carried by a uniform transmission line

in
that is properly terminated at either end. Any abrupt mis­matches in impedance or improper termination creates
reflections that add to or subtract from parts of the desired
signal. Small amounts of this effect are unavoidable, but too
much distorts the signal to the point that the channel
BER increases. It is difficult to fully quantify these effects
because they are influenced by many factors in the overall
system design.

A constant-impedance transmission line is characterized by
ha

ving a uniform cross-section profile over its entire length. In
particular, there should be no stubs, which are branches that
intersect the main run of the transmission line. These can have
an electrical appearance that is approximated by a lumped
element, such as a capacitor, or if long enough, by another
transmission line. If stubs are unavoidable in a design, their
effect can be minimized by making them as short as possible
and as high an impedance as possible.

Figure 37 shows a differential transmission line that connects
tw

o differential outputs from the AD8151 to a generic receiver.
A more generalized system can have more outputs bused and
more receivers on the same bus, but the same concepts apply.
The inputs of the AD8151 can also be considered as a receiver.
The transmission lines that bus the devices together are shown
with terminations at each end.

The individual outputs of the AD8151 are stubs that intersect

he main transmission line. Ideally, their current source outputs

t
would be infinite impedance, and they would have no effect on
signals that propagate along the transmission line. In reality,
each external pin of the AD8151 projects into the package and
has a bond wire connected to the chip inside. On-chip wiring
then connects to the collectors of the output transistors and to
ESD protection diodes.

Unlike some other high speed digital components, the AD8151
d

oes not have on-chip terminations. While this location would
be closer to the actual end of the transmission line for some
architectures, this concept can limit system design options. In
particular, it is not possible to bus more than two inputs or
outputs on the same transmission line and it is also not possible
to change the value of these terminations to use for different
impedance transmission lines. The AD8151, with the added
ability to disable its outputs, is much more versatile in these
types of architectures.

If the external traces are kept to a bare minimum, then the
output

presents a mostly lumped capacitive load of about 2 pF.
A single stub of 2 pF does not adversely affect signal integrity to
a large extent for most transmission lines, but the more of these
stubs, the greater their adverse influence.

One way to mitigate this effect is to locally reduce the capa-

itance of the main transmission line near the point of stub

c
intersection. Some practical means for doing this are to narrow
the PC board traces in the region of the stub and/or to remove
some of the ground plane(s) near this intersection. The effect of
these techniques is to locally lower the capacitance of the main
transmission line at these points, while the added capacitance of
the AD8151 outputs compensate for this reduction in capaci­tance. The overall intent is to create as uniform a transmission
line as possible.

In selecting the location of the termination resistors, it is

portant to keep in mind that, as their name implies, they

im
should be placed at either end of the line. There should be
minimal or no projection of the transmission line beyond the
point where it connects to the termination resistors.

EVALUATION BOARD

An evaluation board has been designed and is available to
rapidly test the main features of the AD8151. This board allows
the user to analyze the analog performance of the AD8151
channels and easily control the configuration of the board with
a PC. The board has limited numbers of differential input/
output pairs. Each differential pair of microstrips is connected
to either top mount or side launch SMA connectors. The top
mount SMA connectors are drilled and stubbed for superior
performance. The FR4 type board contains a total of nine
outputs (all even numbered outputs) and 20 inputs (0, 2, 4, 6, 8,
10, 12, 13, 14, 15, 16, 17, 18, 20, 22, 24, 26, 28, 30, 32). It is
important to note that the shells of the SMA connectors are
attached to V
possible during testing.

. This makes only ECL or negative level swings

CC

Rev. B | Page 23 of 40

AD8151

www.BDTIC.com/ADI

POWER SUPPLIES

The AD8151 is designed to work with standard ECL logic
levels. This means that V
supply. The shells of the I/O SMA connectors are at V
potential. Thus, when operating in the standard ECL
configuration, test equipment can be directly connected to the
board, since the test equipment also has its connector shells at
ground potential.

Operating in PECL mode requires V
voltage while V

is at ground. Since this generates a positive

EE

voltage at the shells of the I/O connectors, it can cause problems
when directly connecting to test equipment. Some equipment,
such as battery-operated oscilloscopes, can be floated from
ground, but care should be taken with line-powered equipment
to avoid creating a dangerous situation. Refer to the manual of
the test equipment that is being used.

is at ground and VEE is at a negative

CC

CC

to be at a positive

CC

There are additional higher value capacitors elsewhere on the
bo

ard for bypassing at lower frequencies. The location of these

capacitors is not as critical.

Input and Output Considerations

Each input contains a 100 Ω differential termination. Although
differential termination eases board layout due to its compact
nature, it can cause problems with the driving generator. A typical
pulse or pattern generator wants to see 50 Ω to ground (or to –2 V
in some cases). High speed probing of the input has shown that if
this type of termination is not present, input amplitudes can be
slightly off. The dc input levels can be even more affected.
Depending on the generator used, these levels can be off as much as
800 mV in either direction. A correction for this problem is to
attach a 6 dB attenuator to each P and N input. Because the
AD8151 has a large common-mode voltage range on its input
stage, it is not significantly affected by dc level errors.

The voltage difference from V

to VEE can range from 3 V to

CC

5 V. Power savings can be realized by operating at a lower
voltage without any compromise in performance.

A separate connection is provided for V
potential of the outputs. This can be at a voltage as high as V
but power savings can be realized if V

, the termination

TT

is at a voltage that is

TT

CC

somewhat lower.

As a practical matter, current on the evaluation board flows

om the V

fr
multiple outputs of the AD8151 and to the V
running in ECL mode, V

supply through the termination resistors into the

TT

supply. When

EE

should be at a negative supply.

TT

Most power supplies do not allow a simultaneous ground

nnection to V

co

and a negative supply at VTT, because it

CC

would force the source current to originate from a negative
supply, which wants to flow to the more-negative V

. In this

EE

case, the source current does not then return to the ground
terminal of the V
V

when running in ECL mode or a true bipolar supply should

EE

supply. Thus, VTT should be referenced to

TT

be used.

The digital supply is provided to the AD8151 by the V
V

pins. VSS should always be at ground potential to make it

SS

compatible with standard CMOS or TTL logic. V

DD

can range

DD

and

from 3 V to 5 V, and should be matched to the supply voltage of
the logic used to control the AD8151. However, since PCs use
5 V logic on their parallel port, V

should be 5 V when using a

DD

PC to program the AD8151.

On this evaluation board, all un

used inputs are tied to V

CC

(GND). All outputs, whether attached to connectors or not, are
tied to V

through a 49.9 Ω resistor. The AD8151 device is on

TT

the component side of the board, while input terminations and
output back terminations are on the circuit side. The input

,

signals from the circuit side transit through via holes to the
DUT’s pads. The component-side output signals connect to via
holes and to circuit-side 49.9 Ω termination resistors.

Board Construction

For this board, FR4 material was chosen over more exotic board
materials. Tests show exotic materials are unnecessary. This is a
4-layer board, so power is bused on both external and internal
layers. Test structures show microstrip performance is unaf­fected by the dc bias levels on the plane beneath it.

The board manufacturing process should ensure a controlled

mpedance board. The board stack consists of a 5-mil-thick

i
layer between external and internal layers. This allows the use of
an 8-mil-wide microstrip trace running from the SMA con­nector to the DUT’s pads. The narrow trace eliminates the need
to reduce the trace width as the DUT’s pads are approached and
helps to control the microstrip trace impedance. The thin 5-mil
dielectric also reduces crosstalk by confining the electromag­netic fields between the trace and the plane below.

Bypassing

Most of the board’s bypass capacitors are opposite the DUT on
the solder side and are connected between V

and VEE. This is

CC

where they are most effective. For low inductance, use 0.01 μF
ceramic chip capacitors.

Rev. B | Page 24 of 40

AD8151

www.BDTIC.com/ADI

CONFIGURATION PROGRAMMING

The board is configurable by one of two methods. For ease of
use, custom software is provided that controls the AD8151
programming via the parallel port of a PC. This requires a
standard printer cable that has a DB-25 connector at one end
(parallel-port or printer-port interface) and a Centronix
connector at the other, which connects to P2 of the AD8151
evaluation board. The programming with this setup is serial, so
it is not the fastest way to configure the AD8151 matrix.
However, the user interface makes it very convenient to use this
programming method.

If a high speed programming interface is desired, the AD8151
addr

ess and data buses are directly available on P3. The source
of the program signals can be a piece of test equipment such as
the Tektronix HFS-9000 digital test generator or other hardware
that generates programming signals. When using the PC inter­face, the jumper at W1 should be installed and no connections
should be made to P3. When using the P3 interface, no jumper
is installed at W1. There are locations for termination resistors
for the address and data signals, if needed.

SOFTWARE INSTALLATION

The software to operate the AD8151 is provided on two 3.5"
floppy disks. To install the software on a PC:

nsert Disk 1 into the floppy disk drive.

1. I

After running the software, the user is prompted to identify

hich of three software drivers is used with the PC parallel

w
port. The default is LPT1, which is most commonly used.
However, some laptops commonly use the PRN driver. It is also
possible that some systems are configured with the LPT2 driver.
If it is not known which driver is used, it is best to select LPT1
and proceed to the next screen, which displays the buttons that
allow the connection of inputs to outputs of the AD8151. All of
the outputs should be in the output off state after the program
starts running. Any of the active buttons can be selected by
clicking the mouse, which sends out a burst of programming
data.

After the software driver has been selected, the user can
ge

nerate a steady stream of programming signals out of the
parallel port by holding down the left or right arrow key on the
keyboard. The clock test point on the AD8151 evaluation board
can be monitored with an oscilloscope for any activity (a user­supplied printer cable must be connected). If there is a square­wave present, the proper software driver is selected for the PC’s
parallel port.

If there is no signal present, select another driver by clicking

Pa

rallel Port on the File menu. Select a different software

driver and carry out the test described previously until signal
activity is present at the clock test point.

un the setup.exe program. This program routinely installs

2. R

the software.

3. I

nsert Disk 2 when prompted.

4. S

elect a program directory when prompted.

Rev. B | Page 25 of 40

AD8151

www.BDTIC.com/ADI

SOFTWARE OPERATION

Click any button in the matrix to program the input to output
c

onnection. This sends the proper programming sequence out
the PC parallel port. Since only one input can be programmed
to a given output at one time, clicking a button in a horizontal
row cancels the other selection that is already selected in that
row. However, any number of outputs can share the same input.

A shortcut for programming all outputs to the same input is to

e the broadcast feature. Click Broadcast Connection and a

us
screen appears that prompts the user to select which input
should be connected to all outputs. Type in an integer from 0 to
32 and then click OK.

AD8151

This sends out the proper program data and returns to the main
screen with a full column of buttons selected under the chosen
input.

The Off col
disable all outputs, click Global Reset. This button selects a full
column of Off buttons.

Two scratch pad memories (Memory 1 and Memory 2) are

rovided to conveniently save a particular configuration.

p
However, these registers are erased when the program is
terminated. For long term storage of configurations, the disk
storage memory should be used. The Save and Load selections
can be accessed from the File menu.

umn can be used to disable the desired output. To

Figure 42. Evaluation Board Controller

Rev. B | Page 26 of 40

02169-042

AD8151

www.BDTIC.com/ADI

02169-043

Figure 43. Component Side

Rev. B | Page 27 of 40

AD8151

www.BDTIC.com/ADI

02169-044

Figure 44. Circuit Side

Rev. B | Page 28 of 40

AD8151

www.BDTIC.com/ADI

02169-045

Figure 45. Silkscreen Top

Rev. B | Page 29 of 40

AD8151

www.BDTIC.com/ADI

02169-046

Figure 46. Solder Mask Top

Rev. B | Page 30 of 40

AD8151

www.BDTIC.com/ADI

02169-047

Figure 47. Silkscreen Bottom

Rev. B | Page 31 of 40

AD8151

www.BDTIC.com/ADI

02169-048

Figure 48. Solder Mask Bottom

Rev. B | Page 32 of 40

AD8151

www.BDTIC.com/ADI

02169-049

Figure 49. INT1 (V

)

EE

Rev. B | Page 33 of 40

AD8151

www.BDTIC.com/ADI

02169-050

Figure 50. INT2 (V

)

CC

Rev. B | Page 34 of 40

AD8151

C

www.BDTIC.com/ADI

EE

C

EE

REF

151

REF
V

150

V

V

CC

V

C8

0.01μF

EE

V

CC

149

148

IN15N

IN15P

147

146

V

C9

0.01μF

EE

V

V

IN14N

IN14P

145

144

143

142

87838889909192

CC

IN13N

IN13P

141

140

C10

0.01μF

EE

V

139

V

CC

C30

0.01μF

138

V

EE

137

IN12N

136

IN12P

135

V

EE

134

IN11N

133

IN11P

132

V

EE

131

IN10N

130

IN10P

129

V

EE

128

IN09N

127

IN09P

126

V

EE

125

IN08N

124

IN08P

123

V

EE

122

IN07N

121

IN07P

120

V

EE

119

IN06N

118

IN06P

117

V

EE

116

IN05N

115

IN05P

114

V

EE

113

IN04N

112

IN04P

111

V

EE

110

IN03N

109

IN03P

108

V

EE

107

IN02N

106

IN02P

105

V

EE

104

IN01N

103

IN01P

102

V

EE

101
100

99
98
97
96
95
94
93

IN00N
IN00P
V

EE

VEEA0
OUT00P
OUT00N
V

A1

EE

V

EE

C60

0.01μF
V

EE

V

CC

EE

V

EE

V

CC

V

EE

V

V

CC

C5

0.01μF

EE

V

V

CC

C4

0.01μF

EE

V

V

CC

C29

0.01μF

C31

0.01μF

V

CC

V

EE

V

EE

V

CC

C32

0.01μF

C11

0.01μF

V

EE

V

CC

V

EE

V

CC

C15

0.01μF

V
IN20P
IN20N

IN21P
IN21N

IN22P
IN22N

V
IN23P
IN23N

V
IN24P
IN24N

V
IN25P
IN25N

V
IN26P
IN26N

V
IN27P
IN27N

V
IN28P
IN28N

V
IN29P
IN29N

V
IN30P
IN30N

V
IN31P
IN31N

V
IN32P
IN32N

V

OUT16N
OUT16P

VEEA16

V

1

EE

2
3
4
5
6
7
8
9

10

EE

11
12
13

EE

14
15
16

EE

17
18
19

EE

20
21
22

EE

23
24
25

EE

26
27
28

EE

29
30
31

EE

32
33
34

EE

35
36
37

EE

38
39
40

EE

41
42
43
44
45
46

EE

IN19N

IN19P

IN18N

IN18P

IN17N

184

183

182

181

180

179

178

177

PIN 1
INDICATOR

4748495051525354555657

C6

0.01μF

IN17P

IN16N

IN16P

176

175

174

173

596061626364656667

58

EE

V

CC

V

C7

0.01μF

CC

V

EE

V

C13

0.01μF

DD

RESETCSREWEUPDATEA0A1A2A3A4D0D1D2D3D4D5D6

V

171

170

169

168

167

166

165

164

163

172

162

161

160

AD8151

184L LQFP

TOP VIEW

(Not to Scale)

68

6970717274757677787379808182848586

159

158

157

C14

0.01μF

156

155

V

DD

154

C12

0.01μF

R203

1.5kΩ

153

V

152

SS

EE

V

A15

EE

V

OUT15P

OUT15N

A14
V

OUT14P

OUT14N

EE

OUT13N

A13

EE

V

OUT13P

A12
V

OUT12P

OUT12N

EE

OUT11N

A11

EE

V

OUT11P

OUT10N

A10

EE

V

OUT10P

A9
V

OUT09P

OUT09N

EE

OUT08N

A8

EE

V

OUT08P

A7

EE

V

OUT07P

OUT07N

A6
V

OUT06P

OUT06N

EE

OUT05N

A5

EE

V

OUT05P

OUT04P

OUT04N

Figure 51. Bypassing Schematic

Rev. B | Page 35 of 40

A4

EE

V

A3
V

OUT03P

OUT03N

EE

OUT02N

A2

EE

V

OUT02P

V

OUT01P

OUT01N

EE

02169-051

AD8151

www.BDTIC.com/ADI

R19

1.65kΩ
P4

P5

R21

1.65kΩ

R28

1.65kΩ

P8

P9

R26

1.65kΩ

R34

1.65kΩ

P12

P13

R32

1.65kΩ

V

CC

IN00P

R20
105Ω

IN00N

V

EE

V

CC

IN02P

R27
105Ω

IN02N

V

EE

V

CC

IN04P

R33
105Ω

IN04N

V

EE

R40

1.65kΩ
P16

P17

R38

1.65kΩ

R44

1.65kΩ

P20

P21

R46

1.65kΩ

R50

1.65kΩ

P24

P25

R52

1.65kΩ

V

CC

IN06P

R39

105Ω

IN06N

V

EE

V

CC

IN08P

R45

105Ω

IN08N

V

EE

V

CC

IN10P

R51

105Ω

IN10N

V

EE

R58

1.65kΩ
P28

P29

R56

1.65kΩ

R59

1.65kΩ
P30

P31

R61

1.65kΩ

R62

1.65kΩ
P32

P33

R64

1.65kΩ

R65

1.65kΩ
P34

P35

R67

1.65kΩ

R68

1.65kΩ

P36

P37

R70

1.65kΩ

R71

1.65kΩ

P38

P39

R73

1.65kΩ

V

CC

IN12P

R57

105Ω

IN12N

V

EE

V

CC

IN13P

R60
105Ω

IN13N

V

EE

V

CC

IN14P

R63

105Ω

IN14N

V

EE

V

CC

IN15P

R66
105Ω

IN15N

V

EE

V

CC

IN16P

R69

105Ω

IN16N

V

EE

V

CC

IN17P

R72
105Ω

IN17N

V

EE

R89

1.65kΩ
P40

P41

R91

1.65kΩ

R85

1.65kΩ

P44

P45

R83

1.65kΩ

R79

1.65kΩ
P48

P49

R77

1.65kΩ

V

CC

1.65kΩ

IN18P

R90

105Ω

IN18N

1.65kΩ

V

EE

V

CC

1.65kΩ

IN20P

R84

105Ω

IN20N

1.65kΩ

V

EE

V

CC

1.65kΩ

IN22P

R78

105Ω

IN22N

1.65kΩ

V

EE

V

CC

P

IN01, IN03, IN05, IN07,
IN09, IN11, IN19, IN21,
IN23, IN25, IN27, IN29, IN31

N

P52

P53

P56

P57

R100

R104

P60

P61

R106

R94

R92

R98

V

CC

IN24P

R93

105Ω

IN24N

V

EE

V

CC

IN26P

R99

105Ω

IN26N

V

EE

V

CC

IN28P

R105

105Ω

IN28N

V

EE

R116

1.65kΩ
P64

P65

R118

1.65kΩ

R112

1.65kΩ

P68

P69

R110

1.65kΩ

V

CC

IN30P

R117
105Ω

OUT08P

OUT08N

IN30N

V

EE

OUT09P

OUT09N

OUT10P

OUT10N

V

CC

OUT11P

IN32P

R111

105Ω

OUT11N

IN32N

V

EE

OUT12P

OUT12N

OUT13P

OUT13N

OUT14P

OUT14N

OUT15P

OUT15N

OUT16P

OUT16N

R160

49.9Ω

R162

49.9Ω

R165

49.9Ω

R163

49.9Ω

R175

49.9Ω

R173

49.9Ω

R170

49.9Ω

R172

49.9Ω

R185

49.9Ω

R183

49.9Ω

R180

49.9Ω

R182

49.9Ω

R195

49.9Ω

R193

49.9Ω

R190

49.9Ω

R192

49.9Ω

R200

49.9Ω

R198

49.9Ω

P87

P86

P83

P82

P79

P78

P75

P74

P71

P70

OUT00P

V

TT

OUT00N

OUT01P

V

TT

OUT01N

OUT02P

V

TT

OUT02N

OUT03P

V

TT

OUT03N

OUT04P

V

TT

OUT04N

OUT05P

V

TT

OUT05N

OUT06P

V

TT

OUT06N

OUT07P

V

TT

OUT07N

V

V

TT

TT

V

TT

V

TT

R121

49.9Ω

R122

49.9Ω

R125

49.9Ω

R127

49.9Ω

R130

49.9Ω

R132

49.9Ω

R135

49.9Ω

R133

49.9Ω

R140

49.9Ω

R142

49.9Ω

R145

49.9Ω

R143

49.9Ω

R150

49.9Ω

R152

49.9Ω

R155

49.9Ω

R153

49.9Ω

C16

0.01μF

C82

0.01μF

C83

0.01μF

P103

P102

P99

P98

P95

P94

P91

P90

V

V

V

V

TT

V

TT

V

TT

V

TT

V

TT

V

TT

V

TT

V

TT

CC

CC

CC

02169-052

Figure 52. Evaluation Board Input/Output Schematic

Rev. B | Page 36 of 40

AD8151

A

www.BDTIC.com/ADI

CLK P2 6

P2 5

DAT

V

P2 25

SS

CHIP_SELECT

CHIP_SELECT P3 9

CLK

DATA

3

74HC14A174HC14

V

SS

P2 7

READ

P2 3

RESET

P2 8

WRITE

P2 4

UPDATE

P2 2

WRITE P3 13

RESET

P3 7

READ P3 11

D0 P3 27
A4

P3 25

A3

P3 23

A2

P3 21
A1 P3 19
A0

P3 17
D6 P3 39
D5 P3 37
D4

P3 35
D3

P3 33
D2

P3 31
D1

P3 29

UPDATE P3 15

V

P3 5

DD

V

P3 14

SS

P3 8
P3 12
P3 28
P3 26
P3 24
P3 22
P3 20
P3 18
P3 40
P3 38
P3 36
P3 34
P3 32
P3 30
P3 16
P3 10

P3 6

A1

1
74HC14

4

V

DD

V

SS

2

A1

9
74HC14
11 10

74HC14

13

74HC14

9
10

74HC132

12
13

74HC132

V

C88

V

DD

SS

A1

A1

A4

A4

8

12

SS

C89

0.1μF

8

11

TP20

TP14
TP15
TP16
TP17
TP18
TP19

.

V

DD

V

SS

02169-053

1

A1

5

6

V

DD

V

SS

R1

20kΩ

W1

V

DD

V

SS

OUT_EN

2

D0

3

D1

4

D2

5

D3

A2

6

D4

74HC74 74HC74

7

D5

8

D6

9

D7

10

GND

V

SS

R8

SS

SS

SS

SS

R3

49kΩ

R5

49kΩ

R2

49kΩ

R4

49kΩ

R6

49kΩ

49Ω

R10
49Ω

1
2

74HC132

V

V

V

V

V

SS

V

SS

V

SS

V

SS

V

SS

20

V

CC

19

Q0

18

Q1

17

Q2

16

Q3

15

Q4

14

Q5

13

Q6

12

Q7

11

CLK

R7

49Ω

R9

49Ω

R11
49Ω

A4

3

160A4

161A3

162A2

163A1

164A0

A4

4
5

74HC132

TP5
TP6

TP4

TP7
TP8

CHIP_SELECT
168

UPDATE
165

WRITE
166

RESET
169

READ
167

V

DD

V

SS

6

1

OUT_EN

2

D0

3

D1

4

D2

5

D3

6

D4

7

D5

8

D6

9

D7

10

GND

V

SS

R13

49Ω

V

SS

V

SS

R15

49Ω

V

SS

V

SS

R17

49Ω

V

SS

V

SS

TP9
TP10
TP11
TP12
TP13

V

TT

P1 6

C3
10μF

+

P1 1

V

CC

P1 2

+

C1
10μF

P1 3

V

EE

P1 4

V

P1 7

DD

+

C2

P1 5

P104
P105

10μF

V

SS

20

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

CC

R12

49Ω

R14
49Ω

R16
49Ω

R18
49Ω

TT
TT

CC
CC

EE
EE

DD

SS

V

DD

19
18
17
16
15
14
13
12
11

0.1μF

V

A3

CLK

V
V

V
V

V
V

V

V

V

DD

153D6

154D5

155D4

156D3

157D2

158D1

159D0

A1, 4 PIN 14 IS TIED TO VDD.
A1, 4 PIN 7 IS TIED TO V

V

V

DD

DD

C86

C87

0.1μF

0.1μF

V

V

SS

SS

Figure 53. Evaluation Board Logic Controls

Rev. B | Page 37 of 40

AD8151

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.75

0.60

0.45

1.60
MAX

184

1

PIN 1

22.20

22.00 SQ

21.80

TOP VIEW

(PINS DOWN)

139

138

20.20

20.00 SQ

19.80

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0.20

0.09
7°

3.5°
0°

0.08 MAX
COPLANARITY

46

VIEW A

47

0.40
BSC

LEAD PITCH

0.23

0.18

0.13

93

92

Figure 54. 184-Lead Low Profile Quad Flat Package [LQFP]

(ST-18

4)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8151AST 0°C to 85°C 184-Lead LQFP ST-184
AD8151ASTZ
AD8151-EVAL Evaluation Board

1

Z = Pb-free part.

1

0°C to 85°C 184-Lead LQFP ST-184

Rev. B | Page 38 of 40

AD8151

www.BDTIC.com/ADI

NOTES

Rev. B | Page 39 of 40

AD8151

www.BDTIC.com/ADI

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02169-0-12/05(B)

Rev. B | Page 40 of 40