Datasheet AD8150 Datasheet (ANALOG DEVICES)

33 × 17, 1.5 Gbps Digital

–

www.BDTIC.com/ADI

FEATURES

Low cost 33 × 17, fully differential, nonblocking array >1.5 Gbps per port NRZ data rate Wide power supply range: +5 V, +3.3 V, −3.3 V, −5 V Low power

400 mA (outputs enabled)

30 mA (outputs disabled) PECL and ECL compatible CMOS/TTL-level control inputs: 3 V to 5 V Low jitter: <50 ps p-p No heat sinks required Drives a backplane directly Programmable output current

Optimize termination impedance

User-controlled voltage at the load

Minimize power dissipation Individual output disable for busing and building Larger arrays Double row latch Buffered inputs Available in 184-lead LQFP

APPLICATIONS

HD and SD digital video Fiber optic network switching

GENERAL DESCRIPTION

AD81501 is a member of the Xstream line of products and is a breakthrough in digital switching, offering a large switch array (33 × 17) on very little power, typically less than 1.5 W. Additionally, it operates at data rates in excess of 1.5 Gbps per port, making it suitable for HDTV applications. Further, the pricing of the AD8150 makes it affordable enough to be used for SD applications. The AD8150 is also useful for OC-24 optical network switching.

The AD8150’s flexible supply voltages allow the user to operate with either PECL or ECL data levels and will operate down to

3.3 V for further power reduction. The control interface is CMOS/TTL compatible (3 V to 5 V).

Its fully differential signal path reduces jitter and crosstalk while allowing the use of smaller single-ended voltage swings. The AD8150 is offered in a 184-lead LQFP package that operates over the industrial temperature range of 0°C to 85°C.

UPDATE

RESET

1

Patent pending.

CS

RE

D

A

WE

500mV

100mV/

500mV

Crosspoint Switch

FUNCTIONAL BLOCK DIAGRAM

7

5

DIV

FIRST RANK

LATCH

OUTPUT

ADDRESS

DECODER

Figure 1. Functional Block Diagram

Figure 2. Output Eye Pattern, 1.5 Gbps

17

7-BIT

SECOND

RANK

×

17

7-BIT

LATCH

100ps/DIV

INPUT

DECODERS

AD8150

INP INN

33 33

17

33 × 17

DIFFERENTIAL

SWITCH MATRIX

17

AD8150

OUTP

OUTN

01074-001

01074-002

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD8150

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TABLE OF CONTENTS

Specifications..................................................................................... 3

High Speed Data Outputs (OUTyyP, OUTyyN) .................... 23

Absolute Maximum Ratings............................................................ 4

Maximum Power Dissipiation.................................................... 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Typical Performance Characteristics ............................................. 9

Test Circuit ......................................................................................13

Control Interface............................................................................. 14

Control Interface Truth Tables ................................................. 14

Control Interface Timing Diagrams ........................................15

Control Interface Programming Example .............................. 20

Control Interface Description................................................... 21

Control Pin Description............................................................ 21

Control Interface Translators.................................................... 22

Circuit Description......................................................................... 23

High Speed Data Inputs (INxxP, INxxN)................................ 23

Output Current Set Pin (REF).................................................. 24

Power Supplies............................................................................ 25

Power Dissipation....................................................................... 27

Heat Sinking................................................................................ 28

Applications..................................................................................... 29

AD8150 Input and Output Busing........................................... 29

Evaluation Board............................................................................ 30

Configuration Programming.................................................... 30

Power Supplies............................................................................ 30

Software Installation.................................................................. 30

Software Operation.................................................................... 31

PCB Layout...................................................................................... 32

Outline Dimensions....................................................................... 42

Ordering Guide .......................................................................... 42

REVISION HISTORY

9/05—Rev. 0 t o R e v. A

Updated Format..................................................................Universal

Change to Absolute Maximum Ratings......................................... 4

Changes to Maximum Power Dissipation Section....................... 4

Change to Figure 3 ........................................................................... 4

Changes to Figure 40...................................................................... 26

Updated Outline Dimensions....................................................... 42

Changes to Ordering Guide.......................................................... 42

Revision 0: Initial Version

Rev. A | Page 2 of 44

AD8150

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SPECIFICATIONS

At 25°C, VCC = 3.3 V to 5 V, VEE = 0 V, RL = 50 Ω (see Figure 25), I

Table 1

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

Max Data Rate/Channel (NRZ) 1.5 Gbps Channel Jitter Data rate < 1.5 Gbps 50 ps p-p RMS Channel Jitter VCC = 5 V 10 ps Propagation Delay Input to output 650 ps Propagation Delay Match 50 100 ps Output Rise/Fall Time 20% to 80% 100 ps

INPUT CHARACTERISTICS

Input Voltage Swing Differential 200 1000 mV p-p Input Voltage Range Common mode VCC − 2 VCC V Input Bias Current 2 μA Input Capacitance 2 pF Input VIN High VCC − 1.2 VCC − 0.2 V Input VIN Low VCC − 2.4 VCC − 1.4 V

OUTPUT CHARACTERISTICS

Output Voltage Swing Differential (see Figure 25) 800 mV p-p Output Voltage Range VCC − 1.8 VCC V Output Current 5 25 mA Output Capacitance 2 pF

POWER SUPPLY

Operating Range

PECL, VCC V ECL, VEE V VDD 3 5 V VSS 0 V

Quiescent Current

VDD 2 mA VEE All outputs enabled, I T All outputs disabled 30 mA

THERMAL CHARACTERISTICS

Operating Temperature Range 0 85 °C θJA 30 °C/W

LOGIC INPUT CHARACTERISTICS VDD = 3 V dc to 5 V dc

Input VIN High 1.9 VDD V Input VIN Low 0 0.9 V

= 0 V 3.3 5 V

EE

= 0 V −5 −3.3 V

CC

to T

MIN

450 mA

MAX

= 16 mA, unless otherwise noted.

OUT

= 16 mA 400 mA

OUT

Rev. A | Page 3 of 44

AD8150

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ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage VDD − VEE 10.5 V Internal Power Dissipation1

AD8150 184-Lead Plastic LQFP (ST) 4.2 W Differential Input Voltage VCC − VEE Output Short-Circuit Duration

Storage Temperature Range2 −65°C to +125°C

1

Specification is for device in free air (TA = 25°C):

184-lead plastic LQFP (ST): θJA = 30°C/W.

2

Maximum reflow temperatures are to JEDEC industry standard J-STD-020.

Observe power derating curves

MAXIMUM POWER DISSIPIATION

The maximum power that can be safely dissipated by the AD8150 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 125°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 125°C for an extended period can result in device failure.

While the AD8150 is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (125°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in

Figure 3.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

6

5

4

3

2

MAXIMUM POWER DISSIPATION (W)

1

–10 9080706050403020100

Figure 3. Maximum Power Dissipation vs. Temperature

AMBIENT TEMPERATURE (°C)

TJ = 150°C

01074-003

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 4 of 44

AD8150

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V IN20P IN20N

V IN21P IN21N

V IN22P IN22N

V IN23P IN23N

V IN24P IN24N

V IN25P IN25N

V IN26P IN26N

V IN27P IN27N

V IN28P IN28N

V IN29P IN29N

V IN30P IN30N

V IN31P IN31N

V IN32P IN32N

V

OUT16N OUT16P

VEEA16

V

EE

CCVDD

IN19N

IN19P

IN18N

IN18P

IN17N

179

OUT14P

178

A14 V

IN17P

177

176

175

A13

EE

V

OUT13P

OUT13N

VEEVEEVEEVEEV

184

183

182

181

180

1

EE

EE CC EE

EE

PIN 1

2

INDICATOR

3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

4748495051525354555657

EE

V

A15

EE

V

OUT15P

OUT15N

OUT14N

V

IN16N

174

58

OUT12N

IN16P

173

OUT12P

RESETCSREWEUPDATEA0A1A2A3A4D0D1D2D3D4D5D6

171

170

169

172

596061626364656667

A12

A11

EE

V

OUT11P

OUT11N

168

OUT10N

167

OUT10P

166

A10 V

EE

165

164

163

162

161

160

159

157

156

155

158

AD8150

184L LQFP TOP VIEW

(Not to Scale)

68

6970717274757677787379808182848586

A9

A8

EE

V

OUT09P

OUT08P

OUT09N

OUT08N

OUT07N

OUT07P

154

A7

A6

EE

V

OUT06P

OUT06N

REF

EE

REF

VSSVCCVEEVEEVEEV

153

152

151

A5

EE

V

OUT05P

OUT05N

V

150

OUT04N

149

OUT04P

IN15N

IN15P

IN14N

IN14P

147

146

145

144

143

148

A4

EE

V

OUT03P

OUT03N

142

87838889909192

A3

A2

EE

V

OUT02P

OUT02N

IN13N

141

OUT01N

IN13P

140

OUT01P

EE

139

138

V

EE

137

IN12N

136

IN12P

135

V

EE

134

IN11N

133

IN11P

132

V

EE

131

IN10N

130

IN10P

129

V

EE

128

IN09N

127

IN09P

126

V

EE

125

IN08N

124

IN08P

123

V

EE

122

IN07N

121

IN07P

120

V

EE

119

IN06N

118

IN06P

117

V

EE

116

IN05N

115

IN05P

114

V

EE

113

IN04N

112

IN04P

111

V

EE

110

IN03N

109

IN03P

108

V

EE

107

IN02N

106

IN02P

105

V

EE

104

IN01N

103

IN01P

102

V

EE

101

IN00N

100

IN00P

99

V

EE

98

V

CC

97

VEEA0

96

OUT00P

95

OUT00N

94

V

EE

93

V

EE

A1

EE

V

01074-004

Figure 4. Pin Configuration

Rev. A | Page 5 of 44

AD8150

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Table 3. Pin Function Descriptions

Pin No. Mnemonic Type Description

V

1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40, 42, 46, 47, 92, 93, 99, 102, 105, 108, 111, 114, 117, 120, 123, 126, 129, 132, 135, 138, 139, 142, 145, 148, 172, 175, 178, 181, 184

2 IN20P PECL High Speed Input 3 IN20N PECL High Speed Input Complement 5 IN21P PECL High Speed Input 6 IN21N PECL High Speed Input Complement 8 IN22P PECL High Speed Input 9 IN22N PECL High Speed Input Complement 11 IN23P PECL High Speed Input 12 IN23N PECL High Speed Input Complement 14 IN24P PECL High Speed Input 15 IN24N PECL High Speed Input Complement 17 IN25P PECL High Speed Input 18 IN25N PECL High Speed Input Complement 20 IN26P PECL High Speed Input 21 IN26N PECL High Speed Input Complement 23 IN27P PECL High Speed Input 24 IN27N PECL High Speed Input Complement 26 IN28P PECL High Speed Input 27 IN28N PECL High Speed Input Complement 29 IN29P PECL High Speed Input 30 IN29N PECL High Speed Input Complement 32 IN30P PECL High Speed Input 33 IN30N PECL High Speed Input Complement 35 IN31P PECL High Speed Input 36 IN31N PECL High Speed Input Complement 38 IN32P PECL High Speed Input 39 IN32N PECL High Speed Input Complement 41, 98, 149, 171 VCC Power supply Most Positive PECL Supply (common with other points labeled VCC) 43 OUT16N PECL High Speed Output Complement 44 OUT16P PECL High Speed Output 45 VEEA16 Power supply Most Negative PECL Supply (unique to this output) 48 OUT15N PECL High Speed Output Complement 49 OUT15P PECL High Speed Output 50 VEEA15 Power supply Most Negative PECL Supply (unique to this output) 51 OUT14N PECL High Speed Output Complement 52 OUT14P PECL High Speed Output 53 VEEA14 Power supply Most Negative PECL Supply (unique to this output) 54 OUT13N PECL High Speed Output Complement 55 OUT13P PECL High Speed Output 56 VEEA13 Power supply Most Negative PECL Supply (unique to this output) 57 OUT12N PECL High Speed Output Complement 58 OUT12P PECL High Speed Output 59 VEEA12 Power supply Most Negative PECL Supply (unique to this output) 60 OUT11N PECL High Speed Output Complement 61 OUT11P PECL High Speed Output 62 VEEA11 Power supply Most Negative PECL Supply (unique to this output) 63 OUT10N PECL High Speed Output Complement 64 OUT10P PECL High Speed Output

Power supply Most Negative PECL Supply (common with other points labeled VEE)

EE

Rev. A | Page 6 of 44

AD8150

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Pin No. Mnemonic Type Description

65 VEEA10 Power supply Most Negative PECL Supply (unique to this output) 66 OUT09N PECL High Speed Output Complement 67 OUT09P PECL High Speed Output 68 VEEA9 Power supply Most Negative PECL Supply (unique to this output) 69 OUT08N PECL High Speed Output Complement 70 OUT08P PECL High Speed Output 71 VEEA8 Power supply Most Negative PECL Supply (unique to this output) 72 OUT07N PECL High Speed Output Complement 73 OUT07P PECL High Speed Output 74 VEEA7 Power supply Most Negative PECL Supply (unique to this output) 75 OUT06N PECL High Speed Output Complement 76 OUT06P PECL High Speed Output 77 VEEA6 Power supply Most Negative PECL Supply (unique to this output) 78 OUT05N PECL High Speed Output Complement 79 OUT05P PECL High Speed Output 80 VEEA5 Power supply Most Negative PECL Supply (unique to this output) 81 OUT04N PECL High Speed Output Complement 82 OUT04P PECL High Speed Output 83 VEEA4 Power supply Most Negative PECL Supply (unique to this output) 84 OUT03N PECL High Speed Output Complement 85 OUT03P PECL High Speed Output 86 VEEA3 Power supply Most Negative PECL Supply (unique to this output) 87 OUT02N PECL High Speed Output Complement 88 OUT02P PECL High Speed Output 89 VEEA2 Power supply Most Negative PECL Supply (unique to this output) 90 OUT01N PECL High Speed Output Complement 91 OUT01P PECL High Speed Output 94 VEEA1 Power supply Most Negative PECL Supply (unique to this output) 95 OUT00N PECL High Speed Output Complement 96 OUT00P PECL High Speed Output 97 VEEA0 Power supply Most Negative PECL Supply (unique to this output) 100 IN00P PECL High Speed Input 101 IN00N PECL High Speed Input Complement 103 IN01P PECL High Speed Input 104 IN01N PECL High Speed Input Complement 106 IN02P PECL High Speed Input 107 IN02N PECL High Speed Input Complement 109 IN03P PECL High Speed Input 110 IN03N PECL High Speed Input Complement 112 IN04P PECL High Speed Input 113 IN04N PECL High Speed Input Complement 115 IN05P PECL High Speed Input 116 IN05N PECL High Speed Input Complement 118 IN06P PECL High Speed Input 119 IN06N PECL High Speed Input Complement 121 IN07P PECL High Speed Input 122 IN07N PECL High Speed Input Complement 124 IN08P PECL High Speed Input 125 IN08N PECL High Speed Input Complement 127 IN09P PECL High Speed Input 128 IN09N PECL High Speed Input Complement 130 IN10P PECL High Speed Input

Rev. A | Page 7 of 44

AD8150

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Pin No. Mnemonic Type Description

131 IN10N PECL High Speed Input Complement 133 IN11P PECL High Speed Input 134 IN11N PECL High Speed Input Complement 136 IN12P PECL High Speed Input 137 IN12N PECL High Speed Input Complement 140 IN13P PECL High Speed Input 141 IN13N PECL High Speed Input Complement 143 IN14P PECL High Speed Input 144 IN14N PECL High Speed Input Complement 146 IN15P PECL High Speed Input 147 IN15N PECL High Speed Input Complement 150 VEEREF R-program

151 REF R-program Connection Point for Output Logic Pull-Down Programming Resistor 152 VSS Power supply Most Negative Control Logic Supply 153 D6 TTL

154 D5 TTL (32) MSB Input Select 155 D4 TTL (16) 156 D3 TTL (8) 157 D2 TTL (4) 158 D1 TTL (2) 159 D0 TTL (1) LSB Input Select 160 A4 TTL (16) MSB Output Select 161 A3 TTL (8) 162 A2 TTL (4) 163 A1 TTL (2) 164 A0 TTL (1) LSB Output Select 165 166

167 168 169 170 VDD Power supply Most Positive Control Logic Supply

173 IN16P PECL High Speed Input 174 IN16N PECL High Speed Input Complement 176 IN17P PECL High Speed Input 177 IN17N PECL High Speed Input Complement 179 IN18P PECL High Speed Input 180 IN18N PECL High Speed Input Complement 182 IN19P PECL High Speed Input 183 IN19N PECL High Speed Input Complement

UPDATE WE RE CS RESET

TTL Second-Rank Program TTL First-Rank Program TTL Enable Readback TTL Enable Chip to Accept Programming TTL Disable All Outputs (Hi-Z)

Connection Point for Output Logic Pull-Down Programming Resistor (must be connected to V

Enable/DISABLE

Output

)

EE

Rev. A | Page 8 of 44

AD8150

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TYPICAL PERFORMANCE CHARACTERISTICS

100

VEE = –3.3V (VOH– VOL = 800mV)

80

100

VEE = –5V (VOH– VOL = 800mV)

80

60

JITTER (ps)

40

20

0

0 –0.2 –0.6 –0.8 –1.0 –1.2–0.4 –1.4

Figure 5. Jitter vs. V

100

80

60

JITTER (ps)

40

20

0

–2.0 –1.5 –0.5 0–1.0 0.5

Figure 6. Jitter vs. V

PK-PK

RMS

(V)

V

OH

1.5 Gbps, PRBS 23

OH

VEE = –3.3V (VIH– VIL = 800mV)

PK-PK

RMS

(V)

V

IN

1.5 Gbps, PRBS 23

IH

01074-005

01074-006

60

JITTER (ps)

40

20

0

0 –0.2 –0.6 –0.8 –1.0 –1.2–0.4 –1.4

Figure 8. Jitter vs. V

100

80

60

JITTER (ps)

40

20

0

–2.0 –1.5 –0.5 0–1.0 0.5

Figure 9. Jitter vs. V

PK-PK

RMS

V

(V)

OH

1.5 Gbps, PRBS 23

OH

VEE = –5V (VIH– VIL = 800mV)

PK-PK

RMS

V

(V)

IN

1.5 Gbps, PRBS 23

IH

01074-008

01074-009

100

80

60

JITTER (ps)

40

20

0

0.1 1.51.31.10.90.70.50.3

VEE = –3.3V

PK-PK

RMS

DATA RATE (Gbps)

Figure 7. Jitter vs. Data Rate, PRBS 23

01074-007

100

80

60

JITTER (ps)

40

20

0

0.1 1.51.31.10.90.70.50.3

Figure 10. Jitter vs. Data Rate, PRBS 23

Rev. A | Page 9 of 44

VEE = –5V

PK-PK

RMS

DATA RATE (Gbps)

01074-010

AD8150

www.BDTIC.com/ADI

100

80

VEE = –3.3V

100

VEE = –5V

80

60

JITTER (ps)

40

20

0

0 5 10 15 20 25

Figure 11. Jitter vs. I

100

80

60

JITTER (ps)

40

20

PK-PK

RMS

(mA)

I

OUT

1.5 Gbps, PRBS 23

OUT

VEE = –3.3V

PK-PK

RMS

01074-011

60

PK-PK

JITTER (ps)

40

20

0

0 5 10 15 20 25

Figure 14. Jitter vs. I

100

80

60

JITTER (ps)

40

20

RMS

(mA)

I

OUT

1.5 Gbps, PRBS 23

OUT

VEE = –5V

PK-PK

RMS

01074-014

0

–25 0 25 50 75 125100

TEMPERATURE (°C)

Figure 12. Jitter vs. Temperature 1.5 Gbps, PRBS 23

100

80

60

VEE = –3.3V

PERCENT

40

23

2

–1 PSEUDO-RANDOM BIT STREAM, ERROR-FREE AREA

ERROR-FREE PERCENTAGE VALUE WAS COMPUTED

20

(DATA_PERIOD – PPJITTER) × 100 / DATA_PERIOD

0

0 500 1000 1500

VOLTAGE (INNER EYE)

USING THE FOLLOWING FORMULA:

TIME DOMAIN

V

100 / V

INNER

VOLTAGE (INNER EYE)

DATA RATE (Mbps)

TIME DOMAIN

@500Mbps

Figure 13. AC Performance

01074-012

01074-013

0

–25 0 25 50 75 125100

TEMPERATURE (°C)

Figure 15. Jitter vs. Temperature 1.5 Gbps, PRBS 23

100

80

VOLTAGE (INNER EYE)

60

VEE = –5V

PERCENT

40

23

2

–1 PSEUDO-RANDOM BIT STREAM, ERROR-FREE AREA

ERROR-FREE PERCENTAGE VALUE WAS COMPUTED

20

0

0 500 1000 1500

USING THE FOLLOWING FORMULA:

(DATA_PERIOD – PPJITTER) × 100 / DATA_PERIOD

TIME DOMAIN

V

100 / V

INNER

VOLTAGE (INNER EYE)

INNER

DATA RATE (Mbps)

TIME DOMAIN

@500Mbps

Figure 16. AC Performance

01074-015

01074-016

Rev. A | Page 10 of 44

AD8150

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100

150

80

60

40

FREQUENCY

20

0

560 580 620600 640 660 680 700 710

DELAY (ps)

Figure 17. Variation in Channel-to-Channel Delay, All 561 Points

17.0

16.5

16.0

(mA)

OUT

I

15.5

01074-017

100

50

0

PROPAGTION DELAY (ps)

–50

–100

–25 0 25 50 75 100

TEMPERATURE (°C)

Figure 20. Propagation Delay, Normalized at 25°C vs. Temperature

100

80

60

PK-PK

JITTER (ps)

40

01074-020

15.0

14.5 –3.3 –3.6 –3.9 –4.2 –4.7 –5.0

Figure 18. I

1V

200mV/DIV

–1V

Figure 19. Rise/Fall Times, V

VEE (V)

vs. Supply, VEE

OUT

200ps/DIV

95.55 RISE

96.32 FALL 20% PROXIMAL 80% DISTAL

= −3.3 V

EE

01074-018

01074-019

20

0

3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V

RMS

CC

, VEE)

Figure 21. Jitter vs. Supply 1.5 Gbps, PRBS 23

1V

87.11 RISE

87.36 FALL 20% PROXIMAL 80% DISTAL

200mV/DIV

–1V

200ps/DIV

Figure 22. Rise/Fall Times, V

= −5 V

EE

01074-021

01074-022

Rev. A | Page 11 of 44

AD8150

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500mV

100mV/DIV

–500mV

Figure 23. Eye Pattern, V

200ps/DIV

= −3.3 V, 1.5 Gbps PRBS 23

EE

01074-023

100mV/DIV

–500mV

Figure 24. Eye Pattern, V

100ps/DIV

= −5 V, 1.5 Gbps PRBS 23

EE

01074-025

Rev. A | Page 12 of 44

AD8150

V

www.BDTIC.com/ADI

TEST CIRCUIT

V

CCVCCVTT

TEKTRONIX

= 50Ω

R

1.65kΩ

HP8133A

PRBS

GENERATOR

1.65kΩ

= 0V, VEE = –3.3V OR –5V, VTT = –1.6V

CC

= 1.54kΩ, I

R

SET

INTRINSIC JITTER OF HP8133A AND TEKTRONIX 11801B = 3ps RMS, 17ps PK-PK

= 16mA, VOH = –0.8V, VOL = –1.8V

OUT

105Ω

V

EE

AD8150

P IN OUT

N

V

EE

L

P

N

R

= 50Ω

L

V

TT

Figure 25. Eye Pattern Test Circuit

11801B

50Ω

SD22

SAMPLING

HEAD

50Ω

01074-024

Rev. A | Page 13 of 44

AD8150

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CONTROL INTERFACE

CONTROL INTERFACE TRUTH TABLES

The following are truth tables for the control interface.

Table 4. Basic Control Functions

Control Pins

CS

RESET

0 X X X X Global Reset. Reset all second-rank enable bits to 0 (disable all outputs). 1 1 X X X

1 0 0 X X

1 0 X 0 X

1 0 X X 0

1 0 0 1 0

Table 5. Address Data Examples

Output Address Pins

A4 A3 A2 A1 A0 D6/E D5 D4 D3 D2 D1 D0 Function

0 0 0 0 0 X 0 0 0 0 0 0

1 0 0 0 0 X 1 0 0 0 0 0

<Binary Output Number1> 0 X X X X X X Disable Output. Disable specified output (D6 = 0). 1 0 0 0 1 X <Binary Input Number>

1 0 0 1 0 X 1 0 0 0 0 1

1

The binary output number may also be the broadcast connection designator, 10001X.

WE RE UPDATE

MSB to LSB

Enable Bit

Function

Control Disable. Ignore all logic (but the signal matrix still functions as programmed). D[6:0] are high impedance.

Single Output Preprogram. Write input configuration data from Data Bus D[6:0] into first rank of latches for the output selected by the Output Address Bus A[4:0].

Single Output Readback. Readback input configuration data from second rank of latches onto Data Bus D[6:0] for the single output selected by the Output Address Bus A[4:0].

Global Update. Copy input configuration data from all 17 first-rank latches into second rank of latches, updating signal matrix connections for all outputs.

Transparent Write and Update. It is possible to write data directly onto rank two. This simplifies logic when synchronous signal matrix updating is not necessary.

Input Address Pins

MSB to LSB

Lower Address/Data Range. Connect Output 00 (A[4:0] = 00000) to Input 00 (D[5:0] = 000000).

Upper Address/Data Range. Connect Output 16 (A[4:0] = 10000) to Input 32 (D[5:0] = 100000).

Enable Output. Connect selected output (A[4:0] = 0 to 16) to designated input (D[5:0] = 0 to 32) and enable output (D6 = 1).

Broadcast Connection. Connect all 17 outputs to the same designated input and set all 17 enable bits to the value of D6. Readback is not possible with the broadcast address.

Reserved. Any address or data code greater or equal to these are reserved for future expansion or factory testing.

Rev. A | Page 14 of 44

AD8150

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CONTROL INTERFACE TIMING DIAGRAMS

CS INPUT

WE INPUT

A[4:0] INPUTS

D[6:0] INPUTS

t

CSW

t

ASW

Figure 26. First-Rank Write Cycle

t

WP

t

DSW

Table 6. First-Rank Write Cycle

Symbol Parameter Conditions Min Typ Max Unit

t

Setup Time Chip select to write enable TA = 25°C 0 ns

CSW

t

Address to write enable VDD = 5 V 0 ns

ASW

t

Data to write enable VCC = 5 V 15 ns

DSW

t

Hold Time Chip select from write enable 0 ns

CHW

t

Address from write enable 0 ns

AHW

t

Data from write enable 0 ns

DHW

tWP Width of Write Enable Pulse 15 ns

t

AHW

t

DHW

t

CHW

01074-026

Rev. A | Page 15 of 44

AD8150

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CS INPUT

UPDATE INPUT

ENABLING

OUT[0:16][N:P]

OUTPUTS

TOGGLE

OUT[0:16][N:P]

OUTPUTS

DISABLING

OUT[0:16][N:P]

OUTPUTS

PREVIOUS RANK 2 DATA

DATA FROM RANK 2

t

CSU

t

UOE

t

Figure 27. Second-Rank Update Cycle

Table 7. Second-Rank Update Cycle

Symbol Parameter Conditions Min Typ Max Unit

t

Setup Time Chip select to update TA = 25°C 0 ns

CSU

t

Hold Time Chip select from update VDD = 5 V 0 ns

CHU

t

Output Enable Times Update to output enable VCC = 5 V 25 40 ns

UOE

t

Output Toggle Times Update to output reprogram 25 40 ns

UOT

t

Output Disable Times Update to output disabled 25 30 ns

UOD

tUW Width of Update Pulse 15 ns

UOD

t

UOT

DATA FROM RANK 1

t

UW

DATA FROM RANK 1

t

CHU

01074-027

Rev. A | Page 16 of 44

AD8150

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CS INPUT

UPDATE INPUT

WE INPUT

ENABLING

OUT[0:16][N:P]

OUTPUTS

DISABLING

OUT[0:16][N:P]

OUTPUTS

t

CSU

t

UOT

t

UOE

INPUT {DATA 1}INPUT {DATA 0}

t

UW

t

WOT

t

WOD

t

INPUT {DATA 2}INPUT {DATA 1}

WHU

t

CHU

01074-028

Figure 28. First-Rank Write Cycle and Second-Rank Update Cycle

Table 8. First-Rank Write Cycle and Second-Rank Update Cycle

Symbol Parameter Conditions Min Typ Max Unit

t

Setup Time Chip select to update TA = 25°C 0 ns

CSU

t

Hold Time Chip select from update VDD = 5 V 0 ns

CHU

t

Output Enable Times Update to output enable VCC = 5 V 25 40 ns

UOE

1

t

Write enable to output enable 25 40 ns

WOE

t

Output Toggle Times Update to output reprogram 25 30 ns

UOT

t

Write enable to output reprogram 25 30 ns

WOT

1

t

Output Disable Times Update to output disabled 25 30 ns

UOD

t

Write enable to output disabled 25 30 ns

WOD

t

Setup Time Write enable to update 10 ns

WHU

tUW Width of Update Pulse 15 ns

1

Not shown.

Rev. A | Page 17 of 44

AD8150

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CS INPUT

RE INPUT

A[4:0]

INPUTS

D[6:0]

OUTPUTS

ADDR 1 ADDR 2

DATA

{ADDR 1}

t

RDE

CSR

Figure 29. Second-Rank Readback Cycle

t

AA

DATA

{ADDR 2}

t

RHA

t

RDD

t

CHR

01074-029

Table 9. Second-Rank Readback Cycle

Symbol Parameter Conditions Min Typ Max Unit

t

Setup Time Chip select to read enable TA = 25°C 0 ns

CSR

t

Hold Time Chip select from read enable VDD = 5 V 0 ns

CHR

t

Address from read enable VCC = 5 V 5 ns

RHA

t

Enable Time Data from read enable 10 kΩ 15 ns

RDE

tAA Access Time Data from address 20 pF on D[6:0] 15 ns t

Release Time Data from read enable Bus 15 30 ns

RDD

Rev. A | Page 18 of 44

AD8150

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RESET INPUT

DISABLING

OUT[0:16][N:P]

OUTPUTS

t

TOD

t

TW

01074-030

Figure 30, Asynchronous Reset

Table 10. Asynchronous Reset

Symbol Parameter Conditions Min Typ Max Unit

t

Disable Time Output disable from reset TA = 25°C 25 30 ns

TOD

tTW Width of Reset Pulse VDD = 5 V 15 ns V

= 5 V

CC

Rev. A | Page 19 of 44

AD8150

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CONTROL INTERFACE PROGRAMMING EXAMPLE

The following conservative pattern connects all outputs to Input 7, except Output 16, which is connected to Input 32. The vector clock period, T

Table 11. Basic Test Pattern

Vector No.

0 0 1 1 1 1 xxxxx xxxxxxx Disable all outputs 1 1 1 1 1 1 xxxxx xxxxxxx 2 1 0 1 1 1 10001 1000111 All outputs to Input 07 3 1 0 0 1 1 10001 1000111 Write to first rank 4 1 0 1 1 1 10001 1000111 5 1 0 1 1 1 10000 1100000 Output 16 to Input 32 6 1 0 0 1 1 10000 1100000 Write to first rank 7 1 0 1 1 1 10000 1100000 8 1 0 1 1 0 xxxxx xxxxxxx Transfer to second rank 9 1 0 1 1 1 xxxxx xxxxxxx 10 1 1 1 1 1 xxxxx xxxxxxx Disable interface

, is 15 ns. It is possible to accelerate the execution of this pattern by deleting Vectors 1, 4, 7, and 9.

0

RESET

CS WE

D[0:6]

RE UPDATE

7

A[4:0] D[6:0] Comments

7

UPDATE

RESET

7

0

7

1

7

2

7

0

7

1

7

2

TO 17× 33

SWITCH

MATRIX

33

7

33

7

33

7

33

7

1 OF 33

DECODERS

01074-031

WE

7

1 OF 17 DECODERS

A[0:4]

7

16

RANK1

17 ROWS OF 7-BIT

LATCHES

RE

16

RANK2

7

Figure 31. Control Interface (Simplified Schematic)

Rev. A | Page 20 of 44

AD8150

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CONTROL INTERFACE DESCRIPTION

The AD8150 control interface receives and stores the desired connection matrix for the 33 input and 17 output signal pairs. The interface consists of 17 rows of double-rank 7-bit latches, one row for each output. The 7-bit data-word stored in each of these latches indicates to which (if any) of the 33 inputs the output will be connected.

One output at a time can be preprogrammed by addressing the output and writing the desired connection data into the first rank of latches. This process can be repeated until each of the desired output changes has been preprogrammed. All output connections can then be programmed at once by passing the data from the first rank of latches into the second rank. The output connections always reflect the data programmed into the second rank of latches and do not change until the first rank of data is passed into the second rank.

If necessary for system verification, the data in the second rank of latches can be read back from the control interface.

At any time, a reset pulse can be applied to the control interface to globally reset the appropriate second-rank data bits, disabling all 17 signal output pairs. This feature can be used to avoid output bus contention on system start-up. The contents of the first rank remain unchanged.

The control interface pins are connected via logic-level translators. These translators allow programming and readback of the control interface using logic levels different from those in the signal matrix.

To facilitate multiple chip address decoding, there is a chipselect pin. All logic signals except the reset pulse are ignored unless the chip-select pin is active. The chip-select pin disables only the control logic interface and does not change the operation of the signal matrix. The chip-select pin does not power down any of the latches, so any data programmed in the latches is preserved.

All control pins are level-sensitive, not edge-triggered.

CONTROL PIN DESCRIPTION

A[4:0] Inputs

Output address pins. The binary encoded address applied to these five input pins determines which one of the 17 outputs is being programmed (or being read back). The most significant bit is A4.

D[6:0] Inputs/Outputs

Input configuration data pins. In write mode, the binary encoded data applied to Pins D[6:0] determine which one of 33 inputs is to be connected to the output specified with the A[4:0] pins. The most significant bit is D5, and the least significant bit is D0. Bit D6 is the enable bit, setting the specified output signal pair to an enabled state if D6 is logic high, or to a disabled state, high impedance, if D6 is logic low.

In readback mode, Pins D[6:0] are low impedance outputs, indicating the data-word stored in the second rank for the output specified with the A[4:0] pins. The readback drivers were designed to drive high impedances only, so external drivers connected to D[6:0] should be disabled during readback mode.

Input

WE

First-rank write enable. Forcing this pin to logic LOW allows the data on Pins D[6:0] to be stored in the first-rank latch for the output specified by Pins A[4:0]. The

returned to a logic high state after a write cycle to avoid overwriting the first-rank data.

UPDATE

Second-rank write enable. Forcing this pin to logic low allows the data stored in all 17 first-rank latches to be transferred to the second-rank latches. The signal connection matrix will be reprogrammed when the second-rank data is changed. This is a global pin, transferring all 17 rows of data at once. It is not necessary to program the address pins. It should be noted that after initial power-up of the device, the first-rank data is undefined. It may be desirable to preprogram all seventeen outputs before performing the first update cycle.

Input

pin must be

WE

Rev. A | Page 21 of 44

AD8150

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Input

RE

Second-rank read enable. Forcing this pin to logic low enables the output drivers on the bidirectional D[6:0] pins, entering the readback mode of operation. By selecting an output address with the A[4:0] pins and forcing

stored in the second-rank latch for that output address will be written to the D[6:0] pins. Data should not be written to the D[6:0] pins externally while in readback mode. The

pins are not exclusive and may be used at the same time, but data should not be written to the D[6:0] pins from external sources while in readback mode.

Input

CS

Chip select. This pin must be forced to logic low to program or receive data from the logic interface, with the exception of the

pin, described below. This pin has no effect on the

RESET signal pairs and does not alter any of the stored control data.

Input

RESET

Global output disable pin. Forcing the

will reset the enable bit, D6, in all 17 second-rank latches, regardless of the state of any other pins. This has the effect of immediately disabling the 17 output signal pairs in the matrix.

to logic low, the 7-bit data

RE

pin to logic low

RESET

and WE

It is useful to momentarily hold

powering up the AD8150 in a system that has multiple output signal pairs connected together. Failure to do this may result in several signal outputs contending after power-up. The reset pin is not gated by the state of the chip-select pin,

noted that the

which will contain undefined data after power-up.

pin does not program the first rank,

RESET

at a logic low state when

RESET

CS

. It should be

CONTROL INTERFACE TRANSLATORS

The AD8150 control interface has two supply pins, VDD and VSS. The potential between the positive logic supply V negative logic supply V 5 V. Regardless of supply, the logic threshold is approximately

1.6 V above V CMOS and TTL logic drivers.

The signal matrix supplies, V of the voltage on V V

) ≤ 10 V. These constraints will allow operation of the

EE

control interface on 3 V or 5 V while the signal matrix is operated on 3.3 V or 5 V PECL, or on −3.3 V or −5 V ECL.

, allowing the interface to be used with most

SS

must be at least 3 V and no more than

SS

and VEE, can be set independent

CC

and VSS, with the constraints that (V

DD

and the

DD

−

Rev. A | Page 22 of 44

AD8150

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CIRCUIT DESCRIPTION

The AD8150 is a high speed 33 × 17 differential crosspoint switch designed for data rates up to 1.5 Gbps per channel. The AD8150 supports PECL-compatible input and output levels when operated from a 5 V supply (V ECL-compatible levels when operated from a −5 V supply (V = GND, V

= −5 V). To save power, the AD8150 can run from

EE

= 5 V, VEE = GND) or

CC

a 3.3 V supply to interface with low voltage PECL circuits or a

−3.3 V supply to interface with low voltage ECL circuits. The AD8150 utilizes differential current-mode outputs with individual disable control, which facilitates busing together the outputs of multiple AD8150s to assemble larger switch arrays. This feature also reduces the system to assemble larger switch arrays, reduces system crosstalk, and can greatly reduce power dissipation in a large switch array. A single external resistor programs the current for all enabled output stages, allowing for user control over output levels with different output termination schemes and transmission line characteristic impedances.

HIGH SPEED DATA INPUTS (INxxP, INxxN)

The AD8150 has 33 pairs of differential voltage-mode inputs. The common-mode input range extends from the positive supply voltage (V input levels (V voltage is less than 300 mV. Unused inputs may be connected directly to any level within the allowed common-mode input range. A simplified schematic of the input circuit is shown in Figure 32.

To maintain signal fidelity at the high data rates supported by the AD8150, the input transmission lines should be terminated as close to the input pins as possible. The preferred input termination structure will depend primarily on the application and the output circuit of the data source. Standard ECL components have open emitter outputs that require pull-down resistors. Three input termination networks suitable for this type of source are shown in im

pedance of the transmission line is shown as Z resistors, R1 and R2, in the Thevenin termination are chosen to synthesize a V open-circuit output voltage equal to V

) down to include standard ECL or PECL

CC

− 2 V). The minimum differential input

CC

V

CC

INxxP

V

EE

Figure 32. Simplified Input Circuit

INxxN

01074-032

Figure 33. The characteristic

. The

O

source with an output resistance of ZO and an

TT

− 2 V. The load

CC

resistors (R to bias the emitter followers of the ECL source.

ECL SOURCE

Figure 33. AD8150 Input Termination from ECL/PECL Sources: a) Parallel

Termination Using V

If the AD8150 is driven from a current-mode output stage such as another AD8150, the input termination should be chosen to accommodate that type of source, as explained in the following section.

HIGH SPEED DATA OUTPUTS (OUTyyP, OUTyyN)

The AD8150 has 17 pairs of differential current-mode outputs. The output circuit, shown in Figure 34, is an open-collector NPN

rent switch with resistor-programmable tail current and output

cur compliance extending from the positive supply voltage (V down to standard ECL or PECL output levels (V outputs may be disabled individually to permit outputs from multiple AD8150’s to be connected directly. Since the output currents of multiple enabled output stages connected in this way sum, care should be taken to ensure that the output compliance limit is not exceeded at any time; this can be achieved by disabling the active output driver before enabling an inactive driver.

) in the differential termination scheme are needed

L

ECL SOURCE

Z

O

Z

O

R

L

(c)

V

CC

2Z

Z

O

Z

O

VCC– 2V

R1

R2 R2

V

(b)

INxxN

INxxP

− 2 V). The

CC

V

CC

Z

O

Z

O

Z

O

VTT = VCG2V

(a)

V

CC

ECL SOURCE

Supply; b) Thevenin Equivalent Termination; and

TT

INxxN

INxxP

Z

O

R

L

V

EE

c) Differential Termination

R1

INxxN

INxxP

EE

01074-033

)

CC

Rev. A | Page 23 of 44

AD8150

(

)

−

=

www.BDTIC.com/ADI

VCC– 2V

V

EE

V

CC

OUTyyP OUTyyN

DISABLE

I

OUT

V

EE

01074-034

Figure 34. Simplified Output Circuit

To ensure proper operation, all outputs (including unused output) must be pulled high, using external pull-up networks, to a level within the output compliance range. If outputs from multiple AD8150s are wired together, a single pull-up network may be used for each output bus. The pull-up network should be chosen to keep the output voltage levels within the output compliance range at all times. Recommended pull-up networks to produce PECL/ECL 100K- and 10K-compatible outputs are shown in Figure 35. Alternatively, a separate supply can be used

provide V

to

AD8150

OUTyyN OUTyyP

Figure 35. Output Pull-Up Networks: a) ECL 100K, b) ECL 10K

, making R

COM

V

R

L

and D

COM

CC

R

COM

V

COM

R

L

COM

AD8150

OUTyyN

OUTyyP

unnecessary.

V

CC

D

COM

V

R

COM

L

R

L

01074-035

The output levels are simply:

VV

=

COMOH

RIVV

−=

COMOL

−=

CCCOM

−=

The common-mode adjustment element (R

L

OUT

RIVVV

=−=

OLOHSWING

COM

OUT

()

COMCCCOM

L

OUT

()

K100

()

ModeDVVV

K10

ModeRIVV

COM

or D

) may be

COM

omitted if the input range of the receiver includes the positive supply voltage. The bypass capacitors reduce common-mode perturbations by providing an ac short from the common nodes (V

) to ground.

COM

maintain signal fidelity at high data rates, the stubs connecting the output pins to the output transmission lines or load resistors should be as short as possible.

V

CC

R

COM

AD8150

OUTyyN OUTyyP

AD8150

OUTyyN

OUTyyP

R

L

Z

O

Z

O

R

L

RECEIVER

V

R

COM

L

Z

O

Z

R

O

L

01074-036

Figure 36. Double Termination of AD8150 Outputs

In this case, the output levels are:

COMOH

COMOL

41

()

43

−=

OLOHSWING

L

OUT

RIVV

L

OUT

()

21

=−=

OUT

RIVVV

L

RIVV

OUTPUT CURRENT SET PIN (REF)

A simplified schematic of the reference circuit is shown in Figure 37. A single external resistor connected between the REF

pin and V stages. This feature allows a choice of pull-up networks and transmission line characteristic impedances while still achieving a nominal output swing of 800 mV. At low data rates, substantial power savings can be achieved by using lower output swings and higher load resistances.

determines the output current for all output

EE

AD8150

1.25V

I

OUT

/25

V

CC

REF

R

SET

V

EE

Figure 37. Simplified Reference Circuit

01074-037

When busing together the outputs of multiple AD8150s or when running at high data rates, double termination of its outputs is recommended to mitigate the impact of reflections due to open transmission line stubs and the lumped capacitance of the AD8150 output pins. A possible connection is shown in Figure 36; the bypass capacitors provide an ac short from the

ommon nodes of the termination resistors to ground. To

c

Rev. A | Page 24 of 44

AD8150

www.BDTIC.com/ADI

The resistor value current is given by the following expression:

R25=

SET

I

OUT

Example:

IforR

OUTSET

The minimum set resistor is R 25 mA. The maximum set resistor is R I

= 5 mA. Nominal 800 mV output swings can be achieved

OUT,min

in a 50 Ω load using R

= 1.56 kΩ (I

SET

doubly terminated 75 Ω load using R

mA2.16k54.1 ==

= 1 kΩ, resulting in I

SET,min

= 5 kΩ, resulting in

SET,max

= 16.2 mA) or in a

OUT

= 1.17 kΩ (I

SET

OUT

OUT,max

=

21.3 mA).

To minimize stray capacitance and avoid the pickup of unwanted signals, the external set resistor should be located close to the REF pin. Bypassing the set resistor is not recommended.

POWER SUPPLIES

There are several options for the power supply voltages for the AD8150, because there are two separate sections of the chip that require power supplies. These are the control logic and the high speed data paths. The voltage levels of these supplies can vary, depending on the system architecture.

Logic Supplies

The control (programming) logic is CMOS and is designed to interface with any of the various standard single-ended logic families (CMOS or TTL). Its supply voltage pins are V 170, logic positive) and V

(Pin 152, logic ground). In all cases

SS

the logic ground should be connected to the system digital ground. V

should be supplied at a voltage between 3.3 V and

DD

5 V to match the supply voltage of the logic family that is used to drive the logic inputs. V

should be bypassed to ground

DD

with a 0.1 µF ceramic capacitor. The absolute maximum voltage from V

to VSS is 5.5 V.

DD

Data Path Supplies

The data path supplies have more options for their voltage levels. The choices here will affect several other areas, such as power dissipation, bypassing, and common-mode levels of the inputs and outputs. The more positive voltage supply for the data paths is V supply is V

(Pins 41, 98, 149, and 171). The more negative

CC

, which appears on many pins that will not be listed

EE

here. The maximum allowable voltage across these supplies is

5.5 V.

DD

(Pin

The first choice in the data path power supplies is to decide whether to run the device as ECL (emitter-coupled logic) or PECL (positive ECL). For ECL operation, V potential, and V

will be at a negative supply between −3.3 V

EE

will be at ground

CC

and −5 V. This will make the common-mode voltage of the inputs and outputs a negative voltage (see Figure 38).

3V TO 5V

0.1μF

V

DD

AD8150

CONTROL

LOGIC

V

SS

GND

Figure 38. Power Supplies and Bypassing for ECL Operation

GND

V

DATA

PATHS

V

3V TO 5V

CC

EE

0.1μF (ONE FOR EVERY TWO V

EE

PINS)

01074-038

If the data paths are to be dc-coupled to other ECL logic devices that run with ground as the most positive supply and a negative voltage for V

, then this is the proper way to run. However, if

EE

the part is to be ac coupled, it is not necessary to have the input/output common mode at the same level as the other system circuits, but it will probably be more convenient to use the same supply rails for all devices.

For PECL operation, V

will be at ground potential, and VCC

EE

will be a positive voltage from 3.3 V to 5 V. Thus, the common mode of the inputs and outputs will be at a positive voltage. These can then be dc coupled to other PECL operated devices. If the data paths are ac coupled, then the common-mode levels do not matter, see

0.1μF

AD8150

Figure 39. Power Supplies and Bypassing for PECL Operation

Figure 39.

3V TO 5V

V

DD

CONTROL

LOGIC

V

SS

GND GND

3V TO 5V

V

DATA

PATHS

V

0.1μF (ONE FOR EACH V 4 REQUIRED)

CC

EE

PIN,

CC

01074-039

Rev. A | Page 25 of 44

AD8150

www.BDTIC.com/ADI

V

CC

V

EE

V

EE CC

EE

0.01μF

CC

0.01μF

EE

0.01μF

C11

C15

C31

C32

V IN20P IN20N

IN21P IN21N

IN22P IN22N

V IN23P IN23N

V IN24P IN24N

V IN25P IN25N

V IN26P IN26N

V IN27P IN27N

V IN28P IN28N

V IN29P IN29N

V IN30P IN30N

V IN31P IN31N

V IN32P IN32N

OUT16N OUT16P

V

EE

EE EE

C29

0.01μF

C5

0.01μF

EE

V

CC

C4

0.01μF

EE

V

CC

IN19N

IN19P

184

183

182

181

1

PIN 1

2

INDICATOR

3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

4748495051525354555657

EE

CC

V

EE

V

CC

V

EE

V

CC

IN18N

IN18P

IN17N

180

179

178

177

C6

0.01μF

IN17P

IN16N

IN16P

176

175

174

173

58

EE

V

CC

V

C7

0.01μF

CC

V

EE

V

C13

0.01μF

DD

RESETCSREWEUPDATEA0A1A2A3A4D0D1D2D3D4D5D6

V

171

170

169

168

167

166

165

164

163

172

596061626364656667

162

161

160

AD8150

184L LQFP

TOP VIEW

(Not to Scale)

68

6970717274757677787379808182848586

159

158

C14

0.01μF

157

156

155

0.01μF

1.5kΩ

V

DD

154

C12

R203

153

SS

V

152

V

CC

V

EE

V

151

150

C8

0.01μF

CC

V

EE

V

C9

0.01μF

EE

V

CC

V

C10

0.01μF

EE

V

CC

V

C30

IN15N

IN15P

IN14N

IN14P

IN13N

149

147

146

145

144

143

142

148

141

87838889909192

0.01μF

IN13P

140

139

138

V

EE

137

IN12N

136

IN12P

135

V

EE

134

IN11N

133

IN11P

132

V

EE

131

IN10N

130

IN10P

129

V

EE

128

IN09N

127

IN09P

126

V

EE

125

IN08N

124

IN08P

123

V

EE

122

IN07N

121

IN07P

120

V

EE

119

IN06N

118

IN06P

117

V

EE

116

IN05N

115

IN05P

114

V

EE

113

IN04N

112

IN04P

111

V

EE

110

IN03N

109

IN03P

108

V

EE

107

IN02N

106

IN02P

105

V

EE

104

IN01N

103

IN01P

102

V

EE

101

IN00N

100

IN00P

99

V

EE

98 97

V

EE

96

OUT00P

95

OUT00N

94

V

EE

93

V

EE

C60

0.01μF

V

CC

V

EE

EEVEEVEEVEEVEEVEEVEEVEEVEEVEEVEEVEEVEEVEEVEEVEE

V

OUT15P

OUT14P

OUT13P

OUT12P

OUT11P

OUT10P

OUT09P

OUT08P

OUT07P

OUT06P

OUT05P

OUT15N

OUT14N

OUT13N

OUT12N

OUT11N

OUT10N

OUT09N

OUT08N

OUT07N

OUT06N

OUT05N

OUT04P

OUT04N

OUT03N

Figure 40. Bypassing Schematic

Rev. A | Page 26 of 44

OUT03P

OUT02P

OUT01P

OUT02N

OUT01N

01074-050

AD8150

[

]

{

(

)

×

=

www.BDTIC.com/ADI

POWER DISSIPATION

For analysis, the power dissipation of the AD8150 can be divided into three separate parts. These are the control logic, the data path circuits, and the (ECL or PECL) outputs, which are part of the data path circuits, but can be dealt with separately. The first of these, the control logic, is CMOS technology and does not dissipate a significant amount of power. This power will, of course, be greater when the logic supply is 5 V than when it is 3 V, but overall it is not a significant amount of power and can be ignored for thermal analysis.

V

DD

AD8150

CONTROL

LOGIC

I, DATA PATH LOGIC

V

SS

GND GND

Figure 41. Major Power Consumption Paths

The data path circuits operate between the supplies VCC and V

. As described in the power supply section, this voltage can

EE

range from 3.3 V to 5 V. The current consumed by this section will be constant, so operating at a lower voltage can save about 40 percent in power dissipation.

The power dissipated in the data path outputs is affected by several factors. The first is whether the outputs are enabled or disabled. The worst case occurs when all of the outputs are enabled. The current consumed by the data path logic can be approximated by

CC

()

#

×

V

CC

DATA

PATHS

V

EE

()

II

OUT

enabledoutputsof

I

OUT

R

OUT

V

LOW – V

OUT

×++=

EE

01074-040

mA3mA20mA5.4mA30

This says that there will always be a minimum of 30 mA flowing. I

will increase by a factor that is proportional to both

CC

the number of enabled outputs and the programmed output current.

The power dissipated in this circuit section will simply be the voltage of this section (V case, assume that V

− VEE) times the current. For a worst

CC

− VEE is 5.0 V, all outputs are enabled and

CC

the programmed output current is 25 mA. The power dissipated by the data path logic will be

[]

()

mW826

=

××++=P

The power dissipated by the output current depends on several factors. These are the programmed output current, the voltage drop from a logic low output to V

, and the number of enabled

EE

outputs. A simplifying assumption is that one of each (enabled) differential output pair will be low and draw the full output current (and dissipate most of the power for that output), while the complementary output of the pair will be high and draw insignificant current. Thus, the power dissipation of the high output can be ignored, and the output power dissipation for each output can be assumed to occur in a single static low output that sinks the full output-programmed current.

The voltage across which this current flows can also vary, depending on the output circuit design and the supplies that are used for the data path circuitry. In general, however, there will be a voltage difference between a logic low signal and V

. This

EE

is the drop across which the output current flows. For a worst case, this voltage can be as high as 3.5 V. Thus, for all outputs enabled and the programmed output current set to 25 mA, the power dissipated by the outputs is

P

W49.117mA25V5.3 =

}

17mA3mA20mA25mA5.4mA25V0.5

Rev. A | Page 27 of 44

AD8150

www.BDTIC.com/ADI

HEAT SINKING

Depending on several factors in its operation, the AD8150 can dissipate 2 W or more. The part is designed to operate without the need for an explicit external heat sink. However, the package design offers enhanced heat removal via some of the package pins to the PC board traces.

The V Pins 93 to 138) have finger extensions inside the package that connect to the paddle on which the IC chip is mounted. These pins provide a lower thermal resistance from the IC to the V pins than pins that just have a bond wire. As a result, these pins can be used to enhance the heat removal process from the IC to the circuit board and ultimately to the ambient.

The V area of circuit board trace material to take the most advantage of their lower thermal resistance. If there is a large area available on an inner layer that is at V provided from the package pin traces to this layer. There should

pins on the input sides of the package (Pins 1 to 46 and

EE

pins described above should be connected to a large

EE

potential, then vias can be

EE

be no thermal-relief pattern when connecting the vias to the inner layers for these V close to the pin leads can provide an even lower thermal resistive path. If possible to use, 2 oz. copper foil will provide better heat removal than 1 oz.

The AD8150 package has a specified thermal impedance, θ 30°C/W. This is the worst case still-air value that can be expected when the circuit board does not significantly enhance the heat removal from the package. By using the concept described above or by using forced-air circulation, the thermal impedance can be lowered.

For an extreme worst case analysis, the junction rise above the ambient can be calculated assuming 2 W of power dissipation and θ

of 30°C/W to yield a 60°C rise above the ambient. There

JA

are many techniques described above that can mitigate this situation. Most actual circuits will not result in such a high rise of the junction temperature above the ambient.

pins. Additional vias in parallel and

EE

JA

, of

Rev. A | Page 28 of 44

AD8150

www.BDTIC.com/ADI

APPLICATIONS

AD8150 INPUT AND OUTPUT BUSING

Although the AD8150 is a digital part, in any application that runs at high speed, analog design details will have to be given very careful consideration. At high data rates, the design of the signal channels will have a strong influence on the data integrity and its associated jitter and ultimately bit error rate (BER).

While it might be considered very helpful to have a suggested circuit board layout for any particular system configuration, this is not something that can be practically realized. Systems come in all shapes, sizes, speeds, performance criteria, and cost constraints. Therefore, some general design guidelines will be presented that can be used for all systems and judiciously modified where appropriate.

High speed signals travel best, that is, maintain their integrity, when they are carried by a uniform transmission line that is properly terminated at either end. Any abrupt mismatches in impedance or improper termination will create reflections that will add to or subtract from parts of the desired signal. Small amounts of this effect are unavoidable, but too much will distort the signal to the point that the channel BER will increase. It is difficult to fully quantify these effects because they are influenced by many factors in the overall system design.

A constant-impedance transmission line is characterized by having a uniform cross-sectional profile over its entire length. In particular, there should be no stubs, which are branches that intersect the main run of the transmission line. These can have an electrical appearance that is approximated by a lumped element, such as a capacitor, or if long enough, as another transmission line. To the extent that stubs are unavoidable in a design, their effect can be minimized by making them as short as possible and as high an impedance as possible.

Figure 36 shows a differential transmission line that connects

o differential outputs from AD8150s to a generic receiver. A

tw more generalized system can have more outputs bused and more receivers on the same bus, but the same concepts apply. The inputs of the AD8150 can also be considered a receiver. The transmission lines that bus all of the devices together are shown with terminations at each end.

The individual outputs of the AD8150 are stubs that intersect the main transmission line. Ideally, their current-source outputs would be infinite impedance, and they would have no effect on signals that propagate along the transmission line. In reality, each external pin of the AD8150 projects into the package and has a bond wire connected to the chip inside. On-chip wiring then connects to the collectors of the output transistors and to ESD protection diodes.

Unlike some other high speed digital components, the AD8150 does not have on-chip terminations. While the location of such terminations would be closer to the actual end of the transmission line for some architectures, this concept can limit system design options. In particular, it is not possible to bus more than two inputs or outputs on the same transmission line and it is not possible to change the value of these terminations to use them for different impedance transmission lines. The AD8150, with the added ability to disable its outputs, is much more versatile in these types of architectures.

If the external traces are kept to a bare minimum, the output will present a mostly lumped capacitive load of about 2 pF. A single stub of 2 pF will not seriously adversely affect signal integrity for most transmission lines, but the more of these stubs, the more adverse their influence will be.

One way to mitigate this effect is to locally reduce the capacitance of the main transmission line near the point of stub intersection. Some practical means for doing this are to narrow the PC board traces in the region of the stub and/or to remove some of the ground plane(s) near this intersection. The effect of these techniques will locally lower the capacitance of the main transmission line at these points, while the added capacitance of the AD8150 outputs will compensate for this reduction in capacitance. The overall intent is to create as uniform a transmission line as possible.

In selecting the location of the termination resistors, it is important to keep in mind that, as their name implies, they should be placed at either end of the line. There should be no, or minimal, projection of the transmission line beyond the point where the termination resistors connect to it.

Rev. A | Page 29 of 44

AD8150

www.BDTIC.com/ADI

EVALUATION BOARD

An evaluation board has been designed and is available to rapidly test the main features of the AD8150. This board lets the user analyze the analog performance of the AD8150 channels and easily control the configuration of the board by a standard PC.

Differential inputs and outputs provide the interface for all channels with the connections made by a 50 Ω SMB-type connector. This type of connector was chosen for its rapid mating and unmating action. The use of SMB-type connectors minimizes the size and minimizes the effort of rearranging interconnects that would be required if using SMA-type connectors.

CONFIGURATION PROGRAMMING

The board is configurable by one of two methods. For ease of use, custom software is provided that controls the AD8150 programming via the parallel port of a PC. This requires a usersupplied standard printer cable that has a DB-25 connector at one end (parallel- or printer-port interface) and a Centronixtype connector at the other that connects to P2 of the AD8150 evaluation board. The programming with this scheme is done in a serial fashion, so it is not the fastest way to configure the AD8150 matrix. However, the user interface makes it very convenient to use this programming method.

If a high speed programming interface is desired, the AD8150 address and data buses are directly available on P3. The source of the program signals can be a piece of test equipment, such as the Tektronix HFS-9000 digital test generator, or some other user-supplied hardware that generates programming signals.

When using the PC interface, the jumper at W1 should be installed and no connections should be made to P3. When using the P3 interface, no jumper is installed at W1. There are locations for termination resistors for the address and data signals if these are necessary.

POWER SUPPLIES

The AD8150 is designed to work with standard ECL logic levels. This means that V supply. The shells of the I/O SMB connectors are at V potential. Thus, when operating in the standard ECL configuration, test equipment can be directly connected to the board, because the test equipment will also have its connector shells at ground potential.

Operating in PECL mode requires V voltage while V

is at ground. Since this would make the shells

EE

of the I/O connectors at a positive voltage, it can cause problems when directly connecting to test equipment. Some equipment, such as battery operated oscilloscopes, can be floated from ground, but care should be taken with line-powered equipment

is at ground and VEE is at a negative

CC

to be at a positive

CC

so that a dangerous situation is not created. Refer to the test equipment’s manual.

The voltage difference from V

to VEE can range from 3 V to 5 V.

CC

Power savings can be realized by operating at a lower voltage without any compromise in performance.

A separate connection is provided for V potential of the outputs. This can be at a voltage as high as V but power savings can be realized if V

, the termination

TT

is at a voltage that is

TT

CC

somewhat lower. Please consult elsewhere in the data sheet for the specification for the limits of the V

supply.

TT

As a practical matter, current on the evaluation board will flow from the V through the AD8150 from its outputs to the V running in ECL mode, V

supply through the termination resistors and then

TT

supply. When

EE

will want to be at a negative supply.

TT

Most power supplies will not allow their ground to connect to V

and will not allow their negative supply to connect to VTT.

CC

This will require them to source current from their negative supply, which will not return to the ground terminal. Thus, V should be referenced to V

when running in ECL mode, or a

EE

TT

true bipolar supply should be used.

The digital supply is provided to the AD8150 by the V

pins. VSS should always be at ground potential to make it

V

SS

compatible with standard CMOS or TTL logic. V

DD

can range

DD

and

from 3 V to 5 V and should be matched to the supply voltage of the logic used to control the AD8150. However, since PCs use 5 V logic on their parallel port, V

should be at 5 V when using a

DD

PC to program the AD8150.

SOFTWARE INSTALLATION

The software to operate the AD8150 is provided on two 3.5" floppy disks. The software is installed by inserting Disk 1 into the floppy drive of a PC and running the setup.exe program. This will routinely install the software and prompt the user to change to Disk 2. The setup program will also prompt the user to select the directory location to store the program.

After running the software, the user will be prompted to identify which (of three) software driver is used with the PC’s parallel port. The default is LPT1, which is most commonly used. However, some laptops commonly use the PRN driver. It is also possible that some systems are configured with the LPT2 driver.

If it is not known which driver is used, it is best to select LPT1 and proceed to the next screen. This will show a full array of buttons that allows the connection of any input to output of the AD8150. All of the outputs should be in the output off state immediately after the program starts running. Any of the active buttons can be selected with a mouse click, which will send out one burst of programming data.

,

Rev. A | Page 30 of 44

AD8150

www.BDTIC.com/ADI

A sh

After this, the PC keyboard’s left or right arrow key can be held down to generate a steady stream of programming signals out of the parallel port. The CLOCK test point on the AD8150 evaluation board can be monitored with an oscilloscope for any activity (a user-supplied printer cable must be connected). If there is a square wave present, then the proper software driver is selected for the PC’s parallel port.

If there is no signal present, then another driver should be tried by selecting the Parallel Port menu item from the File pulldown menu selection under the title bar. Select a different software driver and carry out the above test until signal activity is present at the CLOCK test point.

SOFTWARE OPERATION

Any button can be clicked in the matrix to program the inputto-output connection. This will send the proper programming sequence out of the PC parallel port. Since only one input can be programmed to a given output at a time, clicking a button in a horizontal row will cancel previous selections in that row. However, any number of outputs can share the same input. Refer to Figure 42.

ortcut for programming all outputs to the same input is to use the broadcast feature. After clicking on the Broadcast Connection button, a window will appear that will prompt the user to select which input should be connected to all outputs. The user should type in an integer from 0 to 32 and then click OK. This will send out the proper program data and return to the main screen with a full column of buttons selected under the chosen input.

The off column can be used to disable whichever output one chooses. To disable all outputs, click the Global Reset button. This will select the full column of OFF buttons.

Two scratchpad memories (Memory 1 and Memory 2) are provided to conveniently save a particular configuration. However, these registers are erased when the program is terminated. For long-term storage of configurations, the disk’s storage memory should be used. The Save and Load selections can be accessed from the File pull-down menu under the title bar.

Figure 42. Evaluation Board Controller

Rev. A | Page 31 of 44

01074-041

AD8150

www.BDTIC.com/ADI

PCB LAYOUT

Figure 43. Component Side

Rev. A | Page 32 of 44

01074-042

AD8150

www.BDTIC.com/ADI

Figure 44. Circuit Side

Rev. A | Page 33 of 44

01074-043

AD8150

www.BDTIC.com/ADI

Figure 45. Silkscreen Top

Rev. A | Page 34 of 44

01074-044

AD8150

www.BDTIC.com/ADI

Figure 46. Solder Mask Top

Rev. A | Page 35 of 44

01074-045

AD8150

www.BDTIC.com/ADI

Figure 47. Silkscreen Bottom

Rev. A | Page 36 of 44

01074-046

AD8150

www.BDTIC.com/ADI

Figure 48. Solder Mask Bottom

Rev. A | Page 37 of 44

01074-047

AD8150

www.BDTIC.com/ADI

Figure 49. INT1 (V

Rev. A | Page 38 of 44

)

EE

01074-048

AD8150

www.BDTIC.com/ADI

Figure 50. INT2 (V

Rev. A | Page 39 of 44

)

CC

01074-049

AD8150

www.BDTIC.com/ADI

V

CC

R19

1.65kΩ

P4

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

P15

R21

R25

R23

R28

R26

R31

R29

R34

R32

R37

R35

IN00P

R20 105Ω

IN00N

V

EE

V

CC

IN01P

R24 105Ω

IN01N

V

EE

V

CC

IN02P

R27 105Ω

IN02N

V

EE

V

CC

IN03P

R30 105Ω

IN03N

V

EE

V

CC

IN04P

R33

105Ω

IN04N

V

EE

V

CC

IN05P

R36

105Ω

IN05N

V

EE

R40

1.65kΩ P16

P17

R38

1.65kΩ

R41

1.65kΩ P18

P19

R43

1.65kΩ

R44

1.65kΩ

P20

P21

R46

1.65kΩ

R47

1.65kΩ

P22

P23

R49

1.65kΩ

R50

1.65kΩ

P24

P25

R52

1.65kΩ

R53

1.65kΩ

P26

P27

R55

1.65kΩ

V

CC

IN06P

R39

105Ω

IN06N

V

EE

V

CC

IN07P

R42

105Ω

IN07N

V

EE

V

CC

IN08P

R45

105Ω

IN08N

V

EE

V

CC

IN09P

R48

105Ω

IN09N

V

EE

V

CC

IN10P

R51

105Ω

IN10N

V

EE

V

CC

IN11P

R54

105Ω

IN11N

V

EE

R58

1.65kΩ P28

P29

R56

1.65kΩ

R59

1.65kΩ P30

P31

R61

1.65kΩ

R62

1.65kΩ P32

P33

R64

1.65kΩ

R65

1.65kΩ P34

P35

R67

1.65kΩ

R68

1.65kΩ

P36

P37

R70

1.65kΩ

R71

1.65kΩ

P38

P39

R73

1.65kΩ

V

CC

IN12P

R57

105Ω

IN12N

V

EE

V

CC

IN13P

R60 105Ω

IN13N

V

EE

V

CC

IN14P

R63

105Ω

IN14N

V

EE

V

CC

IN15P

R66

105Ω

IN15N

V

EE

V

CC

IN16P

R69

105Ω

IN16N

V

EE

V

CC

IN17P

R72

105Ω

IN17N

V

EE

R89

1.65kΩ P40

P41

R91

1.65kΩ

R88

1.65kΩ P42

P43

R86

1.65kΩ

R85

1.65kΩ

P44

P45

R83

1.65kΩ

R82

1.65kΩ

P46

P47

R80

1.65kΩ

R79

1.65kΩ P48

P49

R77

1.65kΩ

R76

1.65kΩ P50

P51

R74

1.65kΩ

V

CC

IN18P

R90

105Ω

IN18N

V

EE

V

CC

IN19P

R87

105Ω

IN19N

V

EE

V

CC

IN20P

R84

105Ω

IN20N

V

EE

V

CC

IN21P

R81

105Ω

IN21N

V

EE

V

CC

IN22P

R78

105Ω

IN22N

V

EE

V

CC

IN23P

R75

105Ω

IN23N

V

EE

R94

1.65kΩ P52

P53

R92

1.65kΩ

R95

1.65kΩ P54

P55

R97

1.65kΩ

R98

1.65kΩ

P56

P57

R100

1.65kΩ

R101

1.65kΩ

P58

P59

R103

1.65kΩ

R104

1.65kΩ

P60

P61

R106

1.65kΩ

R107

1.65kΩ

P62

P63

R109

1.65kΩ

V

CC

IN24P

R93 105Ω

IN24N

V

EE

V

CC

IN25P

R96 105Ω

IN25N

V

EE

V

CC

IN26P

R99

105Ω

IN26N

V

EE

V

CC

IN27P

R102

105Ω

IN27N

V

EE

V

CC

IN28P

R105

105Ω

IN28N

V

EE

V

CC

IN29P

R108

105Ω

IN29N

V

EE

R116

1.65kΩ P64

P65

R118

1.65kΩ

R115

1.65kΩ P66

P67

R113

1.65kΩ

R112

1.65kΩ

P68

P69

R110

1.65kΩ

V

CC

IN30P

R117 105Ω

OUT08P

OUT08N

IN30N

V

EE

V

CC

OUT09P

OUT09N

IN31P

R114 105Ω

OUT10P

IN31N

V

EE

V

CC

OUT10N

OUT11P

IN32P

R111 105Ω

OUT11N

IN32N

V

EE

OUT12P

OUT12N

OUT13P

OUT13N

OUT14P

OUT14N

OUT15P

OUT15N

OUT16P

OUT16N

R160

49.9Ω

R162

49.9Ω

R165

49.9Ω

R163

49.9Ω

R175

49.9Ω

R173

49.9Ω

R170

49.9Ω

R172

49.9Ω

R185

49.9Ω

R183

49.9Ω

R180

49.9Ω

R182

49.9Ω

R195

49.9Ω

R193

49.9Ω

R190

49.9Ω

R192

49.9Ω

R200

49.9Ω

R198

49.9Ω

P87

P86

P85

P84

P83

P82

P81

P80

P79

P78

P77

P76

P75

P74

P73

P72

P71

P70

OUT00P

V

TT

OUT00N

OUT01P

V

TT

OUT01N

OUT02P

V

TT

OUT02N

OUT03P

V

TT

OUT03N

OUT04P

V

TT

OUT04N

OUT05P

V

TT

OUT05N

OUT06P

V

TT

OUT06N

OUT07P

V

TT

OUT07N

V

TT

V

TT

V

TT

R121

49.9Ω

R122

49.9Ω

R125

49.9Ω

R127

49.9Ω

R130

49.9Ω

R132

49.9Ω

R135

49.9Ω

R133

49.9Ω

R140

49.9Ω

R142

49.9Ω

R145

49.9Ω

R143

49.9Ω

R150

49.9Ω

R152

49.9Ω

R155

49.9Ω

R153

49.9Ω

C16

0.01μF

C82

0.01μF

C83

0.01μF

P103

P102

P101

P100

P99

P98 P97

P96

P95

P94 P93

P92

P91

P90

P89

P88

V

TT

V

TT

V

TT

V

TT

V

TT

V

TT

V

TT

V

TT

CC

01074-051

Figure 51. Input/Output Connections and Bypassing

Rev. A | Page 40 of 44

AD8150

www.BDTIC.com/ADI

CLK P2 6

DATA

V

CHIP_SELECT

CHIP_SELECT P3 9

P2 5

P2 25

SS

READ RESET WRITE

UPDATE

WRITE P3 13 RESET

READ P3 11

UPDATE P3 15

CLK

DATA

D0 P3 27 A4 A3 A2 A1 P3 19 A0 D6 P3 39 D5 P3 37 D4 D3 D2 D1

V

A1

1 74HC14

4

3

74HC14A174HC14

V

SS

V

DD

V

SS

P2 7 P2 3 P2 8 P2 4 P2 2

P3 7

P3 25 P3 23 P3 21

P3 17

P3 35 P3 33 P3 31 P3 29

P3 5

DD

P3 14

SS

P3 8 P3 12 P3 28 P3 26 P3 24 P3 22 P3 20 P3 18 P3 40 P3 38 P3 36 P3 34 P3 32 P3 30 P3 16 P3 10

P3 6

2

P1 6

P1 1 P1 2

P1 3 P1 4

P1 7

P1 5 P104

P105

V

TP9 TP10 TP11 TP12 TP13

+

10

SS

1 2 3 4 5 6 7 8 9

C3 10μF

C1 10μF

C2 10μF

OUT_EN D0 D1 D2 D3 D4 D5 D6 D7 GND

R13 49Ω

R15 49Ω

R17 49Ω

20

V

Q0 Q1 Q2 Q3

A3

Q4 Q5 Q6 Q7

CLK

V

TT

V

TT

V

CC

V

CC

V

EE

V

EE

V

DD

V

SS

DD

CC

19 18 17 16 15 14 13 12 11

R12 49Ω

R14 49Ω

R16 49Ω

R18 49Ω

A1, 4 PIN 14 IS TIED TO VDD. A1, 4 PIN 7 IS TIED TO V

V

DD

C86

C87

0.1μF

V

SS

153D6

154D5

155D4

156D3

157D2

158D1

159D0

C88

0.1μF

VCCV

TP20

TP14 TP15 TP16 TP17 TP18 TP19

V

DD

.

SS

V

DD

C89

0.1μF

V

SS

J1 J2 J3 J4 J5 J6 J7 J8

J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25

74HC14 11 10

74HC14

13

74HC14

10

74HC132

12 13

VCCV

EE

A1

9

A1

A4

9

A4

74HC132

EE

J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 J41 J42 J43 J44 J45 J46 J47 J48 J49 J50

8

12

8

11

01074-052

1

A1

5

6

V

DD

V

SS

R1

20kΩ

W1

V

DD

V

SS

OUT_EN

2

D0

3

D1

4

D2

5

D3

6

D4

74HC74 74HC74

7

D5

8

D6

9

D7

10

GND

V

SS

49Ω

V

SS

V

SS

R10 49Ω

V

SS

V

SS

1 2

R2

V

49kΩ

SS

R3

49kΩ

SS

R5

49kΩ

R4

49kΩ

R6

49kΩ

V

A2

CLK

R8

A4

74HC132

20

CC

19

Q0

18

Q1

17

Q2

16

Q3

15

Q4

14

Q5

13

Q6

12

Q7

11

R7

49Ω

R9

49Ω

R11 49Ω

A4

3

4 5

74HC132

TP5 TP6

TP4

TP7 TP8

CHIP_SELECT 168

UPDATE 165

WRITE 166

RESET 169

160A4

161A3

162A2

163A1

164A0

V

DD

V

SS

6

V

TT

V

CC

V

EE

V

DD

V

SS

Figure 52. Control Logic and Bypassing

Rev. A | Page 41 of 44

AD8150

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.75

0.60

0.45

1.60 MAX

184

22.20

22.00 SQ

21.80

1

PIN 1

TOP VIEW

(PINS DOWN)

139

138

20.20

20.00 SQ

19.80

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0.20

0.09 7°

3.5° 0°

0.08 MAX COPLANARITY

46

VIEW A

47

0.40 BSC

LEAD PITCH

0.23

0.18

0.13

93

92

Figure 53. 184-Lead Low Profile Quad Flat Package [LQFP]

(ST-184)

Dimensions shown in millimeters

ORDERING GUIDE1

Model Temperature Range Package Description Package Option

AD8150AST 0°C to 85°C 184-Lead Low Profile Quad Flat Package [LQFP] ST-184 AD8150ASTZ2 0°C to 85°C 184-Lead Low Profile Quad Flat Package [LQFP] ST-184 AD8150-EVAL Evaluation Board

1

Details of lead finish composition can be found on the ADI website at www.analog.com by reviewing the Material Description of each relevant package.

2

Z = Pb-free part.

Rev. A | Page 42 of 44

AD8150

www.BDTIC.com/ADI

NOTES

Rev. A | Page 43 of 44

AD8150

www.BDTIC.com/ADI

NOTES

C01074–0–9/05(A)

Rev. A | Page 44 of 44

Datasheet AD8150 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

MAXIMUM POWER DISSIPIATION

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUIT

CONTROL INTERFACE

CONTROL INTERFACE TRUTH TABLES

CONTROL INTERFACE TIMING DIAGRAMS

CONTROL INTERFACE PROGRAMMING EXAMPLE

CONTROL INTERFACE DESCRIPTION

CONTROL PIN DESCRIPTION

A[4:0] Inputs

D[6:0] Inputs/Outputs

CONTROL INTERFACE TRANSLATORS

CIRCUIT DESCRIPTION

HIGH SPEED DATA INPUTS (INxxP, INxxN)

HIGH SPEED DATA OUTPUTS (OUTyyP, OUTyyN)

OUTPUT CURRENT SET PIN (REF)

POWER SUPPLIES

Logic Supplies

Data Path Supplies

POWER DISSIPATION

HEAT SINKING

APPLICATIONS

AD8150 INPUT AND OUTPUT BUSING

EVALUATION BOARD

CONFIGURATION PROGRAMMING

POWER SUPPLIES

SOFTWARE INSTALLATION

SOFTWARE OPERATION

PCB LAYOUT

OUTLINE DIMENSIONS