Datasheet AD8138 Datasheet (Analog Devices)

Low Distortion

Differential ADC Driver

AD8138

FEATURES
Easy to Use Single-Ended-to-Differential Conversion
Adjustable Output Common-Mode Voltage
Externally Adjustable Gain
Low Harmonic Distortion

–94 dBc—Second, –114 dBc—Third @ 5 MHz into

800 ⍀ Load

–87 dBc—Second, –85 dBc—Third @ 20 MHz into

800 ⍀ Load
–3 dB Bandwidth of 320 MHz, G = +1
Fast Settling to 0.01% of 16 ns
Slew Rate 1150 V/␮s
Fast Overdrive Recovery of 4 ns

÷

Low Input Voltage Noise of 5 nV/

Hz

1 mV Typical Offset Voltage
Wide Supply Range +3 V to ⴞ5 V
Low Power 90 mW on 5 V

0.1 dB Gain Flatness to 40 MHz
Available in 8-Lead SOIC and MSOP Packages

APPLICATIONS
ADC Driver
Single-Ended-to-Differential Converter
IF and Baseband Gain Block
Differential Buffer
Line Driver

PIN CONFIGURATION

1

–IN

V

2

OCM

V+

3

4

+OUT

NC = NO CONNECT

AD8138

+IN

8

NC

7

V–

6

–OUT

5

TYPICAL APPLICATION CIRCUIT

AVDD DVDD

AIN

AIN

AVSS

+5V

ADC

DIGITAL

V

REF

OUTPUTS

+5V

499⍀

V

499⍀

IN

499⍀

V

OCM

+

AD8138

–

499⍀

PRODUCT DESCRIPTION

The AD8138 is a major advancement over op amps for differential
signal processing. The AD8138 can be used as a single-ended­to-differential amplifier or as a differential-to-differential
amplifier. The AD8138 is as easy to use as an op amp, and
greatly simplifies differential signal amplification and driving.
Manufactured on ADI’s proprietary XFCB bipolar process, the
AD8138 has a –3 dB bandwidth of 320 MHz and delivers a
differential signal with the lowest harmonic distortion available
in a differential amplifier. The AD8138 has a unique internal
feedback feature that provides balanced output gain and phase
matching, suppressing even order harmonics. The internal feed­back circuit also minimizes any gain error that would be associated
with the mismatches in the external gain setting resistors.

The AD8138’s differential output helps balance the input-to­differential ADCs, maximizing the performance of the ADC.

REV. E

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

The AD8138 eliminates the need for a transformer with high
performance ADCs, preserving the low frequency and dc infor­mation. The common-mode level of the differential output is
adjustable by a voltage on the V

pin, easily level-shifting the

OCM

input signals for driving single-supply ADCs. Fast overload
recovery preserves sampling accuracy.

The AD8138 distortion performance makes it an ideal ADC driver
for communication systems, with distortion performance good
enough to drive state-of-the-art 10-bit to 16-bit converters at
high frequencies. The AD8138’s high bandwidth and IP3 also
make it appropriate for use as a gain block in IF and baseband
signal chains. The AD8138 offset and dynamic performance
make it well suited for a wide variety of signal processing and
data acquisition applications.

The AD8138 is available in both SOIC and MSOP packages for
operation over –40∞C to +85∞C temperatures.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD8138–SPECIFICATIONS

(@ 25ⴗC, VS = ⴞ5 V, V

= 0, G = +1, R

OCM

= 500 ⍀, unless otherwise noted. Refer

L,dm

to Figure 1 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs unless otherwise noted.)

Parameter Conditions Min Typ Max Unit

ⴞDIN to ⴞOUT Specifications

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth V

Bandwidth for 0.1 dB Flatness V
Large Signal Bandwidth V
Slew Rate V
Settling Time 0.01%, V
Overdrive Recovery Time VIN = 5 V to 0 V Step, G = +2 4 ns

NOISE/HARMONIC PERFORMANCE*

Second Harmonic V

Third Harmonic V

IMD 20 MHz –77 dBc
IP3 20 MHz 37 dBm
Voltage Noise (RTI) f = 100 kHz to 40 MHz 5 nV/÷Hz
Input Current Noise f = 100 kHz to 40 MHz 2 pA/÷Hz

INPUT CHARACTERISTICS

Offset Voltage V

Input Bias Current 3.5 7 mA

Input Resistance Differential 6 MW

Input Capacitance 1pF
Input Common-Mode Voltage –4.7 to +3.4 V
CMRR DV

OUTPUT CHARACTERISTICS

Output Voltage Swing Maximum DV
Output Current 95 mA
Output Balance Error DV

V

to ⴞOUT Specifications

OCM

DYNAMIC PERFORMANCE

–3 dB Bandwidth 250 MHz
Slew Rate 330 V/ms

NPUT VOLTAGE NOISE (RTI) f = 0.1 MHz to 100 MHz 17 nV/÷Hz

DC PERFORMANCE

Input Voltage Range ±3.8 V
Input Resistance 200 kW
Input Offset Voltage V
Input Bias Current 0.5 mA

CMRR DV

V

OCM

Gain DV

POWER SUPPLY

Operating Range ±1.4 ±5.5 V
Quiescent Current 18 20 23 mA

Power Supply Rejection Ratio DV

OPERATING TEMPERATURE RANGE –40 +85 ∞C

*Harmonic Distortion Performance is equal or slightly worse with higher values of R

Specifications subject to change without notice.

= 0.5 V p-p, CF = 0 pF 290 320 MHz

OUT

= 0.5 V p-p, CF = 1 pF 225 MHz

V

OUT

= 0.5 V p-p, CF = 0 pF 30 MHz

OUT

= 2 V p-p, CF = 0 pF 265 MHz

OUT

= 2 V p-p, CF = 0 pF 1150 V/ms

V
V

V
V

T

T

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OS,dm

MIN

MIN

= 2 V p-p, CF = 1 pF 16 ns

OUT

= 2 V p-p, 5 MHz, R
= 2 V p-p, 20 MHz, R
= 2 V p-p, 70 MHz, R
= 2 V p-p, 5 MHz, R
= 2 V p-p, 20 MHz, R
= 2 V p-p, 70 MHz, R

= V

to T

to T

/2; V

OUT,dm

MAX

MAX

DIN+

Variation ±4 mV/∞C

Variation –0.01 mA/∞C

= 800 W –94 dBc

L,dm

= 800 W –87 dBc

L,dm

= 800 W –62 dBc

L,dm

= 800 W –114 dBc

L,dm

= 800 W –85 dBc

L,dm

= 800 W –57 dBc

L,dm

= V

DIN–

= V

= 0 V –2.5 ±1 +2.5 mV

OCM

Common Mode 3 MW

/DV

T

OUT,dm

/DV

OUT,cm

= V

OS,cm

/DV

OUT,dm

/DV

OUT,cm

to T

MIN

/DVS; DVS = ± 1 V –90 –70 dB

OUT,dm

; DV

IN,cm

; Single-Ended Output 7.75 V p-p

OUT

OUT,dm

; V

OUT,cm

; DV

OCM

OCM; DVOCM

Variation 40 mA/∞C

MAX

= ± 1 V –77 –70 dB

IN,cm

; DV

DIN+

OCM

= 1 V –66 dB

OUT,dm

= V

DIN–

= V

= 0 V –3.5 ± 1 +3.5 mV

OCM

= ± 1 V –75 dB
= ±1 V 0.9955 1 1.0045 V/V

. See TPCs 13 and 14 for more information.

L,dm

REV. E–2–

AD8138

SPECIFICATIONS

(@ 25ⴗC, VS = 5 V, V
setup and label descriptions. All specifications refer to single-ended input and differential output, unless

= 2.5 V, G = +1, R

OCM

= 500 ⍀, unless otherwise noted. Refer to Figure 1 for test

L,dm

otherwise noted.)

Parameter Conditions Min Typ Max Unit

ⴞ

DIN to ⴞOUT Specifications

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth V

Bandwidth for 0.1 dB Flatness V
Large Signal Bandwidth V
Slew Rate V
Settling Time 0.01%, V
Overdrive Recovery Time VIN = 2.5 V to 0 V Step, G = +2 4 ns

NOISE/HARMONIC PERFORMANCE*

Second Harmonic V

Third Harmonic V

IMD 20 MHz –74 dBc
IP3 20 MHz 35 dBm
Voltage Noise (RTI) f = 100 kHz to 40 MHz 5 nV/÷Hz
Input Current Noise f = 100 kHz to 40 MHz 2 pA/÷Hz

INPUT CHARACTERISTICS

Offset Voltage V

Input Bias Current 3.5 7 mA

Input Resistance Differential 6 MW

Input Capacitance 1pF
Input Common-Mode Voltage 0.3 to 3.2 V
CMRR ⌬V

OUTPUT CHARACTERISTICS

Output Voltage Swing Maximum ⌬V
Output Current 95 mA
Output Balance Error ⌬V

V

to ⴞOUT Specifications

OCM

DYNAMIC PERFORMANCE

–3 dB Bandwidth 220 MHz
Slew Rate 250 V/ms

INPUT VOLTAGE NOISE (RTI) f = 0.1 MHz to 100 MHz 17 nV/÷Hz

DC PERFORMANCE

Input Voltage Range 1.0 to 3.8 V
Input Resistance 100 kW
Input Offset Voltage V
Input Bias Current 0.5 mA

CMRR ⌬V

V

OCM

Gain ⌬V

POWER SUPPLY

Operating Range 2.7 11 V
Quiescent Current 15 20 21 mA

Power Supply Rejection Ratio ⌬V

OPERATING TEMPERATURE RANGE –40 +85 ∞C

*Harmonic Distortion Performance is equal or slightly worse with higher values of R

Specifications subject to change without notice.

= 0.5 V p-p, CF = 0 pF 280 310 MHz

OUT

= 0.5 V p-p, CF = 1 pF 225 MHz

V

OUT

= 0.5 V p-p, CF = 0 pF 29 MHz

OUT

= 2 V p-p, CF = 0 pF 265 MHz

OUT

= 2 V p-p, CF = 0 pF 950 V/ms

V
V

V
V

T

T

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OS,dm

MIN

MIN

= 2 V p-p, CF = 1 pF 16 ns

OUT

= 2 V p-p, 5 MHz, R
= 2 V p-p, 20 MHz, R
= 2 V p-p, 70 MHz, R
= 2 V p-p, 5 MHz, R
= 2 V p-p, 20 MHz, R
= 2 V p-p, 70 MHz, R

= V

to T

to T

/2; V

OUT,dm

MAX

MAX

DIN+

Variation ± 4 mV/∞C

Variation –0.01 mA/∞C

= 800 W –90 dBc

L,dm

= 800 W –79 dBc

L,dm

= 800 W –60 dBc

L,dm

= 800 W –100 dBc

L,dm

= 800 W –82 dBc

L,dm

= 800 W –53 dBc

L,dm

= V

= V

DIN–

= 0 V –2.5 ± 1 +2.5 mV

OCM

Common Mode 3 MW

/⌬V

T

OUT,dm

OUT,cm

OS,cm

OUT,dm

OUT,cm

MIN

OUT,dm

= V

to T

; ⌬V

IN,cm

OUT

/⌬V

OUT,dm

; V

OUT,cm

/⌬V

; ⌬V

OCM

/⌬V

OCM; ⌬VOCM

Variation 40 mA/∞C

MAX

/⌬VS; ⌬VS = ± 1 V –90 –70 dB

= 1 V –77 –70 dB

IN,cm

; Single-Ended Output 2.9 V p-p

; ⌬V

DIN+

OCM

= 1 V –65 dB

OUT,dm

= V

= V

DIN–

= 0 V –5 ± 1+5mV

OCM

= 2.5 ± 1 V –70 dB
= 2.5 ± 1 V 0.9968 1 1.0032 V/V

. See TPCs 13 and 14 for more information.

L,dm

REV. E

–3–

AD8138

ABSOLUTE MAXIMUM RATINGS

1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± V

V

OCM

Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 550 mW

2

(SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155∞C/W

␪

JA

S

Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300∞C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational section
of this specification is not implied. Exposure to Absolute Maximum Ratings for
extended periods may affect device reliability.

2

Thermal resistance measured on SEMI standard four-layer board.

= 499⍀

R

F

RG = 499⍀

49.9⍀
R

G

24.9⍀

= 499⍀

AD8138

RF = 499⍀

R

= 499⍀

L,dm

Figure 1. Basic Test Circuit

PIN CONFIGURATION

1

–IN

V

2

OCM

V+

3

4

+OUT

NC = NO CONNECT

AD8138

+IN

8

NC

7

V–

6

–OUT

5

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 –IN Negative Input Summing Node

2V

OCM

Voltage applied to this pin sets the
common-mode output voltage with a
ratio of 1:1. For example, 1 V dc on

will set the dc bias level on +OUT

V

OCM

and –OUT to 1 V.

3V+ Positive Supply Voltage

4 +OUT Positive Output. Note that the voltage at

–D

is inverted at +OUT. (See Figure 2.)

IN

5 –OUT Negative Output. Note that the voltage

at +D

is inverted at –OUT. (See

IN

Figure 2.)

6V–Negative Supply Voltage

7NC No Connect

8 +IN Positive Input Summing Node

ORDERING GUIDE

Temperature Package Package Branding

Model Range Description Option Information

AD8138AR –40∞C to +85∞C 8-Lead SOIC R-8
AD8138AR-REEL –40∞C to +85∞C 8-Lead SOIC 13" Tape and Reel
AD8138AR-REEL7 –40∞C to +85∞C 8-Lead SOIC 7" Tape and Reel
AD8138ARM –40∞C to +85∞C 8-Lead MSOP RM-8 HBA
AD8138ARM-REEL –40∞C to +85∞C 8-Lead MSOP 13" Tape and Reel HBA
AD8138ARM-REEL7 –40∞C to +85∞C 8-Lead MSOP 7" Tape and Reel HBA
AD8138-EVAL Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8138 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. E–4–

Typical Performance Characteristics–AD8138

Unless otherwise noted, Gain = 1, RG = RF = R

6

3

0

GAIN – dB

–3

–6

–9

1

10 100

FREQUENCY – MHz

TPC 1. Small Signal Frequency
Response

6

3

0

GAIN – dB

–3

–6

VS = +5V

VS = +5V

VS = ⴞ5V

VS = ⴞ5V

VIN = 0.2V p-p

= 0pF

C

F

VIN = 2V p-p

= 0pF

C

F

1000

= 499 V, TA = 25ⴗC; refer to Figure 1 for test setup.

L,dm

6

3

0

GAIN – dB

–3

–6

–9

1

10 100

FREQUENCY – MHz

CF = 0pF

CF = 1pF

VS = ⴞ5V

= 0.2V p-p

V

IN

1000

TPC 2. Small Signal Frequency
Response

6

3

0

GAIN – dB

–3

–6

CF = 1pF

VIN = 2V p-p

= ⴞ5V

V

S

CF = 0pF

0.5
VS = ⴞ5V

= 0.2V p-p

V

IN

0.3

0.1

GAIN – dB

–0.1

–0.3

–0.5

1

10 100

FREQUENCY – MHz

TPC 3. 0.1 dB Flatness vs.
Frequency

30

G = 10, RF = 4.99k⍀

20

G = 5, RF = 2.49k⍀

10

G = 2, RF = 1k⍀

GAIN – dB

G = 1, RF = 499⍀

0

CF = 0pF

CF = 1pF

VS = ⴞ5V

= 0pF

C

F

V

,dm

OUT

= 499⍀

R

G

= 0.2V p-p

–9

1

10 100

FREQUENCY – MHz

TPC 4. Large Signal Frequency
Response

–50

V

= 2V p-p

,dm

OUT

= 800⍀

R

L

–60

–70

HD2(VS = +5V)

–80

–90

DISTORTION – dBc

–100

–110

–120

HD3(VS = ⴞ5V)

010 7020 30 40 50 60

FUNDAMENTAL FREQUENCY – MHz

HD2(VS = ⴞ5V)

HD3(VS = +5V)

TPC 7. Harmonic Distortion vs.
Frequency

1000

–9

1

10 100

FREQUENCY – MHz

TPC 5. Large Signal Frequency
Response

–40

V

= 4V p-p

,dm

OUT

= 800⍀

R

L

–50

–60

–70

–80

DISTORTION – dBc

–90

–100

–110

HD3(VS = +5V)

HD2(VS = +5V)

HD2(VS = ⴞ5V)

HD3(VS = ⴞ5V)

010 7020 30 40 50 60

FUNDAMENTAL FREQUENCY – MHz

TPC 8. Harmonic Distortion vs.
Frequency

1000

–10

1

10 100

FREQUENCY – MHz

TPC 6. Small Signal Frequency
Response for Various Gains

–30

V

= 2V p-p

,dm

OUT

= 800⍀

R

L

–40

= 20MHz

F

O

–50

–60

–70

DISTORTION – dBc

–80

–90

–100

–4 –3 3

HD3(VS = +5)

HD3(VS = ⴞ5)

HD2(VS = ⴞ5)

–2 –1 0 1 2

V

OCM

HD2(VS = +5)

DC OUTPUT – V

TPC 9. Harmonic Distortion vs.
V

OCM

1000

4

REV. E

–5–

AD8138

p

p

p

–60

VS = ⴞ5V

R

= 800⍀

L

–70

–80

–90

–100

DISTORTION – dBc

–110

–120

HD2(F = 20MHz)

0 6

DIFFERENTIAL OUTPUT VOLTAGE – V p-

HD3(F = 20MHz)

HD2(F = 5MHz)

HD3(F = 5MHz)

TPC 10. Harmonic Distortion
vs. Differential Output Voltage

–60

VS = 5V

= 2V p-p

V

,dm

OUT

–70

–80

–90

DISTORTION – dBc

–100

–110

200

HD2(F = 5MHz)

HD3(F = 5MHz)

600 1000 1400 1800

R

LOAD

HD2(F = 20MHz)

HD3(F = 20MHz)

– ⍀

TPC 13. Harmonic Distortion
vs. R

LOAD

–60

VS = 5V

= 800⍀

R

L

–70

–80

–90

–100

DISTORTION – dBc

–110

54321

–120

0

DIFFERENTIAL OUTPUT VOLTAGE – V p-

HD2(F = 20MHz)

HD2(F = 5MHz)

HD3(F = 5MHz)

1

HD3(F = 20MHz)

234

TPC 11. Harmonic Distortion
vs. Differential Output Voltage

–60

VS = ⴞ5V

= 2V p-p

V

,dm

OUT

–70

HD2(F = 20MHz)

–80

–90

–100

DISTORTION – dBc

–110

–120

200

600 1000 1400 1800

HD3(F = 20MHz)

HD2(F = 5MHz)

HD3(F = 5MHz)

R

– ⍀

LOAD

TPC 14. Harmonic Distortion
vs. R

LOAD

–60

VS = 3V
R

= 800⍀

L

–70

HD2(F = 20MHz)

–80

–90

DISTORTION – dBc

–100

–110

0.25

0.50 0.75 1.00 1.25 1.50 1.75

DIFFERENTIAL OUTPUT VOLTAGE – V p-

HD3(F = 20MHz)

HD2(F = 5MHz)

HD3(F = 5MHz)

TPC 12. Harmonic Distortion
vs. Differential Output Voltage

10

FC = 50MHz

V

= ⴞ5V

S

–10

–30

–50

– dBm

OUT

P

–70

–90

–110

49.5

49.7 49.9 50.1 50.3 50.5
FREQUENCY – MHz

TPC 15. Intermodulation Distortion

45

RL = 800⍀

40

V

= ⴞ5V

35

INTERCEPT – dBm

30

25

0

S

VS = +5V

20

40 60 80

FREQUENCY – MHz

TPC 16. Third Order Intercept vs.
Frequency

VS = ⴞ5V

V

OUT,dm

V

OUT–

V

OUT+

V

+DIN

1V

5ns

TPC 17. Large Signal Transient
Response

V

= 0.2V p-p

CF = 0pF

CF = 1pF

40mV

OUT,dm

= ⴞ5V

V

S

5ns

TPC 18. Small Signal Transient
Response

REV. E–6–

AD8138

V

VS = ⴞ5V

VS = +5V

400mV

OUT,dm

C

F

= 2V p-p

= 0pF

5ns

TPC 19. Large Signal Transient
Response

V

OUT,dm

VS = ⴞ5V
F = 20MHz

= 8V p-p

V

+DIN

= 1500)

G = 3(R

F

V

+DIN

CF = 0pF

CF = 1pF

400mV

V

OUT,dm

V

S

= 2V p-p

= ⴞ5V

5ns

TPC 20. Large Signal Transient
Response

499⍀

49.9⍀

24.9⍀

499⍀

499⍀

AD8138

499⍀

24.9⍀

24.9⍀

C

L

453⍀

200␮V

V

+DIN

1V

TPC 21. Settling Time

VS = ⴞ5V
C

= 0pF

F

CL = 5pF

CL = 10pF

CL = 20pF

V

OUT,dm

VS = ⴞ5V
C

= 1pF

F

4ns

4V

30ns

TPC 22. Output Overdrive

–20

VS = ⴞ5V

/⌬V

⌬V

OUT,dm

–30

–40

–50

CMRR – dB

–60

–70

–80

11k10 100

IN,cm

FREQUENCY – MHz

TPC 25. CMRR vs. Frequency

TPC 23. Test Circuit for Cap
Load Drive

499⍀

49.9⍀

499⍀

499⍀

24.9⍀

AD8138

499⍀

249⍀

249⍀

TPC 26. Test Circuit for Output
Balance

400mV

2.5ns

TPC 24. Large Signal Transient
Response for Various Cap Loads

–20

VIN = 2V p-p

–30

–40

–50

BALANCE ERROR – dB

–60

–70

11k10 100

VS = ⴞ5V

VS = +5V

FREQUENCY – MHz

TPC 27. Output Balance Error
vs. Frequency

REV. E

–7–

AD8138

–10

⌬V

/⌬V

OUT,dm

–20

–30

–40

–50

PSRR – dB

–60

–70

–80

–90

11k10 100

S

–PSRR

= ⴞ5V)

(V

S

FREQUENCY – MHz

+PSRR

= +5V, 0V AND ⴞ5V)

(V

S

TPC 28. PSRR vs. Frequency

5

4

VS = ⴞ5V, +5V

3

BIAS CURRENT – ␮A

2

VS = +3V

100

SINGLE-ENDED OUTPUT

10

VS = +5

IMPEDANCE – ⍀

1

VS = ⴞ5V

0.1
110100

FREQUENCY – MHz

TPC 29. Output Impedance
vs. Frequency

30

25

20

15

SUPPLY CURRENT – mA

10

VS = ⴞ5V

VS = +5V

VS = +3V

5.0

2.5

VS = ⴞ5V

0

–2.5

DIFFERENTIAL OUTPUT OFFSET – mV

–5.0

–40 –20 1000204060 80

VS = +5V

VS = +3V

TEMPERATURE – ⴗC

TPC 30. Output Referred
Differential Offset Voltage vs.
Temperature

GAIN – dB

–3

–6

6

3

0

VS = +5V

VS = ⴞ5V

1

–40 –20 1000204060 80

TEMPERATURE – ⴗC

TPC 31. Input Bias Current
vs. Temperature

VS = ⴞ5V
V

= –1V TO +1V

OCM

400mV

TPC 34. V

Transient Response

OCM

V

OUT,cm

5ns

5

–40 –20 1000204060 80

TEMPERATURE – ⴗC

TPC 32. Supply Current vs.
Temperature

100

10

1.1pA / Hz

INPUT CURRENT NOISE – pA/ Hz

1

10 100 1M

1k 10k 100k

FREQUENCY – Hz

TPC 35. Current Noise (RTI)

–9

11k

TPC 33. V

1000

100

10

INPUT VOLTAGE NOISE – nV/ Hz

1

10 100 1M

10 100

FREQUENCY – MHz

Frequency Response

OCM

1k 10k 100k

FREQUENCY – Hz

5.7nV/ Hz

TPC 36. Voltage Noise (RTI)

REV. E–8–

AD8138

OPERATIONAL DESCRIPTION
Definition of Terms

C

F

R

F

R

+IN

+D

V

OCM

–D

G

IN

IN

–IN

R

G

AD8138

R

F

C

F

–OUT

+OUT

R

L,dm

V

,dm

OUT

Figure 2. Circuit Definitions

Differential voltage refers to the difference between two
node voltages. For example, the output differential voltage
(or equivalently output differential-mode voltage) is defined as:

V

+OUT

and V

VVV

refer to the voltages at the +OUT and –OUT

–OUT

=-

()

dm OUT OUTOUT,

+-

terminals with respect to a common reference.

Common-mode voltage refers to the average of two node
voltages. The output common-mode voltage is defined as:

VVV

=+

()

cm OUT OUTOUT,

+-

2

Balance is a measure of how well differential signals are matched
in amplitude and exactly 180⬚ apart in phase. Balance is most
easily determined by placing a well-matched resistor divider
between the differential voltage nodes and comparing the magni­tude of the signal at the divider’s midpoint with the magnitude
of the differential signal (see TPC 26). By this definition, output
balance is the magnitude of the output common-mode voltage
divided by the magnitude of the output differential-mode voltage:

V

OUT cm

Output Balance Error

=

V

OUT dm

,

,

THEORY OF OPERATION

The AD8138 differs from conventional op amps in that it has
two outputs whose voltages move in opposite directions. Like an
op amp, it relies on high open-loop gain and negative feedback
to force these outputs to the desired voltages. The AD8138
behaves much like a standard voltage feedback op amp and makes
it easy to perform single-ended-to-differential conversion, common­mode level-shifting, and amplification of differential signals. Also
like an op amp, the AD8138 has high input impedance and low
output impedance.

Previous differential drivers, both discrete and integrated designs,
have been based on using two independent amplifiers and two
independent feedback loops, one to control each of the outputs.
When these circuits are driven from a single-ended source, the
resulting outputs are typically not well balanced. Achieving a
balanced output has typically required exceptional matching of
the amplifiers and feedback networks.

DC common-mode level-shifting has also been difficult with
previous differential drivers. Level-shifting has required the use
of a third amplifier and feedback loop to control the output
common-mode level. Sometimes the third amplifier has also
been used to attempt to correct an inherently unbalanced

circuit. Excellent performance over a wide frequency range has
proven difficult with this approach.

The AD8138 uses two feedback loops to separately control the
differential and common-mode output voltages. The differential
feedback, set with external resistors, controls only the differential
output voltage. The common-mode feedback controls only the
common-mode output voltage. This architecture makes it easy to
arbitrarily set the output common-mode level. It is forced, by inter­nal common-mode feedback, to be equal to the voltage applied to
the V

input, without affecting the differential output voltage.

OCM

The AD8138 architecture results in outputs that are very highly
balanced over a wide frequency range without requiring tightly
matched external components. The common-mode feedback
loop forces the signal component of the output common-mode
voltage to be zeroed. The result is nearly perfectly balanced
differential outputs of identical amplitude and exactly 180∞ apart
in phase.

Analyzing an Application Circuit

The AD8138 uses high open-loop gain and negative feedback to
force its differential and common-mode output voltages in such
a way as to minimize the differential and common-mode error
voltages. The differential error voltage is defined as the voltage
between the differential inputs labeled +IN and –IN in Figure 2.
For most purposes, this voltage can be assumed to be zero. Simi­larly, the difference between the actual output common-mode
voltage and the voltage applied to V

can also be assumed to

OCM

be zero. Starting from these two assumptions, any application
circuit can be analyzed.

Setting the Closed-Loop Gain

Neglecting the capacitors CF, the differential-mode gain of the
circuit in Figure 2 can be determined to be described by the
following equation:

V

OUT dm

,

V

IN dm

,

This assumes the input resistors, R

S

R

, on each side are equal.

F

S

R

F

=

S

R

G

S

, and feedback resistors,

G

Estimating the Output Noise Voltage

Similar to the case of a conventional op amp, the differential
output errors (noise and offset voltages) can be estimated by
multiplying the input referred terms, at +IN and –IN, by the
circuit noise gain. The noise gain is defined as:

Ê

ˆ

R

F

1

Á

˜

R

Ë

¯

G

G

N

=+

To compute the total output referred noise for the circuit of
Figure 2, consideration must also be given to the contribution of
the resistors R

and RG. Refer to Table I for estimated output

F

noise voltage densities at various closed-loop gains.

Table I.

RGR

Gain (⍀)(⍀) –3 dB 8138 Only 8138 + RG, R

Bandwidth Output Noise Output Noise

F

F

1 499 499 320 MHz 10 nV/÷Hz 11.6 nV/÷Hz
2 499 1.0 k 180 MHz 15 nV/÷Hz 18.2 nV/÷Hz
5 499 2.49 k 70 MHz 30 nV/÷Hz 37.9 nV/÷Hz
10 499 4.99 k 30 MHz 55 nV/÷Hz 70.8 nV/÷Hz

REV. E

–9–

AD8138

When using the AD8138 in gain configurations where

R

F

R

G

of one feedback network is unequal to

R

F

R

G

of the other network, there will be a differential output noise
due to input-referred voltage in the V

circuitry. The output

OCM

noise is defined in terms of the following feedback terms (refer
to Figure 2):

b1=

G

+RRR

FG

for –OUT to +IN loop, and

b2=

G

+RRR

FG

for +OUT to –IN loop. With these defined,

VV

nOUT dm nIN V

=

2

,,

OCM

where V
the input-referred voltage noise in V

is the output differential noise and V

nOUT,dm

OCM

È
Í

Î

˘

–

bb

12

˙

+

bb

12

˚

.

nIN,V

OCM

is

The Impact of Mismatches in the Feedback Networks

As mentioned previously, even if the external feedback networks

) are mismatched, the internal common-mode feedback

(R

F/RG

loop will still force the outputs to remain balanced. The ampli­tudes of the signals at each output will remain equal and 180⬚
out of phase. The input-to-output differential-mode gain will
vary proportionately to the feedback mismatch, but the output
balance will be unaffected.

Ratio matching errors in the external resistors will result in a
degradation of the circuit’s ability to reject input common-mode
signals, much the same as for a four-resistor difference amplifier
made from a conventional op amp.

Also, if the dc levels of the input and output common-mode
voltages are different, matching errors will result in a small
differential-mode output offset voltage. For the G = 1 case, with
a ground referenced input signal and the output common-mode
level set for 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance will result in a worst­case input CMRR of about 40 dB, worst-case differential mode
output offset of 25 mV due to 2.5 V level-shift, and no significant
degradation in output balance error.

Calculating an Application Circuit’s Input Impedance

The effective input impedance of a circuit such as the one in
Figure 2, at +D

and –DIN, will depend on whether the amplifier

IN

is being driven by a single-ended or differential signal source.
For balanced differential input signals, the input impedance

) between the inputs (+DIN and –DIN) is simply:

(R

IN,dm

RR

Idm GN,

=¥2

In the case of a single-ended input signal (for example if –DIN is
grounded and the input signal is applied to +D

), the input

IN

impedance becomes:

R

IN dm

,

Ê
Á

=

Á
Á

Á
Ë

R

G

1

R

-

2

RR

¥+

()

GF

ˆ
˜

˜

F

˜
˜
¯

The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because a
fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor R

.

G

Input Common-Mode Voltage Range in Single-Supply Applications

The AD8138 is optimized for level-shifting “ground” referenced
input signals. For a single-ended input, this would imply, for
example, that the voltage at –D

in Figure 2 would be 0 V when

IN

the amplifier’s negative power supply voltage (at V–) is also
set to 0 V.

Setting the Output Common-Mode Voltage

The AD8138’s V

pin is internally biased at a voltage approxi-

OCM

mately equal to the midsupply point (average value of the voltages
on V+ and V–). Relying on this internal bias will result in an
output common-mode voltage that is within about 100 mV of
the expected value.

In cases where more accurate control of the output common-mode
level is required, it is recommended that an external source, or
resistor divider (made up of 10 kW resistors), be used. The output
common-mode offset listed in the Specifications section assumes
the V

input is driven by a low impedance voltage source.

OCM

Driving a Capacitive Load

A purely capacitive load can react with the pin and bondwire
inductance of the AD8138, resulting in high frequency ringing
in the pulse response. One way to minimize this effect is to place
a small capacitor across each of the feedback resistors. The added
capacitance should be small to avoid destabilizing the amplifier.
An alternative technique is to place a small resistor in series with
the amplifier’s outputs as shown in TPC 23.

LAYOUT, GROUNDING, AND BYPASSING

As a high speed part, the AD8138 is sensitive to the PCB
environment in which it has to operate. Realizing its superior
specifications requires attention to various details of good high
speed PCB design.

The first requirement is for a good solid ground plane that covers
as much of the board area around the AD8138 as possible. The
only exception to this is that the two input pins (Pins 1 and 8)
should be kept a few millimeters from the ground plane, and
ground should be removed from inner layers and the opposite
side of the board under the input pins. This will minimize the
stray capacitance on these nodes and help preserve the gain
flatness versus frequency.

REV. E–10–

AD8138

PRIMARY

C

STRAY

C

STRAY

NO SIGNAL IS COUPLED

ON THIS SIDE

SIGNAL WILL BE COUPLED

ON THIS SIDE VIA C

STRAY

52.3⍀

SECONDARY V

DIFF

500⍀

0.005%
500⍀

0.005%

V

UNBAL

The power supply pins should be bypassed as close as possible
to the device to the nearby ground plane. Good high frequency
ceramic chip capacitors should be used. This bypassing should
be done with a capacitance value of 0.01 mF to 0.1 mF for each
supply. Further away, low frequency bypassing should be provided
with 10 mF tantalum capacitors from each supply to ground.

The signal routing should be short and direct to avoid parasitic
effects. Wherever there are complementary signals, a symmetrical
layout should be provided to the extent possible to maximize the
balance performance. When running differential signals over a
long distance, the traces on the PCB should be close together or
any differential wiring should be twisted together to minimize
the area of the loop that is formed. This will reduce the radiated
energy and make the circuit less susceptible to interference.

BALANCED TRANSFORMER DRIVER

Transformers are among the oldest devices used to perform a
single-ended-to-differential conversion (and vice versa). Trans­formers also can perform the additional functions of galvanic
isolation, step-up or step-down of voltages, and impedance
transformation. For these reasons, transformers will always find
uses in certain applications.

However, when driving a transformer single-endedly and then
looking at its output, there is a fundamental imbalance due to the
parasitics inherent in the transformer. The primary (or driven) side
of the transformer has one side at dc potential (usually ground),
while the other side is driven. This can cause problems in systems
that require good balance of the transformer’s differential output
signals.

If the interwinding capacitance (C
formly distributed, a signal from the driving source will couple
to the secondary output terminal that is closest to the primary’s
driven side. On the other hand, no signal will be coupled to the
opposite terminal of the secondary because its nearest primary
terminal is not driven (see Figure 3). The exact amount of this
imbalance will depend on the particular parasitics of the trans­former, but will mostly be a problem at higher frequencies.

The balance of a differential circuit can be measured by connecting
an equal-valued resistive voltage divider across the differential
outputs and then measuring the center point of the circuit with
respect to ground. Since the two differential outputs are supposed
to be of equal amplitude, but 180⬚ opposite phase, there should
be no signal present for perfectly balanced outputs.

The circuit in Figure 3 shows a Minicircuits T1-6T transformer
connected with its primary driven single-endedly and the second­ary connected with a precision voltage divider across its terminals.
The voltage divider is made up of two 500 W, 0.005% preci­sion resistors. The voltage V
ac common-mode voltage, is a measure of how closely the outputs
are balanced.

The plots in Figure 5 compare the transformer being driven
single-endedly by a signal generator and being driven differen­tially using an AD8138. The top signal trace of Figure 5 shows
the balance of the single-ended configuration, while the bottom

REV. E

UNBAL

) is assumed to be uni-

STRAY

, which is also equal to the

shows the differentially driven balance response. The 100 MHz
balance is 35 dB better when using the AD8138.

The well-balanced outputs of the AD8138 will provide a drive
signal to each of the transformer’s primary inputs that are of equal
amplitude and 180⬚ out of phase. Thus, depending on how the
polarity of the secondary is connected, the signals that conduct
across the interwinding capacitance will either both assist the
transformer’s secondary signal equally, or both buck the secondary
signals. In either case, the parasitic effect will be symmetrical
and provide a well balanced transformer output (see Figure 5).

Figure 3. Transformer Single-Ended-to-Differential
Converter Is Inherently Imbalanced

499⍀

C

STRAY

C

STRAY

V

UNBAL

500⍀

0.005%

500⍀

0.005%

499⍀

499⍀

+IN

–IN

499⍀

49.9⍀

OUT–

AD8138

OUT+

49.9⍀

Figure 4. AD8138 Forms a Balanced Transformer Driver

0

–20

V

, FOR TRANSFORMER

–40

–60

–80

OUTPUT BALANCE ERROR – dB

–100

0.3 500

UNBAL

WITH SINGLE-ENDED DRIVE

V

, DIFFERENTIAL DRIVE

UNBAL

110100

FREQUENCY – MHz

Figure 5. Output Balance Error for Circuits of
Figures 3 and 4

–11–

V

DIFF

AD8138

HIGH PERFORMANCE ADC DRIVING

The circuit in Figure 6 shows a simplified front-end connection
for an AD8138 driving an AD9224, a 12-bit, 40 MSPS A/D
converter. The ADC works best when driven differentially, which
minimizes its distortion as described in its data sheet. The AD8138
eliminates the need for a transformer to drive the ADC and
performs single-ended-to-differential conversion, common-mode
level-shifting, and buffering of the driving signal.

The positive and negative outputs of the AD8138 are connected
to the respective differential inputs of the AD9224 via a pair of

49.9 W resistors to minimize the effects of the switched-capacitor
front end of the AD9224. For best distortion performance, it is
run from supplies of ± 5 V.

The AD8138 is configured with unity gain for a single-ended
input-to-differential output. The additional 23 W, 523 W total, at
the input to –IN is to balance the parallel impedance of the 50 W
source and its 50 W termination that drives the noninverting input.

+5V

499⍀

49.9⍀

49.9⍀

50⍀

SOURCE

49.9⍀

0.1pF

499⍀

523⍀

+

V

OCM

AD8138

499⍀

The signal generator has a ground-referenced, bipolar output,
i.e., it drives symmetrically above and below ground. Connecting

to the CML pin of the AD9224 sets the output common-

V

OCM

mode of the AD8138 at 2.5 V, which is the midsupply level for
the AD9224. This voltage is bypassed by a 0.1 mF capacitor.

The full-scale analog input range of the AD9224 is set to 4 V p-p,
by shorting the SENSE terminal to AVSS. This has been deter­mined to be the scaling to provide minimum harmonic distortion.

For the AD8138 to swing at 4 V p-p, each output swings 2 V p-p
while providing signals that are 180⬚ out of phase. With a
common-mode voltage at the output of 2.5 V, this means that
each AD8138 output will swing between 1.5 V and 3.5 V.

A ground-referenced 4 V p-p, 5 MHz signal at D

+ was used

IN

to test the circuit in Figure 6. When the combined-device circuit
was run with a sampling rate of 20 MSPS, the SFDR (spurious­free dynamic range) was measured at –85 dBc.

+5V

0.1pF 0.1pF

VINB

VINA

DRVDDAVDD

AD9224

AVSS DRVSS

SENSE CML

DIGITAL
OUTPUTS

–5V

Figure 6. AD8138 Driving an AD9224, a 12-Bit, 40 MSPS A/D Converter

REV. E–12–

AD8138

FREQUENCY – MHz

–40

0

THD – dBc

510152025

–45

–50

–55

–60

–65

–70

–75

–80

AD8138–2V

AD8138–1V

FREQUENCY – MHz

65

0

SINAD – dBc

510152025

63

61

59

57

55

53

51

45

49

47

AD8138–1V

AD8138–2V

3 V OPERATION

The circuit in Figure 7 shows a simplified front end connection
for an AD8138 driving an AD9203, a 10-bit, 40 MSPS A/D con­verter that is specified to work on a single 3 V supply. The ADC
works best when driven differentially to make the best use of the
signal swing available within the 3 V supply. The appropriate
outputs of the AD8138 are connected to the appropriate differen­tial inputs of the AD9203 via a low-pass filter.

The AD8138 is configured for unity gain for a single-ended
input to differential output. The additional 23 W at the input to
–IN is to balance the impedance of the 50 W source and its 50 W
termination that drives the noninverting input.

The signal generator has ground-referenced, bipolar output,
i.e., it can drive symmetrically above and below ground. Even
though the AD8138 has ground as its negative supply, it can
still function as a level-shifter with such an input signal.

The output common mode is raised up to midsupply by the
voltage divider that biases V

. In this way, the AD8138 pro-

OCM

vides dc coupling and level-shifting of a bipolar signal, without
inverting the input signal.

The low-pass filter between the AD8138 and the AD9203 pro­vides filtering that helps to improve the signal-to-noise ratio.
Lower noise can be realized by lowering the pole frequency, but
the bandwidth of the circuit will be lowered.

0.1␮F

10k

49.9

10k

⍀

⍀

⍀

0.1␮F

499

523

+3V

499

⍀

499

49.9

20pF

49.9

20pF

⍀

⍀

+

AD8138

⍀

0.1␮F 0.1␮F

⍀

⍀

+3V

AINN

AD9203

AINP

AVSS DRVSS

DRVDDAVDD

DIGITAL
OUTPUTS

The circuit was tested with a –0.5 dBFS signal at various frequen­cies. Figure 8 shows a plot of the total harmonic distortion (THD)
vs. frequency at signal amplitudes of 1 V and 2 V differential
drive levels.

Figure 8. AD9203 THD @ –0.5 dBFS AD8138

Figure 9 shows the signal to noise plus distortion (SINAD)
under the same conditions as above. For the smaller signal
swing, the AD8138 performance is quite good, but its performance
degrades when trying to swing too close to the supply rails.

Figure 7. AD8138 Driving an AD9203, a 10-Bit, 40 MSPS
A/D Converter

REV. E

Figure 9. AD9203 SINAD @ –0.5 dBFS AD8138

–13–

AD8138

OUTLINE DIMENSIONS

8-Lead Standard Small Outline Package [SOIC]

(R-8)

Dimensions shown in millimeters and (inches)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

85

6.20 (0.2440)

5.80 (0.2284)

41

1.27 (0.0500)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

BSC

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.33 (0.0130)

0.25 (0.0098)

0.19 (0.0075)

0.50 (0.0196)

0.25 (0.0099)

8ⴗ
0ⴗ

1.27 (0.0500)

0.41 (0.0160)

8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

3.00
BSC

85

3.00
BSC

1

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187AA

4

SEATING
PLANE

4.90
BSC

1.10 MAX

0.23

0.08

8ⴗ
0ⴗ

0.80

0.40

ⴛ 45ⴗ

REV. E–14–

AD8138

Revision History

Location Page

3/03—Data Sheet changed from REV. D to REV. E.

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to TPC 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Added new paragraph after Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7/02—Data Sheet changed from REV. C to REV. D.

Addition of TPC 35 and TPC 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6/01—Data Sheet changed from REV. B to REV. C.

Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

REV. E

–15–

C01073–0–3/03(E)

–16–