Datasheet AD8133 Datasheet (Analog Devices)

Triple Differential Driver

FEATURES

Triple high speed fully differential driver

225 MHz −3 dB large signal bandwidth
Easily drives 1.4 V p-p video signal into source-terminated

100 Ω UTP cable
1600 V/µs slew rate
Fixed internal gain of 2

Internal common-mode feedback network

Output balance error −60 dB @ 50 MHz

Differential input and output
Differential-to-differential or single-ended-to-differential

operation

Adjustable output common-mode voltage
Output pull-down feature for line isolation
Low distortion: 64 dB SFDR @ 10 MHz on 5 V supply,

= 200 Ω

R

L, dm

Low offset: 4 mV typical output referred on 5 V supply
Low power: 26 mA @ 5 V for three drivers
Wide supply voltage range: +5 V to ±5 V
Available in space-saving packaging: 4 mm × 4 mm LFCSP

APPLICATIONS

KVM (keyboard-video-mouse) networking
UTP (unshielded twisted pair) driving
Differential signal multiplexing

GENERAL DESCRIPTION

The AD8133 is a major advancement beyond using discrete
op amps for driving differential RGB signals over twisted pair
cable. The AD8133 is a triple, low cost differential or single­ended input to differential output driver, and each amplifier has
a fixed gain of 2 to compensate for the attenuation of line ter­mination resistors. The AD8133 is specifically designed for RGB
signals but can be used for any type of analog signals or high speed
data transmission. The AD8133 is capable of driving either Cate­gory 5 unshielded twisted pair (UTP) cable or differential printed
circuit board transmission lines with minimal signal degradation.

With Output Pull-Down

AD8133

FUNCTIONAL BLOCK DIAGRAM

A

B

OCM

VS+–IN B

+IN B

B

A

S+

V

+OUT A

+OUT B

OPD

V

–IN A

+IN A

V

–OUT A

1

2

S–

3

4

5

S–

6

24 23 22 21 20

7 8 9 10 11

Figure 1.

0

∆V

= 2V p-p

OUT, dm

∆V

OUT, cm

/∆V

OUT, dm

FREQUENCY (MHz)

–10

–20

–30

–40
–50
–60

–70

–80

OUTPUT BALANCE ERROR (dB)

–90

–100

1 10 100 500

Figure 2. Output Bal ance vs. Fre quency

Manufactured on Analog Devices’ next generation XFCB bipo­lar process, the AD8133 has a large signal bandwidth of
225 MHz and a slew rate of 1600 V/µs. The AD8133 has an
internal common-mode feedback feature that provides output
amplitude and phase matching that is balanced to −60 dB at
50 MHz, suppressing harmonics and minimizing radiated elec­tromagnetic interference (EMI).

VS–V

AD8133

C

S+

V

–OUT B

OCM

V

19

12

+OUT C

VS = ±5V

18

17

16

15

14

13

V

OCM

V

S+

–IN C
+IN C
V

S–

–OUT C

VS = +5V

C

04769-0-001

04769-0-034

The outputs of the AD8133 can be set to a low voltage state to
be used with series diodes for line isolation, allowing easy dif­ferential multiplexing over the same twisted pair cable. The
AD8133 driver can be used in conjunction with the AD8129
and AD8130 differential receivers.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

The output common-mode level is easily adjustable by applying
a voltage to the V

input pin. The V

OCM

input can also be used

OCM

to transmit signals on the output common-mode voltages.

The AD8133 is available in a 24-lead LFCSP package and can
operate over the temperature range of −40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD8133

TABLE OF CONTENTS

Specifications..................................................................................... 3

Driving a Capacitive Load......................................................... 13

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics............................................. 7

Theory of Operation ...................................................................... 12

Definition of Terms.................................................................... 12

Analyzing an Application Circuit............................................. 12

Closed-Loop Gain...................................................................... 12

Calculating an Application Circuit’s Input Impedance ......... 13

Input Common-Mode Voltage Range in Single-Supply
Applications

.................................................................................. 13

REVISION HISTORY

7/04—Revision 0: Initial Version

Output Pull-Down (OPD) ........................................................ 13

Output Common-Mode Control............................................. 13

Applications..................................................................................... 14

Driving RGB Video Signals Over Category-5 UTP Cable.... 14

Output Pull-Down ..................................................................... 15

KVM Networks........................................................................... 15

Layout and Power Supply Decoupling Considerations .... 15

Amplifier-to-Amplifier Isolation ............................................. 15

Exposed Paddle (EP).................................................................. 15

Outline Dimensions....................................................................... 16

Ordering Guide .......................................................................... 16

Rev. 0 | Page 2 of 16

AD8133

SPECIFICATIONS

VS = ±5V, V

Table 1.

Parameter Conditions Min Typ Max Unit

DIFFERENTIAL INPUT PERFORMANCE
DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth VO = 0.2 V p-p 450 MHz

−3 dB Large Signal Bandwidth VO = 2 V p-p 225 MHz
Bandwidth for 0.1 dB Flatness VO = 0.2 V p-p 60 MHz
V
Slew Rate VO = 2 V p-p, 25% to 75% 1600 V/µs
Settling Time to 0.1% VO = 2 V Step 15 ns
Isolation between Amplifiers f = 10 MHz, between Amplifiers A and B 81 dB

DIFFERENTIAL INPUT CHARACTERISTICS

Input Common-Mode Voltage Range −5 to +5 V
Input Resistance Differential 1.5 kΩ
Single-Ended Input 1.13 kΩ
Input Capacitance Differential 1 pF
DC CMRR ∆V

DIFFERENTIAL OUTPUT CHARACTERISTICS

Differential Signal Gain ∆V
Output Voltage Swing Each Single-Ended Output VS− + 1.9 VS+ – 1.6 V
Output Offset Voltage −24 +4 +24 mV
Output Offset Drift T
Output Balance Error ∆V
DC −70 −58 dB
Output Voltage Noise (RTO) f = 1 MHz 25 nV/√Hz
Output Short-Circuit Current 90 mA

V

to V

OCM

V

DYNAMIC PERFORMANCE

OCM

−3 dB Bandwidth ∆V
Slew Rate V
DC Gain ∆V

V

INPUT CHARACTERISTICS

OCM

Input Voltage Range ±3.1 V
Input Resistance 70 kΩ
Input Offset Voltage −15 −6 +15 mV
Input Offset Voltage Drift T
DC CMRR ∆V

POWER SUPPLY

Operating Range +4.5 ±6 V
Quiescent Current 28 29 mA
PSRR ∆V

OUTPUT PULL-DOWN PERFORMANCE

OPD Input Low Voltage VS− to VS+ − 4.15 V
OPD Input High Voltage VS+ − 3.15 to VS+ V
OPD Input Bias Current 67 90 µA
OPD Assert Time 100 ns
OPD De-Assert Time 100 ns
Output Voltage When OPD Asserted Each Output, OPD Input @ VS+ VS− + 0.86 VS− + 0.90 V

= 0 V @ 25°C, RL, dm = 200 Ω, unless otherwise noted. T

OCM

= 2 V p-p 55 MHz

O

/∆V

OUT, dm

OUT, dm

to T

MIN

/∆V

OUT, cm

PERFORMANCE

O, cm

= 100 mV p-p

OCM

= −1 V to +1 V, 25% to 75% 1000 V/µs

OCM

= ±1 V 0.980 0.995 1.005 V/V

OCM

to T

MIN

OUT, dm

OUT, dm

, ∆V

IN, cm

IN, cm

/∆V

; ∆V

IN, dm

IN, dm

MAX

, ∆V

IN, dm

OUT, dm

MAX

/∆V

, ∆V

OCM

OCM

/∆VS; ∆VS = ±1 V −84 −76 dB

to T

MIN

= −40°C to +85°C.

MAX

= ±1 V −50 dB

= ±1 V 1.925 1.960 2.000 V/V

±30 µV/°C

= 2 V p-p, f = 50 MHz −60 dB

330 MHz

±50 µV/°C

= ±1 V −42 dB

Rev. 0 | Page 3 of 16

AD8133

= 5 V, V

V

S

= 2.5 V @ 25°C, R

OCM

= 200 Ω, unless otherwise noted. T

L, dm

MIN

to T

= −40°C to +85°C.

MAX

Table 2.

Parameter Conditions Min Typ Max Unit

DIFFERENTIAL INPUT PERFORMANCE
DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth VO = 0.2 V p-p 400 MHz

−3 dB Large Signal Bandwidth VO = 2 V p-p 200 MHz
Bandwidth for 0.1 dB Flatness VO = 0.2 V p-p 50 MHz
Slew Rate VO = 2 V p-p, 25% to 75% 1400 V/µs
Settling Time to 0.1% VO = 2 V Step 14 ns
Isolation Between Amplifiers f = 10 MHz, between Amplifiers A and B 75 dB

DIFFERENTIAL INPUT CHARACTERISTICS

Input Common-Mode Voltage Range 0 to 5 V
Input Resistance Differential 1.5 kΩ
Single-Ended Input 1.13 kΩ
Input Capacitance Differential 1 pF
DC CMRR ∆V

OUT, dm

/∆V

IN, cm

, ∆V

= ±1 V −50 dB

IN, cm

DIFFERENTIAL OUTPUT CHARACTERISTICS

Differential Signal Gain ∆V

OUT, dm

/∆V

IN, dm

; ∆V

= ±1 V 1.925 1.960 2.000

IN, dm

Output Voltage Swing Each Single-Ended Output VS− + 1.25 VS+ − 1.15 V
Output Offset Voltage −24 +4 +24 mV
Output Offset Drift T
Output Balance Error ∆V

MIN

to T

OUT, cm

MAX

/∆V

IN, dm

, ∆V

±30 µV/°C

= 2 V p-p, f = 50 MHz −60 dB

OUT, dm

DC −70 −58 dB
Output Voltage Noise (RTO) f = 1 MHz 25 nV/√Hz
Output Short-Circuit Current 90 mA

V

PERFORMANCE

OCM

V

DYNAMIC PERFORMANCE

OCM

−3 dB Bandwidth ∆V
Slew Rate V
DC Gain ∆V

V

INPUT CHARACTERISTICS

OCM

= 100 mV p-p

OCM

= −1 V to +1 V, 25% to 75% 700 V/µs

OCM

= ±1 V, T

OCM

MIN

to T

MAX

290 MHz

0.980 0.995 1.005 V/V

Input Voltage Range 1.25 to 3.85 V
Input Resistance 70 kΩ
Input Offset Voltage −15 +2 +15 mV
Input Offset Voltage Drift T
DC CMRR ∆V

MIN

to T

O, dm

MAX

/∆V

OCM

±50 µV/°C

; ∆V

= ±1 V −42 dB

OCM

POWER SUPPLY

Operating Range +4.5 ±6 V
Quiescent Current 26 27 mA
PSRR ∆V

/∆VS; ∆VS = ±1 V −84 −76 dB

OUT, dm

OUTPUT PULL-DOWN PERFORMANCE

OPD Input Low Voltage VS− to VS+ − 3.85 V
OPD Input High Voltage VS+ − 2.85 to VS+ V
OPD Input Bias Current 63 80 µA
OPD Assert Time 100 ns
OPD De-Assert Time 100 ns
Output Voltage When OPD Asserted Each Output, OPD Input @ VS+ VS− + 0.79 VS− + 0.82 V

Rev. 0 | Page 4 of 16

AD8133

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 12 V
All V

OCM

±V

S

Power Dissipation See Figure 3
Input Common-Mode Voltage ±V

S

Storage Temperature −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature Range

300°C

(Soldering 10 sec)
Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at these or any
other conditions above those indicated in the operational sec­tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, i.e., θJA is specified
for the device soldered in a circuit board in still air.

Table 4. Thermal Resistance with the Underside Pad
Connected to the Plane

Package Type/PCB Type θ

JA

24-Lead LFCSP/4-Layer 70 °C/W

Maximum Power Dissipation

The maximum safe power dissipation in the AD8133 package is
limited by the associated rise in junction temperature (T
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit may change the stresses that
the package exerts on the die, permanently shifting the para­metric performance of the AD8133. Exceeding a junction tem­perature of 175°C for an extended period of time can result in
changes in the silicon devices potentially causing failure.

Unit

) on

J

The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I

). The load current consists of differential

S

and common-mode currents flowing to the loads, as well as
currents flowing through the internal differential and common­mode feedback loops. The internal resistor tap used in the
common-mode feedback loop places a 4 kΩ differential load on
the output. RMS output voltages should be considered when
dealing with ac signals.

Airflow reduces θ

. Als o, more metal dire ctly in contact with

JA

the package leads from metal traces, through holes, ground,
and power planes reduces the θ

JA

underside of the package must be soldered to a pad on the PCB
surface that is thermally connected to a copper plane in order to
achieve the specified θ

.

JA

Figure 3 shows the maximum safe power dissipation in the
package versus ambient temperature for the 24-lead LFCSP
(70°C/W) package on a JEDEC standard 4-layer board with the
underside paddle soldered to a pad that is thermally connected
to a PCB plane. θ

4.0

3.5

3.0

2.5

2.0

1.5

1.0

MAXIMUM POWER DISSIPATION (W)

0.5

0

–40 –20 0 20 40 60 80

Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

values are approximations.

JA

AMBIENT TEMPERATURE (°C)

) is the sum of the

D

) times the

S

. The exposed paddle on the

LFCSP

04769-0-024

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie­tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.

Rev. 0 | Page 5 of 16

AD8133

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

A

B

OCM

VS+–IN B

+IN B

VS–V

B

S+

V

–OUT B

+OUT B

OPD

V

–IN A

+IN A

V

–OUT A

1

2

S–

3

4

5

S–

6

24 23 22 21 20

A

7 8 9 10 11

+OUT A

Figure 4. 24-Lead LFCSP

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 OPD Output Pull-Down
2, 5, 14, 21 V

S−

Negative Power Supply Voltage
3 −IN A Inverting Input, Amplifier A
4 +IN A Noninverting Input, Amplifier A
6 −OUT A Negative Output, Amplifier A
7 +OUT A Positive Output, Amplifier A
8, 11, 17, 24 V

S+

Positive Power Supply Voltage
9 +OUT B Positive Output, Amplifier B
10 −OUT B Negative Output, Amplifier B
12 +OUT C Positive Output, Amplifier C
13 −OUT C Negative Output, Amplifier C
15 +IN C Noninverting Input, Amplifier C
16 −IN C Inverting Input, Amplifier C
18 V
19 V
20 V

C Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier C

OCM

B Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier B

OCM

A Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier A

OCM

22 +IN B Noninverting Input, Amplifier B
23 −IN B Inverting Input, Amplifier B

19

AD8133

C

12

S+

V

+5V

OCM

V

+OUT C

18

17

16

15

14

13

V

OCM

V

S+

–IN C
+IN C
V

S–

–OUT C

C

04769-0-001

V

TEST

TEST
SIGNAL
SOURCE

50Ω

50Ω

53.6Ω

53.6Ω

MIDSUPPLY

AD8133

750Ω

V

OCM

750Ω

Figure 5. Basic Test Circuit

Rev. 0 | Page 6 of 16

V

S+

1.5kΩ

+

–

1.5kΩ

V

S–

–5V

0.1µF ON ALL VS+ PINS

–

200Ω V

R

L, dm

0.1µF ON ALL V

OUT, dm

+

S–

PINS

04769-0-035

AD8133

TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise noted, R
the definition of terms.

9

6

= 200 Ω, VS = ±5 V, TA = 25°C, V

L, dm

–40°C

25°C

85°C

OCM

A = V

OCM

B = V

C = 0 V. Refer to the basic test circuit in Figure 5 for

OCM

9

85°C

6

–40°C

25°C

3

GAIN (dB)

0

V

= 200mV p-p

OUT, dm

–3

1 10 100 1000

FREQUENCY (MHz)

Figure 6. Small Signal Frequency Response at Various Temperatures

9

6

VS = +5V

3

GAIN (dB)

0

–3

V

= 2V p-p

OUT, dm

–6

1 10 100 1000

FREQUENCY (MHz)

VS = ±5V

Figure 7. Large Signal Frequency Response for Various Power Supplies

–30

–40

–50

–60

–70
–80

–90

DISTORTION (dBc)

–100

–110

–120
–130

0.1 1 10 100

Figure 8. Second Harmonic Distortion at V

R

L, dm

= 200Ω

R

FREQUENCY (MHz)

L, dm

= 5 V at Various Loads

S

V

OUT, dm

= 1000Ω

VS = +5V

= 2V p-p

04769-0-010

04769-0-008

04769-0-027

3

GAIN (dB)

0

V

= 2V p-p

OUT, dm

–3

1 10 100 1000

FREQUENCY (MHz)

Figure 9. Large Signal Frequency Response at Various Temperatures

6.9

6.8

6.7
V

= 2V p-p

V

OUT, dm

OUT, dm

= 200mV p-p

6.6

6.5

6.4

GAIN (dB)

6.3

6.2

6.1

6.0

5.9

1 10 100 1000

FREQUENCY (MHz)

Figure 10. 0.1 dB Flatness Response

–30

–40

–50

–60

–70

DISTORTION (dBc)

–80

–90

–100

0.1 1 10 100

Figure 11. Third Harmonic Distortion at V

R

= 200Ω

L, dm

FREQUENCY (MHz)

S

= 5 V at Various Loads

V

OUT, dm

R

L, dm

VS = +5V
= 2V p-p

= 1000Ω

04769-0-011

04769-0-009

04769-0-028

Rev. 0 | Page 7 of 16

AD8133

–30

–40

–50

–60

–70

–80

DISTORTION (dBc)

–90

–100

–110
–120

0.1 1 10 100

Figure 12. Second Harmonic Distortion at V

200

100

VS = ±5V

50

(mV)

0

O, dm

V

–50

R

FREQUENCY (MHz)

VS = +5V

L, dm

V

OUT, dm

= 200Ω

R

L, dm

= ±5 V at Various Loads

S

V

OUT, dm

= 2V p-p

= 1000Ω

= 200mV p-p

04769-0-029

–30

–40

–50

R

= 200

–60

–70

–80

–90

DISTORTION (dBc)

–100

–110

–120
–130

0.1 1 10 100

L, dm

FREQUENCY (MHz)

Figure 15. Third Harmonic Distortion at V

VS = +5V

1.0

VS = ±5V

0.5

(V)

0

O, dm

V

–0.5

V

OUT, dm

Ω

R

L, dm

= ±5 V at Various Loads

S

V

OUT, dm

= 2V p-p

= 1000

= 2V p-p

Ω

04769-0-030

–100

–200

10

8
6

4

2
0

–2

VOLTAGE (V)

–4

–6
–8

–10

5ns/DIV

Figure 13. Small Signal Transient Response

for Various Power Supply Voltages

2 × V

IN, dm

V

OUT, dm

100ns/DIV

Figure 14. Overdrive Recovery

04769-0-007

04769-0-018

–1.0

Figure 16. Large Signal Transient Response

for Various Power Supply Voltages

V

IN, dm

250mV/DIV

SETTLING TIME ERROR
2mV/DIV

t

= 0

Figure 17. Settling Time (0.1%)

10ns/DIV

5ns/DIV

+0.1%

–0.1%

04769-0-016

04769-0-006

Rev. 0 | Page 8 of 16

AD8133

2

1

0

–1

OUTPUT

t

= 0

PULL-DOWN

–2

–3

–4

SINGLE-ENDED OUTPUT VOLTAGE (V)

–5

SINGLE-ENDED OUTPUT

100ns/DIV

Figure 18. Output Pull-Down Response

1000

100

NOISE (nV√Hz)

10

10 100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 19. Output-Referred Voltage Noise vs. Frequency

–30

∆

V

= 200mV p-p

IN, cm

–35

–40

–45

∆

V

/∆V

OUT, dm

–50

–55

COMMON-MODE REJECTION (dB)

–60

–65

1 10 100 1000

IN, cm

FREQUENCY (MHz)

Figure 20. Common-Mode Rejection Ratio vs. Frequency

R

L, dm

V

= ∞

+5

OPD INPUT VOLTAGE (V)

–5

ON

04769-0-017

04769-0-023

04769-0-020

–30

V

OUT, dm/VIN, dm WITH

–32

OUTPUT PULL-DOWN

–34

–36

–38

V

2V p-p

I, dm =

–40

–42

–44

–46

OUTPUT PULL-DOWN ISOLATION (dB)

–48
–50

0.1 1 10 100 1000
FREQUENCY (MHz)

Figure 21. Output Pull-Down Isolation vs. Frequency

0

∆

V

= 2V p-p

OUT, dm

∆

V

OUT, cm

/∆V

OUT, dm

VS = ±5V

FREQUENCY (MHz)

–10

–20

–30

–40
–50
–60

–70

–80

OUTPUT BALANCE ERROR (dB)

–90

–100

1 10 100 500

Figure 22. Output Balance vs. Frequency

10

∆

V

/∆V

OUT, dm

0
–10
–20
–30
–40
–50

PSRR (dB)

–60
–70
–80
–90

–100

0.1 1 10 100 1000

S

PSRR–

PSRR–

FREQUENCY (MHz)

Figure 23. Power Supply Rejection Ratio vs. Frequency

04769-0-021

VS = +5V

04769-0-034

04769-0-022

Rev. 0 | Page 9 of 16

AD8133

–40

–50

–60

–70

–80

ISOLATION (dB)

–90

–100

–110

1 10 100 1000

Figure 24. Amplifier-to-Amplifier Isolation vs. Frequency

–20

–30

–40

AMPLIFIER A TO
AMPLIFIER B

∆

V

B/∆V

OUT, dm

∆

V

= 200mV p-p

OCM

V

IN, dm

A

IN, dm

FREQUENCY (MHz)

= 200mV p-p

V

IN, dm

= 2V p-p

04769-0-015

30

29

28

27

26
25

24

23

22

POWER SUPPLY CURRENT (mA)

21
20

–40–30–10103050708

VS = ±5V

VS = +5V

TEMPERATURE (°C)

Figure 27. Power Supply Current vs. Temperature

1.5

1.0

0.5

VS = +5V

VS = ±5V

V

OUT, cm

= 2V p-p

04769-0-025

5

–50

∆

V

/∆V

CMRR (dB)

OCM

V

GAIN (dB)

OUT, dm

–60

–70

–80

1 10 100 1000

2

∆

V

OUT, cm

1

0
–1
–2
–3

–4
–5
–6
–7
–8

V

OUT, cm

–9

V

OUT, cm

–10

1 10 100 1000

OCM

Figure 25 V

Figure 26. V

OCM

/∆V

OCM

= 100mV p-p

TAKEN SINGLE ENDED

OCM

FREQUENCY (MHz)

CMRR vs. Frequency

VS = +5V

FREQUENCY (MHz)

Frequ ency Response for

Various Power Supply Voltages

VS = ±5V

04769-0-019

04769-0-013

(V)

0

OCM

V

–0.5

–1.0

–1.5

Figure 28. V

Large Signal Transient Response

OCM

5ns/DIV

04769-0-005

for Various Power Supply Voltages

1.0

0.8

0.6

0.4

0.2

0

–0.2

BIAS CURRENT (mA)

–0.4

OCM

V

–0.6
–0.8
–1.0

–5 –4 –3 –2 0–1 43215

Figure 29. V

V

INPUT VOLTAGE

OCM

Bias Current vs. V

OCM

Input Voltage

OCM

04769-0-012

Rev. 0 | Page 10 of 16

AD8133

4.5

3.5

2.5

1.5

0.5

–0.5

–1.5

–2.5

–3.5

–4.5

±5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V)

VS = +5V VS = ±5V

100 1000 10000

LOAD (Ω)

Figure 30. Output Saturation Voltage vs. Single-Ended Output Load

4.0

5

4

3

2

1

0

04769-0-031

+5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V)

100

)

Ω

10

1

OUTPUT IMPEDANCE (

0.1

0.01 0.1 1 10 100 1000

VS = ±5V

VS = +5V

FREQUENCY (MHz)

Figure 32. Single-Ended Output Impedance Magnitude vs. Frequency

–1.0

1.5

04769-0-026

3.5

3.0

2.5

2.0

1.5

±5V SINGLE-ENDED OUTPUT VOLTAGE (V)

1.0
–40 –25 –5 15 35 55 75 85

VS = ±5V

VS = +5V

TEMPERATURE (°C)

Figure 31. Positive Output Saturation Voltage vs. Temperature

5.0

4.5

4.0

3.5

04769-0-032

+5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V)

–1.5

–2.0

–2.5

–3.0

±5V SINGLE-ENDED OUTPUT VOLTAGE (V)

–3.5

–40 –25 –5 15 35 55 75 85

VS = +5V

VS = ±5V

TEMPERATURE (°C)

1.0

0.5

0

+5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V)

04769-0-033

Figure 33. Negative Output Saturation Voltage vs. Temperature

Rev. 0 | Page 11 of 16

AD8133

(

)

+

V

THEORY OF OPERATION

Each differential driver in the AD8133 differs from a conven­tional op amp in that it has two outputs whose voltages move in
opposite directions. Like an op amp, it relies on high open-loop
gain and negative feedback to force these outputs to the desired
voltages. The AD8133 drivers make it easy to perform single­ended-to-differential conversion, common-mode level shifting,
and amplification of differential signals.

Previous differential drivers, both discrete and integrated
designs, have been based on using two independent amplifiers
and two independent feedback loops, one to control each of the
outputs. When these circuits are driven from a single-ended
source, the resulting outputs are typically not well balanced.
Achieving a balanced output has typically required exceptional
matching of the amplifiers and feedback networks.

DC common-mode level shifting has also been difficult with
previous differential drivers. Level shifting has required the use
of a third amplifier and feedback loop to control the output
common-mode level. Sometimes, the third amplifier has also
been used to attempt to correct an inherently unbalanced
circuit. Excellent performance over a wide frequency range has
proven difficult with this approach.

Each of the AD8133 drivers uses two feedback loops to
separately control the differential and common-mode output
voltages. The differential feedback, set by the internal resistors,
controls only the differential output voltage. The internal
common-mode feedback loop controls only the common-mode
output voltage. This architecture makes it easy to arbitrarily set
the output common-mode level by simply applying a voltage to
the V
internal common-mode feedback, to equal the voltage applied to
the V

The AD8133 architecture results in outputs that are highly
balanced over a wide frequency range without requiring exter­nal components or adjustments. The common-mode feedback
loop forces the signal component of the output common-mode
voltage to be zeroed. The result is nearly perfectly balanced dif­ferential outputs of identical amplitude that are exactly 180°
apart in phase.

DEFINITION OF TERMS

Differential Voltage
Differential voltage refers to the difference between two node
voltages that are balanced with respect to each other. For exam­ple, in Figure 34 the output differential voltage (or equivalently
output differential mode voltage) is defined as

input. The output common-mode voltage is forced, by

OCM

input, without affecting the differential output voltage.

OCM

VVV −=

dmOUT

,

ONOP

Common-mode voltage refers to the average of two node volt­ages with respect to a common reference. The output common­mode voltage is defined as

VV

)(

ONOP

V

=

,

cmOUT

2

Output Balance

Output balance is a measure of how well the differential output
signals are matched in amplitude and how close they are to
exactly 180° apart in phase. Balance is most easily determined
by placing a well-matched resistor divider between the differen­tial output voltage nodes and comparing the magnitude of the
signal at the divider’s midpoint with the magnitude of the d

if­ferential signal. By this definition, output balance error is the
magnitude of the change in output common-mode voltage
divided by the magnitude of the change in output differential­mode voltage in response to a differential input signal.

V

∆

cmOUT

,

ErrorBalanceOutput

=

V

∆

dmOUT

,

ANALYZING AN APPLICATION CIRCUIT

The AD8133 uses high open-loop gain and negative feedback to
force its differential and common-mode output voltages to
minimize the differential and common-mode input error
voltages. The differential input error voltage is defined as the
voltage between the differential inputs labeled V

and VAN in

AP

Figure 34. For most purposes, this voltage can be assumed to be
zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to V

can also

OCM

be assumed to be zero. Starting from these two assumptions, any
application circuit can be analyzed.

CLOSED-LOOP GAIN

The differential mode gain of the circuit in Figure 34 can be
described by the following equation.

V

where R

OUT,dm

V

IN,dm

F

IN, dm

R

F

2==

R

G

= 1.5 kΩ and RG = 750 Ω nominally.

R

F

V

R

AP

V

+

V

OCM

V

–

G

IP

IN

V

R

AN

G

R

F

Figure 34.

R

L, dm

V

ON

V

OUT, dm

V

OP

04769-0-003

Rev. 0 | Page 12 of 16

AD8133

W

CALCULATING AN APPLICATION CIRCUIT’S INPUT IMPEDANCE

The effective input impedance of a circuit such as that in
Figure 34 at V

and VIN depends on whether the amplifier is

IP

being driven by a single-ended or differential signal source. For
balanced differential input signals, the differential input imped­ance, R

In the case of a single-ended input signal (for example, if V
grounded and the input signal is applied to V

, between t he inputs VIP and VIN is simply

IN, dm

dmIN,

RR

kΩ1.52 =×=

G

), the input

IP

is

IN

impedance becomes:

⎛
⎜

⎜

=

R

dmIN,

⎜
⎜

⎝

R

G

R

−

1

()

2

⎞
⎟

⎟
⎟

F

⎟

+×

RR

F

G

⎠

kΩ125.1

=

The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because
a fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor R

.

G

INPUT COMMON-MODE VOLTAGE RANGE IN SINGLE­SUPPLY APPLICATIONS

The inputs of the AD8133 are designed to facilitate level­shifting of ground referenced input signals on a single power
supply. For a single-ended input, this would imply, for example,
that the voltage at V
amplifier’s negative power supply voltage was also set to 0 V.

It is important to ensure that the common-mode voltage at the
amplifier inputs, V
Since voltages V
negative feedback, the amplifier’s input common-mode voltage
can be expressed as a single term, V
as follows

=

ACM

where V

ICM

is the common-mode voltage of the input signal, i.e.,

ICM

= .

2

in Figure 34 would be 0 V when the

IN

and VAN, stays within its specified range.

AP

and VAN are driven to be essentially equal by

AP

. V

ACM

VVV+

2

ICMOCM

3

VVV+

INIP

can be calculated

ACM

DRIVING A CAPACITIVE LOAD

A purely capacitive load can react with the output
impedance of the AD8133 to reduce phase margin, resulting in
high frequency ringing in the pulse response. The best way to
minimize this effect is to place a small resistor in series with
each of the amplifier’s outputs to buffer the load capacitance.

OUTPUT PULL-DOWN (OPD)

The AD8133 has an OPD pin that when pulled high signifi­cantly reduces the power consumed while simultaneously
pulling the outputs to within less than 1 V of V

when used

S−

with series diodes (see the Applications section). The equivalent
schematic of the output pull-down circuit is shown in Figure 35.
(The ESD diodes shown in Figure 35 are for ESD protection and
are distinct from the series diodes used with the output pull­down feature.) See Figure 18 and Figure 21 for the output
pull-down transient and isolation performance plots. The
threshold levels for the OPD pin are referenced to the positive
power supply voltage and are presented in the Specifications
tables. When the OPD pin is pulled high, the AD8133 enters the
output low disable state.

V

V

S+

OUT

ESD
DIODE

04769-0-004

V

CC

PULLDOWN
(OUTPUT IS

PULLED DOWN

HEN SWITCH

IS CLOSED)

Figure 35. Output Pull-Down Equivalent Circuit

ESD

DIODE

V

S–

OUTPUT COMMON-MODE CONTROL

The AD8133 allows the user to control each of the three
common-mode output levels independently through the three
V

input pins. The V

OCM

mode output level of each of their respective amplifiers with
330 MHz of small signal bandwidth and an internally fixed
gain of one. In this way, additional control and communication
signals can be embedded on the common-mode levels as the
user sees fit.

With no external circuitry, the level at the V
amplifier defaults to approximately midsupply. An internal
resistive divider with an impedance of approximately 100 kΩ
sets this level. To limit common-mode noise in dc common­mode applications, external bypass capacitors should be
connected from each of the V

pins pass a signal to the common-

OCM

input of each

OCM

input pins to ground.

OCM

Rev. 0 | Page 13 of 16

AD8133

APPLICATIONS

DRIVING RGB VIDEO SIGNALS OVER CATEGORY-5 UTP CABLE

The foremost application of the AD8133 is driving RGB video
signals over UTP cable in KVM networks. Single-ended video
signals are easily converted to differential signals for
transmission over the cable, and the internally fixed gain of 2
automatically compensates for the losses incurred by the source
and load terminations. The common topologies used in KVM
networks, such as daisy -chained, star, and point-to-point, are
supported by the AD8133. Figure 36 shows the AD8133 in a
triple single-ended-to-differential application when driven from
a 75 Ω source, which is typical of how RGB video is driven over
an UTP cable. In applications that use the OPD feature, the
Schottky diodes are placed in series with each of the 49.9 Ω
resistors in the outputs.

+5V

0.1µF ON ALL VS+ PINS

V

S+

AD8133

1.5kΩ

75Ω

VIDEO

SOURCE A

75Ω

VIDEO

SOURCE B

75Ω

VIDEO

SOURCE C

OUTPUT

PULLDOWN

80.6Ω

80.6Ω

80.6Ω

38.3Ω

38.3Ω

38.3Ω

+2.5V

+2.5V

+2.5V

750Ω

750Ω

750Ω

750Ω

750Ω

750Ω

OPD

V

A

OCM

1.5kΩ

1.5k

V

B

OCM

1.5kΩ

1.5kΩ

V

C

OCM

1.5kΩ

V

S–

49.9Ω

49.9Ω

49.9Ω

49.9Ω

49.9Ω

49.9Ω

–
OUT A
+

–
OUT B
+

–
OUT C
+

04769-0-002

Figure 36. AD8133 in Single-Ended-to-Differential Application

Rev. 0 | Page 14 of 16

AD8133

OUTPUT PULL-DOWN

The output pull-down feature, when used in conjunction with
series Schottky diodes, offers a convenient means to connect a
number of AD8133 outputs together to form a video network.
The OPD pin is a binary input that controls the state of the
AD8133 outputs. Its binary input level is referenced to the most
positive power supply (see the Specifications tables for the logic
levels). When the OPD input is driven to its low state, the
AD8133 output is enabled and operates in its normal fashion. In
this state, the V
on the series diodes, allowing the AD8133 to transmit signals
over the network. When the OPD input is driven to its high
state, the outputs of the AD8133 are forced to a low voltage,
irrespective of the level on the V
series diodes and thus presenting high impedance to the net­work. This feature allows a three-state output to be realized that
maintains its high impedance state even when the AD8133 is
not powered. This condition can occur in KVM networks where
the AD8133s do not all reside in the same module, and some
modules in the network are not powered.

It is recommended that the output pull-down feature only be
used in conjunction with series diodes in such a way as to
ensure that the diodes are reverse-biased when the output pull­down feature is asserted, since some loading conditions can
prevent the output voltage from being pulled all the way down.

input can be used to provide a positive bias

OCM

input, reverse-biasing the

OCM

KVM NETWORKS

In daisy-chained KVM networks, the drivers are distributed
along one cable and a triple receiver is located at one end.
Schottky diodes in series with the driver outputs are biased such
that the one driver that is transmitting video signals has its
diodes forward-biased and the disabled drivers have their
diodes reverse-biased. The output common-mode voltage, set
by the V
the output pull-down feature is asserted, the differential outputs
are pulled to a low voltage, reverse-biasing the diodes.

In star networks, all cables radiate out from a central hub,
which contains a triple receiver. The series diodes are all located
at the receiver in the star network. Only one ray of the star is
transmitting at a given time, and all others are isolated by the
reverse-biased diodes. Diode biasing is controlled in the same
way as in the daisy-chained network.

input, supplies the forward-biased voltage. When

OCM

In the daisy-chained and star networks that use diodes for isola­tion, return paths are required for the common-mode currents
that flow through the series diodes. A common-mode tap can
be implemented at each receiver by splitting the100 Ω termina­tion resistor into two 50 Ω resistors in series. The diode currents
are routed from the tap between the 50 Ω resistors back to the
respective transmitters over one of the wires of the fourth
twisted pair in the UTP cable. Series resistors in the common-mode
return path are generally required to set the desired diode current.

In point-to-point networks, there is one transmitter and one
receiver per cable, and the switching is generally implemented
with a crosspoint switch. In this case, there is no need to use
diodes or the output pull-down feature.

Diode and crosspoint switching are by no means the only type
of switching that can be used with the AD8133. Many other
types of mechanical, electromechanical, and electronic switches
can be used.

LAYOUT AND POWER SUPPLY DECOUPLING CONSIDERATIONS

Standard high speed PCB layout practices should be adhered to
when designing with the AD8133. A solid ground plane is
recommended and good wideband power supply decoupling
networks should be placed as close as possible to the supply
pins. Small surface-mount ceramic capacitors are recommended
for these networks, and tantalum capacitors are recommended
for bulk supply decoupling.

AMPLIFIER-TO-AMPLIFIER ISOLATION

The least amount of isolation between the three amplifiers
exists between Amplifier A and Amplifier B. This is therefore
viewed as the worst-case isolation and is what is reflected in the
Specifications tables and Typical Performance Characteristics.
Refer to the Basic Test Circuit shown in Figure 5 for the test
conditions.

EXPOSED PADDLE (EP)

The LFCSP-24 package has an exposed paddle on the underside
of its body. In order to achieve the specified thermal resistance,
it must have a good thermal connection to one of the PCB
planes. The exposed paddle must be soldered to a pad on the
top of the board that is connected to an inner plane with several
thermal vias.

Rev. 0 | Page 15 of 16

AD8133

OUTLINE DIMENSIONS

0.08

0.60 MAX

19

18

BOTTOM

13

12

VIEW

24

7

1

6

2.50 REF

PIN 1
INDICATOR

2.25

2.10 SQ

1.95

0.25 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING
PLANE

12° MAX

4.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65TYP

COMPLIANT TOJEDECSTANDARDSMO-220-VGGD-2

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

Figure 37. 24-Lead Lead Frame Chip Scale Package [LFCSP],

4 mm× 4 mm (CP-24)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Package Package Description Package Outline

AD8133ACP-REEL −40°C to +85°C 24-Lead LFCSP CP-24
AD8133ACP-REEL7 −40°C to +85°C 24-Lead LFCSP CP-24
AD8133ACPZ-REEL
AD8133ACPZ-REEL71 −40°C to +85°C 24-Lead LFCSP CP-24

1

Z = Pb-free part.

1

−40°C to +85°C 24-Lead LFCSP CP-24

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis­tered trademarks are the property of their respective owners.

D04769–0–7/04(0)

Rev. 0 | Page 16 of 16