Page 1
CAT-5 Receiver with
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FEATURES
Tuned to compensate for Category-5 (CAT-5) cable losses
Up to 100 meters @ 120 MHz
2 voltage-controlled frequency response adjustment pins
High frequency peaking adjustment
Broadband gain adjustment
2700 V/μs slew rate
Low output noise
1.5 mV rms integrated noise (1 GHz) @ 100 meters
zed bandwidth
equali
DC output offset adjust
Low offset voltage error: 7 mV typ
Equalized pass-band ripple ±1 dB to 70 MHz
Input: differential or single ended
Supply current: 24 mA on ±5 V
Small 8-lead 3 mm × 3 mm LFCSP
APPLICATIONS
Keyboard-video-mouse (KVM)
RGB video over unshielded twisted pair (UTP) cable receivers
Professional video projection and distribution
Security video
Adjustable Line Equalization
AD8128
FUNCTIONAL BLOCK DIAGRAM
V
OFFSET
AD8128
V
OUT
05699-001
HPF
V
IN+
V
PEAK
V
HPF
LPF
GAIN
Figure 1.
V
IN–
GENERAL DESCRIPTION
The AD8128 is a high speed, differential receiver/equalizer that
compensates for the transmission losses of unshielded twisted
pair (UTP) CAT-5 cables. Various frequency dependent gain
stages are summed together to best approximate the inverse
frequency response of CAT-5/CAT-5e cable. An equalized
bandwidth of 120 MHz can be achieved for 100 meters of cable.
The AD8128 can be used as a standalone receiver/equalizer or
in con
junction with the AD8143, triple differential receiver, to
provide a complete low cost solution for receiving RGB over
UTP cable in such applications as KVM.
The AD8128 has three control pins for optimal CAT-5/CAT-5e
co
mpensation. The equalized cable length is directly proportional
to the voltage applied to the V
amount of high frequency peaking. V
gain from 0 dB to 3 dB, compensating for the resistive cable
loss. V
allows the output to be shifted by ±2.5 V, adding
OFFSET
flexibility for dc-coupled systems.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
pin, which controls the
PEAK
adjusts the broadband
GAIN
Low integrated output noise and offset voltage adjust make the
AD8128 a
n excellent choice for dc-coupled wideband RGBover-CAT-5 applications. For systems where the UTP cable is
longer than 100 meters, two AD8128s can be cascaded to
compensate for up to 200 meters of CAT-5/CAT-5e.
The AD8128 is available in a 3 mm × 3 mm 8-lead LFCSP and
ted to operate over the extended temperature range of
is ra
−40°C to +85°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
Page 2
AD8128
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation .........................................................................9
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Test Cir c ui t .................................................................................... 8
REVISION HISTORY
10/05—Revision 0: Initial Version
Input Common-Mode Voltage Range Considerations ............9
Applications..................................................................................... 10
KVM Applications ..................................................................... 10
DC Control Pins......................................................................... 10
Cascaded Applications............................................................... 11
Exposed Pad (EP)....................................................................... 11
Layout and Power Supply Decoupling Considerations......... 11
Evaluation Boards ...................................................................... 11
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 12
Rev. 0 | Page 2 of 12
Page 3
AD8128
www.BDTIC.com/ADI
SPECIFICATIONS
TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable, V
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Large Signal Bandwidth V
±1 dB Equalized Bandwidth Flatness V
Rise/Fall Time V
Rise/Fall Time V
Settling Time to 2% V
Settling Time to 2% V
Integrated Output Voltage Noise V
DC PERFORMANCE
Input Bias Current 15.5 24 μA
V
Pin Current 1.7 8.2 μA
OFFSET
V
Pin Current 2 3.4 μA
GAIN
V
Pin Current 4.2 6.8 μA
PEAK
INPUT CHARACTERISTICS
Input Differential Voltage ±2.8 V
Input Common-Mode Voltage ±3.0 V
Input Resistance Common mode 380 kΩ
Differential 675 kΩ
Input Capacitance 1.7 pF
Common-Mode Rejection Ratio (CMRR) 200 kHz, ΔV
ADJUSTMENT PINS
V
Input Voltage Relative to ground 0 1 V
PEAK
Maximum Peak Gain @ 120 MHz, V
V
Input Relative to ground 0 1 V
GAIN
Maximum Broadband Gain V
V
Input Range Relative to ground ±2.5 V
OFFSET
V
to V
OFFSET
OUT
Gain
OUTPUT CHARACTERISTICS
Output Voltage Swing −2.55 +2.7 V
Output Offset Voltage V
Output Offset Voltage Drift −5.5 μV/°C
Short-Circuit Output Current 100 mA
POWER SUPPLY
Operating Voltage Range ±4.5 ±5.5 V
Quiescent Supply Current, ICC/I
Supply Current Drift, ICC/I
EE
EE
+Power Supply Rejection Ratio (PSRR) RTO −48 −59 dB
−Power Supply Rejection Ratio (PSRR) RTO −48 −61 dB
TEMPERATURE RANGE −40 +85 °C
= 0 V, V
OFFSET
= 2 V p-p, 100 meter CAT-5 120 MHz
OUT
= 2 V p-p 70 MHz
OUT
= 2 V step, 50 meter CAT-5 2 ns
OUT
= 2 V step, 100 meter CAT-5 3.6 ns
OUT
= 2 V step, 50 meter CAT-5 26 ns
OUT
= 2 V step, 100 meter CAT-5 36.4 ns
OUT
= 0.9 V, V
PEAK
= 1 V 3 dB
GAIN
= 0 V, RTO −10.9 +7 +18.7 mV
OFFSET
and V
GAIN
= 225 mV, BW = 1 GHz 1.5 mV rms
GAIN
/ΔV
OUT
IN, cm
= 1 V 20 dB
PEAK
set to optimized settings (see Figure 4), unless otherwise noted.
PEAK
−63 −74 dB
1 V/V
@ ±5 V +24/−21 +31/−27 mA
+86/−77 μA/°C
Rev. 0 | Page 3 of 12
Page 4
AD8128
A
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±5.5 V
Input Voltage ±V
V
V
PEAK
OFFSET
and V
Control Pins −3 V to +V
GAIN
Control Pins ±V
S
S
S
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θ
JA
8-Lead LFCSP 77 14 °C/W
Maximum Power Dissipation
θ
JC
Unit
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for the output. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
drive depends upon the particular application. For each output,
the power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the
Airflow increases heat dissipation, effectively reducing θ
more metal directly in contact with the package leads from
metal traces, through-holes, ground, and power planes reduces
the θ
. The exposed paddle on the underside of the package
JA
must be soldered to a pad on the PCB surface, which is
thermally connected to a copper plane to achieve the specified θ
Figure 2 shows the maximum safe power dissipation in the
ackage vs. the ambient temperature for the 8-lead LFCSP
p
(48.5°C/W) on a JEDEC standard 4-layer board with the
underside paddle soldered to a pad that is thermally connected
to a PCB plane. Extra thermal relief is required for operation at
high supply voltages.
3.0
2.5
TION (W)
2.0
1.5
The maximum safe power dissipation in the AD8128 package is
limited by the associated rise in junction temperature (T
) on
J
1.0
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even
0.5
MAXIMUM POWER DISSIP
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the AD8128. Exceeding a
junction temperature of 150°C for an extended period can
0
–30–40 –10–20 1003020 5040 7060 9080 110100 130120
Figure 2. Maximum Power Dissipation vs. Temperature
result in changes in the silicon devices potentially causing
failure.
). The power dissipated due to the load
S
AMBIENT T EMPERATURE (°C)
) is the sum of the
D
) times the
S
. Also,
JA
.
JA
05699-020
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 4 of 12
Page 5
AD8128
V
www.BDTIC.com/ADI
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
1V
IN+
IN–
GAIN
PEAK
INDICATOR
2V
AD8128
3V
TOP VIEW
(Not to Scale)
4
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
2 V
3 V
4 V
IN+
IN−
GAIN
PEAK
Positive Equalizer Input
Negative Equalizer Input
0 V to 1 V Broadband Gain Control
0 V to 1 V High Frequency Gain Control
5 VS− Negative Power Supply
6 V
7 V
OUT
OFFSET
Equalizer Output
DC Offset Adjust
8 VS+ Positive Power Supply
EP GND Ground Reference and Thermal Pad (see Exposed Pad (EP) section).
8VS+
7V
OFFSET
6V
OUT
5VS–
05699-002
Rev. 0 | Page 5 of 12
Page 6
AD8128
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable, V
1.0
V
=2Vp-p
OUT
0.9
R
= 150
L
0.8
(V)
0.7
GAIN
0.6
AND V
0.5
PEAK
0.4
0.3
0.2
OPTIMIZED V
0.1
0
0 100
10 20 30 40 50 60 70 80 90
CABLE LENG TH (M)
Figure 4. V
30
20
10
0
–10
–20
–30
MAGNITUDE (dB)
–40
–50
–60
–70
0.1
and V
PEAK
1 10 100 1k 3k
Settings vs. Cable Length
GAIN
V
=0.5V
PEAK
FREQUENC Y (MHz)
Figure 5. Frequency Response for Various V
10
0
–10
–20
–30
–40
MAGNITUDE (dB)
–50
–60
–70
0.1
1 10 100 1k 3k
V
GAIN
V
GAIN
FREQUENCY (MHz)
Figure 6. Frequency Response for Various V
V
PEAK
V
GAIN
V
=1V
PEAK
V
=0V
PEAK
Settings Without Cable
PEAK
=1V
=0V
Settings Without Cable
GAIN
= 0 V, unless otherwise noted.
OFFSET
05699-003
05699-014
V
=0.5V
GAIN
05699-013
2
1
0
–1
–2
–3
–4
–5
MAGNITUDE (d B)
–6
–7
V
AND V
PEAK
–8
WITH OPTIMIZED SETTINGS IN FIGURE 4
=2Vp-p
V
OUT
–9
R
= 150
L
–10
0.1
Figure 7. Equalized Frequency Response fo
2
1
0
–1
–2
–3
–4
–5
MAGNITUDE (dB)
–6
–7
V
AND V
PEAK
–8
WITH OPTIMIZED SETTINGS IN FIGURE 4
=2Vp-p
V
OUT
–9
R
= 150
L
–10
0.1
Figure 8. Equalized Frequency Response fo
1.5
1.0
0.5
0
OUTPUT (V)
–0.5
–1.0
–1.5
20 40 60 80 100 120 140 160 180
0 200
SETTINGS ARE CONSISTENT
GAIN
1 10 100 300
FREQUENCY (MHz)
r 50 M Cable
SETTINGS ARE CONSISTENT
GAIN
1 10 100 300
FREQUENCY (MHz)
r 100 M Cable
V
AND V
PEAK
CONSISTENT WITH OPTIMIZED
SETTINGS IN FIGURE 4
TIME (ns)
SETTINGS ARE
GAIN
Figure 9. Equalized Pulse Response for 50 M of Cable
05699-012
05699-011
05699-010
Rev. 0 | Page 6 of 12
Page 7
AD8128
R
www.BDTIC.com/ADI
1.5
1.0
V
AND V
0.5
0
OUTPUT (V)
–0.5
–1.0
–1.5
20 40 60 80 100 120 140 160 180
0 200
PEAK
CONSISTENT WITH OPTIMIZED
SETTINGS IN FIGURE 4
TIME (ns)
SETTINGS ARE
GAIN
Figure 10. Equalized Pulse Response for 100 M of Cable
40
30
20
10
(mV)
0
OUT
V
–10
–20
–30
–40
–4
–3 –2 –1 0 1 2 3
V
(V)
IN, CM
Figure 11. Output Voltage vs. Common-Mode Input Voltage
100
V
=0.9V
PEAK
V
= 0.225V
GAIN
V
=0V
PEAK
V
=0V
GAIN
VOLTAGE NOISE (nV/ Hz)
10
0.1 1k
1 10 100
FREQUENCY (MHz)
Figure 12. Voltage Noise vs. Frequency
05699-009
05699-008
4
05699-007
1.8
1.6
1.4
1.2
1.0
0.8
1GHz (mV )
0.6
V
SETTI NGS ARE CONSISTENT
0.4
ATED VOLTAGE NOISE FROM 100kHz TO
0.2
INTEG
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0. 7 0. 8 0. 9
Figure 13. Integrated Voltage Noise vs. V
6
V
=0V
PEAK
V
=0V
GAIN
4
2
0
VOLTAGE (V)
–2
–4
–6
0 500
50 100 150 200 250 300 350 400 450
20
10
0
–10
–20
–30
–40
–50
–60
COMMON- MODE REJECTION (dB)
–70
–80
V
V
0.1 1k
GAIN
WITH OPTIMIZED SETTINGS IN FIGURE 4
V
(V)
PEAK
OUTPUT
INPUT
TIME (ns)
Figure 14. Overdrive R
=1V
GAIN
=1V
PEAK
1 10 100
FREQUENCY (MHz)
ecovery Time
V
=0V
GAIN
V
=0V
PEAK
PEAK
Figure 15. Common-Mode Rejection vs. Frequency
05699-006
1.0
05699-005
05699-004
Rev. 0 | Page 7 of 12
Page 8
AD8128
R
VS+VS–
V
www.BDTIC.com/ADI
–10
10
0
VOS=0V
V
PEAK
=0V
V
GAIN
=0V
+PSR
–20
–30
–40
SUPPLY REJECTION (dB)
–50
POWE
–60
–70
0.001 1k
Figure 16. Power Supply R
TEST CIRCUIT
–PSR
0.01 0.1 1 10 100
FREQUENCY (MHz)
ejection vs. Frequency
1µF
CAT-5
0.01µF
50
V
V
VS–
VS+
IN+
IN–
05699-015
S+
+
V
PEAK
LPF
HPF
HPF
V
GAIN
AD8128
V
OFFSET
V
OUT
10µF 10µF
50
+
VS–
1µF 0.01µF
V
PEAK
0.01µF 0. 01µF 0.01µF
V
GAIN
V
OFFSET
Figure 17.
05699-021
Rev. 0 | Page 8 of 12
Page 9
AD8128
www.BDTIC.com/ADI
THEORY OF OPERATION
The AD8128 is a high speed, low noise analog line equalizer
that compensates for losses in CAT-5/CAT-5e cables up to
100 meters with ±1 dB flatness in the pass band out to 70 MHz
(see
Figure 8). Two continuously adjustable control voltages
ter the frequency response to add flexibility to the system by
al
allowing for the compensation of various cable lengths as well
as for variations in the cable itself. The dc control voltage pin
V
adjusts ac broadband gain from 0 dB to 3 dB (see Figure 6) to
GAIN
account for dc resistive losses present in the cable. A second dc
control voltage pin V
peaking (see Figure 5) from 0 dB to 20 dB. This compensates
f
or the high frequency loss due to the skin effect of the cable.
The AD8128 has a high impedance differential input that allows
t to receive dc-coupled signals directly from the cable. For
i
systems with very high CMRR specifications, the AD8128 can
also be used with a dedicated receiver, such as the AD8130 or
AD8143, p
impedance and is capable of driving a 150 Ω load resistor and
up to 20 pF of load capacitance at its output. For systems with
high parasitic capacitances at the output, it is recommended
that a small series resistor be placed between the output and
capacitive load to reduce ringing in the pulse response.
The AD8128 is designed to be used in medium-length systems
hat have stringent low noise requirements as well as longer-
t
length systems that can tolerate more noise. For the mediumlength requirements, a single AD8128 is able to compensate up
to 100 meters of cable with only 1.5 mV rms of output noise.
For longer-length applications that require equalization of up to
200 meters of cable, two AD8128s can be cascaded together to
achieve the desired equalization, while keeping approximately
the same pass-band bandwidth, but with a slight degradation in
settling time and slew rate.
laced in front of it. The output of the AD8128 is low
adjusts the amount of high frequency
PEAK
The AD8128 approximates the magnitude response of
E
quation 1 by summing multiple zero-poles pairs offset at
different frequencies. Equalization adjustment due to varying
line lengths is done by changing the weighting factors of each of
the zero-pole pairs.
INPUT COMMON-MODE VOLTAGE RANGE CONSIDERATIONS
When using the AD8128 as a receiver, it is important to ensure
that the input common-mode (CM) voltage range of the AD8128
stays within the specified range. The input CM level can be
easily calculated by adding the CM level of the driver, the
amplitude of any sync pulses, and the other possible induced
common-mode signals from power lines and fluorescent lights.
V
= VCM + V
ICM
For example, when using a single 5 V supply on the drive side,
t
he CM voltage of the line typically becomes the midsupply
voltage, V
V
SYNC
voltage at 3 V. Assuming that both the driver and receiver have
exactly the same ground potential, the signal is marginally
below the upper end of the common-mode input range of 3.1 V.
Other CM signals that can be picked up by the CAT-5 cable
result in exceeding the CM input range of the AD8128.
The most effective way of not exceeding the CM level of the
AD8128 is t
example, this was the primary contributor to the CM input
level. If this is not possible, a dedicated receiver with a wider
CM input range, such as the AD8130 or AD8143, should be used.
= 2.5 V. Furthermore, an addition of a sync signal,
CM
= 0.5 V, on to the common mode puts the peak CM
o lower the CM level on the driver. In the previous
SYNC
+ V
OTHER
(2)
The frequency response of the AD8128 approximates the
i
nverse frequency response of a lossy transmission line, which
is given by
()
fjkl
()
where:
he frequency.
f is t
s the length.
l i
s the line constant.
k i
1
efH+=
(1)
Rev. 0 | Page 9 of 12
Page 10
AD8128
V
V
www.BDTIC.com/ADI
APPLICATIONS
KVM APPLICATIONS
In KVM applications, cable equalization typically occurs at the
root of the KVM network. In a star configuration, a driver is
located at each of the end nodes and a receiver/equalizer is
located at the single root node. In a daisy-chain configuration,
each of the end nodes are connected to one another, and one of
them is connected to the root. Similarly, the drivers are placed
on the nodes, and the receivers/equalizers are placed at the root.
In both of these aforementioned configurations, three AD8128
eceiver/equalizers can be used at the root node to equalize the
r
transmitted red (R), green (G), and blue (B) channels for up to
100 meters of cable. Since the skew between two pairs of cables
in CAT-5 is less than 1%, the control pins can be tied together
and used as a single set of controls.
If the common-mode levels of the inputs permit using the
AD8128 as a r
ange Considerations section), the input signal should be
R
t
erminated by a 100 Ω shunt resistor between the pairs, or by
two 50 Ω shunt resistors with a common-mode tap in the
middle. This CM tap can be used to extract the sync information
from the signal if sync-on-common-mode is used.
CAT-5
eceiver (see the Input Common-Mode Voltage
V
PEAK
LPF
V
HPF
HPF
GAIN
V
DIFF
V
CM
50
50
V
CM
V
DIFF
Figure 18. Single Receiver Configuration for CAT-5 Equalizer
V
IN+
V
CM
V
IN–
V
OFFSET
AD8128
V
OUT
05699-016
While these equations give a close approximation of the desired
ue for each pin, to achieve optimal performance, it may be
val
necessary to adjust these values slightly.
Figure 19 and Figure 20 illustrate circuits used to adjust the
ntrol pins on the AD8128. In Figure 19, a 1 kΩ potentiometer
co
i
s used to adjust the control pin voltage between the specified
range of 0 V to 1 V. In Figure 20, a 2 kΩ potentiometer is used
o control the offset pin from −2.5 V to +2.5 V. For both of these
t
configurations, a ±5V supply is assumed.
+5
4k
0.01µF
0.01µF
CONTROL PIN
OR V
V
GAIN
PEAK
and V
GAIN
PEAK
OFFSET
(±2.5 V)
OFFSET
5699-017
(0 V to 1 V)
05699-018
1k
Figure 19. Circuit to Control V
+5
1k
2k
1k
–5V
Figure 20. Circuit to Control V
DC CONTROL PINS
The AD8128 uses two control pins (V
the equalization based on the length of the cable and one pin
(V
) to adjust the dc output offset. V
OFFSET
0 V to 1 V broadband gain control pin, and V
adjustable high frequency gain pin to equalize for the skin effect
in CAT-5 cable. The values of both V
correlated to the length of the cable to be equalized. A simple
formula can be used to approximate the desired values for both
of these pins.
)(mlength
V
=
GAIN
425m/V
= (4)
V
PEAK
110m/V
(3)
)(mlength
and V
GAIN
PEAK
PEAK
is a user-adjustable
GAIN
PEAK
and V
GAIN
) to adjust
is a 0 V to 1 V
are linearly
Rev. 0 | Page 10 of 12
Page 11
AD8128
V
V
V
www.BDTIC.com/ADI
S+
1µF 0.01µF
1µF 0.01µF
V
IN+
V
IN–
VS–
VS+
VS–
V
PEAK
LPF
HPF
HPF
AD8128
V
GAIN
V
OFFSET
Figure 21. Cascaded AD8128 Configuration
1µF 0.01µF
V
OUT
V
OFFSETVGAINVPEAK
S+
VS+
V
IN+
V
IN–
V
PEAK
LPF
HPF
HPF
V
GAIN
AD8128
VS–
V
OFFSET
1µF 0.01µF
V
OUT
VS+
VS–
S–
+
+
05699-019
CASCADED APPLICATIONS
To equalize distances longer than the specified 100 meters, the
AD8128 can be cascaded to provide equalization for longer
distances. When combining two AD8128s in series, it is possible to
link the control pins together and use them like a single control
pin for up to 200 meters of equalization.
In this configuration, it is important to note that some key
ideo specifications can be slightly degraded. By combining two
v
equalizers in series, specifications such as rise time and settling
time both increase while 3 dB bandwidth decreases slightly.
Also, integrated noise is increased because the second equalizer
adds gain. Subjective testing should be done to determine the
appropriate setting for the three control pins for optimum
equalization.
EXPOSED PAD (EP)
The 8-lead LFCSP has an exposed paddle on the underside of
its body. To achieve the specified thermal resistance, it must
have a good thermal connection to one of the PCB planes. The
exposed paddle must be soldered to a pad on top of the board
connected to an inner plane with several thermal vias. For the
AD8128, this pad must also be electrically connected to ground
to provide a ground reference to the part.
LAYOUT AND POWER SUPPLY DECOUPLING CONSIDERATIONS
Standard high speed PCB layout practices should be adhered to
when designing with the AD8128. A solid ground plane is
recommended and good wideband power supply decoupling
networks should be placed as close as possible to the supply
pins and control pins. Small surface-mount ceramic capacitors
are recommended for these networks, and tantalum capacitors
are recommended for bulk supply decoupling.
EVALUATION BOARDS
There are two evaluation boards available for easy characterization
of the AD8128. A general-purpose evaluation board consisting
of a single AD8128, with an option of also using a dedicated
receiver, is available for simple characterization of the part.
Additionally, a KVM application specific evaluation board is
available. This evaluation board consists of six AD8128s to
equalize each of the RGB channels up to 200 meters, a 16-pin
26C32 comparator for sync-on-common-mode extract and a
triple op amp to provide additional gain if necessary.
Rev. 0 | Page 11 of 12
Page 12
AD8128
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
0.50
0.40
0.30
1
4
1.50
REF
PIN 1
INDICATOR
1.89
1.74
1.59
PIN 1
INDICATOR
3.00
BSC SQ
TOP
VIEW
2.75
BSC SQ
0.60 MAX
0.50
BSC
8
5
1.60
1.45
1.30
0.90 MAX
0.85 NOM
SEATING
PLANE
12° MAX
0.70 MAX
0.65 TYP
0.05 MAX
0.01 NOM
0.30
0.23
0.18
Figure 22. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
0.20 REF
3
mm × 3 mm Body, Very Thin, Dual Lead
Dimensions shown in millimeters
(CP-8-2)
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8128ACPZ-R2
AD8128ACPZ-RL
AD8128ACPZ-R7
1
Z = Pb-free part.
1
–40°C to +85°C 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2 HZB
1
–40°C to +85°C 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2 HZB
1
–40°C to +85°C 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2 HZB
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05699-0-10/05(0)
Rev. 0 | Page 12 of 12
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