Datasheet AD8124 Datasheet (ANALOG DEVICES)

Triple Differential Receiver with

V

200 Meter Adjustable Cable Equalization

FEATURES

Compensates cables to 200 meters for wideband video

All resolutions through UXGA

Fast rise and fall times

8 ns with 2 V step @ 200 meters of UTP cable
37 dB peak gain at 100 MHz
Two frequency response gain adjustment pins

High frequency peaking adjustment (V

Broadband flat gain adjustment (V
Pole location adjustment pin (V

POLE

)
Compensates for variations between cables
Can be optimized for either UTP or coaxial cable

DC output offset adjust (V

OFFSET

)
Low output offset voltage: 24 mV
Compensates both RGB and YPbPr
Two on-chip comparators with hysteresis

Can be used for common-mode sync extraction

Available in 40-lead, 6 mm × 6 mm LFCSP

APPLICATIONS

Keyboard-video-mouse (KVM)
Digital signage
RGB video over UTP cables
Professional video projection and distribution
HD video
Security video

GENERAL DESCRIPTION

The AD8124 is a triple, high speed, differential receiver and
equalizer that compensates for the transmission losses of UTP
and coaxial cables up to 200 meters in length. Various gain stages
are summed together to best approximate the inverse frequency
response of the cable. Logic circuitry inside the AD8124 controls
the gain functions of the individual stages so that the lowest
noise can be achieved at short-to-medium cable lengths. This
technique optimizes its performance for low noise, short-to­medium range applications, while at the same time provides
the high gain bandwidth required for longer cable equalization
(up to 200 meters). Each channel features a high impedance
differential input that is ideal for interfacing directly with the cable.

GAIN

)

PEAK

)

AD8124

FUNCTIONAL BLOCK DIAGRAM

PEAKVPOLEVOFFSETVGAIN

AD8124

–IN

R

+IN

R

–IN

G

+IN

G

–

IN

B

+IN

B

–IN

CMP1

+IN

CMP1

–IN

CMP2

+IN

CMP2

Figure 1.

The AD8124 has three control pins for optimal cable
compensation, as well as an output offset adjust pin. Two
voltage-controlled pins are used to compensate for different
cable lengths; the V
peaking and the V

pin controls the amount of high frequency

PEAK

pin adjusts the broadband flat gain, which

GAIN

compensates for the low frequency flat cable loss.

For added flexibility, an optional pole adjustment pin, V
allows movement of the pole locations, allowing for the
compensation of different gauges and types of cable as well
as variations between different cables and/or equalizers. The
V

pin allows the dc voltage at the output to be adjusted,

OFFSET

adding flexibility for dc-coupled systems.

The AD8124 is available in a 6 mm × 6 mm, 40-lead LFCSP
and is rated to operate over the extended temperature range of

−40°C to +85°C.

OUT

OUT

OUT

OUT

OUT

R

G

B

CMP1

CMP2

POLE

09601-001

,

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

AD8124

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

Maximum Power Dissipation..................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Description .............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 10

Input Common-Mode Voltage Range Considerations .........10

Applications Information.............................................................. 11

Basic Operation .......................................................................... 11

Comparators ............................................................................... 11

Sync Pulse Extraction Using Comparators............................. 12

Using the V

PEAK

, V

POLE

, V

GAIN

, and V

Inputs................... 12

OFFSET

Using the AD8124 with Coaxial Cable.................................... 13

Driving 75 Ω Video Cable with the AD8124.......................... 13

Driving a Capacitive Load......................................................... 13

Power Supply Filtering............................................................... 13

Layout and Power Supply Decoupling Considerations......... 14

Power-Down ............................................................................... 14

Outline Dimensions....................................................................... 15

Ordering Guide .......................................................................... 15

REVISION HISTORY

1/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 16

AD8124

SPECIFICATIONS

TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable (BL-7987R), V
Figure 16, unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

10% to 90% Rise/Fall Time V
Settling Time to 2% V
–3 dB Large Signal Bandwidth V
V

= 2 V step, 200 meters Cat-5 8 ns

OUT

= 2 V step, 200 meters Cat-5 47 ns

OUT

= 2 V p-p, <10 meters Cat-5 110 MHz

OUT

= 2 V p-p, 200 meters Cat-5 52 MHz

OUT

Integrated Output Voltage Noise 200 meter setting, integrated to 160 MHz 4 mV rms

INPUT DC PERFORMANCE

Input Voltage Range −IN and +IN ±3.0 V
Maximum Differential Voltage Swing 4 V p-p
Voltage Gain ΔVO/ΔVI, V
Common-Mode Rejection Ratio (CMRR) At dc, V
At dc, V
At 1 MHz, V

GAIN

= V

PEAK

= 1.15 V, V

PEAK

PEAK

Input Resistance Common mode 4.4 MΩ
Differential 3.7 MΩ
Input Capacitance Common mode 1.0 pF
Differential 0.5 pF
Input Bias Current 2.4 μA
V

Pin Current 30 μA

OFFSET

V

Pin Current 0.5 μA

GAIN

V

Pin Current 0.4 μA

PEAK

V

Pin Current 0.4 μA

POLE

ADJUSTMENT PINS

V

Input Voltage Range Relative to GND 0 to 1.5 V

PEAK

V

Input Voltage Range Relative to GND 0 to 1.5 V

POLE

V

Input Voltage Range Relative to GND 0 to 1.5 V

GAIN

V

to OUT Gain OUT/V

OFFSET

Maximum Flat Gain V

GAIN

, range limited by output swing 1 V/V

OFFSET

= 1.5 V 1.9 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing 150 Ω load −3.75 to +3.69 V
1 kΩ load −3.66 to +3.69 V
Output Offset Voltage Referred to output, V

Referred to output, V

= 1.5 V

V

POLE

Output Offset Voltage Drift Referred to output 33 μV/°C

POWER SUPPLY

Operating Voltage Range ±4.5 ±5.5 V
Positive Quiescent Supply Current 132 mA
Negative Quiescent Supply Current 126 mA
Supply Current Drift, ICC/IEE 80 μA/°C
Positive Power Supply Rejection Ratio DC, referred to output −51 dB
Negative Power Supply Rejection Ratio DC, referred to output −63 dB
Power Down, VIH (Minimum) Minimum Logic 1 voltage 1.1 V
Power Down, VIL (Maximum) Maximum Logic 0 voltage 0.8 V
Positive Supply Current, Powered Down V
Negative Supply Current, Powered Down V

PEAK

PEAK

= V
= V

GAIN

GAIN

= V
= V

OFFSET

= 0 V, V

PEAK

, V

GAIN

, and V

are set to recommended settings shown in

POLE

set for 0 meters of cable 1 V/V

= V

GAIN

= 1.15 V, V

POLE

POLE

= 0 V −86 dB

POLE

= 1.4 V, V

GAIN

GAIN

= V

PEAK

= 1.15 V, V

PEAK

= 1.4 V, V

GAIN

= 1.5 V −65 dB

POLE

= 1.5 V −50 dB

POLE

= V

= 0 V 24 mV

POLE

= 1.4 V,

GAIN

37 mV

= 0 V 1.1 μA
= 0 V 0.7 μA

Rev. 0 | Page 3 of 16

AD8124

Parameter Test Conditions/Comments Min Typ Max Unit

COMPARATORS

Output Voltage Levels VOH/V
Hysteresis V
Propagation Delay t
Rise/Fall Times t

OL

HYST

PD, LH/tPD, HL

RISE/tFALL

Output Resistance 0.03 Ω

OPERATING TEMPERATURE RANGE −40 +85 °C

3.33/0.043 V
70 mV

17.5/10.0 ns

9.3/9.3 ns

Rev. 0 | Page 4 of 16

AD8124

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage 11 V
Power Dissipation See Figure 2
Input Voltage (Any Input) VS− − 0.3 V to VS+ + 0.3 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions; that is, θJA is
specified for the device soldered in a circuit board in still air.

voltage difference between the associated power supply and the
output voltage. The total power dissipation due to load currents
is then obtained by taking the sum of the individual power
dissipations. RMS output voltages must be used when dealing
with ac signals.

Airflow reduces θ

. In addition, more metal directly in contact

JA

with the package leads from metal traces, through holes, ground,
and power planes reduces the θ

. The exposed paddle on the

JA

underside of the package must be soldered to a pad on the PCB
surface that is thermally connected to a solid plane (usually the
ground plane) to achieve the specified θ

.

JA

Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 40-lead LFCSP
(29°C/W) on a JEDEC standard 4-layer board with the underside
paddle soldered to a pad that is thermally connected to a PCB
plane. θ

values are approximations.

JA

7

6

5

Table 3. Thermal Resistance with the Underside Pad
Connected to the Plane

Package Type/PCB Type θJA Unit

40-Lead LFCSP/4-Layer 29 °C/W

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8124 package
is limited by the associated rise in junction temperature (T
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8124. Exceeding a junction temperature
of 175°C for an extended time can result in changes in the
silicon devices, potentially causing failure.

The power dissipated in the package (P

) is the sum of the

D

quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I

). The power dissipation due to each load

S

) times the

S

current is calculated by multiplying the load current by the

) on

J

4

3

2

MAXIMUM POWER DISSIPATION (W)

1

0
–40 –20 0 20 40 60 80

AMBIENT TEMPERATURE (°C)

Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

ESD CAUTION

09601-003

Rev. 0 | Page 5 of 16

AD8124

PIN CONFIGURATION AND FUNCTION DESCRIPTION

AD8124

TOP VIEW

(Not to Scale)

B

GND

NC

37

38

39

40

VS+–ING+INB–IN

36

R

G

R

S–

V

+IN

+IN

–IN

32

31

33

34

35

NC

1

+IN

2

CMP1

–IN

CMP1

OUT

CMP1

VS+_CMP
OUT

CMP2

–IN

CMP2

+IN

CMP2

VS–_CMP

NC

NC = NO CONNECT

NOTES

1. EXPOSE D PADDLE ON THE BOTTOM OF THE PACKAGE
MUST BE CONNECT ED TO A PCB PL ANE TO ACHIEVE
SPECIFIED THERMAL RESI STANCE.

1

3
4
5
6
7

2

8
9

10

11

12

13

15

17

16

18

14

B

S–

S–

S+

V

V

V

OUT

19

R

G

S–

S+

S+

V

V

V

OUT

OUT

NC

30

V

29

S+

28

PD

27

V

POLE

26

V

PEAK

V

25

GAIN

GND

24

V

23

OFFSET

V

22

S–

NC

21

20

NC

09601-004

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1, 10, 20, 21, 30, 40 NC No Internal Connection.
2 +IN
3 −IN
4 OUT

Positive Input, Comparator 1.

CMP1

Negative Input, Comparator 1.

CMP1

Output, Comparator 1.

CMP1

5 VS+_CMP Positive Power Supply, Comparator. Must be connected to VS+.
6 OUT
7 −IN
8 +IN

Output, Comparator 2.

CMP2

Negative Input, Comparator 2.

CMP2

Positive Input, Comparator 2.

CMP2

9 VS−_CMP Negative Power Supply, Comparator. Must be connected to VS−.
11, 14, 17, 22, 33 VS− Negative Power Supply, Equalizer Sections.
12 OUTB Output, Blue Channel.
13, 16, 19, 29, 36 VS+ Positive Power Supply, Equalizer Sections.
15 OUTG Output, Green Channel.
18 OUTR Output, Red Channel.
23 V

Output Offset Control Voltage.

OFFSET

24, 39 GND Signal Ground Reference.
25 V
26 V
27 V
28

Broadband Flat Gain Control Voltage.

GAIN

Equalizer High Frequency Boost Control Voltage.

PEAK

Equalizer Pole Location Adjustment Control Voltage.

POLE

PD

Power Down.

31 +INR Positive Input, Red Channel.
32 −INR Negative Input, Red Channel.
34 +ING Positive Input, Green Channel.
35 −ING Negative Input, Green Channel.
37 +INB Positive Input, Blue Channel.
38 −INB Negative Input, Blue Channel.
Exposed Underside Pad Thermal Plane Connection. Connect to any PCB plane with voltage between VS+ and VS−.

Rev. 0 | Page 6 of 16

AD8124

T

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable (BL-7987R), V
Figure 16, unless otherwise noted.

4

V

= 0V

PEAK

3

V

= 0V

POLE

V

= 1V p-p

O

2

1

0

–1

GAIN (dB)

–2

–3

–4

V

= 0V

GAIN

V

= 0.6V

GAIN

–5

V

= 1.5V

GAIN

–6

100k 1M 10M 100M 1G

Figure 4. Frequency Response for Various V

40

V

= 0.6V

GAIN

30

V

= 1.5V

POLE

V

= 1V p-p

O

20

10

0

–10

GAIN (dB)

–20

–30

–40

V

–50

–60

PEAK

V

PEAK

100k 1M 10M 100M

Figure 5. Frequency Response for Various V

40

V

= 0.6V

GAIN

30

V

= 1.5V

PEAK

V

= 1V p-p

O

20

10

0

–10

GAIN (dB)

–20

–30

–40

V

–50

–60

POLE

V

POLE

100k 1M 10M 100M

Figure 6. Frequency Response for Various V

= 0V
= 1.5V

= 0V
= 1.5V

FREQUENCY (Hz)

FREQUENCY (Hz)

FREQUENCY (Hz)

Without Cable

GAIN

Without Cable

PEAK

Without Cable

POLE

OFFSET

09601-033

09601-005

09601-006

= 0 V, V

, V

PEAK

, and V

GAIN

3

VO = 2V p-p

0

–3

GAIN (dB)

–6

–9

–12

100k 1M 10M 100M

are set to recommended settings shown in

POLE

50m
100m
150m
200m

FREQUENCY (Hz)

Figure 7. Equalized Frequency Response for Various Cable Lengths

120

100

80

60

BANDWIDTH (MHz)

40

20

0 25 50 75 100 125 150 175 200

CABLE LENGT H (meters)

Figure 8. Equalized −3 dB Bandwidth vs. Cable Length

6

4

2

0

AGE (V)

VOL

–2

–4

INPUT
OUTPUT

–6

0 50 100 150 200 250 300 350 400 450 500

TIME (ns)

Figure 9. Overdrive Recovery

V

V
V
V

OUT

GAIN
PEAK
POLE

= 2V p-p

= 0.6V

= 0V
= 0V

09601-007

09601-008

09601-009

Rev. 0 | Page 7 of 16

AD8124

1.5

1.0

50m
200m

1.5

1.0

50m
200m

0.5

0

–0.5

OUTPUT VOLTAGE (V)

–1.0

–1.5

0 50 100 150 200 250 300 350 400 450 500

TIME (ns)

Figure 10. Pulse Response for Various Cable Lengths (2 MHz)

1000

100

OUTPUT VOLTAGE NOISE (nV/√Hz)

0m
200m

0
100k 1M 10M 100M

FREQUENCY (Hz)

Figure 11. Output Voltage Noise vs. Frequency for Various Cable Lengths

20

V

= 0V, V

GAIN

V

= 1.4V, V

GAIN

10

0

–10

–20

–30

CMRR (dB)

–40

–50

–60

–70

–80

0.1 1 10 100

= 0V, V

PEAK

= 1.15V, V

PEAK

FREQUENCY (MHz)

POLE

= 0V

POLE

= 1.5V

09601-012

Figure 12. CMRR vs. Frequency

0.5

0

–0.5

OUTPUT VOLTAGE (V)

–1.0

–1.5

09601-010

024681

TIME (µs)

0

09601-013

Figure 13. Pulse Response for Various Cable Lengths (100 kHz)

6

5

4

3

2

1

FROM 100kHz T O 160MHz (mV rms)

INTEGRATED OUTPUT VOLTAGE NOISE

0

25 50 75 100 125 150 175 200

09601-011

CABLE LENGT H (meters)

09601-014

Figure 14. Integrated Output Voltage Noise vs. Cable Lengths

20

V

= 0V, V

GAIN

V

GAIN

= 1.4V, V

10

0

–10

–20

–30

–40

CROSSTALK (dB)

–50

–60

–70

–80

100k 1M 10M 100M

= 0V, V

PEAK

= 1.15V, V

PEAK

FREQUENCY (Hz)

POLE

= 0V

POLE

= 1.5V

09601-015

Figure 15. Crosstalk vs. Frequency

Rev. 0 | Page 8 of 16

AD8124

2.0
V

0

02175150125100755025

V
V

PEAK
POLE
GAIN

CABLE LENGT H (meters)

1.8

1.6

1.4

1.2

1.0

0.8

0.6

CONTROL VO LTAGE ( V)

0.4

0.2

Figure 16. Recommended Settings for UTP Cable

00

09601-016

2.0
V

PEAK

V

POLE

1.8
V

GAIN

1.6

1.4

1.2

1.0

0.8

0.6

CONTROL VOLTAGE (V)

0.4

0.2

0

25 50 75 100 125 150 175 200

CABLE LENG TH (meters)

Figure 17. Recommended Settings for Coaxial Cable

09601-017

Rev. 0 | Page 9 of 16

AD8124

THEORY OF OPERATION

The AD8124 is a unity-gain, triple, wideband, low noise analog
line equalizer that compensates for losses in UTP and coaxial
cables up to 200 meters in length. The 3-channel architecture
is targeted at high resolution RGB applications but can be used
in HD YPbPr applications as well.

Three continuously adjustable control voltages, common
to the RGB channels, are available to the designer to provide
compensation for various cable lengths as well as for variations
in the cable itself. The V
of high frequency peaking. V

input is used to control the amount

PEAK

is the primary control that is

PEAK

used to compensate for frequency and cable-length dependent,
high frequency losses that are present due to the skin effect of
the cable. A second control pin, V

, is used to adjust broadband

GAIN

gain to compensate for low frequency flat losses present in the
cable. A third control, V
equalizer poles and can be linearly derived from V

, is used to move the positions of the

POLE

, as illustrated

PEAK

in the Typical Performance Characteristics and Applications
Information sections, for UTP and coaxial cables. Finally, an
output offset adjust control, V

, allows the designer to shift

OFFSET

the output dc level.

The AD8124 has a high impedance differential input that makes
termination simple and allows dc-coupled signals to be received
directly from the cable. The AD8124 input can also be used in a
single-ended fashion in coaxial cable applications.

The AD8124 has a low impedance output that is capable of driving
a 150 Ω load. For systems where the AD8124 has to drive a high
impedance capacitive load, it is recommended that a small series
resistor be placed between the output and load to buffer the
capacitance. The resistor should not be so large as to reduce
the overall bandwidth to an unacceptable level.

The AD8124 is designed such that systems that use short-to­medium-length cables do not pay a noise penalty for excess gain
that they do not require. The high gain is only available for
longer length systems where it is required. This feature is built
into the V

control and is transparent to the user.

PEAK

Two comparators are provided on-chip that can be used for sync
pulse extraction in systems that use sync-on-common mode
encoding. Each comparator has very low output impedance and
can therefore be used in a source-only cable termination scheme
by placing a series resistor equal to the cable characteristic impedance
directly on the comparator output. Additional details are provided
in the Applications Information section.

INPUT COMMON-MODE VOLTAGE RANGE CONSIDERATIONS

When using the AD8124 as a receiver, it is important to ensure
that its input common-mode voltage stays within the specified
range. The received common-mode level is calculated by adding
the common-mode level of the driver, the single-ended peak
amplitude of the received signal, the amplitude of any sync
pulses, and the other induced common-mode signals, such as
ground shifts between the driver and the AD8124 and pickup
from external sources, such as power lines and fluorescent lights.
See the Applications Information section for more details.

Rev. 0 | Page 10 of 16

AD8124

APPLICATIONS INFORMATION

BASIC OPERATION

The AD8124 is easy to apply because it contains everything
on-chip needed for cable loss compensation. Figure 19 shows a
basic application circuit (power supplies not shown) with common­mode sync pulse extraction that is compatible with the common­mode sync pulse encoding technique used in the AD8134, AD8142,

AD8147, and AD8148 triple differential drivers. If sync extraction

is not required, the terminations can be single 100 Ω resistors,
and the comparator inputs can be left floating. In Figure 19, the
AD8124 feeds a high impedance input, such as a delay line or
crosspoint switch, and the additional gain of two that makes up
for double termination loss is not required.

COMPARATORS

In addition to general-purpose applications, the two on-chip
comparators can be used to extract video sync pulses from the
received common-mode voltages or to receive differential digital
information. Built-in hysteresis helps to eliminate false triggers
from noise. The Sync Pulse Extraction Using Comparators
section describes the sync extraction details.

26

V

PEAK

27

V

POLE

25

V

GAIN

23

V

OFFSET

28

PD

31

32

RECEIVED

RED VIDEO

ANALOG

CONTROL

INPUTS

POWER-DO WN

CONTROL

49.9Ω

49.9Ω

The comparator outputs have nearly 0 Ω output impedance and
are designed to drive source-terminated transmission lines. The
source termination technique uses a resistor in series with each
comparator output such that the sum of the comparator source
resistance (≈0 Ω) and the series resistor equals the transmission
line characteristic impedance. The load end of the transmission
line is high impedance. When the signal is launched into the source
termination, its initial value is one-half its source value because its
amplitude is divided by two in the voltage divider formed by the
source termination and the transmission line. At the load, the
signal experiences nearly 100% positive reflection due to the
high impedance load and is restored to nearly its full value. This
technique is commonly used in PCB layouts that involve high
speed digital logic.

Figure 18 shows how to apply the comparators with source
termination when driving a 50 Ω transmission line that is high
impedance at its receive end.

49.9

Ω

Z0 = 50Ω

Figure 18. Using a Comparator with Source Termination

HIGH-Z

AD8124

RED

18

RED VIDEO O UT

09601-018

1

2

GREEN

BLUE

GND REFERENCE

24, 39

15

GREEN VIDEO OUT

12

BLUE VIDEO OUT

4

HSYNC OUT

6

VSYNC OUT

09601-019

RECEIVED

GREEN VIDEO

RECEIVED

BLUE VIDEO

1kΩ

1kΩ

GREEN

CMV

49.9Ω

49.9Ω

49.9Ω

49.9Ω

BLUE CMV

RED CMV

475Ω

34

35

37

38

2

3

8

7

47pF47pF

Figure 19. Basic Application Circuit with Common-Mode Sync Extraction

Rev. 0 | Page 11 of 16

AD8124

V

SYNC PULSE EXTRACTION USING COMPARATORS

The AD8124 is useful in many systems that transport computer
video signals, which typically comprise red, green, and blue (RGB)
video signals and separate horizontal and vertical sync signals.
Because the sync signals are separate and not embedded in the
color signals, it is advantageous to transmit them using a simple
scheme that encodes them among the three common-mode
voltages of the RGB signals. The AD8134, AD8142, AD8147, and

AD8148 triple differential drivers are natural complements to

the AD8124 because they perform the sync pulse encoding with
the necessary circuitry on-chip.

The sync encoding equations follow:

K

VRed

CM

2

K

VGreen

CM

K

VBlue

CM

2

where:

Red V

, Green VCM, and Blue VCM are the transmitted common-

CM

mode voltages of the respective color signals.

K is an adjustable gain constant that is set by the driver.
V and H are the vertical and horizontal sync pulses, defined

with a weight of −1 when the pulses are in their low states and a
weight of +1 when they are in their high states.

The AD8134, AD8142, and AD8146/AD8147/AD8148 data
sheets contain further details regarding the encoding scheme.
Figure 19 illustrates how the AD8124 comparators can be used to
extract the horizontal and vertical sync pulses that are encoded on
the RGB common-mode voltages by the aforementioned drivers.

USING THE V

The V

PEAK

PEAK

input is the main peaking control and is used to
compensate for the low-pass roll-off in the cable response. The
V

input is a secondary frequency response shaping control

POLE

that shifts the positions of the equalizer poles. The V
controls the wideband flat gain and is used to compensate for
the low frequency cable loss that is nominally flat. The V
input is used to produce an offset at the AD8124 output. The
output offset is equal to the voltage applied to the V
limited by the output swing limits.

The V

PEAK

and V

POLE

can be coupled to form a single peaking control. While Figure 16
and Figure 17 show recommended settings vs. cable length,
designers may find other combinations that they prefer. These
two controls give designers extra freedom, as well as the ability
to compensate for different cable types (such as UTP and coaxial
cable), as opposed to having only a single frequency shaping
control.

(1)

[

]

HV

−=

(2)

[]

V22−=

[

(3)

]

HV

+=

, V

, V

POLE

GAIN

, AND V

OFFSET

INPUTS

input

GAIN

OFFSET

input,

OFFSET

controls can be used independently or they

Rev. 0 | Page 12 of 16

In some cases, as would likely be with automatic control, the
V

control is derived from a low impedance source, such as

PEAK

an op amp. Figure 20 shows how to derive V

POLE

from V

PEAK

in a
UTP application according to the recommended curves shown
in Figure 16 when V
Clearly, the 5 V supply must be clean to provide a clean V

originates from a low impedance source.

PEAK

POLE

voltage.

20Ω

V

PEAK

5V

V

Figure 20. Deriving V

PEAK

POLE

5.11kΩ

from V

The 20 Ω series resistor in the V

14kΩ

8.25kΩ

with Low-Z Source for the UTP Cable

PEAK

path provides capacitive load

PEAK

V

POLE

V

PEAK

≈

+ 0.9V

2

09601-020

buffering for the op amp. This value can be modified, depending
on the actual capacitive load.

In automatic equalization circuits that place the control voltages
inside feedback loops, attention must be paid to the poles produced
by the summing resistors and load capacitances.

The peaking can also be adjusted by a mechanical or digitally
controlled potentiometer. In these cases, if the resistance of the
potentiometer is a couple of orders of magnitude lower than the
values of the resistors used to develop V

, its resistance can be

POLE

ignored. Figure 21 shows how to use a 500 Ω potentiometer with
the resistor values shown in Figure 20 scaled up by a factor of 10.

5V

750Ω

500Ω

Figure 21. Deriving V

51.1kΩ

POLE

from V

PEAK

5V

140kΩ

82.5kΩ

with a Potentiometer for the UTP Cable

PEAK

V

POLE

V

PEAK

≈

+ 0.9V

2

09601-021

Many potentiometers have wide tolerances. If a wide tolerance
potentiometer is used, it may be necessary to change the value
of the 750 Ω resistor to obtain a full swing for V

The V

input is essentially a contrast control and can be set

GAIN

PEAK

.

by adjusting it to produce the correct amplitude of a known test
signal (such as a white screen) at the AD8124 output.

V

can also be derived from V

GAIN

according to the linear

PEAK

relationships shown in Figure 16 and Figure 17. Figure 22 shows
how to derive V

POLE

and V

GAIN

from V

in a UTP application

PEAK

that originates from a low-Z source.

V

PEAK

Figure 22. Deriving V

POLE

5.11kΩ

5.11kΩ

and V

20Ω

GAIN

8.25kΩ

133kΩ

from V

V

5V

5V

PEAK

14kΩ

60.4kΩ

with Low-Z Source for the UTP Cable

PEAK

V

V

POLE

GAIN

V

PEAK

≈

2

≈ 0.89 × V

PEAK

+ 0.9V

+ 0.38V

09601-022

AD8124

USING THE AD8124 WITH COAXIAL CABLE

The V
types of cable, including coaxial cable. Figure 17 presents the
recommended settings for V
AD8124 is used with good quality 75 Ω video cable. Figure 23
shows how to derive V
cable application where V

Figure 23. Deriving V

The op amp in the circuit that develops V
the offset of −0.62 V with a gain from V
unity. A passive offset circuit requires an offset injection voltage
that is much larger in magnitude than the available −5 V supply.
Clearly, the V
independently.

The AD8124 differential input can accept signals carried over
unbalanced cable, as shown in Figure 24, for an unbalanced
75 Ω coaxial cable termination.

control allows the AD8124 to be used with other

POLE

, V

+5V

PEAK

and V

POLE

originates from a low-Z source.

PEAK

20Ω

V

5.11kΩ

PEAK

GAIN

47.5kΩ

–5V

from V

75Ω

1.16kΩ

20kΩ

10kΩ

1.24kΩ

and V

POLE

control voltage can also be developed

GAIN

INPUT FROM

75Ω CABLE

, and V

POLE

from V

GAIN

V

PEAK

24.3kΩ

V

≈ 0.76 × V

POLE

V

≈ 1.06 × V

GAIN

with Low-Z Source for the Coaxial Cable

PEAK

GAIN

to V

PEAK

AD8124
INPUT STAGE

when the

GAIN

in a coaxial

PEAK

PEAK

PEAK

is required to insert

that is close to

GAIN

09601-030

Figure 24. Terminating a 75 Ω Cable

– 0.41V

– 0.62V

09601-023

DRIVING 75 Ω VIDEO CABLE WITH THE AD8124

When the RGB outputs must drive a 75 Ω line rather than a
high impedance load, an additional gain of two is required to
make up for the double termination loss (75 Ω source and load
terminations). There are two options available for this.

One option is to place the additional gain of 2 at the drive end
by using the AD8148 triple differential driver to drive the cable.
The AD8148 has a fixed gain of 4 instead of the usual gain of 2
and thereby provides the required additional gain of 2 without
having to add additional amplifiers to the signal chain. The
AD8148 also contains sync-on-common-mode encoding. If
sync-on-common-mode is not required, it can be deactivated
on the AD8148 by connecting its sync level input to ground.

The other option is to include a triple gain-of-2 buffer, such as the

ADA4862-3, on the AD8124 RGB outputs, as shown in Figure 25

for one channel (power supplies not shown). The ADA4862-3
provides the gain of 2 that compensates for the double­termination loss.

ONE VIDEO

OUTPUT

FROM AD8124

ONE CHANNEL OF ADA4862-3

75

Ω

500

Ω

500

Ω

Z0 = 75Ω

Figure 25. Using the ADA4862-3 on AD8124 Outputs

75Ω

DRIVING A CAPACITIVE LOAD

When driving a high impedance capacitive input, it is necessary
to place a small series resistor between each of the three AD8124
video outputs and the load to buffer the input capacitance of the
device being driven. Clearly, the resistor value must be small
enough to preserve the required bandwidth.

POWER SUPPLY FILTERING

External power supply filtering between the system power supplies
and the AD8124 is recommended in most applications to prevent
supply noise from contaminating the received signal as well as
to prevent unwanted feedback through the supplies that may
cause instability. Figure 26 shows that the AD8124 power supply
rejection decreases with increasing frequency. These plots are
for the lowest control settings and shift upward as the peaking
is increased.

10

V

=0V

GAIN

V

=0V

PEAK

V

=0V

POLE

0

–10

–20

–30

PSRR (dB)

–40

–50

–60

100k 1M 10M 100M

FREQUENCY (Hz)

Figure 26. PSRR vs. Frequency

+PSRR
–PSRR

09601-026

09601-025

Rev. 0 | Page 13 of 16

AD8124

A suitable filter that uses a surface-mount ferrite bead is shown
in Figure 27, and its frequency response is shown in Figure 28.
Because the frequency response was taken using a 50 Ω network
analyzer and with only one 0.1 μF capacitor on the AD8124 side,
the actual amount of rejection provided by the filter in a real-world
application is different from that shown in Figure 28. The general
shape of the rejection curve, however, matches Figure 28, providing
substantially increased overall PSRR from approximately 5 MHz to
500 MHz, where it is most needed. One filter is required on each
of the two supplies (not one filter per supply pin).

FAIR-RITE

SYSTEM
SUPPLY

*ALL AD8124 SUPPL Y PINS ARE I NDIVIDUALL Y

DECOUPLED WITH A 0.1µF CAPACI TOR.

0

–20

–40

–60

0.1µF 4700pF 4700pF

Figure 27. Power Supply Filter

2743021447

TO AD8124*

09601-027

LAYOUT AND POWER SUPPLY DECOUPLING CONSIDERATIONS

Standard high speed PCB layout practices should be adhered
to when designing with the AD8124. A solid ground plane is
required and controlled impedance traces should be used when
interconnecting the high speed signals. Source termination resistors
on all outputs must be placed as close as possible to the output pins.

The exposed paddle on the underside of the AD8124 must be
connected to a pad that connects to at least one PCB plane.
Several thermal vias should be used to make the connection
between the pad and the plane(s).

High quality 0.1 μF power supply decoupling capacitors should
be placed as close as possible to all supply pins. Small surface­mount ceramic capacitors should be used, and tantalum capacitors
are recommended for bulk supply decoupling.

POWER-DOWN

The power-down feature is intended to be used to reduce power
consumption when a particular device is not in use and does
not place the output in a high-Z state when asserted. The input
logic levels and supply current in power-down mode are presented
in the Power Supply section of Tab le 1 .

–80

OUTPUT RESPONS E (dB)

–100

–120

10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 28. Power Supply Filter Frequency Response in a 50 Ω System

09601-028

Rev. 0 | Page 14 of 16

AD8124

S

OUTLINE DIMENSIONS

6.00

INDICATOR

1.00

0.85

0.80

EATING

PLANE

PIN 1

12° MAX

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

5.75

BSC SQ

0.20 REF

0.60 MAX

0.05 MAX

0.02 NOM
COPLANARIT Y

0.08

0.50

BSC

0.50

0.40

0.30

Figure 29. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm, Very Thin Quad

(CP-40-4)

Dimensions shown in millimeters

0.60 MAX

29

28

(BOT TOM V IEW)

20

19

EXPOSED

40

1

PAD

10

11

4.50
REF

FOR PROPER CO NNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DESCRI PTIONS
SECTION O F THIS DAT A SHEET.

PIN 1
INDICATOR

4.45

4.30 SQ

4.15

0.25 MIN

122107-A

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD8124ACPZ −40°C to +85°C 40-Lead LFCSP_VQ CP-40-4
AD8124ACPZ-R7 −40°C to +85°C 40-Lead LFCSP_VQ CP-40-4
AD8124ACPZ-RL −40°C to +85°C 40-Lead LFCSP_VQ CP-40-4

1

Z = RoHS Compliant Part.

Rev. 0 | Page 15 of 16

AD8124

NOTES

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09601-0-1/11(0)

Rev. 0 | Page 16 of 16