Page 1
Triple Differential Receiver with
V
www.BDTIC.com/ADI
FEATURES
Compensates cables to 300 meters for wideband video
Fast rise and fall times
4.9 ns with 2 V step @ 150 meters of UTP cable
8.0 ns with 2 V step @ 300 meters of UTP cable
55 dB peak gain at 100 MHz
Two frequency response gain adjustment pins
High frequency peaking adjustment (V
Broadband flat gain adjustment (V
Pole location adjustment pin (V
POLE
)
Compensates for variations between cables
Can be optimized for either UTP or coaxial cable
DC output offset adjust (V
OFFSET
)
Low output offset voltage: 24 mV
Compensates both RGB and YPbPr
Two on-chip comparators with hysteresis
Can be used for common-mode sync extraction
Available in 40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
Keyboard-video-mouse (KVM)
Digital signage
RGB video over UTP cables
Professional video projection and distribution
HD video
Security video
GENERAL DESCRIPTION
The AD8123 is a triple, high speed, differential receiver and
equalizer that compensates for the transmission losses of UTP
and coaxial cables up to 300 meters in length. Various gain
stages are summed together to best approximate the inverse
frequency response of the cable. Logic circuitry inside the AD8123
controls the gain functions of the individual stages so that the
lowest noise can be achieved at short-to-medium cable lengths.
This technique optimizes its performance for low noise, shortto-medium range applications, while at the same time provides
the high gain bandwidth required for long cable equalization
(up to 300 meters). Each channel features a high impedance
differential input that is ideal for interfacing directly with the cable.
The AD8123 has three control pins for optimal cable
compensation, as well as an output offset adjust pin. Two
voltage-controlled pins are used to compensate for different
cable lengths; the V
peaking and the V
which compensates for the low frequency flat cable loss.
pin controls the amount of high frequency
PEAK
pin adjusts the broadband flat gain,
GAIN
GAIN
)
PEAK
)
Adjustable Line Equalization
AD8123
FUNCTIONAL BLOCK DIAGRAM
PEAKVPOLEVOFFSETVGAIN
AD8123
–IN
R
+IN
R
–IN
G
+IN
G
–
IN
B
+IN
B
–IN
CMP1
+IN
CMP1
–IN
CMP2
+IN
CMP2
Figure 1.
For added flexibility, an optional pole adjustment pin, V
allows movement of the pole locations, allowing for the
compensation of different gauges and types of cable as well
as variations between different cables and/or equalizers. The
V
pin allows the dc voltage at the output to be adjusted,
OFFSET
adding flexibility for dc-coupled systems.
The AD8123 is available in a 6 mm × 6 mm, 40-lead LFCSP
a
nd is rated to operate over the extended temperature range of
−40°C to +85°C.
UXGA RESOLUT ION IMAGE
AFTER 300 MET ER CAT-5 CABLE
BEFORE AD8123.
UXGA RESOLUTION IMAGE
AFTER 300 MET ER CAT-5 CABLE
AFTER AD8123.
Figure 2.
OUT
OUT
OUT
OUT
OUT
R
G
B
CMP1
CMP2
6814-001
POLE
,
06814-019
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
Page 2
AD8123
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Description .............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 10
Input Common-Mode Voltage Range Considerations .........10
Applications Information .............................................................. 11
Basic Operation ..........................................................................11
Comparators ............................................................................... 11
Sync Pulse Extraction Using Comparators............................. 12
Using the V
Using the AD8123 with Coaxial Cable.................................... 13
Driving 75 Ω Video Cable With the AD8123 ........................ 13
Driving a Capacitive Load......................................................... 13
Filtering the RGB Outputs........................................................ 13
Power Supply Filtering............................................................... 14
Layout and Power Supply Decoupling Considerations......... 14
Input Common-Mode Range ................................................... 15
Small Signal Frequency Response ............................................ 15
Power-Down ............................................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
PEAK
, V
POLE
, V
GAIN
, and V
Inputs ................... 12
OFFSET
REVISION HISTORY
11/07—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Ordering Guide.......................................................... 16
8/07—Revision 0: Initial Version
Rev. A | Page 2 of 16
Page 3
AD8123
www.BDTIC.com/ADI
SPECIFICATIONS
TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable (BL-7987R), V
Figure 17, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
PEAKING PERFORMANCE (NO CABLE)
Peak Frequency V
V
Peak Gain V
V
PEAK
PEAK
PEAK
PEAK
= 2 V, V
= 2 V, V
= 2 V, V
= 2 V, V
DYNAMIC PERFORMANCE
10% to 90% Rise/Fall Time V
V
Settling Time to 2% V
V
–3 dB Large Signal Bandwidth V
V
V
V
= 2 V step, 150 meters Cat-5 4.9 ns
OUT
= 2 V step, 300 meters Cat-5 8.0 ns
OUT
= 2 V step, 150 meters Cat-5 36 ns
OUT
= 2 V step, 300 meters Cat-5 106 ns
OUT
= 1 V p-p, <10 meters Cat-5 120 MHz
OUT
= 2 V p-p, <10 meters Cat-5 110 MHz
OUT
= 2 V p-p, 150 meters Cat-5 78 MHz
OUT
= 2 V p-p, 300 meters Cat-5 43 MHz
OUT
Integrated Output Voltage Noise 150 meter setting, integrated to 160 MHz 2.5 mV rms
300 meter setting, integrated to 160 MHz 24 mV rms
INPUT DC PERFORMANCE
Input Voltage Range −IN and +IN ±3.0 V
Maximum Differential Voltage Swing 4 V p-p
Voltage Gain ΔVO/ΔVI, V
Common-Mode Rejection Ratio (CMRR) At dc, V
At dc, V
PEAK
PEAK
At 1 MHz, V
Input Resistance Common mode 4.4 MΩ
Differential 3.7 MΩ
Input Capacitance Common mode 1.0 pF
Differential 0.5 pF
Input Bias Current 2.4 μA
V
Pin Current 28.9 μA
OFFSET
V
Pin Current 0.5 μA
GAIN
V
Pin Current 0.4 μA
PEAK
V
Pin Current 0.4 μA
POLE
ADJUSTMENT PINS
V
Input Voltage Range Relative to GND 0 to 2 V
PEAK
V
Input Voltage Range Relative to GND 0 to 2 V
POLE
V
Input Voltage Range Relative to GND 0 to 2 V
GAIN
V
to OUT Gain OUT/V
OFFSET
Maximum Flat Gain V
OFFSET
= 2 V 2 dB
GAIN
OUTPUT CHARACTERISTICS
Output Voltage Swing 150 Ω load −3.75 to +3.69 V
1 kΩ load −3.66 to +3.69 V
Output Offset Voltage Referred to output, V
Referred to output, V
Output Offset Voltage Drift Referred to output 33 μV/°C
= 0 V, V
OFFSET
= 0.6 V, V
GAIN
= 0.6 V, V
GAIN
= 0.6 V, V
GAIN
= 0.6 V, V
GAIN
set for 0 meters of cable 1 V/V
GAIN
= V
= V
GAIN
POLE
= V
= V
GAIN
POLE
= V
GAIN
= V
PEAK
, V
GAIN
, and V
PEAK
= 1 V 100 MHz
POLE
= 2 V 105 MHz
POLE
= 1 V 45 dB
POLE
= 2 V 55 dB
POLE
are set to recommended settings shown in
POLE
= 0 V −86 dB
= 2 V −67 dB
= 2 V −52 dB
POLE
, range limited by output swing 1 V/V
= V
= V
PEAK
PEAK
= V
GAIN
GAIN
= 0 V 24 mV
POLE
= V
= 2 V 32 mV
POLE
Rev. A | Page 3 of 16
Page 4
AD8123
www.BDTIC.com/ADI
Parameter Conditions Min Typ Max Unit
POWER SUPPLY
Operating Voltage Range ±4.5 ±5.5 V
Positive Quiescent Supply Current 132 mA
Negative Quiescent Supply Current 126 mA
Supply Current Drift, ICC/I
Positive Power Supply Rejection Ratio DC, referred to output −51 dB
Negative Power Supply Rejection Ratio DC, referred to output −63 dB
Power Down, VIH (Minimum) Minimum Logic 1 voltage 1.1 V
Power Down, VIL (Maximum) Maximum Logic 0 voltage 0.8 V
Positive Supply Current, Powered Down V
Negative Supply Current, Powered Down V
COMPARATORS
Output Voltage Levels VOH/V
Hysteresis V
Propagation Delay t
Rise/Fall Times t
Output Resistance 0.03 Ω
OPERATING TEMPERATURE RANGE −40 +85 °C
EE
80 μA/°C
= V
= V
PEAK
GAIN
= V
PEAK
GAIN
OL
HYST
PD, LH/tPD, HL
RISE/tFAL L
= 0 V 1.1 μA
POLE
= V
= 0 V 0.7 μA
POLE
3.33/0.043 V
70 mV
17.5/10.0 ns
9.3/9.3 ns
Rev. A | Page 4 of 16
Page 5
AD8123
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage 11 V
Power Dissipation See Figure 3
Input Voltage (Any Input) VS− − 0.3 V to VS+ + 0.3 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in a circuit board in still air.
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
current is calculated by multiplying the load current by the
voltage difference between the associated power supply and the
output voltage. The total power dissipation due to load currents
is then obtained by taking the sum of the individual power
dissipations. RMS output voltages must be used when dealing
with ac signals.
Airflow reduces θ
with the package leads from metal traces, through holes, ground,
and power planes reduces the θ
underside of the package must be soldered to a pad on the PCB
surface that is thermally connected to a solid plane (usually the
ground plane) to achieve the specified θ
Figure 3 shows the maximum safe power dissipation in the
p
(29°C/W) on a JEDEC standard 4-layer board with the underside
Table 3. Thermal Resistance with the Underside Pad
Connected to t
Package Type/PCB Type θ
40-Lead LFCSP/4-Layer 29 °C/W
he Plane
JA
Unit
paddle soldered to a pad that is thermally connected to a PCB
plane. θ
Maximum Power Dissipation
The maximum safe power dissipation in the AD8123 package
is limited by the associated rise in junction temperature (T
) on
J
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8123. Exceeding a junction temperature
of 175°C for an extended time can result in changes in the
silicon devices, potentially causing failure.
). The power dissipation due to each load
S
. In addition, more metal directly in contact
JA
JA
ackage vs. the ambient temperature for the 40-lead LFCSP
values are approximations.
JA
7
6
5
4
3
2
MAXIMUM POWER DISSIPATION (W)
1
0
–40 –20 0 20 40 60 80
AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
) is the sum of the
D
) times the
S
. The exposed paddle on the
.
JA
06814-025
ESD CAUTION
Rev. A | Page 5 of 16
Page 6
AD8123
www.BDTIC.com/ADI
PIN CONFIGURATION AND FUNCTION DESCRIPTION
AD8123
TOP VIEW
(Not to Scale)
B
GND
NC
37
38
39
40
VS+–ING+INB–IN
36
R
G
R
S–
V
+IN
+IN
–IN
32
31
33
34
35
NC
1
+IN
2
CMP1
–IN
CMP1
OUT
CMP1
VS+_CMP
OUT
CMP2
–IN
CMP2
+IN
CMP2
VS–_CMP
NC
NC = NO CONNECT
NOTES
1. EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE
MUST BE CONNECT ED TO A PCB PLANE TO ACHIEVE
SPECIFIED THERMAL RESI STANCE.
1
3
4
5
6
7
2
8
9
10
11
12
13
15
17
16
18
14
B
S–
S–
S+
V
V
V
OUT
19
R
G
S–
S+
S+
V
V
V
OUT
OUT
NC
30
V
29
S+
28
PD
27
V
POLE
26
V
PEAK
V
25
GAIN
GND
24
V
23
OFFSET
V
22
S–
NC
21
20
NC
06814-002
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 10, 20, 21, 30, 40 NC No Internal Connection.
2 +IN
3 −IN
4 OUT
CMP1
CMP1
CMP1
Positive Input, Comparator 1.
Negative Input, Comparator 1.
Output, Comparator 1.
5 VS+_CMP Positive Power Supply, Comparator. Must be connected to VS+.
6 OUT
7 −IN
8 +IN
CMP2
CMP2
CMP2
Output, Comparator 2.
Negative Input, Comparator 2.
Positive Input, Comparator 2.
9 VS−_CMP Negative Power Supply, Comparator. Must be connected to VS−.
11, 14, 17, 22, 33 V
S−
12 OUT
13, 16, 19, 29, 36 V
S+
15 OUT
18 OUT
23 V
OFFSET
B
G
R
Negative Power Supply, Equalizer Sections.
Output, Blue Channel.
Positive Power Supply, Equalizer Sections.
Output, Green Channel.
Output, Red Channel.
Output Offset Control Voltage.
24, 39 GND Signal Ground Reference.
25 V
26 V
27 V
28
GAIN
PEAK
POLE
PD
31 +IN
32 −IN
34 +IN
35 −IN
37 +IN
38 −IN
R
R
G
G
B
B
Broadband Flat Gain Control Voltage.
Equalizer High Frequency Boost Control Voltage.
Equalizer Pole Location Adjustment Control Voltage.
Power Down.
Positive Input, Red Channel.
Negative Input, Red Channel.
Positive Input, Green Channel.
Negative Input, Green Channel.
Positive Input, Blue Channel.
Negative Input, Blue Channel.
Exposed Underside Pad Thermal Plane Connection. Connect to any PCB plane with voltage between VS+ and VS−.
Rev. A | Page 6 of 16
Page 7
AD8123
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable (BL-7987R), V
Figure 17, unless otherwise noted.
4
V
= 0V
GAIN
= 0V
V
POLE
3
V
= 1V p-p
O
2
1
0
–1
GAIN (dB)
–2
–3
–4
V
= 0V
GAIN
V
V
GAIN
V
POLE
= 1V p-p
V
O
V
GAIN
GAIN
= 1V
= 2V
= 0.6V
= 2V
FREQUENCY (Hz)
Without Cable
GAIN
–5
–6
100k 1M 10M 100M
Figure 5. Frequency Response for Various V
60
40
OFFSET
06814-003
= 0 V, V
, V
PEAK
, and V
GAIN
3
VO = 2V p-p
2
1
0
–1
–2
–3
–4
–5
GAIN (dB)
–6
–7
–8
–9
–10
–11
–12
100k 1M 10M 100M
are set to recommended settings shown in
POLE
50m
100m
150m
200m
300m
FREQUENCY (Hz)
Figure 8. Equalized Frequency Response for Various Cable Lengths
120
100
VO = 2V p-p
06814-006
20
0
GAIN (dB)
–20
–40
V
= 0V
PEAK
V
= 1V
PEAK
V
= 2V
PEAK
–60
100k 1M 10M 100M
FREQUENCY (Hz)
Figure 6. Frequency Response for Various V
PEAK
40
V
= 0.6V
GAIN
= 1V
V
PEAK
30
= 1V p-p
V
O
20
10
0
–10
GAIN (dB)
–20
–30
–40
V
= 0V
POLE
–50
V
= 1V
POLE
V
= 2V
POLE
–60
100k 1M 10M 100M
FREQUENCY (Hz)
Figure 7. Frequency Response for Various V
POLE
Without Cable
Without Cable
80
60
40
BANDWIDTH (MHz)
20
0
0 50 100 150 200 250 300
06814-004
Figure 9. Equalized −3 dB B
CABLE LENGT H (meters)
andwidth vs. Cable Length
06814-007
6
4
2
0
VOLTAGE (V)
–2
–4
INPUT
OUTPUT
–6
0 50 100 150 200 250 300 350 400 450 500
06814-005
TIME (ns)
V
V
V
GAIN
PEAK
POLE
= 0.6V
= 0V
= 0V
06814-008
Figure 10. Overdrive Recovery
Rev. A | Page 7 of 16
Page 8
AD8123
www.BDTIC.com/ADI
1.5
1.0
50m
150m
300m
1.5
1.0
50m
150m
300m
0.5
0
–0.5
OUTPUT VOLTAGE (V)
–1.0
–1.5
0 50 100 150 200 250 300 350 400 450 500
TIME (ns)
Figure 11. Pulse Response for Various Cable Lengths (2 MHz)
10000
1000
OUTPUT VOLTAGE NOISE (nV/ Hz)
Figure 12. Output Voltage Noise vs. Fre
0m
150m
300m
100
10
100k 1M 10M 100M
FREQUENCY (Hz)
quency for Various Cable Length
20
V
10
0
–10
–20
–30
–40
CMRR (dB)
–50
–60
–70
–80
–90
100k 1M 10M 100M
V
GAIN
= 1.85V, V
= 0V, V
GAIN
= 0V, V
PEAK
= 1.65V, V
PEAK
FREQUENCY (Hz)
POLE
= 0V
POLE
= 1.75V
Figure 13. CMRR vs. Frequency
0.5
0
–0.5
OUTPUT VOLTAGE (V)
–1.0
–1.5
012345678910
06814-009
TIME (µs)
06814-012
Figure 14. Pulse Response for Various Cable Lengths (100 kHz)
30
25
20
15
10
100kHz TO 160MHz (mV rms)
5
INTEGRATE D OUTPUT VO LTAGE NO ISE FROM
0
25 50 75 100 125 150 175 200 225 250 275 300
06814-010
CABLE LENGT H (meters)
06814-013
Figure 15. Integrated Output Voltage Noise vs. Cable Length
20
V
= 0V, V
GAIN
10
V
= 1.85V, V
GAIN
0
–10
–20
–30
–40
CROSSTALK (d B)
–50
–60
–70
–80
100k 1M 10M 100M
06814-011
= 0V, V
PEAK
= 1.65V, V
PEAK
FREQUENCY (Hz)
POLE
= 0V
POLE
= 1.75V
06814-014
Figure 16. Crosstalk vs. Frequency
Rev. A | Page 8 of 16
Page 9
AD8123
www.BDTIC.com/ADI
2.0
V
PEAK
V
POLE
1.8
V
GAIN
1.6
1.4
1.2
1.0
0.8
0.6
CONTROL VO LTAGE (V)
0.4
0.2
0
25 50 75 100 125 150 175 200 225 250 275 300
CABLE LENGT H (meters)
06814-015
Figure 17. Recommended Settings for UTP Cable
2.0
V
PEAK
V
POLE
1.8
V
GAIN
1.6
1.4
1.2
1.0
0.8
0.6
CONTROL VOLTAGE ( V)
0.4
0.2
0
25 50 75 100 125 150 175 200 225 250 275 300
CABLE LENGTH (meters)
06814-016
Figure 18. Recommended Settings for Coaxial Cable
Rev. A | Page 9 of 16
Page 10
AD8123
www.BDTIC.com/ADI
THEORY OF OPERATION
The AD8123 is a unity-gain, triple, wideband, low noise analog
line equalizer that compensates for losses in UTP and coaxial
cables up to 300 meters in length. The 3-channel architecture is
targeted at high resolution RGB applications but can be used in
HD YPbPr applications as well.
Three continuously adjustable control voltages, common
t
o the RGB channels, are available to the designer to provide
compensation for various cable lengths as well as for variations
in the cable itself. The V
of high frequency peaking. V
used to compensate for frequency and cable-length dependent,
high frequency losses that are present due to the skin effect of
the cable. A second control pin, V
gain to compensate for low frequency flat losses present in the
cable. A third control, V
equalizer poles and can be linearly derived from V
in the Typical Performance Characteristics and Applications
In
formation sections, for UTP and coaxial cables. Finally, an
offset adjust control, V
output
the output dc level.
The AD8123 has a high impedance differential input that makes
ter
mination simple and allows dc-coupled signals to be received
directly from the cable. The AD8123 input can also be used in a
single-ended fashion in coaxial cable applications. For differential
systems that require very high CMRR, a triple differential
receiver, such as the
ront of the AD8123.
f
The AD8123 has a low impedance output that is capable of
dr
iving a 150 Ω load. For systems where the AD8123 has to
drive a high impedance capacitive load, it is recommended that
a small series resistor be placed between the output and load to
buffer the capacitance. The resistor should not be so large as to
reduce the overall bandwidth to an unacceptable level.
input is used to control the amount
PEAK
is the primary control that is
PEAK
, is used to adjust broadband
GAIN
, is used to move the positions of the
POLE
, as illustrated
PEAK
, allows the designer to shift
OFFSET
AD8143 or AD8145, can be placed in
The AD8123 is designed such that systems that use short-to-
edium-length cables do not pay a noise penalty for excess gain
m
that they do not require. The high gain is only available for
longer length systems where it is required. This feature is built
into the V
Two comparators are provided on-chip that can be used for
syn
c pulse extraction in systems that use sync-on-common
mode encoding. Each comparator has very low output impedance
and can therefore be used in a source-only cable termination
scheme by placing a series resistor equal to the cable characteristic
impedance directly on the comparator output. Additional
details are provided in the
control and is transparent to the user.
PEAK
Applications Information section.
INPUT COMMON-MODE VOLTAGE RANGE CONSIDERATIONS
When using the AD8123 as a receiver, it is important to ensure
that its input common-mode voltage stays within the specified
range. The received common-mode level is calculated by adding
the common-mode level of the driver, the single-ended peak
amplitude of the received signal, the amplitude of any sync
pulses, and the other induced common-mode signals, such as
ground shifts between the driver and the AD8123 and pickup
from external sources, such as power lines and fluorescent
lights. See the
Applications Information section for more details.
Rev. A | Page 10 of 16
Page 11
AD8123
www.BDTIC.com/ADI
APPLICATIONS INFORMATION
BASIC OPERATION
The AD8123 is easy to apply because it contains everything
on-chip needed for cable loss compensation. Figure 20 shows a
asic application circuit (power supplies not shown) with
b
common-mode sync pulse extraction that is compatible with
the common-mode sync pulse encoding technique used in the
AD8134, AD8147, and AD8148 triple differential drivers. If
sy
nc extraction is not required, the terminations can be single
100 Ω resistors, and the comparator inputs can be left floating.
In
Figure 20, the AD8123 is feeding a high impedance input,
such as a
delay line or crosspoint switch, and the additional gain
of two that makes up for double termination loss is not required.
COMPARATORS
In addition to general-purpose applications, the two on-chip
comparators can be used to extract video sync pulses from the
received common-mode voltages or to receive differential digital
information. Built-in hysteresis helps to eliminate false triggers
from noise. The
secti
on describes the sync extraction details.
Sync Pulse Extraction Using Comparators
The comparator outputs have nearly 0 Ω output impedance and
re designed to drive source-terminated transmission lines. The
a
source termination technique uses a resistor in series with each
comparator output such that the sum of the comparator source
resistance (≈0 Ω) and the series resistor equals the transmission
line characteristic impedance. The load end of the transmission
line is high impedance. When the signal is launched into the source
termination, its initial value is one-half of its source value because
its amplitude is divided by two in the voltage divider formed by
the source termination and the transmission line. At the load,
the signal experiences nearly 100% positive reflection due to the
high impedance load and is restored to nearly its full value. This
technique is commonly used in PCB layouts that involve high
speed digital logic.
Figure 19 shows how to apply the comparators with source
t
ermination when driving a 50 Ω transmission line that is high
impedance at its receive end.
49.9
Ω
Z0 = 50Ω
HIGH-Z
06814-021
Figure 19. Using Comparator with Source Termination
26
V
PEAK
RED CMV
475Ω
27
V
POLE
25
V
GAIN
23
V
OFFSET
28
PD
31
32
34
35
37
38
2
3
8
7
47pF47pF
RED
GREEN
BLUE
1
2
GND REFERENCE
24, 39
AD8123
18
RED VIDEO OUT
15
GREEN VIDEO OUT
12
BLUE VIDEO O UT
4
HSYNC OUT
6
VSYNC OUT
06814-020
RECEIVED
RED VIDEO
RECEIVE D
GREEN VIDEO
RECEIVED
BLUE VIDEO
1kΩ
1kΩ
GREEN
ANALOG
CONTROL
INPUTS
POWER DOW N
CONTROL
49.9Ω
49.9Ω
49.9Ω
49.9Ω
49.9Ω
49.9Ω
BLUE CMV
CMV
Figure 20. Basic Application Circuit with Common-Mode Sync Extraction
Rev. A | Page 11 of 16
Page 12
AD8123
V
www.BDTIC.com/ADI
SYNC PULSE EXTRACTION USING COMPARATORS
The AD8123 is useful in many systems that transport computer
video signals, which are typically comprised of red, green, and
blue (RGB) video signals and separate horizontal and vertical
sync signals. Because the sync signals are separate and not
embedded in the color signals, it is advantageous to transmit
them using a simple scheme that encodes them among the three
common-mode voltages of the RGB signals. The
AD8147, and AD8148 t
riple differential drivers are natural
complements to the AD8123 because they perform the sync
pulse encoding with the necessary circuitry on-chip.
The sync encoding equations follow:
K
[
]
(1)
VRed
CM
VGreen
CM
VBlue
CM
HV
−=
2
K
[]
V22−=
K
[
HV
+=
2
(2)
(3)
]
where:
d V
Re
, Green VCM, and Blue VCM are the transmitted common-
CM
mode voltages of the respective color signals.
K is an adjustable gain constant that is set by the driver.
V and
H are the vertical and horizontal sync pulses, defined
with a weight of −1 when the pulses are in their low states, and a
weight of +1 when they are in their high states.
The AD8134 and AD8146/AD8147/AD8148 da
further details regarding the encoding scheme. Figure 20 illustrates
h
ow the AD8123 comparators can be used to extract the horizontal
and vertical sync pulses that are encoded on the RGB commonmode voltages by the aforementioned drivers.
USING THE V
The V
input is the main peaking control and is used to
PEAK
PEAK
, V
POLE
, V
GAIN
, AND V
compensate for the low-pass roll-off in the cable response. The
V
input is a secondary frequency response shaping control
POLE
that shifts the positions of the equalizer poles. The V
controls the wideband flat gain and is used to compensate for
the low frequency cable loss that is nominally flat. The V
input is used to produce an offset at the AD8123 output. The
output offset is equal to the voltage applied to the V
limited by the output swing limits.
The V
PEAK
and V
controls can be used independently or they
POLE
can be coupled to form a single peaking control. While Figure 17
a
nd Figure 18 show recommended settings vs. cable length,
desig
ners may find other combinations that they prefer. These
two controls give designers extra freedom, as well as the ability
to compensate for different cable types (such as UTP and coaxial
cable), as opposed to having only a single frequency shaping
control.
AD8134,
ta sheets contain
INPUTS
OFFSET
input
GAIN
OFFSET
input,
OFFSET
Rev. A | Page 12 of 16
In some cases, as would likely be with automatic control, the
V
control is derived from a low impedance source, such as
PEAK
an op amp. Figure 21 shows how to derive V
POLE
from V
PEAK
in a
UTP application according to the recommended curves shown
in Figure 17, when V
originates from a low impedance
PEAK
source. Clearly, the 5 V supply must be clean to provide a clean
V
voltage.
POLE
20Ω
V
PEAK
5V
V
Figure 21. Deriving V
PEAK
5.11kΩ
POLE
from V
The 20 Ω series resistor in the V
14kΩ
8.25kΩ
with Low-Z Source for UTP Cable
PEAK
path provides capacitive
PEAK
V
POLE
V
PEAK
≈
+ 0.9V
2
06814-026
load buffering for the op amp. This value can be modified,
depending on the actual capacitive load.
In automatic equalization circuits that place the control voltages
side feedback loops, attention must be paid to the poles
in
produced by the summing resistors and load capacitances.
The peaking can also be adjusted by a mechanical or digitally
ntrolled potentiometer. In these cases, if the resistance of the
co
potentiometer is a couple of orders of magnitude lower than the
values of the resistors used to develop V
, its resistance can be
POLE
ignored. Figure 22 shows how to use a 500 Ω potentiometer with
t
he resistor values shown in Figure 21 scaled up by a factor of 10.
5V
750Ω
500Ω
Figure 22. Deriving V
51.1kΩ
POLE
from V
PEAK
5V
140kΩ
82.5kΩ
with Potentiometer for UTP Cable
PEAK
V
POLE
V
PEAK
≈
+ 0.9V
2
06814-027
Many potentiometers have wide tolerances. If a wide tolerance
potentiometer is used, it may be necessary to change the value
of the 750 Ω resistor to obtain a full swing for V
The V
input is essentially a contrast control and can be set
GAIN
PEAK
.
by adjusting it to produce the correct amplitude of a known test
signal (such as a white screen) at the AD8123 output.
can also be derived from V
V
GAIN
according to the linear
PEAK
relationships shown in Figure 17 and Figure 18. Figure 23 shows
how
to derive V
POLE
and V
GAIN
from V
in a UTP application
PEAK
that originates from a low-Z source.
V
PEAK
Figure 23. Deriving V
POLE
5.11kΩ
5.11kΩ
and V
20Ω
GAIN
8.25kΩ
133kΩ
from V
V
5V
5V
PEAK
14kΩ
60.4kΩ
PEAK
V
POLE
GAIN
PEAK
≈
≈ 0.89 × V
V
V
with Low-Z Source for UTP Cable
+ 0.9V
2
+ 0.38V
PEAK
6814-028
Page 13
AD8123
www.BDTIC.com/ADI
USING THE AD8123 WITH COAXIAL CABLE
The V
types of cable, including coaxial cable. Figure 18 presents the
ecommended settings for V
r
AD8123 is used with good quality 75 Ω video cable. Figure 24
sho
cable application where V
Figure 24. Deriving V
The op amp in the circuit that develops V
insert the offset of −0.62 V with a gain from V
is close to unity. A passive offset circuit would require an offset
injection voltage that is much larger in magnitude than the
available −5 V supply. Clearly, the V
also be developed independently.
The AD8123 differential input can accept signals carried over
un
75 Ω co
control allows the AD8123 to be used with other
POLE
, V
ws how to derive V
V
+5V
PEAK
20kΩ
10kΩ
POLE
5.11kΩ
1.16kΩ
1.24kΩ
and V
PEAK
and V
POLE
originates from a low-Z source.
PEAK
20Ω
47.5kΩ
–5V
from V
GAIN
, and V
POLE
from V
GAIN
V
PEAK
24.3kΩ
V
≈ 0.76 × V
POLE
V
≈ 1.06 × V
GAIN
with Low-Z Source for Coaxial Cable
PEAK
control voltage can
GAIN
when the
GAIN
in a coaxial
PEAK
PEAK
PEAK
is required to
GAIN
to V
PEAK
– 0.41V
– 0.62V
GAIN
balanced cable, as shown in Figure 25, for an unbalanced
axial cable termination.
AD8123
INPUT FROM
75Ω CABLE
Figure 25. Terminating a 75 Ω Cable
75Ω
INPUT STAGE
06814-030
6814-029
that
DRIVING 75 Ω VIDEO CABLE WITH THE AD8123
When the RGB outputs must drive a 75 Ω line rather than a
high impedance load, an additional gain of two is required to
make up for the double termination loss (75 Ω source and load
terminations). There are two options available for this.
One option is to place the additional gain of 2 at the drive end
by
using the AD8148 triple differential driver to drive the cable.
The AD8148 has a fixed gain of 4 instead of the usual gain of 2
a
nd thereby provides the required additional gain of 2 without
having to add additional amplifiers to the signal chain. The
AD8148 also contains sync-on-common-mode encoding. If
nc-on-common-mode is not required, it can be deactivated
sy
on the
AD8148 by connecting its SYNC LEVEL input to ground.
The other option is to include a triple gain-of-2 buffer, such as the
ADA4862-3, on the AD8123 RGB outputs, as shown in Figure 26
f
or one channel (power supplies not shown). The ADA4862-3
p
rovides the gain of 2 that compensates for the double-
termination loss.
ONE VIDEO
OUTPUT
FROM AD8123
ONE CHANNEL OF ADA4862-3
75
Ω
500
Ω
500
Ω
Figure 26. Using ADA4862-3 on AD8123 Outputs
Z0 = 75Ω
75Ω
DRIVING A CAPACITIVE LOAD
When driving a high impedance capacitive input, it is necessary
to place a small series resistor between each of the three AD8123
video outputs and the load to buffer the input capacitance of the
device being driven. Clearly, the resistor value must be small
enough to preserve the required bandwidth.
FILTERING THE RGB OUTPUTS
In some cases, it is desirable to place low-pass filters on the
AD8123 video outputs to reduce high frequency noise. A 3-pole
Butterworth filter with cutoff frequency in the neighborhood of
140 MHz is sufficient in most applications.
resent filters for the high impedance load case (driving a delay
p
line, crosspoint switch, ADA4862-3) and the double-termination
cas
e (75 Ω source and load resistances), respectively. In the high
impedance load case, the load capacitance must be absorbed in
the capacitor that is placed across the load. For example, in
Figure 27, if the high-Z load were the input to an ADA4862-3,
which has a
n input capacitance of 2 pF, the filter capacitor value
in parallel with the input would be 15 pF to obtain 17 pF.
150nH
100
AD8123
OUTPUT
*INPUT CAPACITANCE OF LOAD MUST BE
ABSORBED INTO THIS VALUE.
Figure 27. 140 MHz Low-Pass Filter on AD8123 Output Feeding High-Z Load
Ω
5.6pF 17pF*
180nH
75
AD8123
OUTPUT
Figure 28. 135 MHz Low-Pass Filter on AD8123 Output Feeding
Ω Z0 = 75Ω
15pF 15pF
Doub
ly Terminated Load
These filters are by no means the only choices but are presented
here as examples. In the high-Z load case, it is important to
keep the filter source resistance large enough to buffer the
capacitive loading presented by the first capacitor in the filter.
Figure 27 and Figure 28
HIGH-Z
06814-023
75Ω
06814-024
06814-022
Rev. A | Page 13 of 16
Page 14
AD8123
www.BDTIC.com/ADI
POWER SUPPLY FILTERING
External power supply filtering between the system power
supplies and the AD8123 is required in most applications to
prevent supply noise from contaminating the received signal as
well as to prevent unwanted feedback through the supplies that
could cause instability.
upply rejection decreases with increasing frequency. These
s
plots are for the lowest control settings and shift upward as the
peaking is increased.
10
V
GAIN
V
PEAK
V
POLE
0
–10
–20
–30
PSRR (dB)
–40
–50
–60
100k 1M 10M 100M
A suitable filter that uses a surface-mount ferrite bead is shown
in Figure 30, and its frequency response is shown in Figure 31.
ecause the frequency response was taken using a 50 Ω network
B
analyzer and with only one 0.1 μF capacitor on the AD8123
side, the actual amount of rejection provided by the filter in a
real-world application will be different from that shown in
Figure 31. The general shape of the rejection curve, however,
tches Figure 31, providing substantially increased overall
ma
PS
RR from approximately 5 MHz to 500 MHz, where it is most
needed. One filter is required on each of the two supplies (not one
filter per supply pin).
SYSTEM
SUPPLY
Figure 29 shows that the AD8123 power
= 0V
= 0V
= 0V
FREQUENCY (Hz)
Figure 29. AD8123 PSRR vs. Frequency
FAIR-RITE
2743021447
TO AD8123*
0.1µF 4700pF 4700pF
+PSRR
–PSRR
06814-017
0
–20
–40
–60
–80
OUTPUT RESPONSE (dB)
–100
–120
10k 100k 1M 10M 100M
FREQUENCY (Hz )
Figure 31. Power Supply Filter Frequency Respo
nse in a 50 Ω System
06814-018
LAYOUT AND POWER SUPPLY DECOUPLING CONSIDERATIONS
Standard high speed PCB layout practices should be adhered
to when designing with the AD8123. A solid ground plane is
required and controlled impedance traces should be used when
interconnecting the high speed signals. Source termination
resistors on all of the outputs must be placed as close as possible
to the output pins.
The exposed paddle on the underside of the AD8123 must be
co
nnected to a pad that connects to at least one PCB plane.
Several thermal vias should be used to make the connection
between the pad and the plane(s).
High quality 0.1 μF power supply decoupling capacitors should
be p
laced as close as possible to all of the supply pins. Small
surface-mount ceramic capacitors should be used for these, and
tantalum capacitors are recommended for bulk supply decoupling.
*ALL AD8123 SUPPL Y PINS ARE INDI VIDUALLY
DECOUPLED WITH A 0.1µF CAPACI TOR.
Figure 30. Power Supply Filter
06814-031
Rev. A | Page 14 of 16
Page 15
AD8123
www.BDTIC.com/ADI
INPUT COMMON-MODE RANGE
Most applications that use the AD8123 as a receiver use a driver
(
such as one from the AD8146/AD8147/AD8148 family, the
AD8133, or the AD8134) powered from ±5 V supplies. This
places t
he common-mode voltage on the line nominally at 0 V
relative to the ground potential at the driver and provides optimum
immunity from any common-mode anomalies picked up along
the cable (including ground shifts between the driver and receiver
ends). In many of these applications, the AD8123 input voltage
range of typically ±3.0 V is sufficient. If wider input range is
required, the
nge equals ±10.5 V on ±12 V supplies) may be placed in front of
ra
the AD8123. Figure 32 illustrates how this is done for one channel.
RECEIVED
The Schottky diodes are required to protect the AD8123 from
any AD8143 o
The 49.9 Ω resistor limits the fault current and produces a pole
at approximately 800 MHz with the effective diode capacitance of
3 pF and the AD8123 input capacitance of 1 pF. The pole drops
the response by only 0.07 dB at 100 MHz and therefore has a
negligible effect on the signal.
When using a single 5 V supply on the driver side, the commonm
ode voltage at the driver is typically midsupply, or V
The largest received differential video signal is approximately
700 mV p-p, and this therefore adds 175 mV
mode voltage, resulting in a worst-case peak voltage of 2.675 V
on an AD8123 input (presuming there is no ground shift between
driver and receiver). This is within the AD8123 input voltage
swing limits, and such a system works well as long as the difference
in ground potential between driver and receiver does not cause
the input voltage swing to exceed its specified limits.
AD8143 triple receiver (input common-mode
ONE AD8143 CHANNE L
POWER SUPPLIES = ±12V
SIGNAL
100Ω
49.9Ω
HBAT-540C
Figure 32. Optional Use of AD8143 in Front of AD8123 for
Wide Input Common-Mode Range
ONE AD8123
2
3
1
utputs that may exceed the AD8123 input limits.
to the common-
PEAK
INPUT
+5V
–5V
= 2.5 V.
CM
06814-033
When used, common-mode sync signals are generally applied
with a peak deviation of 500 mV and thereby increase the
common-mode level from 2.675 V to 3.175 V. This commonmode level exceeds the specified input voltage swing limits of
±3.0 V; therefore, the AD8123 cannot be used with a system
that uses common-mode sync encoding with 500 mV sync peak
deviation and 2.5 V common-mode line level. While it is possible
to operate a driver powered from a single 5 V supply at a commonmode voltage of <2.5 V to obtain a received voltage swing that is
within the specified limits, there is not much margin for other
shifts in the common-mode level due to interference pickup and
differing ground potentials. There are two ways to increase the
common-mode range of the overall system. One is to power the
driver from ±5 V supplies, and the other is to place an
n front of the AD8123, as shown in Figure 32. These techniques
i
ma
y be combined or applied separately.
AD8143
SMALL SIGNAL FREQUENCY RESPONSE
Though the AD8123 large signal frequency response
= 1 V p-p) is of most concern, occasionally designers are
(V
O
interested in the small signal frequency response. The AD8123
frequency response for V
= 300 m V p-p is shown in Figure 33
O
for 200 meter and 300 meter cable lengths.
3
VO = 300mV p-p
2
1
0
–1
–2
–3
–4
–5
GAIN (dB)
–6
–7
–8
–9
–10
–11
–12
Figure 33. Small Signal Frequency Response for Various Cable Lengths
0.1 1 10 1000.01
FREQUENCY (MHz)
300 METERS
200 METERS
06814-032
POWER-DOWN
The power-down feature is intended to be used to reduce power
consumption when a particular device is not in use and does
not place the output in a high-Z state when asserted. The input
logic levels and supply current in power-down mode are presented
in the Power Supply section of
Tabl e 1.
Rev. A | Page 15 of 16
Page 16
AD8123
S
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
6.00
INDICATOR
1.00
0.85
0.80
EATING
PLANE
PIN 1
12° MAX
BSC SQ
TOP
VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
5.75
BCS SQ
0.20 REF
0.60 MAX
0.05 MAX
0.02 NOM
COPLANARIT Y
0.08
0.50
BSC
0.50
0.40
0.30
Figure 34. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm
× 6 mm, Very Thin Quad
(CP-40-4)
Dimensions shown in millimeters
0.60 MAX
29
28
EXPOSED
(BOT TOM V IEW)
20
19
PAD
4.50
REF
40
11
PIN 1
INDICATOR
1
4.45
4.30 SQ
4.15
10
0.25 MIN
080107-A
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD8123ACPZ
AD8123ACPZ-R7
AD8123ACPZ-RL
1
Z = RoHS Compliant Part.
1
1
1
−40°C to +85°C 40-Lead LFCSP_VQ CP-40-4
−40°C to +85°C 40-Lead LFCSP_VQ CP-40-4
−40°C to +85°C 40-Lead LFCSP_VQ CP-40-4
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06814-0-11/07(A)
Rev. A | Page 16 of 16
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