Page 1
Audio/Video, 60 MHz, 16 × 8,
www.BDTIC.com/ADI
FEATURES
Low cost, 16 × 8, high speed, nonblocking switch array
Pin-compatible 16 × 16 version available (AD8113)
Serial or parallel programming of switch array
Serial data out allows daisy chaining control of multiple
16 ×
8 arrays to create larger switch arrays
Output disable allows connection of multiple devices
without loadin
Complete solution
Buffered inputs
8 output amplifiers
Operates on ±5 V or ±12 V supplies
Low supply current of 54 mA
Excellent audio performance V
±10 V output swing
0.002% THD at 20 kHz maximum 20 V p-p (R
Excellent video performance V
0.1 dB gain flatness of 10 MHz
0.1% differential gain error (R
0.1° differential phase error (R
Excellent ac performance
−3 dB bandwidth 60 MHz
Low all-hostile crosstalk of −83 dB at 20 kHz
Reset pin allows disabling of all outputs (connected to a
c
apacitor to ground provides power-on reset capability)
100-lead LQFP (14 mm × 14 mm)
APPLICATIONS
CCTV sur veillance/DVR
Analog/digital audio routers
Video routers (NTSC, PAL, S-Video, SECAM)
Multimedia systems
Video conferencing
g the output bus
= ±12 V
S
= ±5 V
S
L
= 1 kΩ)
= 1 kΩ)
L
= 600 Ω)
L
Gain of +2 Crosspoint Switch
AD8112
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4
SER/PAR
A0
A1
CLK
DATA IN
UPDATE
RESET
CE
80-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL L OADING
40 40
PARALLEL L ATCH
40
DECODE
8 × 5:16 DECODERS
AD8112
16 INPUTS
SWITCH
MATRIX
Figure 1.
128
CONNECT
OUTPUT
BUFFER
G = +2
NO
8
A2
DATA
OUT
TO OFF
SET INDIVIDUAL OR
RESET ALL OUTPUTS
ENABLE/DISABL E
8 OUTPUTS
06523-001
GENERAL DESCRIPTION
The AD8112 is a low cost, fully buffered crosspoint switch matrix
that operates on ±12 V for audio applications and ±5 V for
video applications. It offers a −3 dB signal bandwidth greater
than 60 MHz and channel switch times of less than 60 ns with
0.1% settling for use in both analog and digital audio. The
AD8112 operated at 20 kHz has a crosstalk performance of
−83 dB and isolation of 90 dB. In addition, ground/power pins
surround all inputs and outputs to provide extra shielding for
operation in the most demanding audio routing applications.
With a differential gain and differential phase better than 0.1%
and 0.1°, respectively, and a 0.1 dB flatness output of up to 10 MHz,
The AD8112 includes eight independen
be placed into a disabled state for paralleling crosspoint outputs
so that off channel loading is minimized. The AD8112 has a gain
of +2. It operates on voltage supplies of ±5 V or ±12 V while
consuming only 34 mA or 31 mA of current, respectively. The
channel switching is performed via a serial digital control (which
can accommodate the daisy chaining of several devices) or via
a parallel control, allowing updating of an individual output
without reprogramming the entire array.
The AD8112 is packaged in a 100-lead LQFP and is available
ver the commercial temperature range of 0°C to 70°C.
o
the AD8112 is suitable for many video applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
t output buffers that can
Page 2
AD8112
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features.............................................................................................. 1
Calculation of Power Dissipation............................................. 17
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics (Serial) .................................................. 5
Timing Characteristics (Parallel) ............................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Power Dissipation......................................................................... 7
Pin Configuration and Function Descriptions............................. 9
I/O Schematics............................................................................ 11
Typical Performance Characteristics ........................................... 12
Theory of Operation ...................................................................... 17
Short-Circuit Output Conditions............................................. 18
Application Notes........................................................................... 19
Serial Programming................................................................... 19
Parallel Programming................................................................ 19
Power-On Reset.......................................................................... 20
Specifying Audio Levels ............................................................ 20
Creating Unity-Gain Channels................................................. 20
Video Signals............................................................................... 20
Creating Larger Crosspoint Arrays.......................................... 21
Multichannel Video and Audio................................................ 23
Crosstalk...................................................................................... 23
PCB Layout...................................................................................... 26
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
2/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Page 3
AD8112
www.BDTIC.com/ADI
SPECIFICATIONS
TA = 25°C, VS = ±12 V, RL = 600 Ω, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth V
V
V
V
Gain Flatness 0.1 dB, V
Propagation Delay V
Settling Time 0.1%, 2 V Step, RL = 150 Ω, VS = ±5 V 23 ns
Slew Rate 2 V step, RL = 150 Ω, VS = ±5 V 100 V/μs
20 V step, RL = 600 Ω, VS = ±12 V 120 V/μs
NOISE/DISTORTION PERFORMANCE
Differential Gain Error NTSC, RL = 1 kΩ, VS = ±5 V 0.1 %
Differential Phase Error NTSC, RL = 1 kΩ, VS = ±5 V 0.1 Degrees
Total Harmonic Distortion 20 kHz, RL = 600 Ω, 20 V p-p 0.002 %
Crosstalk, All Hostile f = 5 MHz, RL = 150 Ω, VS = ±5 V −67 dB
f = 20 kHz −83 dB
Off Isolation f = 5 MHz, RL = 150 Ω, VS = ±5 V, one channel −100 dB
f = 20 kHz, one channel −83 dB
Input Voltage Noise 20 kHz 14 nV/√Hz
0.1 MHz to 10 MHz 12 nV/√Hz
DC PERFORMANCE
Gain Error No load, VS = ±12 V, V
R
R
Gain Matching No load, channel-to-channel 0.7 3.5 %
R
R
Gain Temperature Coefficient 20 ppm/°C
OUTPUT CHARACTERISTICS
Output Resistance Enabled 0.3 Ω
Disabled 3.4 4 kΩ
Output Capacitance Disabled 5 pF
Output Voltage Swing VS = ±5 V, no load ±3.2 ±3.5 V
V
I
I
Short-Circuit Current RL = 0 Ω 55 mA
INPUT CHARACTERISTICS
Input Offset Voltage All configurations ±4.5 ±8.5 mV
Temperature coefficient 10 μV/°C
Input Voltage Range No load, VS = ±5 V ±1.5 V
V
Input Capacitance Any switch configuration 4 pF
Input Resistance 50 MΩ
Input Bias Current Any number of enabled inputs +1 ±1.6 μA
= 200 mV p-p, RL = 600 Ω, VS = ±12 V 46 60 MHz
OUT
= 200 mV p-p, RL = 150 Ω, VS = ±5 V 41 60 MHz
OUT
= 8 V p-p, RL = 600 Ω, VS = ±12 V 10 MHz
OUT
= 2 V p-p, RL = 150 Ω, VS = ±5 V 25 MHz
OUT
= 200 mV p-p, RL = 150 Ω, VS = ±5 V 10 MHz
OUT
= 2 V p-p, RL = 150 Ω 20 ns
OUT
= ±8 V 0.3 2.5 %
OUT
= 600 Ω, VS = ±12 V 0.5 %
L
= 150 Ω, VS = ±5 V 0.5 %
L
= 600 Ω, channel-to-channel 0.7 %
L
= 150 Ω, channel-to-channel 0.7 %
L
= ±12 V, no load ±10.3 ±10.5 V
S
= 20 mA, VS = ±5 V ±2.7 ±3 V
OUT
= 20 mA, VS = ±12 V ±9.8 ±10 V
OUT
= ±12 V ±5.0 V
S
Rev. 0 | Page 3 of 28
Page 4
AD8112
www.BDTIC.com/ADI
Parameter Conditions Min Typ Max Unit
SWITCHING CHARACTERISTICS
Enable On Time 80 ns
Switching Time, 2 V Step 50% update to 1% settling 50 ns
Switching Transient (Glitch) 20 mV p-p
POWER SUPPLIES
Supply Current AVCC outputs enabled, no load, VS = ±12 V 50 54 mA
AVCC outputs disabled, VS = ±12 V 34 38 mA
AVCC outputs enabled, no load, VS = ±5 V 45 50 mA
AVCC outputs disabled, VS = ±5 V 31 35 mA
AVEE outputs enabled, no load, VS = ±12 V 50 54 mA
AVEE outputs disabled, VS = ±12 V 34 38 mA
AVEE outputs enabled, no load, VS = ±5 V 45 50 mA
AVEE outputs disabled, VS = ±5 V 31 35 mA
DVCC outputs enabled, no load 8 13 mA
DYNAMIC PERFORMANCE
Supply Voltage Range AVCC 4.5 12.6 V
AVEE −12.6 −4.5 V
DVCC 4.5 5.5 V
PSRR DC 75 80 dB
f = 100 kHz 60 dB
f = 1 MHz 40 dB
OPERATING TEMPERATURE RANGE
Temperature Range Operating (still air) 0 to 70 °C
θJA Operating (still air) 40 °C/W
Rev. 0 | Page 4 of 28
Page 5
AD8112
www.BDTIC.com/ADI
TIMING CHARACTERISTICS (SERIAL)
Table 2.
Limit
Parameter Symbol Min Typ Max Unit
Serial Data Setup Time t1 20 ns
CLK Pulse Width t2 100 ns
Serial Data Hold Time t3 20 ns
CLK Pulse Separation, Serial Mode t4 100 ns
t
CLK to UPDATE Delay
UPDATE Pulse Width
CLK to DATA OUT Valid, Serial Mode t7 200 ns
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode 16 μs
CLK, UPDATE Rise and Fall Times
RESET Time
0 ns
5
t
50 ns
6
50 ns
100 ns
200 ns
CLK
DATA IN
1 = LATCHED
UPDATE
0 = TRANSPARENT
DATA OUT
t
1
0
t1t
1
0
2
3
t
7
t
4
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
TRANSFER DATA FROM SERIAL
LATCHES DURING LOW LEVEL
Figure 2. Timing Diagram, Serial Mode
OUT00 (D0)OUT07 (D3)OUT07 (D4)
t
5
REGISTER TO PARALLEL
t
6
6523-002
Table 3. Logic Levels
Pins VIH V
RESET, SER/PAR,
CLK, DATA IN, CE
2.0 V min 0.8 V max 20 μA max −400 μA min
,
VOH VOL IIH IIL IOH IOL
IL
UPDATE
DATA OUT 2.7 V min 0.5 V max −400 μA max 3.0 mA min
Rev. 0 | Page 5 of 28
Page 6
AD8112
0
www.BDTIC.com/ADI
TIMING CHARACTERISTICS (PARALLEL)
Table 4.
Limit
Parameter Symbol Min Max Unit
Data Setup Time t1 20 ns
CLK Pulse Width t2 100 ns
Data Hold Time t3 20 ns
CLK Pulse Separation t4 100 ns
t
CLK to UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On or Off
CLK, UPDATE Rise and Fall Times
RESET Time
0 ns
5
t
50 ns
6
50 ns
100 ns
200 ns
t
4
Figure 3. Timing Diagram, Parallel Mode
t
5
t
6
6523-003
CLK
D0 TO D4
A0 TO A2
1=LATCHED
UPDATE
= TRANSPARENT
t
1
0
1
0
t
1
2
t
3
Table 5. Logic Levels
Pins VIH V
RESET, SER/PAR,
2.0 V min 0.8 V max 20 μA max −400 μA min
VOH VOL IIH IIL IOH IOL
IL
CLK, D0, D1, D2,
D3, D4, A0, A1, A2,
CE, UPDATE
DATA OUT 2.7 V min 0.5 V max −400 μA max 3.0 mA min
Rev. 0 | Page 6 of 28
Page 7
AD8112
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Analog Supply Voltage (AVCC to AVEE) 26.0 V
Digital Supply Voltage (DVCC to DGND) 6 V
Ground Potential Difference (AGND to DGND) ±0.5 V
Internal Power Dissipation
Analog Input Voltage
Digital Input Voltage DVCC
Output Voltage (Disabled Output) (AVCC − 1.5 V) to
Output Short-Circuit Duration Momentary
Storage Temperature Range −65°C to +125°C
Lead Temperature (Soldering 10 sec) 300°C
1
Specification is for device in free air (TA = 25°C):
100-lead plastic LQFP (ST): θJA = 40°C/W.
2
To avoid differential input breakdown, ensure that one-half the output
voltage (1/2 V
differential. See Output Voltage Swing specification for linear output range.
) and any input voltage is less than 10 V of the potential
OUT
1
2
3.1 W
Maintain linear output
+ 1.5 V)
(AV
EE
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
POWER DISSIPATION
The AD8112 is operated with ±5 V to ±12 V supplies and can
drive loads down to 150 Ω (±5 V) or 600 Ω (±12 V), resulting
in a large range of possible power dissipations. For this reason,
extra care must be taken when derating the operating conditions
based on ambient temperature.
Packaged in a 100-lead LQFP, the AD8112 junction-to-ambient
hermal impedance (θ
t
the maximum allowed junction temperature of the plastic encapsulated die should not exceed 150°C. Temporarily exceeding
this limit may cause a shift in parametric performance due
to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure. The curve in
he range of allowed power dissipations that meet these conditions
t
over the commercial range of ambient temperatures.
4.0
3.5
3.0
) is 40°C/W. For long-term reliability,
JA
Figure 4 shows
TJ= 150°C
ESD CAUTION
MAXIMUM POWER (W)
2.5
2.0
0 1020304050607
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
AMBIENT T EMPERATURE (°C)
06523-004
0
Rev. 0 | Page 7 of 28
Page 8
AD8112
www.BDTIC.com/ADI
Table 7. Operation Truth Table
CE
UPDATE
CLK DATA IN DATA OUT
RESET
1 X X X X X X No change in logic.
0 1
0 1
Data
Data
i
D0 ... D4,
A0 ... A2
1 0
i-80
N/A in
Parallel
1 1
Mode
0 0 X X X 1 X
X X X X X 0 X
D0
DATA
D1
D2
D3
D4
D
CLK
S
D1
Q
Q
D0
S
D1
Q
D0
S
D1
D
QDQDQDQDQ DQ DQ DQ DQDQDQ
Q
D0
CLK
S
D1
Q
D0
CLK CLK CLK
S
D1
Q
D0
PARALLEL
(OUTPUT
ENABLE)
SER/PAR
DATA IN
(SERIAL)
SER
D1
D0
/PAR
S
Q
CLK
Operation/Comment
The data on the serial DATA IN line is loaded into serial register.
he first bit clocked into the serial register appears at DATA OUT
T
80 clocks later.
The data on the parallel data lines, D0 to D4, is loaded into the
80-bit serial shift register location addressed by A0 to A2.
Data in the 80-bit shift register transf
ers into the parallel
latches that control the switch array. Latches are transparent.
Asynchronous operation. All out
puts are disabled. Remainder
of logic is unchanged.
CLK
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
CLK CLK CLK CLK
S
D1
Q
D0
S
D1
Q
D0
CLK
S
D1
Q
D0
DATA OUT
CLK
CE
UPDATE
OUT00 EN
OUT01 EN
OUT02 EN
OUTPUT
ADDRESS
OUT03 EN
OUT04 EN
A0
OUT05 EN
A1
3-TO- 16 DECODE R
OUT06 EN
A2
OUT07 EN
(OUTPUT ENABLE)
RESET
OUT00
B0
DLE
Q
OUT00
B1
DLE
Q
OUT00
B2
DLE
Q
OUT00
B3
DLE
Q
DLE
OUT00
EN
QCLR
128
SWITCH MATRIX
OUT01
B0
DLE
Q
DECODE
OUT06
EN
DLE
QCLR
OUT07
B0
DLE
Q
DLE
OUT07
B1
Q
OUTPUT ENABLE
OUT07
B2
DLE
Q
8
OUT07
B3
DLE
Q
OUT07
EN
DLE
QCLR
06523-005
Figure 5. Logic Diagram
Rev. 0 | Page 8 of 28
Page 9
AD8112
www.BDTIC.com/ADI
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESETCEDATA OUT
CLK
DATA IN
UPDATE
100
SER/PARNCNCNCNCNCNCNCNCNCA0A1A2
99
97
98
93
95
96
929190
94
8988878685
84
83
82
DGNDD0D1D2D3
797877
81
80
D4
76
1
DV
CC
2
DGND
3
AGND
4
IN08
5
AGND
6
IN09
7
AGND
8
IN10
9
AGND
10
IN11
11
AGND
12
IN12
13
AGND
14
IN13
15
AGND
16
IN14
17
AGND
18
IN15
19
AGND
20
AV
EE
21
AV
CC
22
AV
CC
23
NC
24
AV
EE
25
NC
NC = NO CO NNECT
PIN 1
26
CC
AV
75
DV
CC
74
DGND
73
AGND
72
IN07
71
AGND
70
IN06
69
AGND
68
IN05
67
AGND
66
IN04
65
AD8112
TOP VIEW
(Not to Scale)
45
48
03/04
AV
49
47
02/03
OUT03
OUT02
EE
CC
AV
27
28
NC
AV
29
30
EE
CC
NC
AV
31NC32
AV
34
33
EE
NC
AV
36
35
EE
CC
NC
AV
37NC38
AV
40
41
42
39
CC
06/07
05/06
OUT06
OUT07
EE
CC
AV
AV
46
43
44
04/05
OUT05
OUT04
EE
AV
AGND
64
IN03
63
AGND
62
IN02
61
AGND
60
IN01
59
AGND
58
IN00
57
AGND
56
AV
EE
55
AV
CC
54
AVCC00
53
OUT00
52
AVEE00/01
51
OUT01
50
01/02
CC
AV
06523-006
Figure 6. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
58, 60, 62, 64, 66, 68, 70, 72, 4, 6, 8, 10,
IN00 to IN15
1
Analog Inputs for Channel Numbers 00 through 15.
12, 14, 16, 18
96 DATA IN Serial Data Input, TTL-compatible.
97 CLK Clock, TTL-compatible. Falling edge triggered.
98 DATA OUT Serial Data Output, TTL-compatible.
95
UPDATE
Enable (Transparent) Low. Allows serial register to connect directly to switch
matrix. Data latched when high.
100
99
94
RESET
CE
/PAR Serial Data/Parallel Data. When low, this pin selects serial data mode; when
SER
Disable Outputs, Active Low.
Chip Enable, Enable Low. Must be low to clock in and latch data.
high, this pin selects parallel data mode, high. Must be connected.
53, 51, 49, 47, 45, 43, 41, 39
3, 5, 7, 9, 11, 13, 15, 17, 19, 57, 59, 61, 63,
OUT00 to
1
07
OUT
AGND Analog Ground for Inputs and S
Analog Outputs for Channel Numbers 00 Through 07.
witch Matrix. Must be connected.
65, 67, 69, 71, 73
1, 75 DVCC 5 V for Digital Circuitry.
2, 74, 81 DGND Ground for Digital Circuitry.
20, 24, 28, 32, 36, 56 AVEE −5 V for Inputs and Switch Matrix.
Rev. 0 | Page 9 of 28
Page 10
AD8112
www.BDTIC.com/ADI
Pin No. Mnemonic Description
21, 22, 26, 30, 34, 38, 55 AVCC 5 V for Inputs and Switch Matrix.
54 AVCCxx
50, 46, 42 AVCCxx/yy1
52, 48, 44, 40 AVEExx/yy1
84 A0 Parallel Data Input, TTL-compatible (Output Select LSB).
83 A1 Parallel Data Input, TTL-compatible (Output Select).
82 A2 Parallel Data Input, TTL-compatible (Output Select).
80 D0 Parallel Data Input, TTL-compatible (Input Select LSB).
79 D1 Parallel Data Input, TTL-compatible (Input Select).
78 D2 Parallel Data Input, TTL-compatible (Input Select).
77 D3 Parallel Data Input, TTL-compatible (Input Select MSB).
76 D4 Parallel Data Input, TTL-compatible (Output Enable).
23, 25, 27, 29, 31, 33, 35, 37, 85 to 93 NC No Connect.
1
xx = Chanel numbers 00 through 15 for analog inputs; yy = channel numbers 00 through 07 for analog outputs.
5 V for Output Amplifier. This pin is shared by Channel Numbers xx and yy.
Must be connected.
5 V for Output Amplifier. This pin is shared by Channel Numbers xx and yy.
Must be connected.
−5 V for Output Amplifier. This pin is shared by Channel Numbers xx and yy.
Must be connected.
Rev. 0 | Page 10 of 28
Page 11
AD8112
V
V
V
V
V
www.BDTIC.com/ADI
I/O SCHEMATICS
CC
ESD
INPUT
ESD
AV
Figure 7. Analog Input
CC
ESD
ESD
AV
EE
Figure 8. Analog Output
CC
ESD
RESET
ESD
CC
ESD
INPUT
ESD
EE
06523-007
DGND
06523-010
Figure 10. Logic Input
CC
OUTPUT
2k
06523-008
DGND
ESD
ESD
OUTPUT
06523-011
Figure 11. Logic Output
20k
DGND
06523-009
Figure 9. Reset Input
Rev. 0 | Page 11 of 28
Page 12
AD8112
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
3
0
GAIN (dB)
–3
–6
0.01 0.1 1 10 100
FREQUENCY (M Hz)
Figure 12. Small-Signal Bandwidth, V
0.3
0.2
0.1
0
–0.1
GAIN FLATNESS (dB)
–0.2
–0.3
0.1 1 10 100
FREQUENCY (MHz)
Figure 13. Small-Signal Gain Flatness, V
= ±5 V, RL = 150 Ω, V
S
= ±5 V, RL = 150 Ω, V
S
= 200 mV p-p
OUT
= 200 mV p-p
OUT
3
0
GAIN (dB)
–3
06523-013
06523-014
–6
0.1 100101
FREQUENCY (MHz)
Figure 15. Small-Signal Bandwidth, V
0.3
0.2
0.1
0
–0.1
GAIN FLATNESS (dB)
–0.2
–0.3
0.1 100101
FREQUENCY (MHz)
= ±12 V, R
S
= 600 Ω, V
L
OUT
06523-047
= 200 mV p-p
06523-048
Figure 16. Small-Signal Gain Flatness, V
= ±12 V, RL = 600 Ω, V
S
= 200 mV p-p
OUT
3
0
GAIN (dB)
–3
–6
0.1 1 10 100
Figure 14. Large-Signal Bandwidth, V
FREQUENCY (MHz)
= ±5 V, R
S
= 150 Ω, V
L
= 2 V p-p
OUT
06523-015
3
0
GAIN (dB)
–3
–6
0.1 100101
FREQUENCY ( MHz)
Figure 17. Large-Signal Bandwidth, V
Rev. 0 | Page 12 of 28
= ±12 V, RL = 600 Ω, V
S
= 8 V p-p
OUT
06523-049
Page 13
AD8112
–
–
–
–
www.BDTIC.com/ADI
0.3
0.3
0.2
0.1
0
–0.1
GAIN FLATNESS (dB)
–0.2
–0.3
0.1 1 10 100
Figure 18. Large-Signal Gain Flatness, V
40
–50
–60
–70
–80
CROSSTALK (dB)
FREQUENCY (MHz )
= ±5 V, RL = 150 Ω, V
S
ALL HOSTI LE
OUT
ADJACENT
06523-016
= 2 V p-p
0.2
0.1
0
–0.1
GAIN FLAT NESS (dB)
–0.2
–0.3
0.1 101
FREQUENCY ( MHz)
Figure 21. Large-Signal Gain Flatness, V
30
–40
ALL HOST ILE
–50
–60
CROSSTALK (d B)
–70
= ±12 V, R
S
ADJACENT
= 600 Ω, V
L
= 8 V p-p
OUT
06523-050
–90
–100
Figure 19. Crosstalk vs. Frequency, V
50
–60
–70
SECOND HARMONIC
–80
DISTORTION (dBc)
–90
–100
–110
0.001 0.01 0.1 1 10 100
Figure 20. Distortion vs. Frequency, V
10.1 10 100
FREQUENCY (MHz)
= ±5 V, RL = 150 Ω, V
S
THIRD HARMONIC
FREQUENCY (MHz)
= ±5 V, R
S
= 150 Ω, V
L
= 2 V p-p
OUT
= 2 V p-p
OUT
–80
06523-017
06523-018
–90
0.01 0. 1 1 10 100
Figure 22. Crosstalk vs. Frequency, V
70
–75
–80
–85
SECOND HARMONIC
0.001 0.01 0.1 1
DISTORT ION (dBc)
–100
–105
–90
–95
Figure 23. Distortion vs. Frequency, V
FREQUENCY (MHz)
= ±12 V, RL = 600 Ω, V
S
THIRD HARMONIC
FREQUENCY (MHz)
= ±12 V, RL = 600 Ω, V
S
OUT
OUT
06523-051
= 20 V p-p
06523-052
= 20 V p-p
Rev. 0 | Page 13 of 28
Page 14
AD8112
V
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300
250
200
V
150
100
CAPACITIVE L OAD (pF )
50
0
0 5 10 15 20 25 30 35
SERIES RESISTANCE ()
R
=±12V
S
= 600
L
V
R
S
L
=±5V
= 150
06523-019
Figure 24. Capacitive Load vs. Series Resistance for Less than 30% Overshoot
10k
1k
100
IMPEDANCE ()
10
INPUT
5ns/DIV
OUTPUT
2
– INPUT
= ±5 V, R
S
= 150 Ω
L
0.1%/DI
OUTPUT
0 5 10 15 20 25 30 35 40 45 50
Figure 27. Settling Time to 0.1%, 2 V Step, V
10k
1k
100
IMPEDANCE ()
10
06523-022
1
0.1 1 10 100 1k
FREQUENCY (MHz)
Figure 25. Disabled Output Impedance vs. Frequency, V
1k
100
10
IMPEDANCE ()
1
0.1
0.1 1 10 100 1k
Figure 26. Enabled Output I
FREQUENCY (MHz)
mpedance vs. Frequency, V
= ±5 V
S
= ±5 V
S
06523-020
1
FREQUENCY (MHz)
100 1k0.1 1 10
Figure 28. Disabled Output Impedance vs. Frequency, V
1k
100
10
IMPEDANCE ()
1
06523-021
0.1
0.1 1 10 100 1k
FREQUENCY (MHz)
Figure 29. Enabled Output Impedance vs. Frequency, V
S
= ±12 V
S
= ±12 V
06523-053
06523-054
Rev. 0 | Page 14 of 28
Page 15
AD8112
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0
–10
–20
–30
–40
–50
PSRR (dB)
–60
–70
–80
–90
0.01 0.1 1 10
Figure 30. PSRR vs. Frequency, V
+PSRR
–PSRR
FREQUENCY (MHz)
= ±5 V
S
06523-023
PSRR (d B)
–20
–40
–60
–80
–100
0
FREQUENCY (MHz)
Figure 33. PSRR vs. Frequency, V
+PSRR
–PSRR
= ±12 V
S
06523-055
1010.10.01
160
140
120
100
80
60
NOISE (n V/ Hz)
40
20
0
10 100 1k 10k 100 k 1M 10M
FREQUENCY (Hz)
Figure 31. Noise vs. Frequency
50mV/DIV
0
–20
–40
= ±12V
V
–60
–80
OFF ISOLATIO N (dB)
–100
06523-024
–120
0.1 1 10 100
FREQUENCY (MHz)
Figure 34. Off Isolation vs. Fr
50mV/DIV
R
V
S
=600
L
OUT
=8Vp-p
V
S
R
L
V
OUT
equency
=±5V
=150
=2Vp-p
06523-026
50ns/DIV
Figure 32. Small-Signal Pulse Response, V
= ±5 V, R
S
= 150 Ω
L
06523-025
Figure 35. Small-Signal Pulse Response, V
Rev. 0 | Page 15 of 28
100ns/DIV
= ±12 V, R
S
= 600 Ω
L
06523-056
Page 16
AD8112
500m
www.BDTIC.com/ADI
V/DIV
100ns/DIV
Figure 36. Large-Signal Pulse Response, V
2V/DIV
INPUT 0 INPUT 1
V
100ns/DIV
Figure 37. Switching Time, V
UPDATE
OUT
= ±5 V, R
S
= ±5 V, R
S
= 150 Ω
L
= 150 Ω
L
5V/DIV
06523-027
Figure 39. Large-Signal Pulse Response, V
2V/DIV
10V/DIV
06523-028
INPUT 0
Figure 40. Switching Time, V
100ns/DIV
V
OUT
100ns/DIV
= ±12 V, R
S
UPDATE
= ±12 V, R
S
INPUT 1
= 600 Ω
L
= 600 Ω
L
06523-057
06523-058
1V/DIV
OUTPUT
20mV/DIV
Figure 38. Switching Transient, V
100ns/DIV
UPDATE
= ±5 V, R
S
= 150 Ω
L
06523-029
Rev. 0 | Page 16 of 28
1V/DIV
20mV/DIV
OUTPUT
Figure 41. Switching Transient, V
100ns/DIV
UPDATE
= ±12 V, R
S
= 600 Ω
L
06523-059
Page 17
AD8112
(
)
www.BDTIC.com/ADI
THEORY OF OPERATION
The AD8112 has a gain of +2 and is a crosspoint array with
eight outputs, each of which can be connected to any one of 16
inputs. Organized by output row, 16 switchable transconductance
stages are connected to each output buffer in the form of a 16-to-1
multiplexer. Each of the 16 rows of transconductance stages are
wired in parallel to the 16 input pins, for a total array of 256 transconductance stages. Decoding logic for each output selects one
(or none) of the transconductance stages to drive the output
stage. The transconductance stages are NPN input differential
pairs, sourcing current into the folded cascode output stage.
The compensation networks and emitter follower output buffers
are in the output stage. Voltage feedback sets the gain at +2.
When operated with ±12 V supplies, this architecture provides
±
10 V drive for 600 Ω audio loads with extremely low distortion
(<0.002%) at audio frequencies. Provided the supplies are lowered to ±5 V (to limit power consumption), the AD8112 can
drive reverse-terminated video loads, swinging ±3.0 V into
150 Ω. Disabling unused outputs and transconductance
stages minimizes on-chip power consumption.
Features of the AD8112 facilitate the construction of larger
tch matrices. The unused outputs can be disabled, leaving
swi
only a feedback network resistance of 4 kΩ on the output. This
allows multiple ICs to be bused together, provided the output
load impedance is greater than the minimum allowed values.
Because no additional input buffering is necessary, high input
resistance and low input capacitance are easily achieved without
additional signal degradation.
The AD8112 inputs have a unique bias current compensation
s
cheme that overcomes a problem common to transconductance
input array architectures. Typically, an input bias current increases
as more transconductance stages connected to the same input
are turned on. Anywhere from zero to 16 transconductance
stages can share one input pin, so there is a varying amount of
bias current supplied through the source impedance driving
the input. For audio systems with larger source impedances,
this has the potential of creating large offset voltages, audible
as pops when switching between channels. The AD8112 samples
and cancels the input bias current contributions from each
transconductance stage so that the residual bias current is
nominally zero regardless of the number of enabled inputs.
Due to the flexibility in allowed supply voltages, internal crosstal
k isolation clamps have variable bias levels. These levels were
chosen to allow for the necessary input range to accommodate
the full output swing with a gain of +2. Overdriving the inputs
beyond the device’s linear range will eventually forward bias
these clamps, increasing power dissipation. The valid input
range for ±12 V supplies is ±5 V. The valid input range for ±5 V
supplies is ±1.5 V. When outputs are disabled and being driven
externally, the voltage applied to them should not exceed the
valid output swing range for the AD8112. Exceeding ±10.5 V on
the outputs of the AD8112 may apply a large differential voltage
on the unused transconductance stages and should be avoided.
A flexible TTL-compatible logic interface simplifies the pro-
ramming of the matrix. Either parallel or serial loading into
g
a first rank of latches programs each output. A global latch
simultaneously updates all outputs. In serial mode, a serial
output pin allows devices to be daisy-chained together for
single pin programming of multiple ICs. A power-on reset
pin is available to avoid bus conflicts by disabling all outputs.
Regardless of the supply voltage applied to the AV
pins, the digital logic requires 5 V on the DV
and AVEE
CC
pin with respect
CC
to DGND. In order for the digital-to-analog interface to work
properly, DV
must be at least 7 V above AVEE. Finally, internal
CC
ESD protection diodes require that the DGND and AGND pins
be at the same potential.
CALCULATION OF POWER DISSIPATION
4.0
TJ= 150°C
3.5
3.0
MAXIMUM POWER (W)
2.5
2.0
0 10203040506070
Figure 42. Maximum Power Dissipation vs. Ambient Temperature
AMBIENT T EMPERATURE (°C)
The curve in Figure 42 was calculated from
TT
−
P
=
MAXD
,
,
AMBIENTMAXJUNCTION
θ
JA
As an example, if the AD8112 is enclosed in an environment
t 50°C (T
a
), the total on-chip dissipation under all load and
A
supply conditions must not be allowed to exceed 2.5 W.
06523-030
Rev. 0 | Page 17 of 28
Page 18
AD8112
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2.
When calculating on-chip power dissipation, it is necessary to
include the rms current being delivered to the load multiplied
by the rms voltage drop on the AD8112 output devices. The
dissipation of the on-chip, 4 kΩ feedback resistor network
must also be included. For a sinusoidal output, the on-chip
power dissipation due to the load and feedback network can
be approximated by
⎛
V
,
D
()
,
MAX
CC
IVAVP
⎜
+×−=
,,
RMSOUTPUTRMSOUTPUT
⎜
⎜
⎝
RMSOUTPUT
Ω
k4
For nonsinusoidal output, the power dissipation is calculated
y integrating the on-chip voltage drop multiplied by the load
b
current over one period.
The user can subtract the quiescent current for the Class AB
o
utput stage when calculating the loaded power dissipation.
For each output stage driving a load, subtract a quiescent power
according to
P
= (AVCC − AVEE) × I
D, OUTPU T
O, QUIES CENT
where:
I
O, QUIESC ENT
= 0.67 mA.
For each disabled output, the quiescent power supply current
in A
V
and AVEE drops by approximately 1.25 mA, although
CC
there is a power dissipation in the on-chip feedback resistors if
the disabled output is being driven from an external source.
A
CC
I
O, QUIESCENT
QNPN
QPNP
AV
Figure 43. Simplified Output Stage
RF
4k
I
O, QUIESCENT
EE
V
OUTPUT
I
OUTPUT
AGND
06523-031
Example
The power supplies of the AD8112 with an ambient temperature
of 70°C and all eight outputs driving 6 V rms into 600 Ω loads
are ±12 V.
1.
Calculate the power dissipation of the AD8112 using
quiescent currents (see the Specifications section).
P
D, QUIESCENT
× I
(DV
CC
P
D, QUIESCENT
(5 V × 13
= (AVCC + I
)
DVCC
= (12 V × 54 mA) + (−12 V × −54 mA) +
mA) = 1.3 W
) + (AVEE × I
AVCC
AVEE
) +
2
⎞
⎟
⎟
⎟
⎠
Calculate the power dissipation from the loads.
P
V
P
69 mW
= (AVCC − V
D, OUTPUT
2
/4 kΩ
OUTPUT
= (12 V − 6 V) × 6 V/600 Ω + (6 V)2/4 kΩ =
D, OUTPUT
OUTPUT, RMS
) × I
OUTPUT, RMS
+
There are eight outputs, thus
nP
3.
Subtract quiescent output current for number of loads
= 8 × 69 mW = 0.55 W
D, OUTPUT
(assumes output voltage >> 0.5 V).
P
DQ, OUTPUT
P
DQ, OUTPUT
= (AV
− AVEE) × I
CC
O, QUIESCENT
= (12 V − (−12 V)) × 0.67 mA = 16 mW
There are eight outputs, thus
nP
DQ, OUTPUT
4.
Verify that power dissipation does not exceed the maxi-
= 8 × 16 mW = 0.13 W
mum allowed value.
P
P
= P
D, ON-CHIP
D, ON-CHIP
D, QUIESCENT
= 1.3 W + 0.55 W − 0.13 W = 1.7 W
+ nP
D, OUTPUT
− nP
DQ, OUTPUT
This power dissipation is below the maximum allowed
dissi
pation for all ambient temperatures approaching 70°C.
It can be shown that for a dual supply of ±
a, a Class AB output
stage dissipates maximum power into a grounded load when
the output voltage is a/2. Therefore, for a ±12 V supply, the
previous example demonstrates the worst-case power dissipation into 600 Ω. It can be seen from this example that the
minimum load resistance for ±12 V operation is 600 Ω for
full rated operating temperature range. For larger safety margins
when the output signal is unknown, loads of 1 kΩ and greater
are recommended. When operating with ±5 V supplies, this
load resistance can be lowered to 150 Ω.
SHORT-CIRCUIT OUTPUT CONDITIONS
Although there is short-circuit current protection on the AD8112
outputs, the output current can reach values of 55 mA into a
grounded output. Sustained operation with even one shorted
output will exceed the maximum die temperature and may
result in device failure (see the Absolute Maximum Ratings
on).
secti
Rev. 0 | Page 18 of 28
Page 19
AD8112
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APPLICATION NOTES
The AD8112 has two options for changing the programming
of the crosspoint matrix. In the first option, a serial word of 80
bits is provided to update the entire matrix. The serial data needs
to be prefixed with 40 zeros because there are 40 unconnected
bits. The second option allows for changing a single output’s
programming via a parallel interface. The serial option requires
fewer signals but more time (clock cycles) for changing the programming, whereas the parallel programming technique
requires more signals but can change outputs individually
and requires fewer clock cycles to complete programming.
SERIAL PROGRAMMING
The serial programming mode uses the device pins: CE, CLK,
DATA IN,
a low on
CE
the device. The
device when devices are connected in parallel.
The
shifted into the device’s serial port. Although the data shifts in
when
the shifting data to reach the matrix. This causes the matrix to
try to update to every intermediate state as defined by the
shifting data.
The data at DATA IN is clocked in upon each falling edge of
C
LK. A total of 80 bits must be shifted in to complete the programming because there are 40 unconnected bits. For each of
the eight outputs, there are four bits (D0 to D3) that determine
the source of the input followed by one bit (D4) that determines
the enabled state of the output. If D4 is low (output disabled),
the four associated bits (D0 to D3) do not matter, because no
input will be switched to that output.
The most significant output address data is shifted in first, and
t
hen followed in sequence until the least significant output address
data is shifted in. At this point
programs the device with the data that was just shifted in. The
UPDATE
(and
If more than one AD8112 device is t
in a system, the DATA OUT signal from one device can be connected to the DATA IN of the next device to form a serial chain.
All of the CLK,
connected in parallel and operated as described previously. The
serial data is input into the DATA IN pin of the first device
of the chain, and it ripples through to the last device. Therefore, the data for the last device in the chain should come at the
beginning of the programming sequence. The length of the
programming sequence is 80 bits times the number of devices
in the chain.
UPDATE
SER
/PAR to enable the serial programming mode. The
pin for the chip must be low to allow data to be clocked into
CE
UPDATE
UPDATE
CE
signal should be high during the time that data is
is low, the transparent asynchronous latches allow
registers are asynchronous, and when
is low), they are transparent.
CE
SER
, and
signal can be used to address an individual
UPDATE
,
/PAR. The first step is to assert
UPDATE
, and
can be taken low, which
UPDATE
o be serially programmed
SER
/PAR pins should be
is low
PARALLEL PROGRAMMING
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the
matrix. In fact, parallel programming allows the modification
of a single output. Because this requires only one CLK/
cycle, significant time is saved by using parallel programming.
One important consideration when using parallel programming
RESET
hat the
is t
When taken low, the
disabled state. This is helpful during power-up to ensure that
two parallel outputs will not be active at the same time.
After initial power-up, the internal registers in the device gener-
lly have random data, even though the
a
asserted. If parallel programming is used to program one output,
then that output is properly programmed, but the rest of the
device has a random program state depending on the internal
register content at power-up. Therefore, when using parallel
programming, it is essential that all outputs be programmed to
a desired state after power-up to ensure that the programming
matrix is always in a known state. Then, parallel programming
can be used to modify a single output or multiple outputs.
Similarly, if both
power-up, the random power-up data in the shift register is
programmed into the matrix. Therefore, to prevent the crosspoint
from being programmed into an unknown state, do not apply
low logic levels to both
applied. Programming the full shift register one time to a desired
state, by either serial or parallel programming after initial
power-up, eliminates the possibility of programming the matrix
to an unknown state.
To change an output programming via parallel programming,
SER
/PAR and
taken low. The CLK signal should be in the high state. The 3-bit
address of the output to be programmed should be put on A0 to
A2. The first four data bits (D0 to D3) should contain the information identifying the input that is programmed to the addressed
output. The fifth data bit (D4) determines the enabled state of
the output. If D4 is low (output disabled), the data on D0 to D3
does not matter.
After the desired address and data signals have been established,
t
he data can be latched into the shift register by a high to low
transition of the CLK signal. The matrix will not be programmed,
however, until the
possible to latch in new data for several or all outputs via successive negative transitions of CLK while
and then for the new data to take effect when
signal does not reset all registers in the AD8112.
RESET
signal only sets each output to the
RESET
UPDATE
CE
and
UPDATE
UPDATE
CE
and
should be taken high and CE should be
are taken low after initial
UPDATE
signal is taken low. It is therefore
after power is initially
UPDATE
UPDATE
signal has been
is held high,
UPDATE
goes
Rev. 0 | Page 19 of 28
Page 20
AD8112
V
V
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low. This technique should be used when programming the
device for the first time after power-up when using parallel
programming.
Because
600 Ω is 0.775 V rms. This is the voltage reference (0 dB) used
for dBu measurements without regard to the impedance.
2
P = V
/R, the voltage required to create 1 mW into
POWER-ON RESET
When powering up the AD8112, it is usually desirable to have
RESET
the outputs in the disabled state. The
pin, when taken
low, causes all outputs to be in the disabled state. However, the
RESET
signal does not reset all registers in the AD8112. This is
important when operating in the parallel programming mode.
(Please refer to the Parallel Programming section for information
ab
out programming internal registers after power-up.) Serial
programming updates the entire matrix, therefore no special
considerations apply.
Because the data in the shift register is random after power-up,
should not be used to program the matrix; otherwise the matrix
it
can enter an unknown state. To prevent this, do not apply logic
low signals to both
CE
and
UPDATE
immediately after powerup. The shift register should first be loaded with the desired
data, and then
RESET
The
pin has a 20 kΩ pull-up resistor to DVCC that can be
UPDATE
can be taken low to program the device.
used to create a simple power-up reset circuit. A capacitor from
RESET
to ground holds
RESET
low until the device stabilizes.
The low condition causes all the outputs to be disabled. The
capacitor then charges through the pull-up resistor to the high
state, thus allowing full programming capability of the device.
SPECIFYING AUDIO LEVELS
Several methods are used to specify audio levels. A level is actually
a power measurement, which requires not just a voltage measurement, but also a reference impedance. Traditionally both
150 Ω and 600 Ω have been used as references for audio level
measurements.
The typical reference power level is 1 mW. Power levels that are
easured relative to this reference level are given the designation
m
dBm. However, it is necessary to be sure of the reference impedance used for such measurements. This can be either explicit
(for example, 0 dBm (600 Ω)) or implicit (if there is an agreement on what the reference impedance is).
Because modern voltmeters have high input impedances, measu
rements can be made that do not terminate the signal. Therefore,
it is not proper to consider this type of measurement a dBm, or
power measurement. However, a measurement scale that is
designated dBu is used to measure unterminated voltages. This
scale has a voltage reference for 0 dBu that is the same as the
voltage required to produce 0 dBm (600 Ω).
The AD8112 operates as a voltage-in/voltage-out device.
Ther
efore, all parameters are specified in volts, but users
can convert the values to other power units or decibel-type
measurements as required by a particular application.
CREATING UNITY-GAIN CHANNELS
The channels in the AD8112 each have a gain of +2. This gain is
necessary, as opposed to a gain of unity, to restrict the voltage
on internal nodes to less than the breakdown voltage. If it is
desired to create channels with an overall gain of unity, a resistive
divider can be used at the input to divide the signals by 2. After
passing through any input/output channel combination of the
AD8112, the overall gain of unity is achieved.
+12
AUDIO
SOURCE
1k
AD8112
TYPICAL
INPUT
1k
Figure 44. Input Divide Circuit
G=+2
–12V
TYPICAL
OUTPUT
UNITY GAIN
AUDIO OUT
06523-032
Figure 44 shows a typical input with a divide-by-2 input divider
that creates a unity gain channel. The circuit uses 1 kΩ resistors
to form the divider. These resistors need to be high enough so
they do not overload the drive circuit. But if they are too high,
they generate an offset voltage due to the input bias current that
flows through them. Larger resistors also increase the thermal
noise of the channel.
The circuit shown in Figure 44 can handle inputs that swing
u
p to ±10 V when the AD8112 operates on analog supplies of
±12 V. After passing through the divider, the maximum voltage
is ±5 V at the input. This maximum input amplitude is ±10 V at
the output after the gain of +2 of the channels.
VIDEO SIGNALS
Unlike audio signals, which have lower bandwidths and longer
wavelengths, video signals often use controlled-impedance
transmission lines that are terminated in their characteristic
impedance. Although this is not always the case, there are some
considerations when using the AD8112 to route video signals
with controlled-impedance transmission lines. Figure 45 shows
chematic of an input and output treatment of a typical video
a s
channel.
+5
75
VIDEO
SOURCE
OR +12V
TYPICAL
INPUT
AD8112
75
G=+2
–5V
OR –12V
Figure 45. Video Signal Circuit
TYPICAL
OUTPUT
75
75
TRANSMISSION
LINE
75
06523-033
Rev. 0 | Page 20 of 28
Page 21
AD8112
www.BDTIC.com/ADI
Video signals usually use 75 Ω transmission lines that need to
be terminated with this value of resistance at each end. When
such a source is delivered to one of the AD8112 inputs, the high
input impedance does not properly terminate these signals.
Therefore, the line should be terminated with a 75 Ω shunt
resistor to ground. Because video signals are limited in their
peak-to-peak amplitude, there is no need to attenuate video
signals before they pass through the AD8112.
The AD8112 outputs are very low impedance and do not properly terminate the source end of a 75 Ω transmission line. In
these cases, a series 75 Ω resistor should be inserted at an output
that drives a video signal. Then the transmission line should be
terminated with 75 Ω at its far end. This overall termination
scheme divides the amplitude of the AD8112 output by 2. An
overall unity gain channel is produced as a result of the
AD8112’s channel gain of +2.
CREATING LARGER CROSSPOINT ARRAYS
The AD8112 is a high density building block for creating
crosspoint arrays of dimensions larger than 16 × 8. Various
features, such as output disable and chip enable, are useful
for creating larger arrays.
The first consideration in constructing a larger crosspoint is
o determine the minimum number of devices required. The
t
16 × 8 architecture of the AD8112 contains 128 points, which
is a factor of 32 greater than a 4 × 1 crosspoint (or multiplexer).
The PC board area, power consumption, and design effort
savings are readily apparent when compared with using these
smaller devices.
For a nonblocking crosspoint, the number of points required is
he product of the number of inputs multiplied by the number
t
of outputs. Nonblocking requires that the programming of a
given input to one or more outputs does not restrict the availability of that input to be a source for any other outputs.
Some nonblocking crosspoint architectures require more than
his minimum as previously calculated. Also, there are blocking
t
architectures that can be constructed with fewer devices than
this minimum. These systems have connectivity available on a
statistical basis that is determined when designing the overall
system.
The basic concept in constructing larger crosspoint arrays is
t
o connect inputs in parallel in a horizontal direction and to
wire-OR the outputs together in the vertical direction. The
meaning of horizontal and vertical can best be understood by
looking at Figure 46, which illustrates this concept for a 32 × 16
osspoint array that uses four AD8112s.
cr
16
IN00 TO IN15
IN16 TO IN31
Figure 46. 32 x 16 Audio Crosspoint Array Using Four AD8112s
1k
1k
1k
16
1k
AD8112
AD8112
16
AD8112
8
16
8
8
8
AD8112
8
8
06523-035
The inputs are individually assigned to each of the 32 inputs of
he two devices and a divider is used to normalize the channel
t
gain. The outputs are wire-OR’ed together in pairs. The output
from only one wire-OR’ed pair should be enabled at any given
time. The device programming software must be properly
written to for this to happen.
Using additional crosspoint devices in the design can lower the
umber of outputs that must be wire-OR’ed together. Figure 47
n
hows a block diagram of a system using ten AD8112s to create
s
a nonblocking, gain of +2, 128 × 8 crosspoint that restricts the
wire-OR’ing at the output to only four outputs.
Additionally, by using the lower eight outputs from each of the
tw
o Rank 2 AD8112s, a blocking 128 × 16 crosspoint array can
be realized. There are, however, some drawbacks to this technique.
The offset voltages of the various cascaded devices accumulate,
and the bandwidth limitations of the devices compound. In
addition, the extra devices consume more current and take up
more board space. Consider the overall system design specifications when using the various trade-offs.
Rev. 0 | Page 21 of 28
Page 22
AD8112
www.BDTIC.com/ADI
RANK 1
(8 × AD8112)
IN00 TO IN15
1k
16
IN16 TO IN31
1k
16
IN32 TO IN47
1k
16
IN48 TO IN63
1k
16
IN64 TO IN79
1k
16
IN80 TO IN95
1k
16
IN96 TO IN111
1k
16
IN112 TO IN127
1k
16
R
R
R
R
R
R
R
R
128:16
AD8112
TERM
AD8112
TERM
AD8112
TERM
AD8112
TERM
AD8112
TERM
AD8112
TERM
AD8112
TERM
AD8112
TERM
1k
4
1k
1k
1k
1k
1k
1k
1k
1k
1k
1k
1k
1k
1k
1k
1k
16:8 NONBLOCKI NG
(16:16 BLOCKING)
4
1k
4
1k
4
1k
4
1k
RANK 2
AD8112
AD8112
4
OUT00 TO OUT07
NONBLOCKING
4
4
ADDITIONAL
EIGHT OUTPUTS
(SUBJECT
4
TO BLOCKING)
06523-036
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Figure 47. Nonblocking 128 × 8 Audio Array (128 × 16 Blocking)
Rev. 0 | Page 22 of 28
Page 23
AD8112
www.BDTIC.com/ADI
MULTICHANNEL VIDEO AND AUDIO
The video specifications of the AD8112 make it an ideal
candidate for creating composite video crosspoint switches.
These can be made quite dense by taking advantage of the
AD8112’s high level of integration and the fact that composite
video requires only one crosspoint channel per system video
channel. There are, however, other video formats that can be
routed with the AD8112, requiring more than one crosspoint
channel per video channel.
Some systems use twisted pair cables to carry video or audio
sig
nals. These systems utilize differential signals and can lower
costs because they use lower cost cables, connectors, and termination methods. They also have the ability to lower crosstalk
and reject common-mode signals, which can be important
for equipment that operates in noisy environments, or where
common-mode voltages are present between transmitting and
receiving equipment.
In such systems, the audio or video signals are differential;
th
ere are positive and negative (or inverted) versions of the
signals. These complementary signals are transmitted through
each of the two cables of the twisted pair, yielding a first-order
zero common-mode voltage. At the receive end, the signals are
differentially received and converted back into a single-ended
signal.
When switching these differential signals, two channels are
equired in the switching element to handle the two differential
r
signals that compose the video or audio channel. Thus, one differential video or audio channel is assigned to a pair of crosspoint
channels, both input and output. For a single AD8112, eight
differential video or audio channels can be assigned to the 16
inputs, and four differential video or audio channels can be
assigned to the eight outputs. This effectively forms an 8 × 4
differential crosspoint switch.
Programming such a device requires that inputs and outputs be
p
rogrammed in pairs. This information can be deduced through
inspection of the programming format of the AD8112 and the
requirements of the system.
There are other analog video formats requiring more than one
nalog circuit per video channel. One two-circuit format that is
a
commonly being used in systems such as satellite TV, digital
cable boxes, and higher quality VCRs is called S-video or
Y/C video. This format carries the brightness (luminance or
Y) portion of the video signal on one channel and the color
(chrominance, chroma, or C) portion on a second channel.
Because S-video also uses two separate circuits for one video
nnel, creating a crosspoint system requires assigning one
cha
video channel to two crosspoint channels, as in the case of a
differential video system. Aside from the nature of the video
Rev. 0 | Page 23 of 28
format, other aspects of these two systems are the same. Stereo
udio can also be routed in a paired-channel arrangement
a
similar to a two-channel video system.
There are yet other video formats using three channels to carry
th
e video information. Video cameras produce RGB (red, green,
blue) directly from the image sensors. RGB is also the usual format used internally by computers for graphics. RGB can also be
converted to Y, R–Y, B–Y format, sometimes called YUV format.
These three-circuit video standards are referred to as component analog video.
The component video standards require three crosspoint channels
er video channel to handle the switching function. Similar to
p
the two-circuit video formats, the inputs and outputs are assigned
in groups of three, and the appropriate logic programming is
performed to route the video signals.
CROSSTALK
Many systems, such as studio audio or broadcast video, that
handle numerous analog signal channels have strict requirements for keeping the various signals from influencing other
signals in the system. Crosstalk is the term used to describe the
coupling of the signals of other nearby channels to a given
channel.
When there are many signals in close proximity in a system,
as undo
crosstalk issues can be quite complex. A good understanding of
the nature of crosstalk and some definition of terms is required
in order to specify a system that uses one or more AD8112s.
Types of Crosstalk
Crosstalk can be propagated by one of three methods. These fall
into the categories of electric field, magnetic field, and sharing
of common impedances. This section explains these effects.
Every conductor can be both a radiator of electric fields and a
re
occurs when the electric field created by the transmitter propagates
across a stray capacitance (for example, free space) and then
couples with the receiver and induces a voltage. This voltage is
an unwanted crosstalk signal in any channel that receives it.
Currents flowing in conductors create magnetic fields that
cir
generate voltages in any other conductor whose paths is linked.
The undesired induced voltages in these other channels are
crosstalk signals. The channels with crosstalk have a mutual
inductance that couples signals from one channel to another.
The power supplies, grounds, and other signal return paths
o
channels. When a current from one channel flows into one of
these paths, a voltage that is developed across the impedance
becomes an input crosstalk signal for other channels that share
the common impedance.
ubtedly is the case in a system that uses the AD8112, the
ceiver of electric fields. The electric field crosstalk mechanism
culate around the currents. These magnetic fields then
f a multichannel system are generally shared by the various
Page 24
AD8112
www.BDTIC.com/ADI
All these sources of crosstalk are vector quantities; therefore the
magnitudes cannot simply be added together to obtain the total
crosstalk. In fact, there are conditions where driving additional
circuits in parallel in a given configuration can reduce the
crosstalk.
Areas of Crosstalk
A practical AD8112 circuit must be mounted to some sort of
circuit board to connect it to power supplies and measurement
equipment. Great care has been taken to create a characterization board (also available as an evaluation board) that adds
minimum crosstalk to the intrinsic device. This, however, raises
the issue that the crosstalk of a system is a combination of the
intrinsic crosstalk of both the devices and the circuit board to
which they are mounted. It is important to try to separate these
two areas when attempting to minimize the effect of crosstalk.
In addition, crosstalk can occur among the inputs as well as the
output
s of a cross-point. It can also occur from input to output.
The following sections describe techniques for measuring and
identifying the source of crosstalk.
Measuring Crosstalk
Crosstalk is measured by applying a signal to one or more channels
and measuring the relative strength of that signal on a desired
selected channel. The measurement is usually expressed as
decibels down from the magnitude of the test signal. The
crosstalk is expressed by
() ()
=
where:
s = jw is the Laplace transform variable.
Asel(s) = the amplitude of the crosstalk induced signal in the
selected channel.
Atest(s) = the amplitude of the test signal.
It can be seen that crosstalk is a function of frequency, but not
a
function of the magnitude of the test signal (to first order). In
addition, the crosstalk signal has a phase relative to the test
signal associated with it.
A network analyzer is most commonly used to measure crosstalk
ver a frequency range of interest. It can provide both magni-
o
tude and phase information about the crosstalk signal.
()
10
sAtestsAselXT /log 20||
To measure this crosstalk, use one of the following two methods.
I
n the first method, the crosstalk terms associated with driving
a test signal into each of the other 15 inputs is measured one at
a time, while applying no signal to IN00. In the second method,
the crosstalk terms associated with driving a parallel test signal
into all 15 other inputs is measured two at a time in all possible
combinations, then three at a time, and so on, until, finally, there
is only one way to drive a test signal into all 15 other inputs in
parallel.
Each combination is legitimately different from the others and
m
ight yield a unique value, depending on the resolution of the
measurement system. It is not practical to measure and then
specify all these terms. Furthermore, this describes the crosstalk
matrix for just one input channel. A similar crosstalk matrix can
be proposed for every other input. In addition, if the possible
combinations and permutations for connecting inputs to the
other outputs (not used for measurement) are taken into
consideration, the numbers of possibilities quickly grows to
astronomical proportions. If a larger crosspoint array of multiple
AD8112s is constructed, the numbers grow larger still.
Obviously, a subset of all these cases must be selected to be
sed as a guide for a practical measure of crosstalk. One common
u
method is to measure all hostile crosstalk; this means that the
crosstalk to the selected channel is measured while all other
system channels are driven in parallel. In general, this yields the
worst crosstalk number, but this is not always the case, due to
the vector nature of the crosstalk signal.
Other useful crosstalk measurements are those created by the
n
earest neighbor or by the two nearest neighbors on either side.
These crosstalk measurements are generally higher than those
of more distant channels, and therefore can serve as a worstcase measure for any other 1-channel or 2-channel crosstalk
measurements.
Input and Output Crosstalk
The flexible programming capability of the AD8112 can be used
to diagnose whether crosstalk is greater on the input side or the
output side. For example, to identify the source of crosstalk, the
IN07 input channel can be programmed to drive OUT07, with
the input to IN07 terminated to ground (via 50 Ω or 75 Ω) and
no signal applied.
As a crosspoint system or device grows larger, the number of
t
heoretical crosstalk combinations and permutations can become
extremely large. For example, in the case of the 16 × 8
the AD8112, consider the number of possible sources of crosstalk
terms for a single channel, for example the IN00 input. IN00 is
programmed to connect to one of the AD8112 outputs where
crosstalk can be measured.
matrix of
Rev. 0 | Page 24 of 28
All the other inputs are driven in parallel with the same test
sig
nal (practically provided by a distribution amplifier), with all
other outputs except OUT07 disabled. Because grounded IN07
is programmed to drive OUT07, no signal should be present.
Any signal that is present can be attributed to the other 15 hostile
input signals, because no other outputs are driven (they are all
disabled). Therefore, this method measures the all-hostile input
contribution to crosstalk into IN07. This method can be used
for other input channels and combinations of hostile inputs.
Page 25
AD8112
(
)
www.BDTIC.com/ADI
For output crosstalk measurement, a single input channel is
driven (IN00, for example) and all outputs other than a given
output (IN07 in the middle) are programmed to connect to
IN00. OUT07 is programmed to connect to IN15 (not in close
proximity to IN00), which is terminated to ground. Therefore,
OUT07 should not have a signal present because it is listening
to a quiet input. Any signal measured at the OUT07 can be
attributed to the output crosstalk of the other seven hostile
outputs. Again, this method can be modified to measure other
channels and other crosspoint matrix combinations.
Effect of Impedances on Crosstalk
The input side crosstalk can be influenced by the output
impedance of the sources that drive the inputs. The lower
the impedance of the drive source, the lower the magnitude
of the crosstalk. The dominant crosstalk mechanism on the
input side is capacitive coupling. The high impedance inputs do
not have significant current flow to create magnetically induced
crosstalk. However, significant current can flow through the
input termination resistors and the loops that drive them.
Therefore, the PC board on the input side can contribute to
magnetically coupled crosstalk.
From a circuit standpoint, the input crosstalk mechanism looks
lik
e a capacitor coupling to a resistive load. For low frequencies
the magnitude of the crosstalk is given by
XT| = 20 log
|
where:
R
is the source resistance.
S
C
is the mutual capacitance between the test signal circuit and
M
the selected circuit.
s is the Laplace transform variable.
[(R
SCM
) × s]
10
From the equation, it can be observed that this crosstalk
echanism has a high-pass nature. It can also be minimized
m
by reducing the coupling capacitance of the input circuits and
lowering the output impedance of the drivers. If the input is
driven from a 75 Ω terminated cable, the input crosstalk can
be reduced by buffering this signal with a low output impedance buffer.
On the output side, the crosstalk can be reduced by driving a
hter load. Although the AD8112 is specified with excellent
lig
differential gain and phase when driving a standard 150 Ω video
load, the crosstalk is higher than the minimum obtainable
crosstalk due to the high output currents. These currents induce
crosstalk via the mutual inductance of the output pins and bond
wires of the AD8112.
From a circuit standpoint, this output crosstalk mechanism
lo
oks like a transformer with a mutual inductance between
the windings that drive a load resistor. For low frequencies,
the magnitude of the crosstalk is given by
RsMxyXT /log 20||
×=
10
where:
Mxy is the mutual inductance of output x to output y.
R
is the load resistance on the measured output.
L
This crosstalk mechanism can be minimized by keeping the
utual inductance low and increasing R
m
tance can be kept low by increasing the spacing of the conductors
and minimizing their parallel length.
L
. The mutual induc-
L
Rev. 0 | Page 25 of 28
Page 26
AD8112
www.BDTIC.com/ADI
PCB LAYOUT
Extreme care must be exercised to minimize additional crosstalk generated by the system circuit board(s). The areas that
must be carefully designed are grounding, shielding, signal
routing, and supply bypassing.
The packaging of the AD8112 is designed to help minimize
cr
osstalk. Each input is separated from each other input by
an analog ground pin. All of these AGNDs should be directly
connected to the ground plane of the circuit board. These
ground pins provide shielding, low impedance return paths,
and physical separation for the inputs. All of these help to
reduce crosstalk.
Each output is separated from its two neighboring outputs by
an
analog supply pin of one polarity or the other. Each of these
analog supply pins provides power to the output stages of only
the two nearest outputs. These supply pins provide shielding,
physical separation, and a low impedance supply for the outputs.
Individual bypassing of each of these supply pins with a 0.01 μF
chip capacitor connected directly to the ground plane minimizes
high frequency output crosstalk via the mechanism of sharing
common impedances.
In addition, each output has an
tor that is individually tied to the nearby analog ground pins
(AGND00 through AGND07). This technique reduces crosstalk
by preventing the currents that flow in these paths from sharing
a common impedance on the IC and in the package pins. These
AGNDxx signals should all be connected directly to the
ground plane.
The input and output signals have minimum crosstalk if they
located between ground planes on layers above and below,
are
and separated by ground in between. Vias should be located as
close to the IC as possible to carry the inputs and outputs to the
inner layer. The input and output signals surface at the input
termination resistors and at the output series back-termination
resistors. To the extent possible, these signals should also be
separated as soon as they emerge from the IC package.
on-chip compensation capaci-
Rev. 0 | Page 26 of 28
Page 27
AD8112
V
V
A
V
www.BDTIC.com/ADI
D
DGND NC A
CC
P1-1 P1-2 P1-3 P1-4 P1-5 P1-6 P1-7
+
JUMPER
0.1µF 10µF 0.1µF 10µF
INPUT 00
INPUT 01
INPUT 02
INPUT 03
INPUT 04
INPUT 05
INPUT 06
INPUT 07
INPUT 08
INPUT 09
INPUT 10
INPUT 11
INPUT 12
INPUT 13
INPUT 14
INPUT 15
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
R
R
P2-5
P2-4
P2-2
P2-3
P2-1
P2-6
57, 59
3, 73
EE
58
60
61
62
63
64
65
66
67
68
69
70
71
72
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
98
96
AGND
+
IN00
AGND
IN01
AGND
IN02
AGND
IN03
AGND
IN04
AGND
IN05
AGND
IN06
AGND
IN07
AGND
IN08
AGND
IN09
AGND
IN10
AGND
IN11
AGND
IN12
AGND
IN13
AGND
IN14
AGND
IN15
AGND
DATA OUT
DATA IN
NC
CC
+
1, 75
DV
CC
DV
CC
0.01µF
21, 55
AV
CC
0.01µF
CC
20, 56
AV
EE
0.01µF
AV
EE
AD8112
DGND
2,741009997 958483 828180797877 9476
RESETCECLK
R
R
UPDATE
A0
A1
A2
DGND
D0
CR
R R
85 TO 9 3
D1
NCAV
AV
0.01µF
0.01µF
0.01µF
0.01µF
0.01µF
0.01µF
0.01µF
0.01µF
DV
CC
CC
OUTPUT 00
75
AV
EE
OUTPUT 01
75
AV
CC
OUTPUT 02
75
AV
EE
OUTPUT 02
75
AV
CC
OUTPUT 04
75
AV
EE
OUTPUT 05
75
AV
CC
OUTPUT 06
75
AV
EE
OUTPUT 07
75
54
AV
CC
53
OUT00
D4
OUT01
OUT02
OUT03
OUT04
OUT05
OUT06
OUT07
RRRRRRRR
SER
CC
/PAR
52
51
50
49
48
47
46
45
44
43
42
41
40
39
22AV
R33
20k
SERIAL MO DE
JUMP
AVEE00/01
AVCC01/02
AVEE02/03
AVCC03/04
AVEE04/05
AVCC05/06
AVEE06/07
D2
D3
P3-1
P3-2
P3-3
NOTES
1. R = OPTIONAL 50 TERMI NATOR RESISTO RS.
2. C = O PTIO NAL SMOO THING CAPACITOR.
3. NC = NO CONNECT.
P3-4
P3-5
P3-6
P3-7
P3-8
P3-10
P3-11
P3-12
P3-13
Figure 48. Evaluation Board Schematic
Rev. 0 | Page 27 of 28
P3-14
06523-037
Page 28
AD8112
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
16.20
16.00 SQ
15.80
PIN 1
TOP VIEW
(PINS DOWN)
0.50
BSC
LEAD PITCH
0.27
0.22
0.17
76100
75
14.20
14.00 SQ
13.80
51
50
1.45
1.40
1.35
0.15
SEATING
0.05
PLANE
VIEW A
ROTATED 90° CCW
1.60 MAX
0.75
0.60
0.45
0.20
0.09
7°
3.5°
0°
0.08
COPLANARIT Y
25
VIEW A
1
26
COMPLIANT TO JEDEC STANDARDS MS-026-BED
051706-A
Figure 49. 100-Lead Low Profile Quad Flat Package [LQFP]
(ST-10
0)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD8112JSTZ
AD8112-EVALZ
1
Z = Pb-free part.
1
0°C to 70°C 100-Lead Plastic LQFP ST-100
1
Evaluation Board
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06523-0-2/07(0)
Rev. 0 | Page 28 of 28
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