Datasheet AD8106, AD8107 Datasheet (ANALOG DEVICES)

260 MHz, 16 × 5 Buffered

FEATURES

16 × 5 high speed, nonblocking switch arrays

AD8106: G = 1, AD8107: G = 2

Pin compatible with AD8110/AD8111, 16 × 8 switch arrays

For a 16 × 16 array, see
For a 16 x 8 array, see AD8110/AD8111

Complete solution

Buffered inputs
Five output amplifiers
Drives 150

Ω loads

Excellent video performance

60 MHz 0.1 dB gain flatness

0.02% differential gain error (R

0.028 differential phase error (RL = 150 Ω)

Excellent ac performance

−3 dB bandwidth > 260 MHz

500 V/μs slew rate
Low power of 50 mA
Low all-hostile crosstalk of −78 dB @ 5 MHz
Output disable allows connection of multiple device outputs
Reset pin allows disabling of all outputs
Excellent ESD rating: Exceeds 4000 V human body model
80-lead LQFP (12 mm × 12 mm)

APPLICATIONS

Routing of high speed signals including:

Composite video (NTSC, PAL, S, SECAM)

Component video (YUV, RGB)

Compressed video (MPEG, Wavelet)

3-level digital video (HDB3)

AD8114/AD8115

= 150 Ω)

L

Video Crosspoint Switches

AD8106/AD8107

FUNCTIONAL BLOCK DIAGRAM

D0 D1 D2 D3 D4

CLK

25-BIT REGISTER

(RANK 1)

UPDATE

CE

RESET

5 × 5:16 DECODERS

AD8106/AD8107

16 INPUTS

25

PARALLEL LATCH

(RANK 2)

25

DECODE

80

SWITCH

MATRIX

Figure 1.

SET INDI VIDUAL
OR RESET ALL
OUTPUTS
TO OFF

OUTPUT
BUFFER

G = 1,

G = 2

5

A0
A1

A2

5 OUTPUTS

ENABLE/DISABLE

05774-001

GENERAL DESCRIPTION

The AD8106 and AD8107 are high speed, 16 × 5 video crosspoint
switch matrices. They offer a −3 dB signal bandwidth greater
than 260 MHz, and channel switch times of less than 25 ns
with 1% settling. With −78 dB of crosstalk and
(@ 5 MHz), the AD8106/AD8107 are useful in many high speed
applications. The differential gain and differential phase of
greater than 0.02% and 0.02° respectively, along with 0.1 dB
flatness out to 60 MHz, make the AD8106/AD8107 ideal for
video signal switching.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

−97 dB isolation

The AD8106 and AD8107 include five independent output
buffers that can be placed into a high impedance state for parallel­ing crosspoint outputs, preventing off channels from loading the
output bus. The AD8106 has a gain of 1, while the AD8107
offers a gain of 2. Both operate on voltage supplies of ±5 V while
consuming only 30 mA of idle current. The channel switching is
performed via a parallel control, allowing updating of an
individual output without reprogramming the entire array.

The AD8106/AD8107 are offered in an 80-lead LQFP and are
available over the extended industrial temperature range of

−40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD8106/AD8107

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

Maximum Power Dissipation ..................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 8

I/O Schematics.................................................................................. 9

Typical Performance Characteristics ........................................... 10

REVISION HISTORY

Theory of Operation ...................................................................... 16

Power-On Reset .......................................................................... 16

Initialization ................................................................................ 16

Gain Selection............................................................................. 16

Creating Larger Crosspoint Arrays.......................................... 16

Crosstalk ...................................................................................... 18

PCB Layout ................................................................................. 19

Evaluation Board ............................................................................ 21

Controlling the Evaluation Board from a PC ......................... 25

Data-Line Overshoot on Printer Ports.................................... 25

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 27

3/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD8106/AD8107

SPECIFICATIONS

VS = ±5 V, TA = 25°C, RL = 1 kΩ, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit Reference

DYNAMIC PERFORMANCE

−3 dB Bandwidth 200 mV p-p, RL = 150 Ω 300/190 390/260 MHz Figure 10, Figure 16
2 V p-p, RL = 150 Ω 150 MHz Figure 10, Figure 16
Propagation Delay 2 V p-p, RL = 150 Ω 5 ns
Slew Rate 2 V step, RL = 150 Ω 500 V/μs
Settling Time 0.1%, 2 V step, RL = 150 Ω 40 ns Figure 15, Figure 21
Gain Flatness 0.05 dB, 200 mV p-p, RL = 150 Ω 60/40 MHz Figure 10, Figure 16

0.05 dB, 2 V p-p, RL = 150 Ω 65/40 MHz Figure 10, Figure 16

0.1 dB, 200 mV p-p, RL = 150 Ω 80/57 MHz Figure 10, Figure 16

0.1 dB, 2 V p-p, RL = 150 Ω 70/57 MHz Figure 10, Figure 16
NOISE/DISTORTION PERFORMANCE

Differential Gain Error NTSC or PAL, RL = 1 kΩ 0.01 %
NTSC or PAL, RL = 150 Ω 0.02 %
Differential Phase Error NTSC or PAL, RL = 1 kΩ 0.01 Degrees
NTSC or PAL, RL = 150 Ω 0.02 Degrees
Crosstalk, All Hostile f = 5 MHz 78/85 dB Figure 11, Figure 17
f = 10 MHz 70/80 dB Figure 11, Figure 17
Off Isolation, Input/Output f = 10 MHz, RL = 150 Ω, one channel 93/99 dB Figure 26, Figure 32
Input Voltage Noise 0.01 MHz to 50 MHz 15 nV/√Hz Figure 23, Figure 29

DC PERFORMANCE

Gain Error RL = 1 kΩ 0.04/0.1 0.07/0.5 %
R
Gain Matching No load, channel-to-channel 0.02/1.0 %

R

Gain Temperature Coefficient 0.5/8 ppm/°C

OUTPUT CHARACTERISTICS

Output Impedance DC, enabled 0.2 Ω Figure 27, Figure 33
Disabled 10/0.001 MΩ Figure 24, Figure 30
Output Disable Capacitance Disabled 2 pF
Output Leakage Current Disabled, AD8106 only 1/NA μA
Output Voltage Range No load ±2.5 ±3 V
Output Current 20 40 mA
Short-Circuit Current 65 mA

INPUT CHARACTERISTICS

Input Offset Voltage Worst case (all configurations) 5 20 mV Figure 38, Figure 44
Temperature coefficient 12 μV/°C Figure 39, Figure 45
Input Voltage Range ±2.5/±1.25 ±3/±1.5 V
Input Capacitance Any switch configuration 2.5 pF
Input Resistance 1 10 MΩ
Input Bias Current Per output selected 2 5 μA

SWITCHING CHARACTERISTICS

Enable On Time 60 ns
Switching Time, 2 V Step

Switching Transient (Glitch) Measured at output 20/30 mV p-p Figure 25, Figure 31

= 150 Ω 0.15/0.25 %

L

= 1 kΩ, channel-to-channel 0.09/1.0 %

L

50%

UPDATE

to 1% settling

25 ns

Rev. 0 | Page 3 of 28

AD8106/AD8107

Parameter Conditions Min Typ Max Unit Reference

POWER SUPPLIES

Supply Current AVCC, outputs enabled, no load 30 mA

AVCC, outputs disabled 15 mA

AVEE, outputs enabled, no load 30 mA

AVEE, outputs disabled 15 mA

DVCC 11 mA

Supply Voltage Range ±4.5 to ±5.5 V

PSRR f = 100 kHz 75/78 dB Figure 22, Figure 28
f = 1 MHz −55/−58 dB
OPERATING TEMPERATURE

Temperature Range Operating (still air) −40 to +85 °C

θJA

Operating (still air) 48 °C/W

Rev. 0 | Page 4 of 28

AD8106/AD8107

TIMING CHARACTERISTICS

Table 2.

Parameter Limit at T

t1 20 ns min Data setup time
t 100 ns min CLK pulse width

2

t 20 ns min Data hold time

3

t 100 ns min CLK pulse separation

4

t5 0 ns min
t6 50 ns min
– 8 ns max
– 100 ns max
– 200 ns min

, T Unit Description

MIN

MAX

UPDATE delay

CLK to
UPDATE pulse width
Propagation delay,

UPDATE rise and fall times

CLK,
RESET time

UPDATE to switch on or off

CLK

D0 TO D4
A0 TO A2

1 = LATCHED

0 = TRANSPARENT

UPDATE

t

1

0

1

0

t

1

2

t

3

t

4

Figure 2. Timing Diagram

Table 3. Logic Levels

VIH V I

RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2, CE, UPDATE

IL IH

RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2, CE, UPDATE

I

RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2,

2.0 V min 0.8 V max 20 μA max

t

5

IL

t

6

05774-002

RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2, CE, UPDATE CE, UPDATE

−400 μA min

Rev. 0 | Page 5 of 28

AD8106/AD8107

A

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage 12.0 V
Internal Power Dissipation

AD8106/AD8107 80-Lead LQFP (ST-80-1) 2.6 W
Input Voltage ±V
Output Short-Circuit Duration

θJA 48°C/W
Operating Temperature Range −40°C to 85°C
Storage Temperature Range −65°C to +125°C
Lead Temperature (Soldering 10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

S

Observe power
derating curves

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8106/AD8107 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit can cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package.

Exceeding a junction temperature of 175°C for an extended
period can result in device failure.

While the AD8106/AD8107 is internally short-circuit
protected, this may not be sufficient to guarantee that the
maximum junction temperature (150°C) is not exceeded under
all conditions. To ensure proper operation, it is necessary to
observe the maximum power derating curves shown in

5

4

TION (W)

3

Figure 3.

TJ = 150°C

2

1

MAXIMUM POWER DISSIP

0

–50 80–40 –30 –20 –10 0 10 20 30 40 50 60 70

Figure 3. Maximum Power Dissipation vs. Temperature

AMBIENT TEMPERATURE (°C)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

05774-003

90

Rev. 0 | Page 6 of 28

AD8106/AD8107

Table 5. Operation Truth Table

CE UPDATE

CLK DATA IN DATA OUT

RESET

1 X X X X X No change in logic.
0 1 1

f

D0 … D4
A0 … A2

NA in parallel
mode

0 0 X X X 1

X X X X X 0

D0

DATA

D1
D2
D3
D4

PARALLEL

(OUTPUT
ENABLE)

Operation/Comment

The data on the parallel data lines, D0 to D4, are loaded into
the 40-bit serial shift register location addressed by A0 to A2.

Data in the 40-bit shift register transfers into the parallel
latches that control the switch array. Latches are transparent.

Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.

CLK

CE

UPDATE

A0

A1

A2

3 TO 5 DECODER

(OUTPUT DI SABLE)

OUT0 EN

OUT1 EN

OUT2 EN

OUT3 EN

OUT4 EN

RESET

D

CLK

OUT0

D

D

CLK

OUT0

D

Q

Q

CLK

DLE

B2

Q

OUT0

B3

DLE

Q

Q

Q

CLK

DLE

DLE

OUT0

B0

B1

Q

Q

D

D

CLK

OUT0

EN

SWITCH MATRIX

Q

Q

CLK

DLE

OUT1

B0

QCLR

80

D

CLK

DLE

OUT3

Q

DECODE

EN

D

Q

CLK

DLE

QCLR

Q

OUT4

B0

D

CLK

DLE

Q

Q

DLE

OUT4

B1

Q

OUTPUT ENABL E

D

CLK

OUT4

D

Q

CLK

DLE

B2

Q

5

Q

OUT4

B3

D

Q

CLK

DLE

Q

OUT4

CLR

EN

DLE

Q

05774-004

Figure 4. Logic Diagram

Rev. 0 | Page 7 of 28

AD8106/AD8107

A

A

A

A

A

A

A

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

IN06

IN07

AGND

DVCC

IN08

GND

IN09

GND

IN10

GND

IN11

GND

IN12

GND

IN13

GND

IN14

GND

IN15

GND

AVE E

AVC C

AVC C

NC

DGND

80

79787776757473727170696867

1

2

PIN 1

3

INDICATO R

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

22

21

AVE E

AGND

23

NC

AGND

24

26

25

NC

AVC C

AGND

Figure 5. 80-Lead Plastic LQFP

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

64 , 66, 68, 70, 72, 74, 76, 78, 1,

INxx Analog Inputs; xx = Channel Numbers 00 through 15.

3, 5, 7, 9, 11, 13, 15,
58 CLK Clock, TTL Compatible. Falling edge triggered.
56

UPDATE

Enable (Transparent) Low. Allows serial register to connect directly to switch matrix. Data

latched when high.
61
60

RESET
CE

Disable Outputs, Active Low.

Chip Enable, Enable Low. Must be low to clock in and latch data.
41, 38, 35, 32, 29 OUTyy Analog Outputs; yy = Channel Numbers 00 Through 04.
2, 4, 6, 8, 10, 12, 14, 16, 21, 24, 27,

AGND Analog Ground for Inputs and Switch Matrix.

46, 65, 67, 69, 71, 73, 75, 77
63, 79 DVCC 5 V for Digital Circuitry.
62, 80 DGND Ground for Digital Circuitry.
17, 22, 45 AVEE −5 V for Inputs and Switch Matrix.
18, 19, 25, 44 AVCC +5 V for Inputs and Switch Matrix.
42, 39, 36, 33, 30 AGNDxx Ground for Output Amp; xx = Output Channel Numbers 00 Through 07. Must be connected.
43, 37, 31, 22 AVCCxx/yy +5 V for Output Amplifier. Shared by channel numbers xx and yy. Must be connected.
40, 34, 28 AVEExx/yy −5 V for Output Amplifier. Shared by channel numbers xx and yy. Must be connected.
54 A0 Parallel Data Input, TTL Compatible (Output Select LSB).
53 A1 Parallel Data Input, TTL Compatible (Output Select).
52 A2 Parallel Data Input, TTL Compatible (Output Select MSB).
51 D0 Parallel Data Input, TTL Compatible (Input Select LSB).
50 D1 Parallel Data Input, TTL Compatible (Input Select).
49 D2 Parallel Data Input, TTL Compatible (Input Select).
48 D3 Parallel Data Input, TTL Compatible (Input Select MSB).
47 D4 Parallel Data Input, TTL Compatible (Output Enable).

AGND

IN03

IN04

IN05

AGND

AD8106/AD8107

80L LQFP

(12mm × 12mm)

TOP VIEW

(PINS DOWN)

0.5mm LEAD PITCH

27

28

AGND

AVE E04

16 × 5

29

OUT04

AGND

31

30

32

OUT03

AGND04

VCC03/04

IN02

66

33

35

34

OUT02

AGND03

AVEE02/03

656463

37

36

AGND02

VCC01/02

DGND

RESET

62

61

60

CE

59

RESERVED

58

CLK

57

RESERVED

56

UPDATE

55

RESERVED

54

A0

53

A1

52

A2

51

D0

50

D1

49

D2

48

D3

47

D4

46

AGND

45

AVE E

44

AVC C

43

AVCC00

42

AGND00

41

OUT00

40

38

39

OUT01

AGND01

AVEE00/01

05774-010

IN00

DVCC

IN01

AGND

AGND

Rev. 0 | Page 8 of 28

AD8106/AD8107

V

V

V

V

I/O SCHEMATICS

CC

ESD

INPUT

ESD

RESET

CC

ESD

ESD

20kΩ

AV

EE

05774-005

Figure 6. Analog Input

CC

ESD

OUTPUT

1kΩ

ESD

(AD8107 ONLY)

AV

EE

05774-006

INPUT

Figure 7. Analog Output

DGND

RESET

Figure 8.

ESD

ESD

Input

CC

DGND

Figure 9. Logic Input

05774-007

05774-008

Rev. 0 | Page 9 of 28

AD8106/AD8107

V

V

–

V

–

TYPICAL PERFORMANCE CHARACTERISTICS

5

RL = 150Ω

4

3

2

1

GAIN (dB)

0

–1

–2

–3

100k 1 M 1G10M 100M

FLATNESS

GAIN

2V p-p

FREQUENCY (Hz)

200mV p-p

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

FLATNESS (dB)

05774-011

RL = 150Ω

50

25

0

25mV/DI

–25

–50

05774-014

25ns/DIV

Figure 13. AD8106 Step Response, 100 mV Step Figure 10. AD8106 Frequency Response

30

RL = 1kΩ

–40

–50

–60

–70

CROSSTALK (dB)

–80

–90

–100

0.3 1 20010 100

ALL HOSTILE

ADJACENT

FREQUENCY (Hz)

Figure 11. AD8106 Crosstalk vs. Frequency

40

RL = 150Ω
V

= 2V p-p

OUT

–50

–60

–70

DISTORTION (dB)

–80

–90

2ND HARMONIC

3RD HARMONIC

RL = 150Ω

1.0

0.5

0

0.5V/DI

–0.5

–1.0

05774-012

25ns/DIV

05774-015

Figure 14. AD8106 Step Response, 2 V Step

2V = STEP
R

= 150Ω

L

0.1%/DI

–100

100k

1M 100M10M

FREQUENCY (Hz)

Figure 12. AD8106 Distortion vs. Frequency

05774-013

0 1020304050607080

10ns/DIV

Figure 15. AD8106 Settling Time

05774-016

Rev. 0 | Page 10 of 28

AD8106/AD8107

V

V

–

V

–

5

0.8

4

3

2

1

GAIN (dB)

0

–1

–2

–3

100k 1M 1G10M 100M

FLATNESS

GAIN

2V p-p

FREQUENCY (Hz)

Figure 16. AD8107 Frequency Response

20

RL = 1kΩ

–30

–40

–50

–60

–70

CROSST ALK (dB)

–80

–90

–100

–110

0.3 1 20010 100

ADJACENT

FREQUENCY (MHz)

ALL HOSTIL E

200mV p-p

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

1.0

0.5

0

25mV/DI

FLATNESS (dB)

05774-017

–0.5

–1.0

25ns/DIV

05774-020

Figure 19. AD8107 Step Response, 100 mV Step

1.0

0.5

0

500mV/DI

–0.5

–1.0

05774-018

25ns/DIV

05774-021

Figure 17. AD8107 Crosstalk vs. Frequency

30

RL = 150Ω

–40

V

= 2V p-p

OUT

–50

–60

–70

DISTORTION (dB)

–80

–90

–100

100k

2ND HARMONIC

3RD HARMONIC

1M 10M 100M

FREQUENCY (Hz)

0.1%/DI

05774-019

Figure 18. AD8107 Distortion vs. Frequency

Figure 20. AD8107 Step Response, 2 V Step

2V STEP RTO
R

= 150Ω

L

0 1020304050607080

10ns/DIV

Figure 21. AD8107 Settling Time

05774-022

Rev. 0 | Page 11 of 28

AD8106/AD8107

V

–

30

RL = 150Ω

–40

–50

–60

–70

–80

POWER SUPPL Y REJECTIO N RATIO (d B)

–90

10k 100k 10M1M

FREQUENCY (Hz)

Figure 22. AD8106 PSRR vs. Frequency

100.00

56.30

31.60

17.80

(nV/ Hz)

10.00

5.630

3.16

100 10k 1M

10 1k 10M

FREQUENCY (Hz)

100k

5

4

3

1V/DIV

2

1

0

10

0

10mV/DI

–10

05774-023

Figure 25. AD8106 Switching Transient (Glitch)

VIN = 2V p-p

–50

R

= 150Ω

L

–60

–70

–80

–90

–100

OFF IS OLATION (dB)

–110

–120

–130

05774-024

100k 1M 500M10M 100M

SWITCHING BETWEEN

TWO INPUTS

UPDATE INPUT

TYPICAL VIDEO OUT (RTO)

50ns/DIV

FREQUENCY (Hz)

05774-026

05774-027

Figure 23. AD8106 Voltage Noise vs. Frequency

1M

100k

10k

OUTPUT IMPEDANCE (Ω)

1k

100

0.1 1 50010
FREQUENCY (MHz)

Figure 24. AD8106 Output Impedance, Disabled

100

OUTPUT IMPEDANCE (Ω)

05774-025

Figure 26. AD8106 Off Isolation, Input/Output

10k

1k

100

10

1

0.1
100k

1M 500M10M 100M

FREQUENCY (Hz)

Figure 27. AD8106 Output Impedance, Enabled

05774-028

Rev. 0 | Page 12 of 28

AD8106/AD8107

V

–

–

30

RL = 150Ω

–40

–50

–60

–70

POWER SUPPLY REJECTI ON RATIO (dB RTI)

–80

10k 100k 1M 10 M

FREQUENCY (Hz)

5

4

3

1V/DIV

2

1

0

10

0

10mV/DI

–10

05774-029

SWITCHING BETWEEN

TWO INPUTS

UPDATE INPUT

TYPICAL VI DEO OUT (RTO)

50ns/DIV

05774-032

Figure 28. AD8107 PSRR vs. Frequency

100.00

56.30

31.60

17.80

(nV/ Hz)

10.00

5.63

3.16
10 1k 10M100k

100 10k 1M

FREQUENCY (Hz)

Figure 29. AD8107 Voltage Noise vs. Frequency

100k

10k

Figure 31. AD8107 Switching Transient (Glitch)

40

`

= 2V p-p

V

OUT

= 150Ω

R

–50

L

–60

–70

–80

–90

–100

OFF IS OLATIO N (dB)

–110

–120

05774-030

–130

100k 1M 500M10M 100M

FREQUENCY (Hz)

05774-033

Figure 32. AD8107 Off Isolation, Input/Output

1k

100

1k

OUTPUT IMPEDANCE (Ω)

100

10

0.1 1 50010

FREQUENCY (MHz)

Figure 30. AD8107 Output Impedance, Disabled

100

05774-031

10

OUTPUT IMPEDANCE (Ω)

1

0.1
100k

1M 500M10M 100M

FREQUENCY (Hz)

Figure 33. AD8107 Output Impedance, Enabled

05774-034

Rev. 0 | Page 13 of 28

AD8106/AD8107

V

10M

1M

100k

10k

INPUT IMPEDANCE (Ω)

1k

100

30k

100k 1M 10M 100M 500M

FREQUENCY (Hz)

INPUT 1 AT +1V

1

0

1V/DIV

–1

5

0

2V/DI

05774-035

INPUT 0 AT –1V

50ns/DIV

V

OUT

UPDATE

05774-038

Figure 34. AD8106 Input Impedance vs. Frequency

14

VIN = 200mV p-p

12

R

= 150Ω

L

10

8

6

4

GAIN (dB)

2

0

–2

–4

0.1M 1M

10M 100M 1G

FREQUENCY (Hz)

18pF = 7.7 dB

12pF = 4.5 dB

260

240

220

200

180

160

140

120

FREQUENCY

100

80

60

40

05774-036

3G

20

–0.02

0

Figure 37. AD8106 Switching Time

–0.01 0 0.01

OFFSET VOLTAGE (V)

Figure 35. AD8106 Frequency Response vs. Capacitive Load Figure 38. AD8106 Offset Voltage Distribution

0.7

= 200mV p-p

V

IN

0.6

R

= 150Ω

L

0.5

0.4

0.3

0.2

FLATNESS (dB)

0.1

0

–0.1

–0.2

0.1M 1M 10M 100M 1G

CL = 18pF

CL = 12pF

FREQUENCY (Hz)

Figure 36. AD8106 Flatness vs. Capacitance Load

05774-037

3G

2.0

1.5

1.0

0.5

0

(mV)

OS

V

–0.5

–1.0

–1.5

–2.0

–60 –40 100–200 20406080

TEMPERATURE (° C)

Figure 39. AD8106 Offset Voltage vs. Temperature (Normalized at 25°C)

0.02

05774-039

05774-040

Rev. 0 | Page 14 of 28

AD8106/AD8107

V

10M

INPUT 1 AT +1V

1M

100k

10k

INPUT IMPEDANCE (Ω)

1k

100

30k 1M 500M10M 100M

100k

FREQUENCY (Hz)

Figure 40. AD8107 Input Impedance vs. Frequency

12

10

8

6

4

2

GAIN (dB)

0

–2

–4

–6

0.1M 1M 10M 100M 1G 3G

FREQUENCY (Hz)

18pF

12pF

Figure 41. AD8107 Frequency Response vs. Capacitive Load

1

0

1V/DIV

–1

5

0

2V/DI

05774-041

INPUT 0 AT –1V

50nS/DIV

V

OUT

UPDATE

05774-044

Figure 43. AD8107 Switching Time

480

440

400

360

320

280

240

200

FREQUENCY

160

120

80

05774-042

40

0

–0.02 0.02–0.01 0 0.01

OFFSET VO LTAGE (V)

05774-045

Figure 44. AD8107 Offset Voltage Distribution (RTI)

0.7

VIN = 100mV

0.6
R

= 150Ω

L

0.5

0.4

0.3

0.2

GAIN (dB)

0.1

0

–0.1

–0.2

–0.3

0.1M 1M 10M 100M 1G

18pF

12pF

FREQUENCY (Hz)

Figure 42. AD8107 Flatness vs. Capacitive Load

05774-043

3G

2.0

1.5

1.0

0.5

(mV)

0

OS

V

–0.5

–1.0

–1.5

–2.0

–60 –40 100–20 0 20 40 60 80

TEMPERATURE (° C)

05774-046

Figure 45. AD8107 Offset Voltage Drift vs. Temperature (Normalized at 25°C)

Rev. 0 | Page 15 of 28

AD8106/AD8107

THEORY OF OPERATION

The AD8106 (G = 1) and AD8107 (G = 2) share a common core
architecture consisting of an array of 80 transconductance (gm)
input stages that are organized as five 16:1 multiplexers with a
common, 16-line analog input bus. Each multiplexer is
essentially a folded-cascode high speed voltage, feedback
amplifier with 16 input stages. The input stages are NPN
differential pairs whose differential current outputs are
combined at the output stage, which contains the high
impedance node, compensation, and a complementary emitter
follower output buffer. In the AD8106, the output of each
multiplexer is fed directly back to the inverting inputs of its
16 gm stages. In the AD8107, the feedback network is a voltage
divider consisting of two equal-value resistors.

This switched-gm architecture results in a low power crosspoint
switch that is able to directly drive a back-terminated video load
(150 Ω) with low distortion (differential gain and differential
phase errors are better than 0.02% and 0.02°, respectively). This
design also achieves high input resistance and low input
capacitance without the signal degradation and power
dissipation of additional input buffers. However, the small input
bias current at any input increases almost linearly with the
number of outputs programmed to that input.

The output disable feature of these crosspoints allows larger
switch matrices to be built simply by busing together the
outputs of multiple 16 × 5 ICs. However, while the disabled
output impedance of the AD8106 is very high (10 MΩ), the
AD8107 output impedance is limited by the resistive feedback
network, which has a nominal total resistance of 1 kΩ and
appears in parallel with the disabled output. If the outputs of
multiple AD8107s are connected through separate back
termination resistors, the loading lowers the effective back
termination impedance of the overall matrix because of these
finite output impedances. This problem is eliminated if the
outputs of multiple AD8107s are connected directly and share a
single back-termination resistor for each output of the overall
matrix. This configuration increases the capacitive loading of
the disabled AD8107 on the output of the enabled AD8107.

POWER-ON RESET

When powering up the AD8106/AD8107, it is usually necessary

RESET

to have the outputs be in the disabled state. The
when taken low, causes all outputs to be in the disabled state.

RESET

The
be used to create a simple power-up reset circuit. A capacitor
from
the rest of the device stabilizes. The low condition causes all the
outputs to disable. The capacitor then charges through the pull­up resistor to the high state, allowing full programming
capability of the device.

pin has a 20 kΩ pull-up resistor to DVDD that can

RESET

to ground holds

RESET

low for some time while

pin,

INITIALIZATION

The AD8106/AD8107 should be initialized after power up to
control the supply and bias currents, and to make sure that no
unexpected program states are encountered. Initialization is
performed by writing a data word of 00000 into all address
locations 00 to 07 (000 to 111 binary).

GAIN SELECTION

The 16 × 5 crosspoints come in two versions depending on the
desired gain of the analog circuit paths. The AD8106 device is
unity gain and can be used for analog logic switching and other
applications where unity gain is desired. The AD8106 can also
be used for the input and interior sections of larger crosspoint
arrays where termination of output signals is not usually used.
The AD8106 outputs have very high impedance when their
outputs are disabled.

For devices that drive a terminated cable with its outputs, the
AD8107 can be used. This device has a built-in gain of two that
eliminates the need for a gain-of-two buffer to drive a video
line. Because of the presence of the feedback network in these
devices, the disabled output impedance is about 1 kΩ.

CREATING LARGER CROSSPOINT ARRAYS

The AD8106/AD8107 are high density building blocks that
create crosspoint arrays for dimensions larger than 16 × 5.
Various features such as output disable, chip enable, and gain­of-one and gain-of-two options are useful for creating larger
arrays. For very large arrays, they can be used with the

AD8114/AD8115, 16 × 16 video crosspoint devices, or the
AD8110/AD8111, 16 x 8 video crosspoint devices. When required

for customizing a crosspoint array size, the parts can also be
used with the
gain-of-two) of 8 × 8 video crosspoint switches.

The first consideration in constructing a larger crosspoint is to
determine the minimum number of required devices. The 16 × 5
architecture of the AD8106/AD8107 contains 80 points. For a
nonblocking crosspoint, the number of points required is the
product of the number of inputs multiplied by the number of
outputs. Nonblocking requires that the programming of a given
input to one or more outputs does not restrict the availability of
that input to be a source for any other output.

Some nonblocking crosspoint architectures require more than this
minimum as calculated above. In addition, there are blocking
architectures that can be constructed with fewer devices than this
minimum. These systems have connectivity available on a statistical
basis that is determined when designing the overall system.

The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to wire-OR
the outputs together in a vertical direction.

AD8108 and AD8109, a pair (unity gain and

Rev. 0 | Page 16 of 28

AD8106/AD8107

Figure 46 illustrates this concept for a 32 × 5 crosspoint array.

16

16

AD8106

OR

AD8107

5

AD8106

OR

AD8107

5

5774-047

R

R

16

TERM

16

TERM

IN 00–15

IN 16–31

Figure 46. A 32 × 5 Crosspoint Array Using Two AD8106s or Two AD8107s

The inputs are uniquely assigned to each of the 32 inputs of the
two devices and terminated appropriately. The outputs are wire­OR’ed together in pairs. The output from only one of a wire-OR’ed
pair should be enabled at any given time. The device program­ming software must be properly written to cause this to happen.

At some point, the number of outputs that are wire-OR’ed becomes
too great to maintain system performance. This varies according
to which system specifications are most important. It also
depends on whether the matrix consists of AD8106s or AD8107s.

RANK 1

(8 × AD8106)

IN 00–15

128:16

R

AD8106

TERM

16

5

5

The output disabled impedance of the AD8106 is much
higher than that of the AD8107. As a result, its disabled
parasitics have a smaller effect on the one output that is
enabled. For example, a 128 × 5 crosspoint can be created
with eight AD8106s/AD8107s. This design has 128 separate
inputs and the corresponding outputs of each device wire­OR’ed together in groups of eight.

Using additional crosspoint devices in the design can lower the
number of outputs that must be wire-OR’ed together.

Figure 47
shows a block diagram of a system using eight AD8106s and
two AD8107s to create a nonblocking, gain-of-two, 128 × 5
crosspoint that restricts the wire-OR’ing at the output to only
four outputs.

Additionally, by using the lower four outputs from each of the
two Rank 2 AD8107s, a blocking 128 × 10 crosspoint array can
be realized. There are, however, some drawbacks to this technique.
The offset voltages of the various cascaded devices accumulate
and the bandwidth limitations of the devices compound. The
extra devices also consume more current and take up more
board space. Once again, the overall system design specifica­tions determine which tradeoffs should be made.

IN 16–31

IN 32–47

IN 48–63

IN 64–79

IN 80–95

IN 96–111

IN 112–127

16

16

16

16

16

16

16

R

R

R

R

R

R

R

AD8106

TERM

AD8106

TERM

AD8106

TERM

AD8106

TERM

AD8106

TERM

AD8106

TERM

AD8106

TERM

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

1kΩ

5

1kΩ

RANK 2

16:8 NONBLOCKING

(16:16 BLOCKING)

5

AD8107

5

1kΩ

5
1kΩ

AD8107

5

5

5

OUT 00–04
NONBLOCKING

ADDITIONAL
5 OUTPUTS
(SUBJECT TO
BLOCKING)

Figure 47. A Gain-of-Two 128 × 5 Nonblocking Crosspoint Array (128 × 10 Blocking)

05774-048

Rev. 0 | Page 17 of 28

AD8106/AD8107

(

(

CROSSTALK

Many systems, such as broadcast video, handle numerous
analog signal channels that have strict requirements for keeping
the various signals from influencing others in the system.
Crosstalk is the term used to describe the undesired coupling
between signals of other nearby channels to a given channel.

When many signals are in close proximity in a system, as is
undoubtedly the case in a system that uses the AD8106/
AD8107, the crosstalk issues can be quite complex. A good
understanding of the nature of crosstalk and its associated
terms is required to specify a system that uses one or more
AD8106s/AD8107s.

Types of Crosstalk

Crosstalk can be propagated by means of one of three methods.
These fall into the categories of electric field, magnetic field, and
sharing of common impedances. This section explains these effects.

Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter
propagates across a stray capacitance (free space, for example),
couples with the receiver, and induces a voltage. This voltage is
an unwanted crosstalk signal in any channel that receives it.

Currents flowing into conductors create magnetic fields that
circulate around the currents. These magnetic fields then
generate voltages in any other conductors whose paths they
link. The undesired induced voltages in these channels are
crosstalk signals. The channels that crosstalk have a mutual
inductance that couples signals from one channel to another.

The power supplies, grounds, and other signal return paths of a
multichannel system are generally shared by the various
channels. When a current from one channel flows into one of
these paths, a voltage develops across the impedance and
becomes an input crosstalk signal for other channels that share
the common impedance.

All these sources of crosstalk are vector quantities, so the magni­tudes cannot simply be added together to obtain the total crosstalk.
In fact, there are conditions when driving additional circuits in
parallel in a given configuration can actually reduce the crosstalk.

Areas of Crosstalk

A practical AD8106/AD8107 circuit is required to be mounted
to some sort of circuit board to connect to power supplies and
measurement equipment. Great care has been taken to create a
characterization board (also available as an evaluation board) that
adds minimum crosstalk to the intrinsic device. This, however,
raises the issue that a system’s crosstalk is a combination of the
device’s intrinsic crosstalk and the circuit board to which they
are mounted. It is important to try to separate these two areas of
crosstalk when attempting to minimize its effect.

In addition, crosstalk can occur among the inputs to a
crosspoint as well as among the outputs. It can also occur
from input to output. Refer to the
section for techniques to diagnose which part of a system is
contributing to crosstalk.

Input and Output Crosstalk

Measuring Crosstalk

Crosstalk is measured by applying a signal to one or more
channels and measuring the relative strength of that signal on a
desired selected channel. The measurement is usually expressed
as dB down from the magnitude of the test signal. The crosstalk
is expressed by

=

where:

s = jw is the Laplace transform variable.
Asel(s) is the amplitude of the crosstalk-induced signal in the

selected channel.
Atest(s) is the amplitude of the test signal.

It can be seen that crosstalk is a function of frequency, but not a
function of the test signal’s magnitude (to first order). The crosstalk
signal also has a phase relative to its associated test signal.

A network analyzer is most commonly used to measure
crosstalk over a frequency range of interest. It can provide both
magnitude and phase information about the crosstalk signal.

As a crosspoint system or device grows, the number of theoretical
crosstalk combinations and permutations can become extremely
large. For example, in the case of the 16 x 5 matrix of the
AD8106/AD8107, examine the number of crosstalk terms that
can be considered for a single channel, such as the IN00 input.
IN00 is programmed to connect to one of the AD8106/AD8107
outputs where the measurement can be made.

First, measure the crosstalk terms associated with driving a test
signal into each of the other 15 inputs one at a time. Then measure
the crosstalk terms associated with driving a parallel test signal
into all 15 other inputs taken two at a time in all possible
combinations; and then three at a time, and so on, until finally,
there is only one way to drive a test signal into all 15 other inputs.

Each of these cases is legitimately different from the others and
could yield a unique value depending on the resolution of the
measurement system. However, it is impractical to measure all
of these terms and then to specify them. In addition, this
describes the crosstalk matrix for only one input channel. A
similar crosstalk matrix can be proposed for every other input.
If the possible combinations and permutations for connecting
inputs to the other outputs (not used for measurement) are
taken into consideration, the numbers grow rather quickly to
astronomical proportions. If a larger crosspoint array of
multiple AD8106/AD8107s is constructed, the numbers grow
larger still.

10

)()

)

(1)

sAtestsAselXT /log20

Rev. 0 | Page 18 of 28

AD8106/AD8107

(

[

(

)

Obviously, some subset of all these cases must be selected to be
used as a guide for a practical measure of crosstalk. One
common method is to measure all hostile crosstalk, which
means that the crosstalk to the selected channel is measured
while all other system channels are driven in parallel. In general,
this yields the worst crosstalk number, but this is not always the
case due to the vector nature of the crosstalk signal.

Other useful crosstalk measurements are those created by one
of the nearest neighbors or by two of the nearest neighbors on
either side. These crosstalk measurements are generally higher
than those of more distant channels, so they can serve as a
worst-case measure for any other one-channel or two-channel
crosstalk measurements.

Input and Output Crosstalk

The flexible programming capability of the AD8106/AD8107
can be used to diagnose whether crosstalk is occurring more on
the input side or the output side. For example, a given input
channel, such as IN07 in the middle, can be programmed to
drive OUT01. The input to IN07 is terminated to ground (via
50 Ω or 75 Ω) and no signal is applied.

All the other inputs are driven in parallel with the same test
signal (practically provided by a distribution amplifier) with all
other outputs disabled, except OUT01. Because grounded IN07
is programmed to drive OUT01, no signal should be present. If
any signal is present, it can be attributed to the other 15 hostile
input signals because no other outputs are driven; that is, they
are all disabled. Thus, this method measures the all-hostile input
contribution to crosstalk into IN07. This method can also be used
for other input channels and combinations of hostile inputs.

For output crosstalk measurement, a single input channel
(IN00, for example) is driven and all outputs other than a given
output are programmed to connect to IN00. OUT01 is
programmed to connect to IN15, which is far away from IN00,
and is terminated to ground. As a result, OUT01 should not
have a signal present because it is listening for a quiet input.
Any signal measured at the OUT01 can be attributed to the
output crosstalk of the other seven hostile outputs. Again, this
method can be modified to measure other channels and other
crosspoint matrix combinations.

Effect of Impedances on Crosstalk

The input side crosstalk can be influenced by the output
impedance of the sources that drive the inputs. The lower the
impedance of the drive source, the lower the magnitude of the
crosstalk. The dominant crosstalk mechanism on the input side
is capacitive coupling. The high impedance inputs do not have
significant current flow to create magnetically induced crosstalk.
However, significant current can flow through the input
termination resistors and the loops that drive them. Thus,
the PC board on the input side can contribute to magnetically
coupled crosstalk.

From a circuit standpoint, the input crosstalk mechanism looks
like a capacitor coupling to a resistive load. For low frequencies,
the magnitude of the crosstalk is given by

)

(2)

]

sCRXT

×=10log20

M

S

where:

R

is the source resistance.

S

is the mutual capacitance between the test signal circuit and

C

M

the selected circuit.
s is the Laplace transform variable.

Equation 2 shows that this crosstalk mechanism has a high-pass
nature; it can also be minimized by reducing the coupling
capacitance of the input circuits and lowering the output
impedance of the drivers. If the input is driven from a 75 Ω
terminated cable, the input crosstalk can be reduced by
buffering this signal with a low output impedance buffer.

On the output side, the crosstalk can be reduced by driving a
lighter load. Although the AD8106/AD8107 are specified with
excellent differential gain and phase when driving a standard
150 Ω video load, the crosstalk is higher than the minimum
obtainable because of the high output currents. These currents
induce crosstalk via the mutual inductance of the output pins
and bond wires of the AD8106/AD8107.

From a circuit standpoint, this output crosstalk mechanism
looks like a transformer with a mutual inductance between the
windings that drive a load resistor. For low frequencies, the
magnitude of the crosstalk is given by

(3)

RsMxyXT /log20

10

where:

Mxy is the mutual inductance of output x to output y.
R

is the load resistance on the measured output.

L

This crosstalk mechanism can be minimized by keeping the
mutual inductance low and increasing R
inductance can be kept low by increasing the spacing of the
conductors and minimizing their parallel length.

×=

L

. The mutual

L

PCB LAYOUT

Extreme care must be exercised to minimize additional
crosstalk generated by the system circuit board(s). The areas
that must be carefully detailed are grounding, shielding, signal
routing, and supply bypassing.

The packaging of the AD8106/AD8107 is designed to help keep
the crosstalk to a minimum. Each input is separated from other
inputs by an analog ground pin. All of these AGNDs should be
connected directly to the ground plane of the circuit board.
These ground pins provide shielding, low impedance return
paths, and physical separation for the inputs. All of these help to
reduce crosstalk.

Rev. 0 | Page 19 of 28

AD8106/AD8107

Each output is separated from its two neighboring outputs by an
analog ground pin and an analog supply pin of one polarity or
the other. Each of these analog supply pins provides power to
the output stages for only the two nearest outputs. These supply
pins and analog grounds provide shielding, physical separation,
and a low impedance supply for the outputs. Individual
bypassing of these supply pins with a 0.01 μF chip capacitor
directly to the ground plane minimizes high frequency output
crosstalk via the mechanism of sharing common impedances.

Each output also has an on-chip compensation capacitor that is
individually tied to the nearby analog ground pins AGND00
through AGND03. This technique reduces crosstalk by preventing

the currents that flow in these paths from sharing a common
impedance on the IC and in the package pins. These AGNDxx
signals should all be connected directly to the ground plane.

The input and output signals have minimum crosstalk if they
are located between ground planes on layers above and below,
and separated by ground in between. Vias should be located as
close to the IC as possible to carry the inputs and outputs to the
inner layer. The only place the input and output signals surface
is at the input termination resistors and the output series back
termination resistors. These signals should also be separated, to
the largest extent possible, as soon as they emerge from the IC
package.

Rev. 0 | Page 20 of 28

AD8106/AD8107

R

EVALUATION BOARD

A 4-layer evaluation board is available for the AD8106/
AD8107. The same board and external components are used for
each device. The only difference is the device itself, which offers
a selection of a gain of unity or a gain of two through the analog
channels. This board has been carefully laid out and tested to
demonstrate the specified high speed performance of the
device.

Figure 49 shows the schematic of the evaluation board.
Figure 50 shows the component side silkscreen. The layout of
the board’s four layers are given in:

• Component Layer (see

• Signal Routing Layer (see

• Power Layer (see

• Bottom Layer (see

Figure 51)

Figure 52)

Figure 53)

Figure 54)

b = 0.024"

(0.6mm)

Figure 48. Cross Section of Input and Output Traces

The board has 24 BNC-type connectors: 16 inputs and 8 outputs.
The connectors are arranged in a crescent around the device.
As shown in
and all 8 signal output traces having the same length. This is
useful in tests such as all-hostile crosstalk where the phase
relationship and delay between signals needs to be maintained
from input to output.

w = 0.008"

(0.2mm)

COMPONENT LAYER

SIGNAL ROUTING LAYE

POWER PLANE LAYER

BOTTOM LAYER

a = 0.008"

(0.2mm)

t = 0.00135" (0.0343mm)

h = 0.011325"

(0.288mm)

Figure 53, this results in all 16 input signal traces

05774-049

The evaluation board package includes the following:

• Fully populated board with BNC-type connectors.

• Windows®-based software for controlling the board from a

PC via the printer port.

• Custom cable to connect evaluation board to PC.

• Disk containing Gerber files of board layout.

Optimized for video applications, all signal inputs and outputs
are terminated with 75 Ω resistors. Stripline techniques are used
to achieve a characteristic impedance on the signal input and
output lines, also of 75 Ω.

Figure 48 shows a cross section of one
of the input or output tracks along with the arrangement of the
PCB layers. Note that unused regions of the four layers are filled
up with ground planes. As a result, the input and output traces,
in addition to having controlled impedances, are well shielded.

The three power supply pins, AVCC, DVCC, and AVEE, should
be connected to good quality, low noise, ±5 V supplies. While
the same ±5 V power supplies are used for analog and digital,
separate cables should be run for the power supply to the
evaluation board’s analog and digital power supply pins.

As a general rule, each power supply pin (or group of adjacent
power supply pins) should be locally decoupled with a 0.01 μF
capacitor. If there is a space constraint, decouple analog power
supply pins before digital power supply pins. A 0.1 μF capacitor
located reasonably close to the pins can be used to decouple a
number of power supply pins. Finally, a 10 μF capacitor should
be used to decouple power supplies as they come on to the board.

Rev. 0 | Page 21 of 28

AD8106/AD8107

A

V

A

VCC

DVCC DGND NC

P1-1

P1-2

+

CR1

CR2

0.1µF 10µF 0.1µF 10µF

EE AGND

NC

P1-3

P1-4

0.1µF 10µF

INPUT 00 IN00

INPUT 01 IN01

INPUT 02 IN02

INPUT 03 IN03

INPUT 04 IN04

INPUT 05 IN05

INPUT 06 IN06

INPUT 07 IN07

INPUT 08 IN08

INPUT 09 IN09

INPUT 10 IN10

INPUT 11 IN11

INPUT 12 IN12

INPUT 14 IN13

INPUT 14 IN14

INPUT 15 IN15

P2-5

P2-4

P2-2

P2-3

P2-1

P2-6

P1-6

P1-5

+

75Ω

75Ω

75Ω

75Ω

75Ω

75Ω

75Ω

75Ω

75Ω

75Ω

75Ω

75Ω

75Ω

75Ω

75Ω

75Ω

+

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

1

2

3
4

5

6

7

8

9

10

11

12

13

14

15
16

57

59

80

P1-7

DVCCDVCC

0.01µF

79

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

RESERVED

RESERVED

DGND

DGND

62 61 60 58 56 55 54 53 52 51 50 49 48 47

P2-5

63

DVCCDVCC

CE

CLK

RESET

P2-4

P2-3

P2-3

AVC C

0.01µF 0.01µF 0.01µF 0.01µF

43

AVC C

AD8106/AD8107

RESERVED

UPDATE

A0A1A2D0D1D2D3

P2-1

P2-6

P2-5

P2-4

Figure 49. Evaluation Board Schematic

AVC C

44

AVC C

P2-3

AVE E

45

AVE E

D4

P2-2

P2-1

P2-6

P2-5

P2-4

AGND

AGND

OUT00

AVE E

AGND

OUT01

AVC C

AGND

OUT02

AVE E

AGND

OUT03

AVC C

AGND

OUT04

AVE E

AGND

NC

AVC C

AGND

NC

AVE E

AGND

NC

AVC C

AVC C

AVE E

46

42

75Ω

41

40

39

75Ω

38

37

36

75Ω

35

34

33

75Ω

32

31

30

75Ω

29

28

27

26

25

24

23

22

21

20

19

18

17

R25

20kΩ

SERIAL MODE
JUMP

0.01µF

0.01µF

0.01µF

0.01µF

0.01µF

0.01µF

0.01µF

0.01µF

0.01µF

DVCC

AVE E

AVC C

AVE E

AVC C

AVE E

AVC C

AVE E

AVC C

AVC C

AVE E

05774-050

Rev. 0 | Page 22 of 28

AD8106/AD8107

AD8106
AD8107

5774-051

Figure 50. Component Side Silkscreen

05774-052

Figure 51. Board Layout (Component Side)

05774-053

Figure 52. Board Layout (Signal Routing Layer)

Rev. 0 | Page 23 of 28

AD8106/AD8107

Figure 53. Board Layout (Power Plane Layer)

05774-054

05774-055

Figure 54. Board Layout (Bottom Layer)

Rev. 0 | Page 24 of 28

AD8106/AD8107

CONTROLLING THE EVALUATION BOARD FROM A PC

The evaluation board includes Windows-based control software
and a custom cable that connects the board’s digital interface to
the printer port of a PC. The wiring of this cable is shown in
Figure 55. The software requires Windows 3.1 or later to operate.
Before the start of the installation, terminate any other Windows
applications that are running. To install the software, insert
the disk labeled Disk #1 of 2 in the PC and run the setup.exe file.
Additional installation instructions are given on-screen.

MOLEX 0.100" CENTER

CRIMP TERMI NAL HOUSING

RESET

CLK

CE

UPDATE

DATA IN

DGND

2
3
4
5
6
25

EVALUATION BOARD PC

1

6

MOLEX

TERMINAL HOUSI NGD-SUB-25

3
1
4
5
2
6

SIGNAL
CE

RESET
UPDATE
DATA IN
CLK

DGND

Figure 55. Evaluation Board PC Connection Cable

D-SUB 25 PIN (MALE)

1

14

25

13

05774-056

When launching the crosspoint control software, users are
asked to select their desired printer port. Most modern PCs
have only one printer port, usually called LPT1. However, some
laptop computers use the PRN port.

Figure 56 shows the main screen of the control software in its
initial reset state (all outputs off). Using the mouse, any input
can be connected with one or more outputs by simply clicking
on the appropriate radio buttons in the 16 × 8 on-screen array.
Each time a button is clicked on, the software automatically sends
and latches the required 40-bit data stream to the evaluation board.
An output can be turned off by clicking the appropriate button
in the off column. To turn all outputs on, click

RESET

.

The software offers volatile and nonvolatile configuration
storage. For volatile storage, up to two configurations can be
stored and recalled using the Memory 1 Buffer and Memory 2
Buffer. These function in an identical fashion to the memory on
a pocket calculator. For nonvolatile storage of a configuration,
the Save Setup and Load Setup functions can be used. This
stores the configuration as a data file on disk.

DATA-LINE OVERSHOOT ON PRINTER PORTS

The data lines on some printer ports have excessive overshoot.
Overshoot on the pin that is used as the serial clock (Pin 6 on
the D-Sub-25 connector) can cause communication problems.
This overshoot can be eliminated by connecting a capacitor
from the CLK line on the evaluation board to ground. A pad
has been provided on the solder side of the evaluation board to
allow this capacitor to be soldered into place. Depending upon
the overshoot from the printer port, this capacitor may need to
be as large as 0.01 μF.

Rev. 0 | Page 25 of 28

AD8106/AD8107

AD8106/AD8107

Figure 56. Evaluation Board Control Panel

5774-057

Rev. 0 | Page 26 of 28

AD8106/AD8107

OUTLINE DIMENSIONS

PIN 1

14.00

BSC SQ

6180

60

0.75

0.60

0.45

1.60
MAX

1

12.00

BSC SQ

41

40

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0.20

0.09

7°

3.5°
0°

0.08 MAX
COPLANARITY

COMPLIANT TO JEDEC STANDARDS MS-026-BDD

VIEW A

20

21

LEAD PITCH

0.50

BSC

TOP VIEW

(PINS DOWN)

0.27

0.22

0.17

Figure 57. 80-Lead Low Profile Quad Flat Package [LQFP]

(ST-80-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8106ASTZ −40°C to +85°C 80-Lead Low Profile Quad Flat Package [LQFP] ST-80-1
AD8107ASTZ1 −40°C to +85°C 80-Lead Low Profile Quad Flat Package [LQFP] ST-80-1
AD8106-EB Evaluation Board
AD8107-EB Evaluation Board

1

Z = Pb-free part.

1

Rev. 0 | Page 27 of 28

AD8106/AD8107

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05774-0-3/06(0)

T

Rev. 0 | Page 28 of 28

TTT