Datasheet AD809BR-REEL7, AD809BR Datasheet (Analog Devices)

a

155.52 MHz Frequency Synthesizer
AD809

FEATURES
Frequency Synthesis to 155.52 MHz

19.44 MHz or 9.72 MHz Input
Reference Signal Select Mux
Single Supply Operation: +5 V or –5.2 V
Output Jitter: 2.0 Degrees RMS
Low Power: 90 mW
10 KH ECL/PECL Compatible Output
10 KH ECL/PECL/TTL/CMOS Compatible Input
Package: 16-Pin Narrow 150 Mil SOIC

PRODUCT DESCRIPTION

The AD809 provides a 155.52 MHz ECL/PECL output clock from
either a 19.44 MHz or a 9.72 MHz TTL/CMOS/ECL/PECL refer­ence frequency. The AD809 functionality supports a distributed
timing architecture, allowing a backplane or PCB 19.44 MHz or

9.72 MHz timing reference signal to be distributed to multiple

FUNCTIONAL BLOCK DIAGRAM

CLKIN

CLKINN

PECLIN

PECLINN

MUX

13

12

10

2

1

15

AUTO

SELECT

AD809

PFD

(19.44MHz

OR

9.72MHz)

TTL/CMOSIN

(155MHz)

155.52 Mbps ports. The AD809 can be applied to create the trans­mit bit clock for one or more ports.

An input signal multiplexer supports loop-timed applications
where a 155.52 MHz transmit bit clock is recovered from the

155.52 Mbps received data.
The low jitter VCO, low power and wide operating temperature

range make the device suitable for generating a 155.52 MHz bit
clock for SONET/SDH/Fiber in the Loop systems.

The device has a low cost, on-chip VCO that locks to either
8× or 16× the frequency at the 19.44 MHz or 9.72 MHz input.
No external components are needed for frequency synthesis; how­ever, the user can adjust loop dynamics through selection of a
damping factor capacitor whose value determines loop damping.

The AD809 design guarantees that the clock output frequency
will drift low (by roughly 20%) in the absence of a signal at the
input.

The AD809 consumes 90 mW and operates from a single power
supply at either +5 V or –5.2 V.

CF1 CF2

8

7

LOOP

FILTER

BW
ADJUST

AUTO SELECT
DIVIDE BY 8/16

MUX

VCO

5

CLKOUT

4

CLKOUTN
(155MHz
PECL
OUTPUT)

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

AD809–SPECIFICATIONS

(TA = T

MIN

to T

MAX

, VS = V

MIN

to V

, CD = 22 nF, unless otherwise noted)

MAX

Parameter Condition Min Typ Max Units

TRACKING AND CAPTURE RANGE

1

×8 Synthesis 19.42 19.46 MHz
×16 Synthesis 9.71 9.73 MHz

OUTPUT JITTER ×8 Synthesis 1.6 2.9 Degrees RMS

×16 Synthesis 1.6 2.9 Degrees RMS

JITTER TRANSFER

Bandwidth 200 kHz
Peaking C

= 5.6 nF (ζ = 5) 0.08 dB

D

C

= 22 nF (ζ = 10) 0.02 dB

D

DUTY CYCLE TOLERANCE ×8 or ×16 Synthesis

Output Jitter ≤ 2.9 Degrees RMS 15 85 %

INPUT VOLTAGE LEVELS

PECL

Input Logic High, V
Input Logic Low, V

IL

IH

@ CLKIN/N and 3.8 V

CC

Volts

PECLIN/N Inputs 3.1 3.6 Volts

TTL

Input Logic High, V
Input Logic Low, V

IH

IL

OUTPUT VOLTAGE LEVELS Referenced to V

@ TTL/CMOSIN 2.0 Volts
and MUX Inputs 0.8 Volts

CC

PECL

Output Logic High, V
Output Logic Low, V

OL

OH

–1.2 –1.0 –0.7 Volts
–2.0 –1.8 –1.7 Volts

SYMMETRY (Duty Cycle) ×8 Synthesis or 46 52 62 %

×16 Synthesis %

OUTPUT RISE/FALL TIMES 1.5

Rise Time (t

) 20%–80% 1.1 1.5 ns

R

Fall Time (tF) 80%–20% 1.1 1.5 ns

POWER SUPPLY VOLTAGE V

MIN

to V

MAX

4.5 5.5 Volts

POWER SUPPLY CURRENT 17 26 mA

OPERATING TEMPERATURE RANGE T

NOTES

1

Device design is guaranteed for operation over Capture Ranges and Tracking Ranges, however the device has wider capture and tracking ranges
(for both ×8 and ×16 synthesis).

Specifications subject to change without notice.

MIN

to T

MAX

–40 +85 °C

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V

Input Voltage (Pin 12 or Pin 13) . . . . . . . . . . . . . . V

+ 0.6 V

CC

“ON” TIME

t

ON

Maximum Junction Temperature. . . . . . . . . . . . . . . . . +165°C

Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C

ESD Rating (Human Body Model) . . . . . . . . . . . . . . . .1500 V

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics:
16-Pin Narrow Body SOIC Package: θJA = 110°C/W.

OUTPUT 50%

(PINS 4 & 5)

PERIOD

SYMMETRY = (100 ×

τ

t

/τ)

ON

Figure 1. Symmetry

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD809BR –40°C to +85°C 16-Pin Narrow Body SOIC R-16A
AD809BR-REEL7 –40°C to +85°C 750 Pieces, 7" Reel R-16A

–2–

REV. A

AD809

WARNING!

ESD SENSITIVE DEVICE

PIN DESCRIPTIONS

Pin
No. Mnemonic Description

1 PECLINN Differential 155 MHz Input
2 PECLIN Differential 155 MHz Input
3V

CC2

Digital VCC for PECL Outputs
4 CLKOUTN Differential 155 MHz Output
5 CLKOUT Differential 155 MHz Output
6V

CC1

Digital VCC for Internal Logic
7 CF1 Loop Damping Capacitor
8 CF2 Loop Damping Capacitor
9AV

EE

Analog V

EE

10 TTL/CMOSIN TTL/CMOS Reference Clock Input
11 AV

CC1

Analog VCC for PLL
12 CLKINN PECL Differential Reference Clock Input
13 CLKIN PECL Differential Reference Clock Input
14 AV

CC2

Analog VCC for Input Stage
15 MUX Input Signal Mux Control Input
16 V

EE

Digital V

EE

PIN CONFIGURATION

PECLINN

PECLIN

V

CC2

CLKOUTN

CLKOUT

V

CC1

CF1
CF2

1
2
3

AD809

4

TOP VIEW

5

(Not to Scale)

6
7
8

V

16

EE

MUX

15

AV

14

CLKIN

13
12

CLKINN
AV

11

TTL/CMOSIN

10

AV

9

CC2

CC1

EE

Table I.

MUX Input Input Selected

TTL “0” CLKIN/CLKINN
TTL “1” PECLIN/PECLINN

Table II. Applying a PECL/ECL or CMOS/TTL Reference
Input to the AD809

Input Reference AD809 Configuration

PECL/ECL Differential Apply the valid PECL–level reference

frequency to Pins 13 and 12.
AD809 frequency synthesizer ignores

the input at Pin 10.

TTL/CMOS Apply the reference frequency to
Single-Ended Pin 10.

Connect Pins 13 and 12 to AV

EE

(Pins 9 and 16). The AD809 senses
the common-mode signal at these pins
as less than valid PECL and selects the
TTL/CMOS input as active.

AD809 Phase Skew

The AD809 output is in phase with the input. The falling edge
at Pin 4, CLKOUTN, occurs 700 ps before the rising edge at
Pin 10, TTL/CMOSIN at 27°C. The phase skew remains rela­tively constant over temperature. Refer to Table III for phase
skew data.

Table III. Phase Skew vs. Temperature

Skew (CLKOUTN, Pin 4, Relative to
Temperature TTL/CMOSIN, Pin 10 Measured in
(8C) ps at Package Pins)

–35 –1000
–20 –950
0 –850
10 –750
30 –700
50 –600
70 –450
80 –450
90 –350
100 –250

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD809 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. A

–3–

AD809

POPULATION – Devices

RMS JITTER – Degrees

1200

1000

0

More1.8

800

600

400

200

0.2 0.4 0.60.81.01.2 1.4 1.6 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4

100
90

80

70

60
50

40

30

20

10

0

CUMULATIVE – %

AD809 FREQUENCY SYNTHESIZER

JITTER DISTRIBUTION MATRIX

75 DEVICES (3 LOTS)

[ECL, TTL] × [×8, ×16] × [RISE, FALL] × [+4.5V, +5.0V, +5.5V] × [–40°C, +25°C, +85°C]

THIS CHART DESCRIBES THE
AD809 OUTPUT JITTER
SPECIFICATION OVER MANY
CONDITIONS. THE DATA
REPRESENTED ARE TAKEN
WITH RESPECT TO THE RISING
AND FALLING EDGES, FOR
EACH FREQUENCY RANGE,
LOCKED TO EITHER TTL OR
ECL INPUT, OVER ALL
TEMPERATURE AND SUPPLY
CONDITIONS.

0.0

FREQUENCY

CUMULATIVE %

INPUT DUTY CYCLE – %

RMS JITTER – Degrees

1.9

1.3

1.0
0 10010 20 30 40 50 60 70 80 90

1.8

1.2

1.1

1.6

1.4

1.7

1.5

TA = +25°C
V

CC

= +5V

19.44MHz
9 72MHz

DEFINITION OF TERMS

Maximum, Minimum and Typical Specifications

Specifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. Typical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the distribu­tion. This procedure is intended to tolerate production varia­tions: if the mean shifts by 1.5 standard deviations, the remaining

4.5 standard deviations still provide a failure rate of only 3.4
parts per million. For all tested parameters, the test limits are
guardbanded to account for tester variation to thus guarantee
that no device is shipped outside of data sheet
specifications.

Capture and Tracking Range

This is the range of input data rates over which the AD809 will
remain in lock.

Jitter

This is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms.
Jitter on the input clock causes jitter on the synthesized clock.

Output Jitter

This is the jitter on the synthesized clock (OUTPUT, OUTPUT),
in degrees rms.

Jitter Transfer

The AD809 exhibits a low-pass filter response to jitter applied
to its input data.

Bandwidth

This describes the frequency at which the AD809 attenuates
sinusoidal input jitter by 3 dB.

Peaking

This describes the maximum jitter gain of the AD809 in dB.

Damping Factor, z

Damping factor, ζ describes the compensation of the second or­der PLL. A larger value of ζ corresponds to more damping and
less peaking in the jitter transfer function.

Duty Cycle Tolerance

The AD809 exhibits a duty cycle tolerance that is measured
by applying an input signal (nominal input frequency) with a
known duty cycle imbalance and measuring the ×8 or ×16
output frequency.

Symmetry-Recovered Clock Duty Cycle

Symmetry is calculated as (100× on time)/period, where on time
equals the time that the clock signal is greater than the midpoint
between its “0” level and its “1” level.

Typical Characteristic Curves

Figure 2. Jitter Histogram

Figure 3. Jitter vs. Input Duty Cycle

–4–

REV. A

USING THE AD809

2*I

TTL

80µA

OR

0µA

2*I

TTL

80µA

OR

0µA

500Ω

V

CC1

V

EE

V

CC2

DIFFERENTIAL
OUTPUT

V

EE

2.6mA

460Ω460Ω

500Ω

7.5kΩ7.5kΩ

I

TTL

V

CC1

V

EE

500Ω

40µA

40µA

Ground Planes

Use of one ground plane for connections to both analog and
digital grounds is recommended.

Power Supply Connections

Use of a 10 µF capacitor between V

and ground is recom-

CC

mended. Care should be taken to isolate the +5 V power trace
to V

(Pin 3). The V

CC2

pin is used inside the device to pro-

CC2

vide the CLKOUT/CLKOUTN signals.
Use of a trace connecting Pin 14 and Pin 6 (AV

CC2

and V

CC1

respectively) is recommended. Use of 0.1 µF capacitors between
IC power supply and ground is recommended. Power supply
decoupling should take place as close to the IC as possible.
Refer to the schematic, Figure 5, for advised connections.

Transmission Lines

Use of 50 Ω transmission lines are recommended for PECL
inputs.

Terminations

Termination resistors should be used for PECL input signals.
Metal, thick film, 1% tolerance resistors are recommended.
Termination resistors for the PECL input signals should be
placed as close as possible to the PECL input pins.

Connections from the power supply to load resistors for input
and output signals should be individual, not daisy chained. This
will avoid crosstalk on these signals.

Loop Damping Capacitor, C

D

A ceramic capacitor may be used for the loop damping capaci­tor. A 22 nF capacitor provides a damping factor of 10.

AD809

Synthesizer Input
TTL/CMOSIN

Synthesizer Input
CLKIN/CLKINN
PECL INPUT

PLL Differential
Output Stage–
CLKOUT/CLKOUTN

C2 0.1µF

J1

ECL INN

J2

ECL IN

CLKOUTN

CLKOUT

C3 0.1µF

C4 0.1µF

J3

C5 0.1µF

J4

R3

R4
100Ω

100Ω

C6

0.1µF

VECTOR PINS SPACED FOR THROUGH-HOLE
CAPACITOR ON VECTOR CUPS.
COMPONENT SHOWN FOR REFERENCE ONLY.

C1

0.1µF

R6

3.65kΩ

JUMPER

R7 100Ω
R8 100Ω

R11

154Ω

W2

R5
301Ω

49.9Ω

R1

R12
154Ω

R2

49.9Ω

TP1

CD

TP2

C11

10µF

+5V GND

50Ω STRIP LINE

EQUAL LENGTH

16-PIN SOIC

SOLDERED TO BOARD

1

PECLINN

2

PECLIN

3

V

CC2

C7

4

CLKOUTN
CLKOUT

5

V

6

CC1

C8

7

CF1

8

CF2

GUARD RING

TP4TP3

AD809

TTL/CMOSIN

V

MUX

AV

CC2

CLKIN

CLKINN

AV

CC1

AV

16

EE

15
14
13
12
11
10

9

EE

Figure 5. Evaluation Board Schematic

Figure 4. Simplified Schematics

J5

+5V

MUX

R16
301Ω

JUMPER
W3

R14

49.9Ω

R15

49.9Ω

R13

49.9Ω

C12

0.1µF

R17

3.65kΩ

C13 0.1µF

C14 0.1µF

C15 0.1µF

JUMPER

NOTE: C7–C10 ARE 0.1µF BYPASS CAPACITORS

EXT

W1

GND

C9

C10

RIGHT ANGLE SMA CONNECTOR
OUTER SHELL TO GND PLANE

ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT
TPx

TEST POINTS ARE VECTOR PINS

J6

CLKIN

J7

CLKINN

J8

CMOS/TTL IN

REV. A

–5–

AD809

Figure 6. Evaluation Board: Component Side

Figure 7. Evaluation Board: Solder Side

–6–

REV. A

AD809

Figure 8. Evaluation Board: INT2

REV. A

–7–

AD809

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead Small Outline IC Package

(R-16A)

16 9

PIN 1

1

0.0098 (0.25)

0.0040 (0.10)

0.0500
(1.27)

0.3937 (10.00)

0.3859 (9.80)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.1574 (4.00)

0.1497 (3.80)

8

0.0688 (1.75)

0.0532 (1.35)

0.2440 (6.20)

0.2284 (5.80)

0.0099 (0.25)

0.0075 (0.19)

8°
0°

0.0196 (0.50)

0.0099 (0.25)

0.0500 (1.27)

0.0160 (0.41)

C2045a–2–1/97

x 45°

–8–

PRINTED IN U.S.A.

REV. A