Page 1
–
V
Low Cost, High Speed
FEATURES
Low cost single (AD8091), dual (AD8092) amplifiers
Fully specified at +3 V, +5 V, and ±5 V supplies
Single-supply operation
Output swings to within 25 mV of either rail
High-speed and fast settling on 5 V
110 MHz, −3 dB bandwidth (G = +1)
145 V/µs slew rate
50 ns settling time to 0.1%
Good video specifications (G = +2)
Gain flatness of 0.1 dB to 20 MHz; R
0.03% differential gain error; R
0.03° differential phase error; R
Low distortion
−80 dBc total harmonic @ 1 MHz; R
Outstanding load drive capability
Drives 45 mA, 0.5 V from supply rails
Drives 50 pF capacitive load (G = +1)
Low power of 4.4 mA/Amplifier
APPLICATIONS
Coaxial cable drivers
Active filters
Video switchers
Professional cameras
CCD imaging systems
CDs/DVDs
GENERAL DESCRIPTION
L
= 1 kΩ
L
= 1 kΩ
L
= 100 Ω
L
= 150 Ω
Rail-to-Rail Amplifiers
AD8091/AD8092
CONNECTION DIAGRAMS
NC
1
AD8091
–IN
2
3
+IN
V
4
S
NC = NO CONNECT
Figure 1. SOIC-8 (R-8)
AD8091
1
OUT
2
–V
S
+IN
3
Figure 2. SOT23-5 (RT-5)
AD8092
1
OUT1
–IN1
2
3
+IN1
–V
4
S
NC = NO CONNECT
Figure 3. MSOP-8 and SOIC-8 (RM-8, R-8)
NC
8
+V
7
S
6
V
OUT
NC
5
02859-001
+V
5
S
–IN
4
02859-003
8
+V
S
OUT
7
6
–IN2
5
+IN2
02859-002
The AD8091 (single) and AD8092 (dual) are low cost, voltage
feedback, high speed amplifiers designed to operate on +3 V,
+5 V, or ±5 V supplies. They have true single-supply capability,
with an input voltage range extending 200 mV below the
The AD8091/AD8092 offer a low power supply current and can
operate on a single 3 V power supply. These features are ideally
suited for portable and battery-powered applications where size
and power are critical.
negative rail and within 1 V of the positive rail.
The wide bandwidth and fast slew rate make these amplifiers
Despite their low cost, the AD8091/AD8092 provide excellent
overall performance and versatility. The output voltage swing
extends to within 25 mV of each rail, providing the maximum
useful in many general-purpose, high speed applications where
dual power supplies of up to ±6 V and single supplies from +3
V to +12 V are needed.
output dynamic range with excellent overdrive recovery. This
makes the AD8091/AD8092 useful for video electronics, such
as cameras, video switchers, or any high speed portable
equipment. Low distortion and fast settling make them ideal for
This low cost performance is offered in an 8-lead SOIC
(AD8091/AD8092), along with a tiny SOT23-5 (AD8091) and a
MSOP (AD8092).
active filter applications.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
www.analog.com
Page 2
A8091/AD8092
TABLE OF CONTENTS
Specifications..................................................................................... 3
Input-to-Output Coupling ........................................................ 13
Absolute Maximum Ratings............................................................ 7
Maximum Power Dissipation ..................................................... 7
ESD Caution.................................................................................. 7
Typical Performance Characteristics ............................................. 9
Layout, Grounding, and Bypassing Considerations ..................13
Power Supply Bypassing ............................................................13
Grounding ................................................................................... 13
Input Capacitance....................................................................... 13
REVISION HISTORY
3/05—Rev. A to Rev. B
Changes to Format ............................................................. Universal
Changes to Features.......................................................................... 1
Updated Outline Dimensions....................................................... 17
Changes to Ordering Guide.......................................................... 18
5/02–Rev. 0 to Rev. A
Edits to Product Description ...........................................................1
Edit to TPC 6 .....................................................................................7
Edits to TPCs 21–24........................................................................10
Edits to Figure 3...............................................................................11
Driving Capacitive Loads.............................................................. 14
Overdrive Recovery ................................................................... 14
Active Filters ............................................................................... 14
Sync Stripper ............................................................................... 15
Single-Supply Composite Video Line Driver ......................... 15
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 18
2/02—Revision 0: Initial Version
Rev. B | Page 2 of 20
Page 3
AD8091/AD8092
SPECIFICATIONS
TA = 25°C, VS = 5 V, RL = 2 kΩ to 2.5 V, unless otherwise noted.
Table 1.
AD8091A/AD8092A
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = +1, VO = 0.2 V p-p 70 110 MHz
G = −1, +2, VO = 0.2 V p-p 50 MHz
Bandwidth for 0.1 dB Flatness
G = +2, V
= 150 Ω to 2.5 V, RF = 806 Ω
R
L
= 0.2 V p-p,
O
Slew Rate G = −1, VO = 2 V step 100 145 V/µs
Full Power Response G = +1, VO = 2 V p-p 35 MHz
Settling Time to 0.1% G = −1, VO = 2 V step 50 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion (See Figure 11) fC = 5 MHz, VO = 2 V p-p, G = +2 −67 dB
Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 10 kHz 850 fA/√Hz
Differential Gain Error (NTSC) G = +2, RL = 150 Ω to 2.5 V 0.09 %
R
= 1 kΩ to 2.5 V 0.03 %
L
Differential Phase Error (NTSC) G = +2, RL = 150 Ω to 2.5 V 0.19 Degrees
R
= 1 kΩ to 2.5 V 0.03 Degrees
L
Crosstalk f = 5 MHz, G = +2 −60 dB
DC PERFORMANCE
Input Offset Voltage 1.7 10 mV
T
MIN
to T
MAX
Offset Drift 10 µV/°C
Input Bias Current 1.4 2.5 µA
T
MIN
to T
MAX
Input Offset Current 0.1 0.75 µA
Open-Loop Gain RL = 2 kΩ to 2.5 V 86 98 dB
T
R
T
to T
MIN
MAX
= 150 Ω to 2.5 V 76 82 dB
L
to T
MIN
MAX
INPUT CHARACTERISTICS
Input Resistance 290 kΩ
Input Capacitance 1.4 pF
Input Common-Mode Voltage Range −0.2 to +4 V
Common-Mode Rejection Ratio VCM = 0 V to 3.5 V 72 88 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 10 kΩ to 2.5 V 0.015 to 4.985 V
R
R
Output Current V
T
= 2 kΩ to 2.5 V 0.100 to 4.900 0.025 to 4.975 V
L
= 150 Ω to 2.5 V 0.300 to 4.625 0.200 to 4.800 V
L
= 0.5 V to 4.5 V 45 mA
OUT
to T
MIN
MAX
Short-Circuit Current Sourcing 80 mA
Sinking 130 mA
Capacitive Load Drive G = +1 50 pF
POWER SUPPLY
Operating Range 3 12 V
Quiescent Current/Amplifier 4.4 5 mA
Power Supply Rejection Ratio ∆VS = ±1 V 70 80 dB
OPERATING TEMPERATURE RANGE −40 +85 °C
20 MHz
25 mV
3.25 µA
96 dB
78 dB
45 mA
Rev. B | Page 3 of 20
Page 4
A8091/AD8092
TA = 25°C, VS = +3 V, RL = 2 kΩ to +1.5 V, unless otherwise noted.
Table 2.
AD8091A/AD8092A
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = +1, VO = 0.2 V p-p 70 110 MHz
G = −1, +2, VO = 0.2 V p-p 50 MHz
Bandwidth for 0.1 dB Flatness
G = +2, V
R
= 150 Ω to 2.5 V, RF = 402 Ω
L
= 0.2 V p-p,
O
Slew Rate G = −1, VO = 2 V step 90 135 V/µs
Full Power Response G = +1, VO = 1 V p-p 65 MHz
Settling Time to 0.1% G = −1, VO = 2 V step 55 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion (see Figure 11)
= 5 MHz, VO = 2 V p-p, G = −1,
f
C
= 100 Ω to 1.5 V
R
L
Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 10 kHz 600 fA/√Hz
Differential Gain Error (NTSC) G = +2, VCM = 1 V
R
R
= 150 Ω to 1.5 V 0.11 %
L
= 1 kΩ to 1.5 V 0.09 %
L
Differential Phase Error (NTSC) G = +2, VCM = 1 V
R
R
= 150 Ω to 1.5 V 0.24 Degrees
L
= 1 kΩ to 1.5 V 0.10 Degrees
L
Crosstalk f = 5 MHz, G = +2 −60 dB
DC PERFORMANCE
Input Offset Voltage 1.6 10 mV
T
MIN
to T
MAX
Offset Drift 10 µV/°C
Input Bias Current 1.3 2.6 µA
T
MIN
to T
MAX
Input Offset Current 0.15 0.8 µA
Open-Loop Gain RL = 2 kΩ 80 96 dB
T
R
T
to T
MIN
MAX
= 150 Ω 74 82 dB
L
to T
MIN
MAX
INPUT CHARACTERISTICS
Input Resistance 290 kΩ
Input Capacitance 1.4 pF
Input Common-Mode Voltage Range −0.2 to +2.0 V
Common-Mode Rejection Ratio VCM = 0 V to 1.5 V 72 88 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 10 kΩ to 1.5 V 0.01 to 2.99 V
R
R
Output Current V
T
= 2 kΩ to 1.5 V 0.075 to 2.9 0.02 to 2.98 V
L
= 150 Ω to 1.5 V 0.20 to 2.75 0.125 to 2.875 V
L
= 0.5 V to 2.5 V 45 mA
OUT
to T
MIN
MAX
Short Circuit Current Sourcing 60 mA
Sinking 90 mA
Capacitive Load Drive G = +1 45 pF
17 MHz
−47 dB
25 mV
3.25 µA
94 dB
76 dB
45 mA
Rev. B | Page 4 of 20
Page 5
AD8091/AD8092
AD8091A/AD8092A
Parameter Conditions Min Typ Max Unit
POWER SUPPLY
Operating Range 3 12 V
Quiescent Current/Amplifier 4.2 4.8 mA
Power Supply Rejection Ratio ∆VS = +0.5 V 68 80 dB
OPERATING TEMPERATURE RANGE −40 +85 °C
Rev. B | Page 5 of 20
Page 6
A8091/AD8092
TA = 25°C, VS = ±5 V, RL = 2 kΩ to ground, unless otherwise noted.
Table 3.
AD8091A/AD8092A
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth G = +1, VO = 0.2 V p-p 70 110 MHz
G = −1, +2, VO = 0.2 V p-p 50 MHz
Bandwidth for 0.1 dB Flatness
G = +2, V
= 150 Ω, RF = 1.1 kΩ
R
L
= 0.2 V p-p,
O
Slew Rate G = −1, VO = 2 V step 105 170 V/µs
Full Power Response G = +1, VO = 2 V p-p 40 MHz
Settling Time to 0.1% G = −1, VO = 2 V step 50 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, G = +2 −71 dB
Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 10 kHz 900 fA/√Hz
Differential Gain Error (NTSC) G = +2, RL = 150 Ω 0.02 %
R
= 1 kΩ 0.02 %
L
Differential Phase Error (NTSC) G = +2, RL = 150 Ω 0.11 Degrees
R
= 1 kΩ 0.02 Degrees
L
Crosstalk f = 5 MHz, G = +2 −60 dB
DC PERFORMANCE
Input Offset Voltage 1.8 11 mV
T
MIN
to T
MAX
Offset Drift 10 µV/°C
Input Bias Current 1.4 2.6 µA
T
MIN
to T
MAX
Input Offset Current 0.1 0.75 µA
Open-Loop Gain RL = 2 kΩ 88 96 dB
T
R
T
to T
MIN
MAX
= 150 Ω 78 82 dB
L
to T
MIN
MAX
INPUT CHARACTERISTICS
Input Resistance 290 kΩ
Input Capacitance 1.4 pF
Input Common-Mode Voltage Range −5.2 to +4.0 V
Common-Mode Rejection Ratio VCM = −5 V to +3.5 V 72 88 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 10 kΩ −4.98 to +4.98 V
R
R
Output Current V
T
= 2 kΩ −4.85 to +4.85 −4.97 to +4.97 V
L
= 150 Ω −4.45 to +4.30 −4.60 to +4.60 V
L
= −4.5 V to +4.5 V 45 mA
OUT
to T
MIN
MAX
Short Circuit Current Sourcing 100 mA
Sinking 160 mA
Capacitive Load Drive G = +1 (AD8091/AD8092) 50 pF
POWER SUPPLY
Operating Range 3 12 V
Quiescent Current/Amplifier 4.8 5.5 mA
Power Supply Rejection Ratio ∆VS = ±1 V 68 80 dB
OPERATING TEMPERATURE RANGE −40 +85 °C
20 MHz
27 mV
3.5 µA
96 dB
80 dB
45 mA
Rev. B | Page 6 of 20
Page 7
AD8091/AD8092
(
)
×+=
(
)
−+=
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 12.6 V
The still-air thermal properties of the package (θ
temperature (T
(P
) can be used to determine the junction temperature of the die.
D
A
Power Dissipation See Figure 4
Common-Mode Input Voltage ±V
S
The junction temperature can be calculated as
Differential Input Voltage ±2.5 V
J
Output Short-Circuit Duration See Figure 4
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature Range (Soldering 10 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
quiescent current (I
midsupply, then the total drive power is V
which is dissipated in the package and some in the load
(V
OUT
the load power is the drive power dissipated in the package.
A
× I
). The difference between the total drive power and
OUT
device reliability.
D
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8091/AD8092
package is limited by the associated rise in junction temperature
) on the die. The plastic encapsulating the die locally reaches
(T
J
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8091/AD8092.
Exceeding a junction temperature of 175°C for an extended
period of time can result in changes in the silicon devices,
potentially causing failure.
RMS output voltages should be considered. If R
V
S−
V
S
If the rms signal levels are indeterminate, then consider the
worst case, when V
()
D
, as in single-supply operation, then the total drive power is
× I
.
OUT
()
D
), and the total power dissipated in the package
θPTT
D
JA
D
). Assuming the load (RL) is referenced to
S
VV
⎛
S
OUT
IVP
SS
IVP
SS
×+×=
⎜
⎝
OUT
+×=
R
2
= VS/4 for RL to midsupply
2
V
⎞
⎛
S
⎟
⎜
4
⎠
⎝
R
L
V
⎛
⎞
−
⎜
⎟
⎜
L
⎠
⎝
), ambient
JA
) is the sum of the
) times the
S
/2 × I
S
, some of
OUT
powerloadpowerdrivetotalpowerquiescentP
2
⎞
OUT
⎟
⎟
R
L
⎠
is referenced to
L
In single-supply operation with R
is V
= VS/2.
OUT
referenced to VS−, worst case
L
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 7 of 20
Page 8
A8091/AD8092
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θ
. Care must be taken to minimize parasitic capacitances
JA
at the input leads of high speed op amps as discussed in the
board layout section.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the SOIC-8
(125°C/W), SOT23-5 (180°C/W), and MSOP-8 (150°C/W) on a
JEDEC standard four-layer board.
2.0
TJ = 150°C
1.5
1.0
0.5
MAXIMUM POWER DISSIPATION (W)
0
–40–30–20–100 102030405060708090
SOIC-8
MSOP-8
SOT23-5
AMBIENT TEMPERATURE (°C)
02859-004
Figure 4. Maximum Power Dissipation vs.
Temperature for a Four-Layer Board
Rev. B | Page 8 of 20
Page 9
AD8091/AD8092
TYPICAL PERFORMANCE CHARACTERISTICS
3
2
1
0
–1
–2
–3
–4
NORMALIZED GAIN (dB)
VS = 5V
–5
GAIN AS SHOWN
AS SHOWN
R
F
= 2kΩ
R
–6
L
= 0.2V p-p
V
O
–7
0.1 1 10 100 500
G = +10
= 2kΩ
R
F
FREQUENCY (MHz)
Figure 5. Normalized Gain vs. Frequency; V
G = +2
R
= 2kΩ
F
G = +5
R
= 2kΩ
F
= +5 V
S
3
2
1
0
–1
–2
GAIN (dB)
–3
–4
–5
VS AS SHOWN
G = +1
–6
= 2kΩ
R
L
= 0.2V p-p
V
O
–7
0.1 1 10 100 500
VS = +3V
V
S
FREQUENCY (MHz)
= ±5V
V
= +5V
S
Figure 6. Gain vs. Frequency vs . Supply
3
2
1
0
–1
–2
GAIN (dB)
–3
–4
VS = 5V
–5
G = +1
= 2kΩ
R
L
–6
= 0.2V p-p
V
O
TEMPERATURE AS SHOWN
–7
0.1 1 10 100 500
FREQUENCY (MHz)
+85°C
–40°C
+25°C
Figure 7. Gain vs. Frequency vs . Temperature
G = +1
= 0Ω
R
F
02859-005
02859-006
02859-007
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
GAIN FLATNESS (dB)
VS = 5V
5.5
G = +2
RL = 150kΩ
5.4
= 806Ω
R
F
V
= 0.2V p-p
O
5.3
0.1 1 10 100
FREQUENCY (MHz)
Figure 8. 0.1 dB Gain Flatness vs. Frequency; G = +2
9
8
7
6
5
V
= ±5V
4
GAIN (dB)
3
2
VS AS SHOWN
1
G = +2
= 2kΩ
R
L
0
= 2kΩ
R
F
AS SHOWN
V
O
–1
0.1 1 10 100 500
S
= 4V p-p
V
O
FREQUENCY (MHz)
VS = +5V
= 2V p-p
V
O
Figure 9. Large S ignal Frequenc y Respons e; G = +2
70
60
50
40
30
20
10
OPEN-LOOP GAIN (dB)
0
–10
–20
0.1 1 10 100 500
PHASE
GAIN
50° PHASE
MARGIN
FREQUENCY (MHz)
Figure 10. Open-Loop Gain and Phase vs. Frequency
V
R
= 5V
S
= 2kΩ
L
0
–45
–90
–135
–180
02859-008
02859-009
PHASE (Degrees)
02859-010
Rev. B | Page 9 of 20
Page 10
A8091/AD8092
–20
VO = 2V p-p
–30
–40
V
= 5V, G = +1
S
–50
= 100Ω
R
L
–60
–70
–80
–90
TOTAL HARMONIC DISTORTION (dBc)
–100
–110
110
–30
–40
–50
–60
–70
–80
–90
–100
WORST HARMONIC (dBc)
–110
VS = 5V
–120
R
L
G = +2
–130
0 5.04.54.03.53.02.52.01.51.00.5
5.0
VS = 5V
4.5
G = –1
R
F
4.0
R
L
3.5
3.0
2.5
2.0
1.5
1.0
0.5
OUTPUT VOLTAGE SWING (THD ≤ 0.5%) (V p-p)
0
0.1 50101
Figure 13. Low Distortion Rail-to-Rail Output Swing
FUNDAMENTAL FREQUENCY (MHz)
Figure 11. Total Harmonic Distortion
= 2kΩ
Figure 12. Worst Harmonic vs. Output Voltage
= 2kΩ
= 2kΩ
= 5V, G = +2
V
S
R
= 2kΩ, RL = 100Ω
F
= 5V, G = +2
V
S
R
= 2kΩ, RL = 2kΩ
F
10MHz
5MHz
1MHz
OUTPUT VOLTAGE (V p-p)
FREQUENCY (MHz)
VS = 3V, G = –1
R
= 2kΩ, RL = 100Ω
F
V
= 5V, G = +1
S
= 2kΩ
R
L
0.10
NTSC SUBSCRIBER (3.58MHz)
0.08
0.06
0.04
0.02
0
–0.02
V
= 5, G = +2
DIFFERENTIAL
DIFFERENTIAL
02859-011
98765432
S
GAIN ERROR (%)
–0.04
R
= 2kΩ, RL AS SHOWN
F
–0.06
0 102030405060708090100
0.10
0.05
0
–0.05
–0.10
–0.15
= 5, G = +2
V
S
–0.20
= 2kΩ, RL AS SHOWN
R
F
–0.25
PHASE ERROR (Degrees)
0 102030405060708090100
MODULATING RAMP LEVEL (IRE)
R
RL = 1kΩ
RL = 150Ω
= 1kΩ
L
= 150Ω
R
L
02859-014
Figure 14. Differential Gain and Phase Errors
1000
VS = 5V
100
10
VOLTAGE NOISE (nA Hz)
02859-012
1
10 10M1M100k10k1k100
FREQUENCY (Hz)
02859-015
Figure 15. Input Voltage No ise vs. Frequency
100
VS = 5V
10
1
CURRENT NOISE (pA Hz)
02859-013
0.1
10 10M1M100k10k1k100
FREQUENCY (Hz)
02859-016
Figure 16. Input Current Noise vs. Frequency
Rev. B | Page 10 of 20
Page 11
AD8091/AD8092
–10
VS = 5V
= 2kΩ
R
F
–20
R
= 2kΩ
L
= 2V p-p
V
O
–30
–40
–50
–60
CROSSTALK (dB)
–70
–80
–90
–100
0.1 1 10 100 500
FREQUENCY (MHz)
Figure 17. AD8092 Crosstalk (Output-to-Output) vs. Frequency
0
VS = 5V
–10
–20
–30
–40
–50
CMRR (dB)
–60
–70
–80
–90
–100
0.03 0.1 1 10 100 500
FREQUENCY (MHz)
Figure 18. CMRR vs. Fre quency
100.000
VS = 5V
G = +1
31.000
10.000
3.100
1.000
0.310
OUTPUT RESISTANCE (Ω)
0.100
0.031
0.010
0.1 1 10 100 500
FREQUENCY (MHz)
Figure 19. Closed-Loop Output Resistance vs. Frequency
02859-017
02859-018
02859-019
20
VS = 5V
10
0
–10
–20
–30
PSRR (dB)
–40
–50
–60
–70
–80
0.01 0.1 1 10 100 500
–PSRR
+PSRR
FREQUENCY (MHz)
Figure 20. PSRR v s. Frequency
70
VS = 5V
G = –1
60
= 2kΩ
R
L
50
40
30
20
SETTLING TIME TO 0.1% (ns)
10
0
0.5 1.0 1.5 2.0
INPUT STEPS (V p-p)
Figure 21. Setting Time vs. Input Step
1.0
VS = 5V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
OUTPUT SATURATION VOLTAGE (V)
0.1
0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
VOH = –40°C
LOAD CURRENT (mA)
V
V
= +25°C
OH
= +85°C
OH
V
OL
= –40°C
V
V
OL
= +85°C
OL
= +25°C
Figure 22. Output Saturation Voltage vs. Load Current
02859-020
02859-021
02859-022
Rev. B | Page 11 of 20
Page 12
A8091/AD8092
2
3
100
90
80
RL = 2kΩ
= 150Ω
R
L
.5V
.5V
VS = 5V
G = +2
= 2kΩ
R
L
= 1V p-p
V
IN
OPEN-LOOP GAIN (dB)
70
= 5V
V
S
60
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
Figure 23. Open-Loop Gain vs. Output Voltage
V
= 0.1V p-p
IN
G = +1
= 2kΩ
R
L
= 3V
V
S
1.50V
20mV 20ns
Figure 24. 100 mV Step Response; G = +1
V
S
G = +1
R
L
2.60V
2.50V
2.40V
50mV 20ns
Figure 25. 200 mV Step Response; V
= +5 V, G = +1
S
= 5V
= 2kΩ
02859-023
02859-024
02859-025
1.5V
Figure 26. Large Signal Step Response; V
5V
2.5V
1V 2µs
Figure 27. Output Swing; G = −1, R
VS =±5V
4V
G = +1
= 2kΩ
R
L
3V
2V
1V
–1V
–2V
–3V
–4V
1V 20ns
Figure 28. Large Signal Step Response; V
= +5 V, G = +2
S
VS = 5V
G = –1
= 2kΩ
R
F
= 2kΩ
R
L
= 2 kΩ
L
= ±5 V, G = +1
S
02859-026
02859-027
02859-028
Rev. B | Page 12 of 20
Page 13
AD8091/AD8092
LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS
POWER SUPPLY BYPASSING
Power supply pins are actually inputs and care must be taken so
that a noise-free stable dc voltage is applied. The purpose of
bypass capacitors is to create low impedances from the supply
to ground at all frequencies, thereby shunting or filtering a
majority of the noise.
Decoupling schemes are designed to minimize the bypassing
impedance at all frequencies with a parallel combination of
capacitors. Chip capacitors of 0.01 µF or 0.001 µF (X7R or
NPO) are critical and should be as close as possible to the
amplifier package. Larger chip capacitors, such as the 0.1 µF
capacitor, can be shared among a few closely spaced active
components in the same signal path. A 10 µF tantalum
capacitor is less critical for high frequency bypassing and, in
most cases, only one per board is needed at the supply inputs.
GROUNDING
A ground plane layer is important in densely packed PC boards
to spread the current-minimizing parasitic inductances.
However, an understanding of where the current flows in a
circuit is critical to implementing effective high speed circuit
design. The length of the current path is directly proportional to
the magnitude of parasitic inductances and thus the high
frequency impedance of the path. High speed currents in an
inductive ground return create an unwanted voltage noise.
The length of the high frequency bypass capacitor leads are
most critical. A parasitic inductance in the bypass grounding
works against the low impedance created by the bypass
capacitor. Place the ground leads of the bypass capacitors at the
same physical location. Because load currents flow from the
supplies as well, the ground for the load impedance should be at
the same physical location as the bypass capacitor grounds. For
the larger value capacitors, which are intended to be effective at
lower frequencies, the current return path distance is less
critical.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can
be sensitive to parasitic capacitance between the inputs and
ground. A few pF of capacitance reduces the input impedance
at high frequencies, in turn increasing the amplifier’s gain,
causing peaking of the frequency response or even oscillations,
if severe enough. It is recommended that the external passive
components, which are connected to the input pins, be placed
as close as possible to the inputs to avoid parasitic capacitance.
The ground and power planes must be kept at a distance of at
least 0.05 mm from the input pins on all layers of the board.
INPUT-TO-OUTPUT COUPLING
The input and output signal traces should not be parallel to
minimize capacitive coupling between the inputs and output
and to avoid any positive feedback.
Rev. B | Page 13 of 20
Page 14
A8091/AD8092
DRIVING CAPACITIVE LOADS
A highly capacitive load reacts with the output of the amplifiers,
causing a loss in phase margin and subsequent peaking or even
oscillation, as shown in Figure 29 and Figure 30. There are two
methods to effectively minimize its effect.
10000
1000
VS = 5V
≤
30%
OVERSHOOT
RS = 3Ω
• Put a small value resistor in series with the output to isolate
the load capacitor from the amplifier’s output stage.
• Increase the phase margin with higher noise gains or by
adding a pole with a parallel resistor and capacitor from
−IN to the output.
8
6
4
2
0
–2
GAIN (dB)
–4
–6
VS = 5V
–8
G = +1
= 2kΩ
R
L
= 50pF
C
–10
L
= 200mV p-p
V
O
–12
0.1 500100110
FREQUENCY (MHz)
Figure 29. Closed-Loop Frequency Response: C
2.60V
2.55V
2.50V
2.45V
2.40V
VS = 5V
G = +1
R
= 2kΩ
L
C
= 50pF
L
= 50 pF
L
02859-029
R
= 0Ω
100
CAPACITIVE LOAD (pF)
10
1
165234
S
V
IN
100mV STEP
ACL (V/V)
R
50Ω
R
G
F
R
S
V
OUT
C
L
02859-031
Figure 31. Capacitive Load Drive vs. Closed-Loop Gain
OVERDRIVE RECOVERY
Overdrive of an amplifier occurs when the output and/or input
range is exceeded. The amplifier must recover from this
overdrive condition. The AD8091/AD8092 recover within 60 ns
from negative overdrive and within 45 ns from positive
overdrive, as shown in Figure 32.
=±5V
V
S
G = +5
= 2kΩ
R
INPUT 1V/DIV
OUTPUT 2V/DIV
V/DIV AS SHOWN 100ns
Figure 32. Overdrive Recovery
R
F
= 2kΩ
L
02859-032
Figure 30. 200 mV Step Response: C
100ns50mV
= 50 pF
L
02859-030
As the closed-loop gain is increased, the larger phase margin
allows for large capacitor loads with less peaking. Adding a low
value resistor in series with the load at lower gains has the same
effect. Figure 31 shows the effect of a series resistor for various
voltage gains. For large capacitive loads, the frequency response
of the amplifier is dominated by the series resistor and
capacitive load.
Rev. B | Page 14 of 20
ACTIVE FILTERS
Active filters at higher frequencies require wider bandwidth op
amps to work effectively. Excessive phase shift produced by
lower frequency op amps can significantly impact active filter
performance.
Figure 33 shows an example of a 2 MHz biquad bandwidth filter
that uses three op amps. Such circuits are sometimes used in
medical ultrasound systems to lower the noise bandwidth of the
analog signal before A/D conversion. Note that the unused
amplifiers’ inputs should be tied to ground.
Page 15
AD8091/AD8092
C1
50pF
R2
2kΩ
R1
3kΩ
V
IN
2
3
2kΩ
1
AD8092
R6
1kΩ
R4
2kΩ
R3
6
5
2kΩ
7
AD8092
C2
50pF
R5
2
6
V
3
AD8091
OUT
02859-033
Figure 33. 2 MHz Biquad Band-Pass Filter
The frequency response of the circuit is shown in Figure 34.
0
–10
–20
GAIN (dB)
–30
–40
10k 100k 1M 10M 100M
FREQUENCY (Hz)
02859-034
Figure 34. Frequency Response of 2 MHz Band-Pass Biquad Filter
SYNC STRIPPER
Synchronizing pulses are sometimes carried on video signals so
as not to require a separate channel to carry the synchronizing
information. However, for some functions, such as A/D
conversion, it is not desirable to have the sync pulses on the
video signal. These pulses reduce the dynamic range of the
video signal and do not provide any useful information for such
a function.
A sync stripper removes the synchronizing pulses from a video
signal while passing all the useful video information. Figure 35
shows a practical single-supply circuit that uses only a single
AD8091. It is capable of directly driving a reverse terminated
video line.
VIDEO WITHOUT SYNC
+
10µF0.1µF
R2
1kΩ
6
100Ω
GROUND
TO A/D
V
BLANK
GROUND
VIDEO WITH SYNC
V
IN
(OR 2
+0.8V
×
V
3
2
R1
1kΩ
BLANK
+0.4V
3V OR 5V
7
AD8091
4
)
Figure 35. Sync Stripper
The video signal plus sync is applied to the noninverting input
with the proper termination. The amplifier gain is set equal to 2
via the two 1 kΩ resistors in the feedback circuit. A bias voltage
must be applied to R1 for the input signal to have the sync
pulses stripped at the proper level.
The blanking level of the input video pulse is the desired place
to remove the sync information. The amplifier multiplies this
level by 2. This level must be at ground at the output in order
for the sync stripping action to take place. Because the gain of
the amplifier from the input of R1 to the output is −1, a voltage
equal to 2 × V
must be applied to make the blanking level
BLANK
come out at ground.
SINGLE-SUPPLY COMPOSITE VIDEO LINE DRIVER
Many composite video signals have their blanking level at
ground and have video information that is both positive and
negative. Such signals require dual-supply amplifiers to pass
them. However, by ac level-shifting, a single-supply amplifier
can be used to pass these signals. The following complications
may arise from such techniques.
Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capacity than their
(bounded) peak-to-peak amplitude after they are ac-coupled.
As a worst case, the dynamic signal swing approaches twice the
peak-to-peak value. One of two conditions that define the
maximum dynamic swing requirements is a signal that is
mostly low but goes high with a duty cycle that is a small
fraction of a percent. The opposite condition defines the second
condition.
02859-035
The worst case of composite video is not quite this demanding.
One bounding condition is a signal that is mostly black for an
entire frame but has a white (full amplitude) minimum width
spike at least once in a frame.
Rev. B | Page 15 of 20
Page 16
A8091/AD8092
C
The other extreme is a full white video signal. The blanking
intervals and sync tips of such a signal have negative-going
excursions in compliance with the composite video
specifications. The combination of horizontal and vertical
blanking intervals limit such a signal to being at the highest
(white) level for a maximum of about 75% of the time.
As a result of the duty cycles between the two extremes, a 1 V pp composite video signal that is multiplied by a gain of 2
requires about 3.2 V p-p of dynamic voltage swing at the output
for an op amp to pass a composite video signal of arbitrary
varying duty cycle without distortion.
Some circuits use a sync tip clamp to hold the sync tips at a
relatively constant level to lower the amount of dynamic signal
swing required. However, these circuits can have artifacts like
sync tip compression unless they are driven by a source with a
very low output impedance. The AD8091/AD8092 have
adequate signal swing when running on a single 5 V supply to
handle an ac-coupled composite video signal.
The input to the circuit in Figure 36 is a standard composite
(1 V p-p) video signal that has the blanking level at ground. The
input network level shifts the video signal by means of ac
coupling. The noninverting input of the op amp is biased to half
of the supply voltage.
5V
4.99kΩ
+
10µF
3
AD8091
2
220µF
7
4
+
10kΩ
R
G
1kΩ
+
0.1µF10µF
1000µF
+
6
0.1µF
R
F
1kΩ
R
75Ω
BT
V
OUT
R
L
75Ω
OMPOSITE
VIDEO IN
75Ω
4.99kΩ
47µF
R
T
Figure 36. Single-Supply Composite Video Line Driver
The feedback circuit provides unity gain for the dc biasing of
the input and provides a gain of 2 for any signals that are in the
video bandwidth. The output is ac-coupled and terminated to
drive the line.
The capacitor values were selected for providing minimum tilt
or field time distortion of the video signal. These values would
be required for video that is considered to be studio or
broadcast quality. However, if a lower consumer grade of video,
sometimes referred to as consumer video, is all that is desired,
the values and the cost of the capacitors can be reduced by as
much as a factor of 5 with minimum visible degradation in the
picture.
02859-036
Rev. B | Page 16 of 20
Page 17
AD8091/AD8092
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
85
1.27 (0.0500)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
BSC
6.20 (0.2440)
5.80 (0.2284)
41
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
8°
1.27 (0.0500)
0°
0.40 (0.0157)
Figure 37. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
× 45°
0.15
0.00
COPLANARITY
3.00
BSC
8
5
4
SEATING
PLANE
4.90
BSC
1.10 MAX
0.23
0.08
8°
0°
3.00
BSC
1
PIN 1
0.65 BSC
0.38
0.22
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 38. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
0.80
0.60
0.40
2.90 BSC
4 5
0.50
0.30
3
2.80 BSC
0.95 BSC
1.45 MAX
SEATING
PLANE
0.22
0.08
1.60 BSC
1.30
1.15
0.90
0.15MAX
1
2
PIN 1
1.90
BSC
COMPLIANT TO JEDEC STANDARDS MO-178AA
Figure 39. 5-Lead Small Outline Transistor Package [SOT-23]
(RT-5)
Dimensions shown in millimeters
10°
5°
0°
0.60
0.45
0.30
Rev. B | Page 17 of 20
Page 18
A8091/AD8092
ORDERING GUIDE
Model Temperature Range Package Description Package Outline Branding Information
AD8091AR −40°C to +85°C 8-Lead SOIC R-8
AD8091AR-REEL −40°C to +85°C 8-Lead SOIC, 13” Tape and Reel R-8
AD8091AR-REEL7 −40°C to +85°C 8-Lead SOIC, 7” Tape and Reel R-8
AD8091ARZ
AD8091ARZ-REEL1 −40°C to +85°C 8-Lead SOIC, 13” Tape and Reel R-8
AD8091ARZ-REEL71 −40°C to +85°C 8-Lead SOIC, 7” Tape and Reel R-8
AD8091ART-R2 −40°C to +85°C 5-Lead SOT-23 RT-5 HVA
AD8091ART-REEL −40°C to +85°C 5-Lead SOT-23, 13” Tape and Reel RT-5 HVA
AD8091ART-REEL7 −40°C to +85°C 5-Lead SOT-23, 7” Tape and Reel RT-5 HVA
AD8091ARTZ-R21 −40°C to +85°C 5-Lead SOT-23 RT-5 HVA#
AD8091ARTZ-R71 −40°C to +85°C 5-Lead SOT-23, 7” Tape and Reel RT-5 HVA#
AD8091ARTZ-RL1 −40°C to +85°C 5-Lead SOT-23, 13” Tape and Reel RT-5 HVA#
AD8092AR −40°C to +85°C 8-Lead SOIC R-8
AD8092AR-REEL −40°C to +85°C 8-Lead SOIC, 13” Tape and Reel R-8
AD8092AR-REEL7 −40°C to +85°C 8-Lead SOIC, 7” Tape and Reel R-8
AD8092ARZ1 −40°C to +85°C 8-Lead SOIC R-8
AD8092ARZ-REEL1 −40°C to +85°C 8-Lead SOIC, 13” Tape and Reel R-8
AD8092ARZ-REEL71 −40°C to +85°C 8-Lead SOIC, 7” Tape and Reel R-8
AD8092ARM −40°C to +85°C 8-Lead MSOP RM-8 HWA
AD8092ARM-REEL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HWA
AD8092ARM-REEL7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HWA
AD8092ARMZ1 −40°C to +85°C 8-Lead MSOP RM-8 HWA#
AD8092ARMZ-REEL1 −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HWA#
AD8092ARMZ-REEL71 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HWA#
1
Z = Pb-free part. # denotes lead-free, may be top or bottom marked.
1
−40°C to +85°C 8-Lead SOIC R-8
Rev. B | Page 18 of 20
Page 19
AD8091/AD8092
NOTES
Rev. B | Page 19 of 20
Page 20
A8091/AD8092
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02859–0–3/05(B)
Rev. B | Page 20 of 20
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