Datasheet AD8079BR-REEL7, AD8079BR-REEL, AD8079BR, AD8079AR-REEL7, AD8079AR-REEL Datasheet (Analog Devices)

a

1

2

3

4

5

6

7

8

AD8079

+IN1

GND

GND

+IN2

OUT1

+V

S

–V

S

OUT2

Dual 260 MHz

Gain = +2.0 & +2.2 Buffer

AD8079

FEATURES
Factory Set Gain

AD8079A: Gain = +2.0 (Also +1.0 & –1.0)
AD8079B: Gain = +2.2 (Also +1 & –1.2)
Gain of 2.2 Compensates for System Gain Loss
Minimizes External Components
Tight Control of Gain and Gain Matching (0.1%)

Optimum Dual Pinout

Simplifies PCB Layout
Low Crosstalk of –70 dB @ 5 MHz

Excellent Video Specifications (R

= 150 V)

L

Gain Flatness 0.1 dB to 50 MHz

0.01% Differential Gain Error

0.028 Differential Phase Error
Low Power of 50 mW/Amplifier (5 mA)
High Speed and Fast Settling

260 MHz, –3 dB Bandwidth
750 V/ms Slew Rate (2 V Step), 800 V/ms (4 V Step)
40 ns Settling Time to 0.1% (2 V Step)

Low Distortion of –65 dBc THD, f

= 5 MHz

C

High Output Drive of Over 70 mA

Drives Up to 8 Back-Terminated 75 V Loads (4 Loads/

Side) While Maintaining Good Differential Gain/

Phase Performance (0.01%/0.178)
High ESD Tolerance (5 kV)
Available in Small 8-Pin SOIC

APPLICATIONS
Differential A-to-D Driver
Video Line Driver
Differential Line Driver
Professional Cameras
Video Switchers
Special Effects
RF Receivers

PRODUCT DESCRIPTION

The AD8079 is a dual, low power, high speed buffer designed
to operate on ±5 V supplies. The AD8079’s pinout offers excel­lent input and output isolation compared to the traditional dual
amplifier pin configuration. With two ac ground pins separating
both the inputs and outputs, the AD8079 achieves very low
crosstalk of less than –70 dB at 5 MHz.

Additionally, the AD8079 contains gain setting resistors factory
set at G = +2.0 (A grade) or Gain = +2.2 (B grade) allowing
circuit configurations with minimal external components. The
B grade gain of +2.2 compensates for gain loss through a system
by providing a single-point trim. Using active laser trimming of
these resistors, the AD8079 guarantees tight control of gain and
channel-channel gain matching. With its performance and con­figuration, the AD8079 is well suited for driving differential

FUNCTIONAL BLOCK DIAGRAM

8-Pin Plastic SOIC

cables and transformers. Its low distortion and fast settling are
ideal for buffering high speed dual or differential A-to-D con­verters.

The AD8079 features a unique transimpedance linearization
circuitry. This allows it to drive video loads with excellent differ­ential gain and phase performance of 0.01% and 0.02° on only
50 mW of power per amplifier. It features gain flatness of 0.1 dB
to 50 MHz. This makes the AD8079 ideal for professional video
electronics such as cameras and video switchers.

The AD8079 offers low power of 5 mA/amplifier (V

= ±5 V)

S

and can run on a single +12 V power supply while delivering
over 70 mA of load current. All of this is offered in a small 8-pin
SOIC package. These features make this amplifier ideal for por­table and battery powered applications where size and power are
critical.

The outstanding bandwidth of 260 MHz along with 800 V/µs of
slew rate make the AD8079 useful in many general purpose high
speed applications where dual power supplies of ± 3 V to ±6 V
are required.

The AD8079 is available in the industrial temperature range of
–40°C to +85°C.

1

0

RL = 100Ω
VIN = 50mV rms

0.1

0
–0.1

–0.2

–0.3

–0.4

NORMALIZED FLATNESS – dB

–0.5

50Ω

1M

50Ω

SIDE 1

FREQUENCY – Hz

SIDE 1

SIDE 2

SIDE 2

–1

–2
–3

–4
–5

–6

–7

–8

NORMALIZED FREQUENCY RESPONSE – dB

–9

1G10M 100M

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Figure 1. Frequency Response and Flatness

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1996

AD8079–SPECIFICA TIONS

(@ TA = +258C, VS = 65 V, RL = 100 V, unless otherwise noted)

AD8079A/AD8079B

Parameter Conditions Min Typ Max Units

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth V
Bandwidth for 0.1 dB Flatness V
Large Signal Bandwidth V
Slew Rate V

Settling Time to 0.1% V

= 50 mV rms 260 MHz

IN

= 50 mV rms 50 MHz

IN

= 1 V rms 100 MHz

IN

= 2 V Step 750 V/µs

O

= 4 V Step 800 V/µs

V

O

= 2 V Step 40 ns

O

Rise & Fall Time VO = 2 V Step 2.5 ns

NOISE/HARMONIC PERFORMANCE

Total Harmonic Distortion f

= 5 MHz, VO = 2 V p-p –65 dBc

C

Crosstalk, Output to Output f = 5 MHz –70 dB
Input Voltage Noise f = 10 kHz 2.0 nV/√
Input Current Noise f = 10 kHz, +In 2.0 pA/√
Differential Gain Error NTSC, R

NTSC, R

Differential Phase Error NTSC, R

= 150 Ω 0.01 %

L

= 75 Ω 0.01 %

L

= 150 Ω 0.02 Degree

L

RL = 75 Ω 0.07 Degree

DC PERFORMANCE

Offset Voltage, RTO 10 15 mV

T

MIN–TMAX

10 20 mV
Offset Drift, RTO 20 µV/°C
+Input Bias Current 3.0 6.0 ±µA

T

MIN–TMAX

10 ±µA

Gain No Load 1.998/2.198 2.0/2.2 2.002/2.202 V/V

= 150 Ω 1.995/2.195 2.0/2.2 2.005/2.205 V/V

R

L

Gain Matching Channel-to-Channel, No Load 0.1 %

Channel-to-Channel, RL = 150 Ω 0.5 %

Hz
Hz

INPUT CHARACTERISTICS

+Input Resistance +Input 10 MΩ
+Input Capacitance +Input 1.5 pF

OUTPUT CHARACTERISTICS

Output Voltage Swing R
Output Current

Short Circuit Current

1

1

= 150 Ω 2.7 3.1 ±V

L

= 75 Ω 2.8 ±V

R

L

70 mA

85 110 mA

POWER SUPPLY

Operating Range ±3.0 ±6.0 V
Quiescent Current/Both Amplifiers T
Power Supply Rejection Ratio, RTO +V

+Input Current T

NOTES

1

Output current is limited by the maximum power dissipation in the package. See the power derating curves.

Specifications subject to change without notice.

MIN–TMAX

= +4 V to +6 V, –VS = –5 V 49 69 dB

S

= –4 V to –6 V, +VS = +5 V 40 50 dB

–V

S

MIN–TMAX

10.0 11.5 mA

0.1 0.5 µA/V

–2–

REV. A

AD8079

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6V

Internal Power Dissipation

2

1

Small Outline Package (R) . . . . . . . . . . . . . . . . . . 0.9 Watts

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V

S

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves

Storage Temperature Range . . . . . . . . . . . . .–65°C to +125°C

Operating Temperature Range (A Grade) . . . –40°C to +85°C

Lead Temperature Range (Soldering10 sec) . . . . . . . . +300°C

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

Specification is for device in free air:
8-Pin SOIC Package: θJA = 160°C/Watt

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8079 is limited by the associated rise in junction tempera­ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition tem­perature of the plastic, approximately +150°C. Exceeding this
limit temporarily may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of +175°C for an extended
period can result in device failure.

While the AD8079 is internally short circuit protected, this
may not be sufficient to guarantee that the maximum junction
temperature (+150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves.

2.0

1.5

1.0

8-PIN SOIC PACKAGE

0.5

TJ = +150°C

9

MAXIMUM POWER DISSIPATION – Watts

0

–50 90–40 –30 –20 –10 0 10 20 30 40 50 60 70

AMBIENT TEMPERATURE – °C

Figure 2. Plot of Maximum Power Dissipation vs.
Temperature

ORDERING GUIDE

Temperature Package Package

Model Gain Range Description Option

AD8079AR G = +2.0 –40°C to +85°C 8-Pin Plastic SOIC SO-8
AD8079AR-REEL G = +2.0 –40°C to +85°C REEL SOIC SO-8
AD8079AR-REEL7 G = +2.0 –40°C to +85°C REEL 7 SOIC SO-8
AD8079BR G = +2.2 –40°C to +85°C 8-Pin Plastic SOIC SO-8
AD8079BR-REEL G = +2.2 –40°C to +85°C REEL SOIC SO-8
AD8079BR-REEL7 G = +2.2 –40°C to +85°C REEL 7 SOIC SO-8

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8079 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

80

REV. A

–3–

AD8079

V

IN

PULSE

GENERATOR

TR/TF = 250ps

50Ω

2

AD8079

1

+5V

–5V

1

0

10µF

0.1µF

7

8

0.1µF

6

10µF

R

L

= 100Ω

RL = 100Ω
VIN = 50mV rms

0.1

0
–0.1

–0.2

–0.3

–0.4

NORMALIZED FLATNESS – dB

–0.5

50Ω

1M

50Ω

SIDE 1

FREQUENCY – Hz

SIDE 1

SIDE 2

SIDE 2

–1

–2
–3

–4
–5

–6

–7

–8

NORMALIZED FREQUENCY RESPONSE – dB

–9

1G10M 100M

Figure 3. Test Circuit

100mV STEP

SIDE 1

SIDE 2

20mV

5ns

Figure 4. 100 mV Step Response

1V STEP

SIDE 1

Figure 6. Frequency Response and Flatness

–50

RL = 100Ω

–60

–70

–80

–90

DISTORTION – dBc

–100

–110

10k 100M100k 1M 10M

2ND HARMONIC

3RD HARMONIC

FREQUENCY – Hz

Figure 7. Distortion vs. Frequency, RL = 100

–60

RL = 1kΩ

= 2Vp-p

V

OUT

–70

Ω

SIDE 2

200mV

5ns

Figure 5. 1 V Step Response

–4–

–80

2ND HARMONIC

–90

–100

DISTORTION – dBc

–110

–120

100k 100M10M1M10k

FREQUENCY – Hz

3RD HARMONIC

Figure 8. Distortion vs. Frequency, RL = 1 k

Ω

REV. A

AD8079

–10

VIN = 2V p-p

–20

= 100Ω

R

L

= ±5V

V

S

–30

–40

–50

–60

–70

CROSSTALK – dB

–80

–90

–100
–110

100k 200M0.1M 1M 10M 100M

FREQUENCY – Hz

Figure 9. Crosstalk (Output-to-Output) vs. Frequency

0.02
NTSC

0.01

0.00

–0.01

DIFF GAIN – %

–0.02

123 4567891011

0.08

0.06

0.04

0.02

0.00

DIFF PHASE – Degrees

2 BACK TERMINATED

NTSC

12

LOADS (75Ω)

34567891011

2 BACK TERMINATED

LOADS (75Ω)

1 BACK TERMINATED

LOAD (150Ω)

IRE

1 BACK TERMINATED

LOAD (150Ω)

IRE

3
0

–3

–6

–9

–12

–15

INPUT LEVEL – dBV

–18

–21

–24
–27

1M 500M10M 100M

VIN = 1.0V rms

VIN = 0.5V rms

VIN = 0.25V rms

VIN = 125mV rms

VIN = 62.5mV rms

FREQUENCY – Hz

VS = ±5V
RL = 100Ω

Figure 12. Large Signal Frequency Response

5
4

3

2

1

0

0.1%/DIV
–1

–2

–3

–4
–5

0 12020 40 60 80 100

TIME – ns

2V STEP
RC = 100Ω

RL = 150Ω

3
0

–3

–6

–9

–12

–15

–18

–21

NORMALIZED OUTPUT LEVEL – dBV

–24
–27

9

Figure 10. Differential Gain and Differential Phase

(per Amplifier)

RL = 100Ω

SIDE 1

SIDE 2

5ns

NOTES: SIDE 1: VIN = 0V; 8mV/div RTO

SIDE 2: 1V STEP RTO; 400mV/div

Figure 11. Pulse Crosstalk, Worst Case, 1 V Step

Figure 13. Short-Term Settling Time

2V STEP
R

= 100Ω

L

ERROR,

(0.05%/DIV)

OUTPUT

INPUT

400mV

2µs

Figure 14. Long-Term Settling Time

REV. A

–5–

AD8079

3.4

3.3

3.2

3.1

3.0

2.9

2.8

OUTPUT SWING – Volts

2.7

2.6

2.5

+V

OUT

–35–55

|–V

JUNCTION TEMPERATURE – °C

OUT

RL = 150Ω

VS = ±5V

|

Figure 15. Output Swing vs. Temperature

7

6

5

4

3

2

1

INPUT BIAS CURRENT – µA

0

–1

–55 125–35 –15 5 25 45 65 85 105

JUNCTION TEMPERATURE – °C

+IN

11.5

11.0

10.5
VS = ±5V

10.0

9.5

TOTAL SUPPLY CURRENT – mA

105856545255–15

125

9.0
–55

–35

JUNCTION TEMPERATURE – °C

125

105856545255–15

Figure 18. Total Supply Current vs. Temperature

120

115
110

105

100

95
90

85

80

SHORT CIRCUIT CURRENT – mA

75

70

–35–55

|SINK ISC|

JUNCTION TEMPERATURE – °C

SOURCE I

SC

125

105856545255–15

Figure 16. Input Bias Current vs. Temperature

8

DEVICE #1

6

4

2

0

–2

INPUT OFFSET VOLTAGE RTO – mV

–4

–6

JUNCTION TEMPERATURE – °C

DEVICE #2

DEVICE #3

125–35–55 105856545255–15

Figure 17. Input Offset Voltage vs. Temperature

Figure 19. Short Circuit Current vs. Temperature

100

10

NONINVERTING CURRENT VS = ±5V

NOISE VOLTAGE, RTI – nV/ Hz

1

10 100k100

VOLTAGE NOISE VS = ±5V

FREQUENCY – Hz

1k 10k

100

10

1

Figure 20. Noise vs. Frequency

NOISE CURRENT – pA/ Hz

–6–

REV. A

100

VS = ±5.0V

10

POWER = 0dBm
(223.6mV rms)

1

RESISTANCE – Ω

0.1

0.01

10k 1G100k 1M 10M 100M

RbT = 50Ω

RbT = 0Ω

FREQUENCY – Hz

Figure 21. Output Resistance vs. Frequency

–44.0

–46.5
–49.0

–51.5

–54.0
–56.5

PSRR – dB

–59.0

–61.5

–64.0
–66.5
–69.0

–35–55

–PSRR

2V SPAN
CURVES ARE FOR WORST

CASE CONDITION WHERE
ONE SUPPLY IS VARIED
WHILE THE OTHER IS
HELD CONSTANT.

+PSRR

JUNCTION TEMPERATURE – °C

105856545255–15

Figure 22. PSRR vs. Temperature

0

VIN = 200mV

–4

–14

–24

–34

–44

PSRR – dB

–54

–64

–74

–84

30k 500M100k 1M 10M 100M

–PSRR

+PSRR

FREQUENCY – Hz

Figure 23. PSRR vs. Frequency

125

AD8079

THEORY OF OPERATION

The AD8079, a dual current feedback amplifier, is internally
configured for a gain of either +2 (AD8079A) or +2.2
(AD8079B). The internal gain-setting resistors effectively elimi­nate any parasitic capacitance associated with the inverting in­put pin, accounting for the AD8079’s excellent gain flatness
response. The carefully chosen pinout greatly reduces the cross­talk between each amplifier. Up to four back-terminated 75 Ω
video loads can be driven by each amplifier, with a typical dif­ferential gain and phase performance of 0.01%/0.17°, respec­tively. The AD8079B, with a gain of +2.2, can be employed as a
single gain-trimming element in a video signal chain. Finally,
the AD8079A/B used in conjunction with our AD8116 cross­point matrix, provides a complete turn-key solution to video
distribution.

Printed Circuit Board Layout Considerations

As to be expected for a wideband amplifier, PC board parasitics
can affect the overall closed-loop performance. If a ground
plane is to be used on the same side of the board as the signal
traces, a space (5 mm min) should be left around the signal lines
to minimize coupling. Line lengths on the order of less than
5 mm are recommended. If long runs of coaxial cable are being
driven, dispersion and loss must be considered.

Power Supply Bypassing

Adequate power supply bypassing can be critical when optimiz­ing the performance of a high frequency circuit. Inductance in
the power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors
(typically greater than 1 µF) will be required to provide the best
settling time and lowest distortion. A parallel combination of

4.7 µF and 0.1 µF is recommended. Some brands of electrolytic
capacitors will require a small series damping resistor ≈ 4.7 Ω
for optimum results.

DC Errors and Noise

There are three major noise and offset terms to consider in a
current feedback amplifier. For offset errors refer to the equa­tion below. For noise error the terms are root-sum-squared to
give a net output error. In the circuit below (Figure 24) they are
input offset (V
noise gain of the circuit (1 + R
(I

× RN) also multiplied by the noise gain, and the inverting

BN

input current, which when divided between R
sequently multiplied by the noise gain always appears at the out­put as I

BN

2 nV/√

Hz. At low gains though the inverting input current noise

times R

F

vice matching contribute to better offset and drift specifications
for the AD8079 compared to many other current feedback am­plifiers. The typical performance curves in conjunction with the
equations below can be used to predict the performance of the
AD8079 in any application.

V

OUT=VIO

where:

R

= RI = 750 Ω for AD8079A

F

R

= 750 Ω, RI = 625 Ω for AD8079B

F

) which appears at the output multiplied by the

IO

), noninverting input current

F/RI

and RI and sub-

F

× RF. The input voltage noise of the AD8079 is a low

is the dominant noise source. Careful layout and de-




× 1+






R

F



±IBN× RN× 1+



R



I





R

F





R

I

±IBI× R







F

9

REV. A

–7–

AD8079

R

F

(INTERNAL)

R

I

I

(INTERNAL)

R

BI

R

I

BN

N

SERIES

V

OUT

C

L

Figure 24. Output Offset Voltage

Driving Capacitive Loads

The AD8079 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, best
frequency response is obtained by the addition of a small series
output resistance (R
optimum value for R

). The graph in Figure 25 shows the

SERIES

vs. capacitive load. It is worth noting

SERIES

that the frequency response of the circuit when driving large
capacitive loads will be dominated by the passive roll-off of
R

and CL.

SERIES

40

30

– Ω

20

SERIES

R

10

0

0255

Figure 25. Recommended R

10 15 20

CL – pF

SERIES

vs. Capacitive Load

Operation as a Video Line Driver

The AD8079 has been designed to offer outstanding perfor­mance as a video line driver. The important specifications of
differential gain (0.01%) and differential phase (0.02°) meet the
most exacting HDTV demands for driving one video load with
each amplifier. The AD8079 also drives four back terminated
loads (two each), as shown in Figure 26, with equally impressive
performance (0.01%, 0.07°). Another important consideration is
isolation between loads in a multiple load application. The
AD8079 has more than 40 dB of isolation at 5 MHz when driv­ing two 75 Ω back terminated loads.

75Ω

CABLE

75Ω

+V

S

4.7µF

0.1µF

7

2

1/2

AD8079

1

6

75Ω

CABLE

V

IN

75Ω

–V

4

1/2

AD8079

3

8

0.1µF

4.7µF

S

5

75Ω

75Ω

75Ω

75Ω

CABLE

75Ω

CABLE

75Ω

CABLE

75Ω

75Ω

75Ω

75Ω

V

#1

OUT

V

#2

OUT

V

#3

OUT

V

#4

OUT

Figure 26. Video Line Driver

Single-Ended to Differential Driver Using an AD8079

The two halves of an AD8079 can be configured to create a
single-ended to differential high speed driver with a –3dB band­width in excess of 110 MHz as shown in Figure 27. Although
the individual op amps are each current feedback with internal
feedback resistors, the overall architecture yields a circuit with
attributes normally associated with voltage feedback amplifiers,
while offering the speed advantages inherent in current feedback
amplifiers. In addition, the gain of the circuit can be changed by
varying a single resistor, R

, which is often not possible in a dual

F

op amp differential driver.

CC = 1.5pF

R

750Ω

1/2

1/2

F

OP AMP #1

OP AMP #2

50Ω

50Ω

OUTPUT #1

OUTPUT #2

R

G

V

IN

750Ω

AD8079

AD8079

–8–

Figure 27. Differential Line Driver

REV. A

The current feedback nature of the op amps, in addition to

FREQUENCY – Hz

0.1M 1G1M 10M 100M

CC = 1.3pF
V

IN

= 10dBm

6
4

2

0
–2

–4

–6

–8

–10

–12
–14

OUTPUT – dB

OUT+

OUT–

enabling the wide bandwidth, provides an output drive of more
than 3 V p-p into a 20 Ω load for each output at 20MHz. On
the other hand, the voltage feedback nature provides symmetri­cal high impedance inputs and allows the use of reactive compo­nents in the feedback network.

The circuit consists of the two op amps each configured as a
unity gain follower by the 750 Ω feedback resistors between
each op amp’s output and inverting input. The output of each
op amp has a 750 Ω resistor to the inverting input of the other
op amp. Thus, each output drives the other op amp through a
unity gain inverter configuration. By connecting the two ampli­fiers as cross-coupled inverters, their outputs are free to be equal
and opposite, assuring zero-output common-mode voltage.

With this circuit configuration, the common-mode signal of the
outputs is reduced. If one output moves slightly higher, the
negative input to the other op amp drives its output to go
slightly lower and thus preserves the symmetry of the comple­mentary outputs which reduces the common-mode signal.

The resulting architecture offers several advantages. First, the
gain can be changed by changing a single resistor. Changing
either R

or RG will change the gain as in an inverting op amp

F

circuit. For most types of differential circuits, more than one
resistor must be changed to change gain and still maintain good
CMR.

Reactive elements can be used in the feedback network. This is
in contrast to current feedback amplifiers that restrict the use of
reactive elements in the feedback. The circuit described requires
about 1.3 pF of capacitance in shunt across R

in order to opti-

F

mize peaking and realize a –3 dB bandwidth of more than
110 MHz.

The peaking exhibited by the circuit is very sensitive to the
value of this capacitor. Parasitics in the board layout on the or­der of tenths of picofarads will influence the frequency response
and the value required for the feedback capacitor, so a good lay­out is essential.

The shunt capacitor type selection is also critical. Good micro­wave type chip capacitors with high Q were found to yield best
performance.

AD8079

Figure 28. Differential Driver Frequency Response

Layout Considerations

The specified high speed performance of the AD8079 requires
careful attention to board layout and component selection.
Proper RF design techniques and low parasitic component se­lection are mandatory.

The PCB should have a ground plane covering all unused por­tions of the component side of the board to provide a low im­pedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.

Chip capacitors should be used for supply bypassing (see Figure

29). One end should be connected to the ground plane and the
other within 1/8 in. of each power pin. An additional large
(4.7 µF–10 µF) tantalum electrolytic capacitor should be con-
nected in parallel, but not necessarily so close, to supply current
for fast, large-signal changes at the output.

Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly termi­nated at each end.

9

REV. A

–9–

AD8079

+V

S

IN

R

T

50Ω

–V

S

OUT

Inverting Configuration

+V

S

–V

S

C1

0.1µF

C2

0.1µF

C3
10µF

C4
10µF

Supply Bypassing

+V

S

50Ω

IN

R

T

–V

S

*

SEE TABLE I

OUT

Noninverting Configuration (G = +2)

TRIM

200Ω

R

AD8079B

T

IN

OUT

Figure 30. Board Layout (Silkscreen)

Optional Gain Trim (G = +2

TIE INPUT PINS

TOGETHER

TO MINIMIZE

PEAKING

IN

+V

S

R

T

–V

S

→ +

2.2)

OUT

Noninverting Configuration (G = +1)

Figure 29. Inverting and Noninverting Configurations

Table I. Recommended Component Values

Component –1 +1 +2/+2.2

RT (Nominal) (Ω) 53.6 49.9 49.9
Small Signal BW (MHz) 220 750 260

0.1 dB Flatness (MHz) 50 100 50

Figure 31. Board Layout (Component Layer)

Figure 32. Board Layout (Solder Side; Looking Through
the Board)

–10–

REV. A

0.1574 (4.00)

0.1497 (3.80)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead SOIC (SO-8)

0.1968 (5.00)

0.1890 (4.80)

8

5

0.2440 (6.20)

41

0.2284 (5.80)

AD8079

PIN 1

0.0098 (0.25)

0.0040 (0.10)

SEATING

PLANE

0.0500
(1.27)

BSC

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

0.0098 (0.25)

0.0075 (0.19)

0.0196 (0.50)

0.0099 (0.25)

8°
0°

0.0500 (1.27)

0.0160 (0.41)

x 45°

9

REV. A

–11–

C2185a–12–11/96

–12–

PRINTED IN U.S.A.