Page 1
Fiber Optic Receiver with Quantizer and
a
Clock Recovery and Data Retiming
FEATURES
Meets CCITT G.958 Requirements
for STM-1 Regenerator—Type A
Meets Bellcore TR-NWT-000253 Requirements for OC-3
Output Jitter: 2.0 Degrees RMS
155 Mbps Clock Recovery and Data Retiming
Accepts NRZ Data, No Preamble Required
Phase-Locked Loop Type Clock Recovery—
No Crystal Required
Quantizer Sensitivity: 2 mV
Level Detect Range: 2.0 mV to 30 mV
Single Supply Operation: +5 V or –5.2 V
Low Power: 170 mW
10 KH ECL/PECL Compatible Output
Package: 16-Pin Narrow 150 mil SOIC
PRODUCT DESCRIPTION
The AD807 provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming for
155 Mbps NRZ data. The device, together with a PIN
diode/preamplifier combination, can be used for a highly integrated, low cost, low power SONET OC-3 or SDH STM-1
fiber optic receiver.
The receiver front end signal level detect circuit indicates when
the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor. The signal level detect circuit 3 dB optical hysteresis prevents chatter at
the signal level detect output.
The PLL has a factory trimmed VCO center frequency and a
frequency acquisition control loop that combine to guarantee
AD807
frequency acquisition without false lock. This eliminates a reliance on external components such as a crystal or a SAW filter,
to aid frequency acquisition.
The AD807 acquires frequency and phase lock on input data
using two control loops that work without requiring external
control. The frequency acquisition control loop initially acquires
the frequency of the input data, acquiring frequency lock on
random or scrambled data without the need for a preamble. At
frequency lock, the frequency error is zero and the frequency
detector has no further effect. The phase acquisition control
loop then works to ensure that the output phase tracks the input
phase. A patented phase detector has virtually eliminated pattern jitter throughout the AD807.
The device VCO uses a ring oscillator architecture and patented
low noise design techniques. Jitter is 2.0 degrees rms. This low
jitter results from using a fully differential signal architecture,
Power Supply Rejection Ratio circuitry and a dielectrically
isolated process that provides immunity from extraneous signals
on the IC. The device can withstand hundreds of millivolts of
power supply noise without an effect on jitter performance.
The user sets the jitter peaking and acquisition time of the PLL
by choosing a damping factor capacitor whose value determines
loop damping. CCITT G.958 Type A jitter transfer requirements can easily be met with a damping factor of 5 or greater.
Device design guarantees that the clock output frequency will
drift by less than 20% in the absence of input data transitions.
Shorting the damping factor capacitor, C
put frequency to the VCO center frequency.
The AD807 consumes 140 mW and operates from a single
power supply at either +5 V or –5.2 V.
, brings the clock out-
D
FUNCTIONAL BLOCK DIAGRAM
PIN
NIN
THRADJ
QUANTIZER
DETECTOR
LEVEL
DETECT
COMPARATOR/
BUFFER
SIGNAL
LEVEL
SDOUT
Φ
DET
F
DET
AD807
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
CF1 CF2
COMPENSATING
ZERO
PHASE-LOCKED LOOP
RETIMING
DEVICE
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1997
LOOP
∑
FILTER
VCO
CLKOUTP
CLKOUTN
DATAOUTP
DATAOUTN
Page 2
AD807–SPECIFICA TIONS
(TA = T
MIN
to T
MAX
, VS = V
MIN
to V
, CD = 0.1 mF, unless otherwise noted)
MAX
Parameter Condition Min Typ Max Units
QUANTIZER–DC CHARACTERISTICS
Input Voltage Range @ P
Input Sensitivity, V
Input Overdrive, V
SENSE
OD
PIN–NIN, Figure 1, BER = ≤ 1 × 10
Figure 1, BER = ≤ 1 × 10
IN
or N
IN
–10
2.5 V
–10
2mV
S
V
0.001 2.5 V
Input Offset Voltage 50 500 µV
Input Current 510µA
Input RMS Noise BER = ≤ 1 × 10
Input Pk-Pk Noise BER = ≤ 1 × 10
–10
–10
50 µV
650 µV
QUANTIZER–AC CHARACTERISTICS
Upper –3 dB Bandwidth 180 MHz
Input Resistance 1MΩ
Input Capacitance 2pF
Pulse Width Distortion 100 ps
LEVEL DETECT
Level Detect Range R
R
R
= INFINITE 0.8 2 4.0 mV
THRESH
= 49.9 kΩ 4 5 7.4 mV
THRESH
= 3.4 kΩ 14 20 25 mV
THRESH
Response Time DC Coupled 0.1 1.5 µs
Hysteresis (Electrical) R
R
R
= INFINITE 2.3 4.0 10.0 dB
THRESH
= 49.9 kΩ 3.0 5.0 9.0 dB
THRESH
= 3.4 kΩ 3.0 7.0 10.0 dB
THRESH
SDOUT Output Logic High Load = +4 mA 3.6 V
SDOUT Output Logic Low Load = –1.2 mA 0.4 V
PHASE-LOCKED LOOP NOMINAL
CENTER FREQUENCY 155.52 MHz
CAPTURE RANGE 155 156 MHz
TRACKING RANGE 155 156 MHz
STATIC PHASE ERROR 27–1 PRN Sequence 4 20 Degrees
SETUP TIME (tSU) Figure 2 3.0 3.2 3.5 ns
HOLD TIME (tH) Figure 2 3.0 3.1 3.3 ns
PHASE DRIFT 240 Bits, No Transitions 40 Degrees
7
JITTER 2
–1 PRN Sequence 2.0 Degrees RMS
223–1 PRN Sequence 2.0 2.7 Degrees RMS
JITTER TOLERANCE f = 10 Hz 3000 Unit Intervals
f = 6.5 kHz 4.5 7.6 Unit Intervals
f = 65 kHz 0.45 1.0 Unit Intervals
f = 1.3 MHz 0.45 0.67 Unit Intervals
JITTER TRANSFER
Peaking (Figure 20) C
= 0.15 µF 0.08 dB
D
C
= 0.33 µF 0.04 dB
D
Bandwidth 65 92 130 kHz
Acquisition Time
C
= 0.1 µF2
D
CD = 0.33 µFV
POWER SUPPLY VOLTAGE V
POWER SUPPLY CURRENT V
23
–1 PRN Sequence, TA = +25°C4 × 1052 × 106Bit Periods
= 5 V, VEE = GND 2 × 10
CC
to V
MIN
CC
MAX
= 5.0 V, VEE = GND,
4.5 5.5 Volts
6
Bit Periods
TA = +25°C 25 34.5 39.5 mA
PECL OUTPUT VOLTAGE LEVELS
Output Logic High, V
Output Logic Low, V
OL
OH
Referenced to V
SYMMETRY (Duty Cycle) ρ = 1/2, T
CC
= +25°C,
A
–1.2 –1.0 –0.7 Volts
–2.0 –1.8 –1.7 Volts
Recovered Clock Output, Pin 5 VCC = 5 V, VEE = GND 50.1 54.1 %
OUTPUT RISE / FALL TIMES
Rise Time (t
) 20%–80% 1.1 1.5 ns
R
Fall Time (tF) 80%–20% 1.1 1.5 ns
Specifications subject to change without notice.
–2–
REV. A
Page 3
AD807
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V
Input Voltage (Pin 12 or Pin 13) . . . . . . . . . . . . . .V
+ 0.6 V
CC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . +165°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature Range (Soldering10 sec) . . . . . . . . +300°C
ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . .500 V
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Thermal Characteristics:
16-Pin Narrow Body SOIC Package: θJA = 110°C/Watt.
OUTPUT
NOISE
1
0
OFFSET
OVERDRIVE
SENSITIVITY
INPUT (V)
Figure 1. Input Sensitivity, Input Overdrive
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Description
1 DATAOUTN Differential Retimed Data Output
2 DATAOUTP Differential Retimed Data Output
3V
CC2
Digital VCC for ECL Outputs
4 CLKOUTN Differential Recovered Clock Output
5 CLKOUTP Differential Recovered Clock Output
6V
CC1
Digital VCC for Internal Logic
7 CF1 Loop Damping Capacitor
8 CF2 Loop Damping Capacitor
9AV
EE
Analog V
EE
10 THRADJ Level Detect Threshold Adjust
11 AV
CC1
Analog VCC for PLL
12 NIN Quantizer Differential Input
13 PIN Quantizer Differential Input
14 AV
CC2
Analog VCC for Quantizer
15 SDOUT Signal Detect Output
16 V
EE
Digital VEE for Internal Logic
SETUP HOLD
t
SU
DATAOUTP
(PIN 2)
CLKOUTP
(PIN 5)
Figure 2. Setup and Hold Time
t
H
PIN CONFIGURATION
DATAOUTN
DATAOUTP
CLKOUTN
CLKOUTP
1
2
3
V
2
CC
AD807
4
TOP VIEW
5
6
1
7
8
(NOT TO SCALE)
V
CC
CF1
CF2
16
15
14
13
12
11
10
9
V
EE
SDOUT
AV
CC2
PIN
NIN
AV
CC1
THRADJ
AV
EE
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD807-155BR or AD807A-155BR –40°C to +85°C 16-Pin Narrowbody SOIC R-16A
AD807-155BR-REEL7 or AD807A-155BRRL7 –40°C to +85°C 750 Pieces, 7" Reel R-16A
AD807-155BR-REEL or AD807A-155BRRL –40°C to +85°C 2500 Pieces, 13" Reel R-16A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
WARNING!
Although the AD807 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
REV. A
–3–
Page 4
AD807
DEFINITION OF TERMS
Maximum, Minimum and Typical Specifications
Specifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. Typical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the distribution. This procedure is intended to tolerate production variations: if the mean shifts by 1.5 standard deviations, the remaining
4.5 standard deviations still provide a failure rate of only 3.4 parts
per million. For all tested parameters, the test limits are guardbanded to account for tester variation to thus guarantee that no
device is shipped outside of data sheet specifications.
Input Sensitivity and Input Overdrive
Sensitivity and Overdrive specifications for the Quantizer involve offset voltage, gain and noise. The relationship between
the logic output of the quantizer and the analog voltage input is
shown in Figure 1.
For sufficiently large positive input voltage the output is always
Logic 1 and similarly, for negative inputs, the output is always
Logic 0. However, the transitions between output Logic Levels
1 and 0 are not at precisely defined input voltage levels, but occur over a range of input voltages. Within this Zone of Confusion, the output may be either 1 or 0, or it may even fail to attain
a valid logic state. The width of this zone is determined by the
input voltage noise of the quantizer (650 µV at the 1 × 10
–10
confidence level). The center of the Zone of Confusion is the
quantizer input offset voltage (± 500 µV maximum). Input Overdrive is the magnitude of signal required to guarantee correct
logic level with 1 × 10
–10
confidence level.
With a single-ended PIN-TIA (Figure 3), ac coupling is used
and the inputs to the Quantizer are dc biased at some commonmode potential. Observing the Quantizer input with an oscilloscope probe at the point indicated shows a binary signal with
average value equal to the common-mode potential and instantaneous values both above and below the average value. It is
convenient to measure the peak-to-peak amplitude of this signal
and call the minimum required value the Quantizer Sensitivity.
Referring to Figure 1, since both positive and negative offsets
need to be accommodated, the Sensitivity is twice the Overdrive. The AD807 Quantizer has 2 mV Sensitivity.
With a differential TIA (Figure 3), Sensitivity seems to improve
from observing the Quantizer input with an oscilloscope probe.
This is an illusion caused by the use of a single-ended probe. A
1 mV peak-to-peak signal appears to drive the AD807 Quantizer. However, the single-ended probe measures only half the
signal. The true Quantizer input signal is twice this value since
the other Quantizer input is a complementary signal to the signal being observed.
Response Time
Response time is the delay between removal of the input signal
and indication of Loss of Signal (LOS) at SDOUT. The response time of the AD807 (1.5 µs maximum) is much faster
than the SONET/SDH requirement (3 µs
≤
response time ≤
100 µs). In practice, the time constant of the ac coupling at the
Quantizer input determines the LOS response time.
Nominal Center Frequency
This is the frequency at which the VCO will oscillate with the
loop damping capacitor, C
, shorted.
D
Tracking Range
This is the range of input data rates over which the AD807 will
remain in lock.
Capture Range
This is the range of input data rates over which the AD807 will
acquire lock.
Static Phase Error
This is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling instant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error, and IC input and output signals prohibit direct measurement of static phase error.
Data Transition Density, ρ
This is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods. ρ is the ratio
(0 ≤ ρ ≤ 1) of data transitions to bit periods.
Jitter
This is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms or
Unit Intervals (UI). Jitter on the input data can cause dynamic
phase errors on the recovered clock sampling edge. Jitter on the
recovered clock causes jitter on the retimed data.
Output Jitter
This is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some pseudorandom input data sequence
(PRN Sequence).
Jitter Tolerance
Jitter Tolerance is a measure of the AD807’s ability to track a
jittery input data signal. Jitter on the input data is best thought
of as phase modulation, and is usually specified in unit intervals.
The PLL must provide a clock signal that tracks the phase
modulation in order to accurately retime jittered data. In order
for the VCO output to have a phase modulation that tracks the
input jitter, some modulation signal must be generated at the
output of the phase detector. The modulation output from the
phase detector can only be produced by a phase error between
its data input and its clock input. Hence, the PLL can never
perfectly track jittered data. However, the magnitude of the
phase error depends on the gain around the loop. At low frequencies, the integrator of the AD807 PLL provides very high
gain, and thus very large jitter can be tracked with small phase
errors between input data and recovered clock. At frequencies
closer to the loop bandwidth, the gain of the integrator is much
smaller, and thus less input jitter can be tolerated. The AD807
output will have a bit error rate less than 1 × 10
–10
when in lock
and retiming input data that has the CCITT G.958 specified
jitter applied to it.
Jitter Transfer (Refer to Figure 20)
The AD807 exhibits a low-pass filter response to jitter applied
to its input data.
Bandwidth
This describes the frequency at which the AD807 attenuates
sinusoidal input jitter by 3 dB.
Peaking
This describes the maximum jitter gain of the AD807 in dB.
–4–
REV. A
Page 5
Damping Factor, ζ
Damping factor, ζ describes the compensation of the second order PLL. A larger value of ζ corresponds to more damping and
less peaking in the jitter transfer function.
Acquisition Time
This is the transient time, measured in bit periods, required for
the AD807 to lock onto input data from its free-running state.
Symmetry—Recovered Clock Duty Cycle
Symmetry is calculated as (100 × on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.
Bit Error Rate vs. Signal-to-Noise Ratio
AD807 Bit Error Rate vs. Signal-to-Noise Ratio performance is
shown in Figure 11. Wideband amplitude noise is summed with
the input data signal as shown in Figure 4. Performance is
shown for input data levels of 5 mV and 10 mV.
2mVp-p
AD807 QUANTIZER
BINARY
OUTPUT
EPITAXX ERM504
V
CM
SCOPE
PROBE
AV
CC2
DIFFERENTIAL
INPUT
AV
VBE ù 0.8V
CURRENT SOURCES
HEADROOM ≥ 0.7V
EE
0.5mA 1mA 0.5mA
400Ω 400Ω
a. Quantizer Differential Input Stage
1.2V +V
BE
5.9kΩ
THRADJ
94.6kΩ
AV
b. Threshold Adjust
I
OH
I
OL
150Ω
150Ω
EE
V
CC1
SDOUT
AD807
V
CM
a. Single-Ended Input Application
1mVp-p
AD807 QUANTIZER
BINARY
OUTPUT
AD8015
DIFFERENTIAL
OUTPUT TIA
+OUT
–OUT
V
CM
SCOPE
PROBE
V
CM
b. Differential Input Application
Figure 3. (a–b) Single-Ended and Differential Input
Applications
DIFFERENTIAL
SIGNAL
SOURCE
POWER COMBINER
+
∑
+
POWER
COMBINER
+
∑
–
0.47µF
POWER
SPLITTER
0.47µF
50Ω
50Ω
75Ω 100Ω1.0µF
PIN
D.U.T.
AD807
NIN
V
EE
c. Signal Detect Output (SDOUT)
V
450Ω 450Ω
2.5mA
CC2
DIFFERENTIAL
OUTPUT
V
EE
d. PLL Differential Output Stage—DATAOUT(N),
CLKOUT(N)
Figure 5. (a–d) Simplified Schematics
FILTER100MHz
NOISE
SOURCE
GND
Figure 4. Bit Error Rate vs. Signal-to-Noise Ratio
Test: Block Diagram
REV. A
+5V
–5–
Page 6
AD807–Typical Characteristic Curves
200.0E+3
180.0E+3
160.0E+3
140.0E+3
120.0E+3
– Ω
100.0E+3
80.0E+3
THRESH
R
60.0E+3
40.0E+3
20.0E+3
0.0E+0
000.0E+0 35.0E–35.0E–3
10.0E–3 15.0E–3 20.0E–3 25.0E–3 30.0E–3
SIGNAL DETECT LEVEL – Volts
Figure 6. Signal Detect Level vs. R
35.0E–3
R
= 0Ω
30.0E–3
25.0E–3
20.0E–3
15.0E–3
10.0E–3
SIGNAL DETECT LEVEL – Volts
5.0E–3
000.0E+0
–40 100–20
THRESH
R
= 49.9k
THRESH
R
THRESH
0 20406080
TEMPERATURE – °C
= OPEN
THRESH
35.000E–3
R
= 0Ω
R
THRESH
R
THRESH
THRESH
= 49.9k
= OPEN
30.000E–3
25.000E–3
20.000E–3
15.000E–3
10.000E–3
SIGNAL DETECT LEVEL – Volts
5.000E–3
000.000E+0
4.4 4.6
SUPPLY VOLTAGE – Volts
4.8 5.0 5.2 5.4 5.6
Figure 9. Signal Detect Level vs. Supply Voltage
8.00
7.00
6.00
R
THRESH
= 49.9kΩ
4.8 5.0 5.2 5.4
5.00
4.00
3.00
2.00
ELECTRICAL HYSTERESIS – dB
1.00
0.00
4.4 5.64.6
POWER SUPPLY – V
R
THRESH
R
THRESH
= 0Ω
= OPEN
Figure 7. Signal Detect Level vs. Temperature
9.00
8.00
R
= 0Ω
R
THRESH
THRESH
= 49.9k
R
THRESH
= OPEN
7.00
6.00
5.00
ELECTRICAL HYSTERESIS – dB
4.00
3.00
–40 100–20
0 20406080
TEMPERATURE – °C
Figure 8. Signal Detect Hysteresis vs. Temperature
Figure 10. Signal Detect Hysteresis vs. Power Supply
1E-1
5E-2
3E-2
2E-2
1E-2
S
1
1
1E-3
1E-4
BIT ERROR RATE
1E-5
1E-6
1E-8
1E-10
1E-12
10 12 16 18 22 24
erfc
2
1278
1279
1277
NSN
1276
14 20
2 2
N
S/N – dB
Figure 11. Bit Error Rate vs. Signal-to-Noise Ratio
–6–
REV. A
Page 7
AD807
30
TEST CONDITIONS
WORST CASE:
25
– 40°C, 4.5V
20
15
10
PERCENTAGE – %
5
0
1.4 2.31.5
1.6 1.7 1.8 1.9 2.0 2.1 2.2
RMS JITTER – Degrees
Figure 12. Output Jitter Histogram
1E+3
100E+0
10E+0
AD807
JITTER TOLERANCE – UI
1E+0
SONET MASK
100E–3
10E+0 10E+6100E+0
10E+3 100E+3 1E+6
1E+3
FREQUENCY – Hz
Figure 13. Jitter Tolerance
3.0
2.0
PSR – NO FILTER
XFCB’s dielectric isolation allows the different blocks within
this mixed-signal IC to be isolated from each other, hence the
2 mV Sensitivity is achieved. Traditionally, high speed comparators are plagued by crosstalk between outputs and inputs, often
resulting in oscillations when the input signal approaches 10 mV.
The AD807 quantizer toggles at ±650 µV (1.3 mV sensitivity) at
the input without making bit errors. When the input signal is
lowered below ±650 µV, circuit performance is dominated by
input noise, and not crosstalk.
AD807
AV
AV
13
PIN
12
NIN
14
CC2
11
CC1
6
V
1
CC
3
V
2
CC
3.65kΩ
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
500Ω
0.1µF
50Ω50Ω
309Ω
0.1µF
QUANTIZER
INPUT
500Ω
OPTIONAL FILTER
FERRITE BEAD
0.1µF
0.1µF
50Ω
+5V
10µF
CHOKE
"BIAS TEE"
311MHz
NOISE
INPUT
Figure 15. Power Supply Noise Sensitivity Test Circuit
AD807
AV
AV
13
PIN
12
NIN
14
CC2
11
CC1
6
V
1
CC
3
V
2
CC
3.65kΩ
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
500Ω
500Ω
0.1µF
QUANTIZER
INPUT
CHOKE
"BIAS TEE"
0.1µF
50Ω
+5V
10µF
311MHz
NOISE
INPUT
0.1µF
50Ω50Ω
309Ω
CMR
JITTER – ns p-p
1.0
PSR – WITH FILTER
0
0.1 0.3 0.5 0.7 0.9
0 0.2
0.4 0.6 0.8 1.0
NOISE – Vp-p @311MHz
Figure 14. Output Jitter vs. Supply Noise and
Output Jitter vs. Common Mode Noise
THEORY OF OPERATION
Quantizer
The quantizer (comparator) has three gain stages, providing a
net gain of 350. The quantizer takes full advantage of the Extra
Fast Complementary Bipolar (XFCB) process. The input stage
uses a folded cascode architecture to virtually eliminate pulse
width distortion, and to handle input signals with commonmode voltage as high as the positive supply. The input offset
voltage is factory trimmed and guaranteed to be less than 500 µV.
REV. A
–7–
Figure 16. Common-Mode Rejection Test Circuit
Signal Detect
The input to the signal detect circuit is taken from the first stage
of the quantizer. The input signal is first processed through a
gain stage. The output from the gain stage is fed to both a positive and a negative peak detector. The threshold value is subtracted from the positive peak signal and added to the negative
peak signal. The positive and negative peak signals are then
compared. If the positive peak, POS, is more positive than the
negative peak, NEG, the signal amplitude is greater than the
threshold, and the output, SDOUT, will indicate the presence
of signal by remaining low. When POS becomes more negative
than NEG, the signal amplitude has fallen below the threshold,
and SDOUT will indicate a loss of signal (LOS) by going high.
The circuit provides hysteresis by adjusting the threshold level
higher by a factor of two when the low signal level is detected.
This means that the input data amplitude needs to reach twice
the set LOS threshold before SDOUT will signal that the data is
again valid. This corresponds to a 3 dB optical hysteresis.
Page 8
AD807
10 20k10k100 1k
C
D
PEAK
0.1 0.12
0.15 0.08
0.22 0.06
0.33 0.04
0.02dB/DIV
FREQUENCY IN kHz
PIN
NIN
AD807
COMPARATOR STAGES
& CLOCK RECOVERY PLL
POSITIVE
PEAK
DETECTOR
NEGATIVE
PEAK
DETECTOR
THRESHOLD
BIAS
+
∑
ITHR
LEVEL
SHIFT
DOWN
LEVEL
SHIFT
UP
+
Figure 17. Signal Level Detect Circuit Block Diagram
Phase-Locked Loop
The phase-locked loop recovers clock and retimes data from
NRZ data. The architecture uses a frequency detector to aid initial frequency acquisition; refer to Figure 18 for a block diagram. Note the frequency detector is always in the circuit. When
the PLL is locked, the frequency error is zero and the frequency
detector has no further effect. Since the frequency detector is always in the circuit, no control functions are needed to initiate
acquisition or change mode after acquisition.
DATA
INPUT
Φ
DET
F
DET
S + 1
RETIMING
DEVICE
∑
1
S
VCO
RECOVERED CLOCK
OUTPUT
RETIMED DATA
OUTPUT
Figure 18. PLL Block Diagram
The frequency detector delivers pulses of current to the charge
pump to either raise or lower the frequency of the VCO. During
the frequency acquisition process the frequency detector output
is a series of pulses of width equal to the period of the VCO.
These pulses occur on the cycle slips between the data frequency and the VCO frequency. With a maximum density data
pattern (1010 . . . ), every cycle slip will produce a pulse at the
frequency detector output. However, with random data, not
every cycle slip produces a pulse. The density of pulses at the
frequency detector output increases with the density of data
transitions. The probability that a cycle slip will produce a pulse
increases as the frequency error approaches zero. After the frequency error has been reduced to zero, the frequency detector
output will have no further pulses. At this point the PLL begins
the process of phase acquisition, with a settling time of roughly
2000 bit periods.
Jitter caused by variations of density of data transitions (pattern
jitter) is virtually eliminated by use of a new phase detector (patented). Briefly, the measurement of zero phase error does not
cause the VCO phase to increase to above the average run rate
set by the data frequency. The jitter created by a 2
random code is 1/2 degree, and this is small compared to random jitter.
The jitter bandwidth for the PLL is 0.06% of the center frequency. This figure is chosen so that sinusoidal input jitter at
7
–1 pseudo-
92 kHz will be attenuated by 3 dB.
The damping ratio of the PLL is user programmable with a
single external capacitor. At 155 MHz, a damping ratio of 5 is
obtained with a 0.15 µF capacitor. More generally, the damping
ratio scales as (f
DATA
× CD)
1/2
.
IHYS
SDOUT
A lower damping ratio allows a faster frequency acquisition;
generally the acquisition time scales directly with the capacitor
value. However, at damping ratios approaching one, the acquisition time no longer scales directly with capacitor value. The
acquisition time has two components: frequency acquisition and
phase acquisition. The frequency acquisition always scales with
capacitance, but the phase acquisition is set by the loop bandwidth of the PLL and is independent of the damping ratio.
Thus, the 0.06% fractional loop bandwidth sets a minimum
acquisition time of 2000 bit periods. Note the acquisition time
for a damping factor of one is 15,000 bit periods. This comprises 13,000 bit periods for frequency acquisition and 2,000 bit
periods for phase acquisition. Compare this to the 400,000 bit
periods acquisition time specified for a damping ratio of 5; this
consists entirely of frequency acquisition, and the 2,000 bit
periods of phase acquisition is negligible.
While a lower damping ratio affords faster acquisition, it also allows more peaking in the jitter transfer response (jitter peaking).
For example, with a damping ratio of 10, the jitter peaking is
0.02 dB, but with a damping ratio of 1, the peaking is 2 dB.
Center Frequency Clamp (Figure 19)
An N-channel FET circuit can be used to bring the AD807
VCO center frequency to within ±10% of 155 MHz when
SDOUT indicates a Loss of Signal (LOS). This effectively reduces the frequency acquisition time by reducing the frequency
error between the VCO frequency and the input data frequency
at clamp release. The N-FET can have “on” resistance as high
as 1 kΩ and still attain effective clamping. However, the chosen
N-FET should have greater than 10 MΩ “off” resistance and
less than 100 nA leakage current (source and drain) so as not to
alter normal PLL performance.
N_FET
1
DATAOUTN
2
DATAOUTP
3
V
CC2
CLKOUTN
4
CLKOUTP
5
V
6
1
CC
CF1
7
C
D
CF2
8
AD807
V
SDOUT
AV
CC2
PIN
NIN
AV
CC1
THRADJ
AV
16
EE
15
14
13
12
11
10
9
EE
Figure 19. Center Frequency Clamp Schematic
Figure 20. Jitter Transfer vs. C
D
–8–
REV. A
Page 9
1
2
5
6
7
3
4
8
16
15
12
11
10
14
13
9
V
EE
SDOUT
NIN
AV
CC1
THRADJ
AV
EE
AD807
R10
154Ω
R9
154Ω
R6 100Ω
C7
R5 100Ω
R1
100ΩR2100Ω
C1 0.1µF
DATAOUTN
DATAOUTP
CLKOUTN
CLKOUTP
C5 0.1µF
C2
0.1µF
R4
100Ω
R8 100Ω
R7 100Ω
R3
100Ω
C8
R12
154Ω
TP1
TP2
R11
154Ω
CD
TP7
SDOUT
TP5
TP6
R
THRESH
C11
10µF
C10
GND
R14
49.9Ω
R15
49.9Ω
C12 0.1µF
C4 0.1µF
C3 0.1µF
C6 0.1µF
J1
J2
J3
J4
+5V
TP3
TP4
AV
CC2
PIN
DATAOUTN
DATAOUTP
V
CC2
CLKOUTN
CLKOUTP
V
CC1
CF1
CF2
NOTE: INTERCONNECT RUN
UNDER DUT
VECTOR PINS SPACED FOR RN55C
TYPE RESISTOR; COMPONENT
SHOWN FOR REFERENCE ONLY
VECTOR PINS SPACED THROUGH-HOLE
CAPACITOR ON VECTOR CUPS; COMPONENT
SHOWN FOR REFERENCE ONLY
TP8
J5
C9
R13
301Ω
R16 3.65kΩ
J6
J7
C13 0.1µF
C14 0.1µF
PIN
NIN
50Ω STRIP LINE
EQUAL LENGTH
NOTE:
C7–C10 ARE 0.1µF BYPASS CAPACITORS
RIGHT ANGLE SMA CONNECTOR
OUTER SHELL TO GND PLANE
ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT
TPxoTEST POINTS ARE VECTORBOARD K24A/M PINS
Figure 21. Evaluation Board Schematic
AD807
REV. A
CIRCUIT SIDE
08-002901-02
REV A
SILKSCREEN TOP
08-002901-03
REV A
INT2
08-002901-08
REV A
COMPONENT SIDE
08-002901-01
REV A
–9–
Figure 22. Evaluation Board Pictorials
INT1
08-002901-07
REV A
SOLDERMASK TOP
08-002901-04
REV A
Page 10
AD807
DATAOUTN
DATAOUTP
CLKOUTN
CLKOUTP
C1 0.1µF
C2
R1
0.1µF
100R2100
C3
0.1µF
C4
0.1µF
C5
0.1µF
R4
R3
100
100
C6
0.1µF
NOTES
1. ALL CAPS ARE CHIP,
15pF ARE MICA.
2. 150nH ARE SMT
R5 100
R6 100
R7 100
R8 100
R11
154
R12
154
154
R9
C7
C8
CD
R10
154
1
DATAOUTN
2
DATAOUTP
3
V
CC2
4
CLKOUTN
5
CLKOUTP
6
V
TP1
TP2
CC1
7
CF1
CF2
8
GND
TP4
ABB HAFO 1A227
FC HOUSING
0.1µF
THRADJ
AD807
C9
10µF
0.8 A/W, 0.7pF
2.5GHz
0.01µF
V
SDOUT
AV
PIN
NIN
AV
AV
5V TP3
EE
CC
CC
EE
1
2
3
4
SDOUT
TP7
R17
3.65k
16
NC
I
NC
V
15
14
13
12
11
10
IN
BYP
C11
C10
TP6
9
+V
S
+OUT
–OUT
–V
S
AD8015
NC = NO CONNECT
R13
THRADJ
TP5
8
7
6
5
Figure 23. Low Cost 155 Mbps Fiber Optic Receiver Schematic
C12
2.2µF
0.1µF
10µF
150nH
15pF
150nH
R16
301
C15
0.1µF
15pF
R14
50
0.1µF
50Ω
LINE
C14
R15
50
50Ω
LINE
C13
0.1µF
Table I. AD807—AD8015 Fiber Optic Receiver Circuit:
Output Bit Error Rate & Output Jitter vs. Input Power
Average Optical
Input Power Output Bit Output Jitter
(dBm) Error Rate (ps rms)
–6.4 Loses Lock
–6.5 7.5 × 10
–6.6 9.4 × 10
–6.7 0 × 10
–7.0 to –35.5 0 × 10
–36.0 3 × 10
–36.5 4.8 × 10
–37.0 2.8 × 10
–38.0 1.3 × 10
–39.0 1.0 × 10
–39.2 1.9 × 10
–14
–14
–12
–3
–4
<40
<40
–10
–8
–5
–3
–3
–39.3 Loses Lock
APPLICATIONS
Low Cost 155 Mbps Fiber Optic Receiver
The AD807 and AD8015 can be used together for a complete
155 Mbps Fiber Optic Receiver (Quantizer and Clock Recovery,
and Transimpedance Amplifier) as shown in Figure 23.
The PIN diode front end is connected to a single mode 1 300 nm
laser source. The PIN diode has 3.3 V reverse bias, 0.8 A/W responsively, 0.7 pF capacitance, and 2.5 GHz bandwidth.
The AD8015 outputs (P
OUT
and N
) drive a differential, con-
OUT
stant impedance (50 Ω) low-pass filter with a 3 dB cutoff of
100 MHz. The outputs of the low-pass filter are ac coupled to
the AD807 inputs (PIN and NIN). The AD807 PLL damping
factor is set at 7 using a 0.22 µF capacitor.
Figure 24. Receiver Output (Data) Eye Diagram,
–7.0 dBm Optical Input
Figure 25. Receiver Output (Data) Eye Diagram,
–36.0 dBm Optical Input
–10–
REV. A
Page 11
AD807
C1 0.1µF
SDOUT
C2
R1
0.1µF
C4
0.1µF
C5
0.1µF
C3
0.1µF
R3
100
C6
0.1µF
100R2100
J1
J2
J3
J4
100
R5 100
R6 100
R7 100
R8 100
R4
R11
150
154
0.1µF
R12
150
R10
R9
154
C7 0.1µF
C8
CD
0.1µF
1
DATAOUTN
2
DATAOUTP
3
V
CC2
4
CLKOUTN
5
CLKOUTP
6
V
CC1
CF1
7
CF2
8
AD807
C9 10
+5V
V
SDOUT
AV
CC2
PIN
NIN
AV
CC1
THRADJ
AV
16
EE
15
14
C11 0.1
13
12
C10 0.1
11
10
9
EE
R13
THRADJ
R14
47
R16
330
R15
47
Figure 26. AD807 Application with Epitaxx PIN—Transimpedance Amplifier Module
C12 0.1
C13
0.1
R17
3.9k
120nH
0.1
NOISE FILTER
1
30pF30pFC14
PIN TIA
2
EPITAXX
ERM504
3
NOTE
PIN TIA PIN 4 (CASE)
IS CONNECTED TO
GROUND
1µF
The entire circuit was enclosed in a shielded box. Table I summarizes results of tests performed using a 2
23
-1 PRN Sequence,
and varying the average power at the PIN diode.
The circuit acquires and maintains lock with an average input
power as low as –39.25 dBm.
Table II. AD807—Epitaxx ERM504 PIN TIA 155 Mbps
Fiber Optic Receiver Circuit:
Output Bit Error Rate & Output Jitter vs. Average Input Power
Average Optical
Input Power Output Bit Output Jitter
(dBm) Error Rate (ps rms)
0 0.0 × 10
–3 0.0 × 10
–10 0.0 × 10
–20 0.0 × 10
–30 0.0 × 10
–32 0.0 × 10
–34 0.0 × 10
–35 0.0 × 10
–35.5 0.0 × 10
–36 0.0 × 10
–37.0 0.0 × 10
–37.6 0.5 × 10
–38.0 4 × 10
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
–6
29
35
40
37
33
35
36
39
40
41
42
43
50
250mV
50mV/
DIV
–250mV
38.12ns
1ns/DIV
48.12ns
Figure 27. Receiver Output (Data) Eye Diagram,
0 dBm Optical Input
250mV
50mV/
DIV
SONET (OC-3)/SDH (STM-1) Fiber Optic Receiver Circuit
A light wave receiver circuit for SONET/SDH application at
155 Mbps is shown in Figure 26, with test results given in Table
II. The circuit operates from a single +5 V supply, and uses two
major components: an Epitaxx ERM504 PIN-TIA module with
AGC, and the AD807 IC.
A 120 MHz, third order, low-pass Butterworth filter at the output of the PIN-TIA module provides adequate bandwidth (70%
of the bit rate), and attenuates high frequency (out of band)
noise.
REV. A
–11–
–250mV
38.12ns
1ns/DIV
48.12ns
Figure 28. Receiver Output (Data) Eye Diagram,
–38 dBm Optical Input
Page 12
AD807
USING THE AD807
Ground Planes
Use of one ground plane for connections to both analog and
digital grounds is recommended.
Power Supply Connections
Use of a 10 µF capacitor between VCC and ground is recommended. Care should be taken to isolate the +5 V power trace
to V
(Pin 3). The V
CC2
pin is used inside the device to pro-
CC2
vide the CLKOUT and DATAOUT signals.
Use of 0.1 µF capacitors between IC power supply and ground
is recommended. Power supply decoupling should take place as
close to the IC as possible. Refer to the schematic, Figure 21,
for recommended connections.
Transmission Lines
Use of 50 Ω transmission lines are recommended for PIN, NIN,
CLKOUT, and DATAOUT signals.
Terminations
Termination resistors should be used for PIN, NIN, CLKOUT,
and DATAOUT signals. Metal, thick film, 1% tolerance resistors
are recommended. Termination resistors for the PIN, NIN signals should be placed as close as possible to the PIN, NIN pins.
Connections from +5 V to load resistors for PIN, NIN,
CLKOUT, and DATAOUT signals should be individual, not
daisy chained. This will avoid crosstalk on these signals.
Loop Damping Capacitor, C
D
A ceramic capacitor may be used for the loop damping capacitor. Using a 0.15 µF,
+20% capacitor for a damping factor of
five provides < 0.1 dB jitter peaking.
AD807 Output Squelch Circuit
A simple P-channel FET circuit can be used in series with the
Output Signal ECL Supply (V
, Pin 3) to squelch clock and
CC2
data outputs when SDOUT indicates a loss of signal (Figure
29). The V
supply pin draws roughly 61 mA (14 mA for each
CC2
of 4 ECL loads, plus 5 mA for all 4 ECL output stages). This
means that selection of a FET with ON RESISTANCE of
0.5 Ω will affect the common mode of the ECL outputs by only
31 mV.
5V
BYPASS
CAP
P_FET
CC1
1
DATAOUTN
2
DATAOUTP
V
3
CLKOUTN
4
CLKOUTP
5
6
V
CF1
7
CF2
8
CC2
CC
1
AD807
CC2
SDOUT
AV
AV
THRADJ
AV
V
CC2
PIN
NIN
CC1
16
EE
15
14
13
12
11
10
9
EE
TO V
, AVCC, AV
Figure 29. Squelch Circuit Schematic
C2044a–2–3/97
16-Lead Small Outline IC Package
16 9
PIN 1
1
0.0098 (0.25)
0.0040 (0.10)
0.0500
(1.27)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
(R-16A)
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
8
0.2284 (5.80)
0.3937 (10.00)
0.3859 (9.80)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
0.0099 (0.25)
0.0075 (0.19)
8°
0°
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
0.0160 (0.41)
x 45°
PRINTED IN U.S.A.
–12–
REV. A
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