Datasheet AD8065 Datasheet (Analog Devices)

High Performance, 145 MHz

V

FEATURES

FET input amplifier 1 pA input bias current Low cost High speed: 145 MHz, −3 dB bandwidth (G = +1) 180 V/µs slew rate (G = +2) Low noise

7 nV/√Hz (f = 10 kHz)

0.6 fA/√Hz (f = 10 kHz) Wide supply voltage range: 5 V to 24 V Single-supply and rail-to-rail output Low offset voltage 1.5 mV max High common-mode rejection ratio: −100 dB Excellent distortion specifications SFDR −88 dB @ 1 MHz Low power: 6.4 mA/amplifier typical supply current No phase reversal Small packaging: SOIC-8, SOT-23-5, and MSOP

GENERAL DESCRIPTION

APPLICATIONS

Instrumentation Photodiode preamps Filters A/D drivers Level shifting Buffering

CONNECTION DIAGRAMS

AD8065

1

OUT

–V

2

S

3

+IN

TOP VIEW

(Not to Scale)

V

OUT1

Fast

FET™ Op Amps

AD8065/AD8066

+V

5

S

4

–IN

AD8066

1

2

–IN1

3

+IN1 –IN2

–V

4

S

TOP VIEW

(Not to Scale)

Figure 1.

1

NC

27

–IN

3

+IN

–V

4

S

(Not to Scale)

8

+V

7

V

6

5

+IN2

AD8065

TOP VIEW

S

OUT2

8

NC

+V

S

6

V

OUT

NC

5

02916-E-001

The AD8065/AD80661 FastFET amplifiers are voltage feedback amplifiers with FET inputs offering high performance and ease of use. The AD8065 is a single amplifier, and the AD8066 is a dual amplifier. These amplifiers are developed in the Analog Devices, Inc. proprietary XFCB process and allow exceptionally low noise operation (7.0 nV/√Hz and 0.6 fA/√Hz) as well as very high input impedance.

With a wide supply voltage range from 5 V to 24 V, the ability to operate on single supplies, and a bandwidth of 145 MHz, the AD8065/AD8066 are designed to work in a variety of applications. For added versatility, the amplifiers also contain rail-to-rail outputs.

Despite the low cost, the amplifiers provide excellent overall performance. The differential gain and phase errors of 0.02% and 0.02°, respectively, along with 0.1 dB flatness out to 7 MHz, make these amplifiers ideal for video applications. Additionally, they offer a high slew rate of 180 V/µs, excellent distortion (SFDR of −88 dB @ 1 MHz), extremely high common-mode rejection of −100 dB, and a low input offset voltage of 1.5 mV maximum under warmed up conditions. The AD8065/AD8066

1

Protected by U. S. Patent No. 6,262,633.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

operate using only a 6.4 mA/amplifier typical supply current and are capable of delivering up to 30 mA of load current.

The AD8065/AD8066 are high performance, high speed, FET input amplifiers available in small packages: SOIC-8, MSOP-8, and SOT-23-5. They are rated to work over the industrial temperature range of −40°C to +85°C.

24

21

G = +10

18

G = +5

15

12

9

G = +2

GAIN (dB)

6

3

G = +1

0

–3

–6

10.1 10 100 1000 FREQUENCY (MHz)

Figure 2. Small Signal Frequency Response

V

= 200mV p-p

O

02916-E-002

AD8065/AD8066

SPECIFICATIONS

@ TA = 25°C, VS = ±5 V, RL = 1 kΩ, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, VO = 0.2 V p-p (AD8065) 100 145 MHz G = +1, VO = 0.2 V p-p (AD8066) 100 120 MHz G = +2, VO = 0.2 V p-p 50 MHz G = +2, VO = 2 V p-p 42 MHz Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 7 MHz Input Overdrive Recovery Time G = +1, −5.5 V to +5.5 V 175 ns Output Recovery Time G = −1, −5.5 V to +5.5 V 170 ns Slew Rate G = +2, VO = 4 V Step 130 180 V/µs

Settling Time to 0.1% G = +2, VO = 2 V Step 55 ns G = +2, VO = 8 V Step 205 ns NOISE/HARMONIC PERFORMANCE

SFDR fC = 1 MHz, G = +2, VO = 2 V p-p −88 dBc

f

Third-Order Intercept fC = 10 MHz, RL = 100 Ω 24 dBm

Input Voltage Noise f = 10 kHz 7 nV/√Hz

Input Current Noise f = 10 kHz 0.6 fA/√Hz

Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.02 %

Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.02 Degree DC PERFORMANCE

Input Offset Voltage VCM = 0 V, SOIC Package 0.4 1.5 mV

Input Offset Voltage Drift 1 17 µV/°C

Input Bias Current SOIC Package 2 6 pA

T

Input Offset Current 1 10 pA

T

Open-Loop Gain VO = ±3 V, RL = 1 kΩ 100 113 dB INPUT CHARACTERISTICS

Common-Mode Input Impedance 1000 || 2.1 GΩ || pF

Differential Input Impedance 1000 || 4.5 GΩ || pF

Input Common-Mode Voltage Range

FET Input Range −5 to +1.7 −5.0 to +2.4 V Usable Range See the Theory of Operation section −5.0 to +5.0 V

Common-Mode Rejection Ratio VCM = −1 V to +1 V −85 −100 dB V OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 1 kΩ −4.88 to +4.90 −4.94 to +4.95 V

R

Output Current VO = 9 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 35 mA

Short-Circuit Current 90 mA

Capacitive Load Drive 30% Overshoot G = +1 20 pF POWER SUPPLY

Operating Range 5 24 V

Quiescent Current per Amplifier 6.4 7.2 mA

Power Supply Rejection Ratio ±PSRR −85 −100 dB

= 5 MHz, G = +2, VO = 2 V p-p −67 dBc

C

= 1 MHz, G = +2, VO = 8 V p-p −73 dBc

C

to T

MIN

CM

= 150 Ω −4.8 to +4.7 V

L

25 pA

MAX

to T

1 pA

MAX

= −1 V to +1 V (SOT-23) −82 −91 dB

Rev. E | Page 3 of 28

AD8065/AD8066

@ TA = 25°C, VS = ±12 V, RL = 1 kΩ, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE MHz

−3 dB Bandwidth G = +1, VO = 0.2 V p-p (AD8065) 100 145 MHz G = +1, VO = 0.2 V p-p (AD8066) 100 115 MHz G = +2, VO = 0.2 V p-p 50 MHz G = +2, VO = 2 V p-p 40 MHz Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 7 MHz Input Overdrive Recovery G = +1, −12.5 V to +12.5 V 175 ns Output Overdrive Recovery G = −1, −12.5 V to +12.5 V 170 ns Slew Rate G = +2, VO = 4 V Step 130 180 V/µs

Settling Time to 0.1% G = +2, VO = 2 V Step 55 ns G = +2, VO = 10 V Step 250 ns NOISE/HARMONIC PERFORMANCE

SFDR fC = 1 MHz, G = +2, VO = 2 V p-p −100 dBc f f

Third-Order Intercept fC = 10 MHz, RL = 100 Ω 24 dBm

Input Voltage Noise f = 10 kHz 7 nV/√Hz

Input Current Noise f = 10 kHz 1 fA/√Hz

Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.04 %

Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.03 Degree DC PERFORMANCE

Input Offset Voltage VCM = 0 V, SOIC Package 0.4 1.5 mV

Input Offset Voltage Drift 1 17 µV/°C

Input Bias Current SOIC Package 3 7 pA

T

Input Offset Current 2 10 pA

T

Open-Loop Gain VO = ±10 V, RL = 1 kΩ 103 114 dB INPUT CHARACTERISTICS

Common-Mode Input Impedance 1000 || 2.1 GΩ || pF

Differential Input Impedance 1000 || 4.5 GΩ || pF

Input Common-Mode Voltage Range

FET Input Range −12 to +8.5 −12.0 to +9.5 V Usable Range See the Theory of Operation section −12.0 to +12.0 V

Common-Mode Rejection Ratio VCM = −1 V to +1 V −85 −100 dB V OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 1 kΩ −11.8 to +11.8 −11.9 to +11.9 V

R

Output Current VO = 22 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 30 mA

Short-Circuit Current 120 mA

Capacitive Load Drive 30% Overshoot G = +1 25 pF POWER SUPPLY

Operating Range 5 24 V

Quiescent Current per Amplifier 6.6 7.4 mA

Power Supply Rejection Ratio ±PSRR −84 −93 dB

= 5 MHz, G = +2, VO = 2 V p-p −67 dBc

C

= 1 MHz, G = +2, VO = 10 V p-p −85 dBc

C

to T

MIN

CM

= 350 Ω −11.25 to +11.5 V

L

25 pA

MAX

to T

2 pA

MAX

= −1 V to +1 V (SOT-23) −82 −91 dB

Rev. E | Page 4 of 28

AD8065/AD8066

@ TA = 25°C, VS = 5 V, RL = 1 kΩ, unless otherwise noted.

Table 3.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, VO = 0.2 V p-p (AD8065) 125 155 MHz G = +1, VO = 0.2 V p-p (AD8066) 110 130 MHz G = +2, VO = 0.2 V p-p 50 MHz G = +2, VO = 2 V p-p 43 MHz Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 6 MHz Input Overdrive Recovery Time G = +1, −0.5 V to +5.5 V 175 ns Output Recovery Time G = −1, −0.5 V to +5.5 V 170 ns Slew Rate G = +2, VO = 2 V Step 105 160 V/µs Settling Time to 0.1% G = +2, VO = 2 V Step 60 ns

NOISE/HARMONIC PERFORMANCE

SFDR fC = 1 MHz, G = +2, VO = 2 V p-p −65 dBc f Third-Order Intercept fC = 10 MHz, RL = 100 Ω 22 dBm Input Voltage Noise f = 10 kHz 7 nV/√Hz Input Current Noise f = 10 kHz 0.6 fA/√Hz Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.13 % Differential Phase Error NTSC, G = +2, RL = 150 Ω 0.16 Degree

DC PERFORMANCE

Input Offset Voltage V Input Offset Voltage Drift 1 17 µV/ºC Input Bias Current SOIC Package 1 5 pA T Input Offset Current 1 5 pA T

Open-Loop Gain VO = 1 V to 4 V (AD8065) 100 113 dB V INPUT CHARACTERISTICS

Common-Mode Input Impedance 1000 || 2.1 GΩ || pF

Differential Input Impedance 1000 || 4.5 GΩ || pF

Input Common-Mode Voltage Range

FET Input Range 0 to 1.7 0 to 2.4 V

Usable Range See the Theory of Operation section 0 to 5.0 V

Common-Mode Rejection Ratio VCM = 1 V to 4 V −74 −100 dB V OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 1 kΩ 0.1 to 4.85 0.03 to 4.95 V

R

Output Current VO = 4 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 35 mA

Short-Circuit Current 75 mA

Capacitive Load Drive 30% Overshoot G = +1 5 pF POWER SUPPLY

Operating Range 5 24 V

Quiescent Current per Amplifier 5.8 6.4 7.0 mA

Power Supply Rejection Ratio ±PSRR −78 −100 dB

= 5 MHz, G = +2, VO = 2 V p-p −50 dBc

C

= 1.0 V, SOIC Package 0.4 1.5 mV

CM

to T

MIN

= 1 V to 4 V (AD8066) 90 103 dB

O

CM

= 150 Ω 0.07 to 4.83 V

L

25 pA

MAX

to T

1 pA

MAX

= 1 V to 2 V (SOT-23) −78 −91 dB

Rev. E | Page 5 of 28

AD8065/AD8066

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage 26.4 V Power Dissipation See Figure 3 Common-Mode Input Voltage VEE − 0.5 V to VCC + 0.5 V Differential Input Voltage 1.8 V Storage Temperature −65°C to +125°C Operating Temperature Range −40°C to +85°C Lead Temperature Range

(Soldering, 10 sec)

300°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. E | Page 6 of 28

AD8065/AD8066

(

)

(

)

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8065/AD8066 packages is limited by the associated rise in junction temperature (T

) on the die. The plastic encapsulating the die

J

will locally reach the junction temperature. At approximately 150°C, which is the glass transition temperature, the plastic will change its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8065/AD8066. Exceeding a junction temperature of 175°C for an extended period of time can result in changes in the silicon devices, potentially causing failure.

2.0

1.5 MSOP-8

SOIC-8

1.0

SOT-23-5

0.5

MAXIMUM POWER DISSIPATION (W)

The still-air thermal properties of the package and PCB (θ ambient temperature (T package (P

) determine the junction temperature of the die. The

D

), and total power dissipated in the

A

JA

junction temperature can be calculated as

PTT θ×+=

J

The power dissipated in the package (

D

A

JA

P

) is the sum of the

D

quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent

V

power is the voltage between the supply pins ( quiescent current (I midsupply, then the total drive power is

). Assuming the load (RL) is referenced to

S

VS /2 × I

) times the

S

, some of

OUT

which is dissipated in the package and some in the load (V

I

). The difference between the total drive power and the load

OUT

power is the drive power dissipated in the package.

PowerLoadPowerDriveTotalPowerQuiescentP

D

⎛

()

D

IVP

S

⎜

SS

2

⎝

VV

×+×=

OUT

R

V

OUT

⎞

−

⎟

R

L

⎠

RMS output voltages should be considered. If

V

−, as in single-supply operation, then the total drive power is

S

V

× I

.

S

OUT

−+=

2

R

is referenced to

L

OUT

),

0

AMBIENT TEMPERATURE (°C)

Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

200–40 –20–60 40 60 80 100

02916-E-003

Airflow will increase heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes will reduce the θ

. Care must be taken to minimize parasitic

JA

capacitances at the input leads of high speed op amps as discussed in the Layout, Grounding, and Bypassing Considerations section.

Figure 3 shows the maximum safe power dissipation in the

×

package versus the ambient temperature for the SOIC (125°C/W), SOT-23 (180°C/W), and MSOP (150°C/W) packages on a JEDEC standard 4-layer board. θ

values are

JA

approximations.

OUTPUT SHORT CIRCUIT

Shorting the output to ground or drawing excessive current for the AD8065/AD8066 will likely cause catastrophic failure.

If the rms signal levels are indeterminate, then consider the

V

worst case, when

()

D

In single-supply operation with R is V

= VS/2.

OUT

= VS/4 for RL to midsupply.

OUT

2

()

4/

V

S

+×=

IVP

SS

R

L

referenced to VS−, worst case

L

Rev. E | Page 7 of 28

AD8065/AD8066

TYPICAL PERFORMANCE CHARACTERISTICS

Default Conditions: ±5 V, CL = 5 pF, RL = 1 kΩ, V

24

21

G = +10

18

G = +5

15

12

9

G = +2

GAIN (dB)

6

3

G = +1

0

–3

–6

10.1 10 100 1000 FREQUENCY (MHz)

Figure 4. Small Signal Frequency Response for Various Gains

6

VO = 200mV p-p G = +1

4

2

0

GAIN (dB)

–2

V

S

V

S

= ±12V

= +5V

= 200mV p-p

V

O

= 2 V p-p, Temperature = 25°C.

OUT

02916-E-004

V

= ±5V

S

6.9 RL = 150Ω

6.8

G = +2

6.7

6.6

6.5

6.4

GAIN (dB)

6.3

6.2

6.1

6.0

5.9

0.1 101 100

V

= 0.2V p-p

OUT

V

= 0.7V p-p

OUT

V

= 1.4V p-p

OUT

FREQUENCY (MHz)

Figure 7. 0.1 dB Flatness Frequency Response (See Figure 43)

9

VO = 200mV p-p G = +2

8

7

6

GAIN (dB)

5

VS = +5V

V

= ±12V

S

V

= ±5V

S

02916-E-007

–4

–6

10.1 10 100 1000 FREQUENCY (MHz)

Figure 5. Small Signal Frequency Response for Various Supplies (See Figure 42)

2

VO = 2V p-p G = +1

1

0

–1

V

–2

GAIN (dB)

–3

–4

–5

10.1 10 100 1000

= ±12V

S

FREQUENCY (MHz)

V

= ±5V

S

Figure 6. Large Signal Frequency Response for Various Supplies (See Figure 42)

4

3

02916-E-005

10.1 10 100 1000 FREQUENCY (MHz)

02916-E-008

Figure 8. Small Signal Frequency Response for Various Supplies (See Figure 43)

8

G = +2

7

6

5

4

GAIN (dB)

3

2

1

0

02916-E-006

VS = +5V

V

= ±12V

S

10.1 10 100 1000 FREQUENCY (MHz)

V

= ±5V

S

02916-E-009

Figure 9. Large Signal Frequency Response for Various Supplies (See Figure 43)

Rev. E | Page 8 of 28

AD8065/AD8066

9

VO = 200mV p-p G = +1

6

3

C

= 25pF

L

CL = 20pF

C R

= 25pF

L SNUB

= 20

Ω

8

6

4

2

C

= 5pF

L

= 55pF

C

L

CL = 25pF

0

GAIN (dB)

–3

–6

–9

10.1 10 100 1000 FREQUENCY (MHz)

Figure 10. Small Signal Frequency Response for Various C

8

6

G = +2

4

2

0

GAIN (dB)

–2

–4

–6

–8

V

OUT

V

OUT

10.1 10 100 1000 FREQUENCY (MHz)

= 2V p-p

= 4V p-p

C

= 5pF

L

V

OUT

LOAD

= 0.2V p-p

(See Figure 42)

Figure 11. Frequency Response for Various Output Amplitudes (See Figure 43)

14

VO = 200mV p-p

12

G = +2

R

10

8

6

4

GAIN (dB)

2

0

–2

–4

R

= RG = 1kΩ,

F

= 500Ω,

R

S

= 3.3pF

C

F

10.1 10 100 1000 FREQUENCY (MHz)

Figure 12. Small Signal Frequency Response for Various R

= RG = 1kΩ,

F

= 500

Ω

R

S

RF = RG = 500Ω, R

= 250

Ω

S

RF = RG = 500Ω,

= 250Ω,

R

S

C

= 2.2pF

F

(See Figure 43)

F/CF

0

GAIN (dB)

–2

–4

VO = 200mV p-p

–6

G = +2

–8

02916-E-010

Figure 13. Small Signal Frequency Response for Various C

8

7

6

5

4

GAIN (dB)

3

2

VO = 200mV p-p

1

G = +2

0

02916-E-011

Figure 14. Small Signal Frequency Response for Various R

80

60

40

20

OPEN-LOOP GAIN (dB)

0

–20

0.01 0.1 1 10 100 1000

02916-E-012

10.1 10 100 1000 FREQUENCY (MHz)

(See Figure 43)

LOAD

RL = 100

Ω

RL = 1k

Ω

10.1 10 100 1000 FREQUENCY (MHz)

(See Figure 43)

LOAD

PHASE

GAIN

FREQUENCY (MHz)

120

60

0

–60

–120

–180

02916-E-013

02916-E-014

PHASE (DEGREES)

02916-E-015

Figure 15. Open-Loop Response

Rev. E | Page 9 of 28

AD8065/AD8066

–30

–40

G = +2

–50

–60

–70

–80

–90

DISTORTION (dBc)

–100

–110

–120

0.1 101 100

Figure 16. Harmonic Distortion vs. Frequency for Various Loads (See Figure 43)

–30

–40

G = +2 V

S

F = 1MHz

–50

–60

–70

–80

–90

DISTORTION (dBc)

–100

–110

–120

01234 6 105 789 1211 1413 15

Figure 17. Harmonic Distortion vs. Amplitude for Various Loads V

50

45

HD2 RL = 1k

= ±12V

HD3 RL = 150

VS = ±12V

HD2 RL = 150

HD3 RL = 300

OUTPUT AMPLITUDE (V p-p)

Ω

FREQUENCY (MHz)

HD2 RL = 150

Ω

HD3 RL = 1k

HD3 RL = 150

Ω

(See Figure 43)

Ω

HD2 RL = 300

RL = 100

Ω

S

Ω

= ±12 V

–40

–50

–60

–70

–80

DISTORTION (dBc)

–90

–100

–110

0.1 101 100

02916-E-016

HD2 G = +1

FREQUENCY (MHz)

HD2 G = +2

HD3 G = +1

HD3 G = +2

02916-E-019

Figure 19. Harmonic Distortion vs. Frequency for Various Gains

(See Figure 42 and Figure 43)

–20

VS = ±12V

–30

G = +2

–40

–50

–60

–70

–80

DISTORTION (dBc)

–90

–100

–110

–120

0.1 1.0 10.0

02916-E-017

HD2 VO = 10V p-p

HD3 VO = 10V p-p

HD2 VO = 20V p-p

HD3 VO = 20V p-p

FREQUENCY (MHz)

HD2 VO = 2V p-p

HD3 VO = 2V p-p

02916-E-020

Figure 20. Harmonic Distortion vs. Frequency for Various Amplitudes

(See Figure 42 and Figure 43)

100

40

VS = ±5V

35

30

25

INTERCEPT POINT (dBm)

20

15

VS = +5V

110

FREQUENCY (MHz)

02916-E-018

Figure 18. Third-Order Intercept vs. Frequency and Supply Voltage

Rev. E | Page 10 of 28

10

NOISE (nV/ Hz)

1

100k10k100 1k10 1M 10M 100M 1G

FREQUENCY (Hz)

02916-E-021

Figure 21. Voltage Noise

AD8065/AD8066

G = +1

CL = 5pF

CL = 20pF

G = +1

50mV/DIV

20ns/DIV

Figure 22. Small Signal Transient Response 5 V Supply (See Figure 52)

G = +1 VS = ±12V

V

= 10V p-p

OUT

V

= 4V p-p

OUT

V

= 2V p-p

OUT

2V/DIV

80ns/DIV

Figure 23. Large Signal Transient Response (See Figure 42)

G = –1 V

= ±5V

S

–IN

OUT

50mV/DIV

02916-E-022

20ns/DIV

02916-E-025

Figure 25. Small Signal Transient Response ±5 V (See Figure 42)

G = +2

5µs

V

= 10V p-p

OUT

V

= 2V p-p

OUT

2V/DIV

02916-E-023

VS = ±12V

80ns/DIV

02916-E-026

Figure 26. Large Signal Transient Response (See Figure 43)

IN

OUT

G = +1

= ±5V

V

S

1.5V/DIV

100ns/DIV

Figure 24. Output Overdrive Recovery (See Figure 44)

02916-E-024

Rev. E | Page 11 of 28

1.5V/DIV

100ns/DIV

Figure 27. Input Overdrive Recovery (See Figure 42)

02916-E-027

AD8065/AD8066

+0.1%

–0.1%

t = 0

2mV/DIV

Figure 28. Long-Term Settling Time (See Figure 49)

0

–5

–10

–15

–20

INPUT BIAS CURRENT (pA)

–25

–30

Figure 29. Input Bias Current vs. Temperature

0.3

0.2

0.1

0

–0.1

OFFSET VOLTAGE (mV)

–0.2

VIN = 140mV/DIV

V

– 2V

OUT

IN

64µs/DIV

–I

b

+I

b

45 5525 35 65 75 85

TEMPERATURE (°C)

VS = +5V

VS = ±5V

VS = ±12V

VIN= 500mV/DIV

+0.1%

2mV/DIV

t = 0

V

OUT

10ns/DIV

– 2V

IN

02916-E-031

–0.1%

02916-E-028

Figure 31. 0.1% Short-Term Settling Time (See Figure 49)

42 36 30 24

A)

µ

(

18

b

I

12

6 0

10

–I

5

b

0

–5

–10

(pA)

b

I

–15 –20 –25

–30

–12 8–2–100–8 2–6 4–4

02916-E-029

+I

b

COMMON-MODEVOLTAGE (V)

+I

b

–I

b

FET INPUT STAGE BJT INPUT STAGE

10 12

6

02916-E-032

Figure 32. Input Bias Current vs. Common-Mode Voltage Range

(see the Input and Output Overload Behavior section)

40

35

30

25

20

15

10

5

N = 299 SD = 0.388 MEAN = –0.069

–0.3

–14 –10–12 –8–6–4 0 8–2 2 4 6 10 12 14

COMMON-MODE VOLTAGE (V)

Figure 30. Input Offset Voltage vs. Common-Mode Voltage

02916-E-030

Rev. E | Page 12 of 28

0 –2.0 2.0–1.5 –1.0 –0.5 0 0.5 1.0 1.5

INPUT OFFSET VOLTAGE (mV)

Figure 33. Input Offset Voltage

02916-E-033

AD8065/AD8066

–30

100

–40

–50

–60

–70

CMRR (dB)

VS = ±12V

–80

–90

–100

0.1 101 100

VS = ±5V

FREQUENCY (MHz)

Figure 34. CMRR v s. Frequen cy (See Fi gure 46)

0.30

0.25 VCC– V

OH

0.20

0.15

0.10

VOL– V

0.05

OUTPUT SATURATION VOLTAGE (V)

0

100203040

EE

I

LOAD

(mA)

Figure 35. Output Saturation Voltage vs. Output Load Current

0

–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

0.01 0.1 1 10 100 1000

–PSRR

+PSRR

FREQUENCY (MHz)

Figure 36. PSRR vs. Frequency (See Figure 48 and Figure 50)

10

)

Ω

1

0.1

OUTPUT IMPEDANCE (

0.01

0

02916-E-034

10k 100k100 1k 1M 10M 100M

FREQUENCY (Hz)

G = +2

G = +1

02916-E-037

Figure 37. Output Impedance vs. Frequency (See Figure 45 and Figure 47)

80

70

VCC– V

OH

60

50

40

OUTPUT SATURATION VOLTAGE (mV)

30

02916-E-035

45 5525 35 65 75 85

TEMPERATURE (°C)

VOL– V

EE

02916-E-038

Figure 38. Output Saturation Voltage vs. Temperature

0

VIN = 2V p-p

–10

G = +1

–20

–30

–40

–50

CROSSTALK (dB)

–60

–70

–80

–90

0.1 101 100

02916-E-036

B TO A

FREQUENCY (MHz)

A TO B

02916-E-039

Figure 39. Crosstalk vs. Frequency (See Figure 51)

Rev. E | Page 13 of 28

AD8065/AD8066

6.60

6.55

6.50

6.45

6.40

6.35

SUPPLY CURRENT (mA)

6.30

6.25

VS = ±5V

VS = +5V

020–40 –20 40 60 80

TEMPERATURE (°C)

Figure 40. Quiescent Supply Current vs. Temperature for Various Supply Voltages

VS = ±12V

125

120

115

110

105

100

95

OPEN-LOOP GAIN (dB)

90

85

80

02916-E-040

VS = +5V

VS = ±5V

100203040

I

LOAD

VS = ±12V

(mA)

02916-E-041

Figure 41. Open-Loop Gain vs. Load Current for Various Supply Voltages

Rev. E | Page 14 of 28

AD8065/AD8066

TEST CIRCUITS

SOIC-8 Pinout

+V

CC

4.7µF

+V

CC

4.7µF

0.1µF

24.9Ω

V

IN

49.9Ω

SNUB

1kΩ

FET PROBE

C

LOAD

02916-E-042

AD8065

R

V

IN

49.9Ω

–V

0.1µF

4.7µF

EE

499Ω 499Ω

Figure 42. G = +1

+V

CC

4.7µF

2.2pF

249Ω

Figure 44. G = −1

+V

CC

AD8065

–V

4.7µF

0.1µF

FET PROBE

0.1µF

4.7µF

EE

1kΩ

02916-E-044

499Ω 499Ω

V

IN

49.9Ω

249Ω

2.2pF

AD8065

–V

Figure 43. G = +2

0.1µF

24.9Ω

R

FET PROBE

SNUB

AD8065

0.1µF

4.7µF

EE

1kΩ

C

LOAD

02916-E-043

–V

0.1µF

NETWORK ANALYZER S22

0.1µF

4.7µF

EE

02916-E-045

Figure 45. Output Impedance G = +1

Rev. E | Page 15 of 28

AD8065/AD8066

499Ω 499Ω

V

IN

49.9Ω 499Ω

499Ω

+V

CC

AD8065

4.7µF

0.1µF

FET PROBE

1kΩ

24.9Ω

AD8065

49.9Ω

0.1µF

V

IN

1V p-p

+V

CC

FET PROBE

1kΩ

499Ω 499Ω

249Ω

–V

Figure 46. CMRR

+V

CC

AD8065

4.7µF

EE

4.7µF

0.1µF

NETWORK ANALYZER

0.1µF

4.7µF

S22

4.7µF

–V

02916-E-046

EE

02916-E-048

Figure 48. Positive PSRR

+V

CC

4.7µF

0.1µF

2.2pF

249Ω

499Ω

AD8065

0.1µF

4.7µF

976Ω

TO SCOPE

49.9Ω

499Ω

V

IN

49.9Ω

–V

EE

Figure 47. Output Impedance G = +2

02916-E-047

Rev. E | Page 16 of 28

–V

EE

Figure 49. Settling Time

02916-E-049

AD8065/AD8066

V

+V

CC

4.7µF

2.2pF

24.9Ω

V

IN

1V p-p

24.9Ω

0.1µF

AD8065

49.9Ω

–V

EE

Figure 50. Negative PSRR

1kΩ

FET PROBE

499Ω

1.5V

V

IN

02916-E-050

249Ω

49.9Ω

1.5V

499Ω

5V

AD8065

4.7µF

0.1µF

FET PROBE

1kΩ

1.5V

02916-E-052

Figure 52. Single Supply

24.9Ω

FET PROBE

AD8066

+5V

4.7µF

0.1µF

RECEIVE SIDE

1kΩ

AD8066

IN

49.9Ω

DRIVE SIDE

–5V

0.1µF

4.7µF

1kΩ

02916-E-051

Figure 51. Crosstalk—AD8066

Rev. E | Page 17 of 28

AD8065/AD8066

(

)

×

π

+

×π−

THEORY OF OPERATION

The AD8065/AD8066 are voltage feedback operational amplifiers that combine a laser-trimmed JFET input stage with the Analog Devices eXtra Fast Complementary Bipolar (XFCB) process, resulting in an outstanding combination of precision and speed. The supply voltage range is from 5 V to 24 V. The amplifiers feature a patented rail-to-rail output stage capable of driving within 0.5 V of either power supply while sourcing or sinking up to 30 mA. Also featured is a single-supply input stage that handles common-mode signals from below the negative supply to within 3 V of the positive rail. Operation beyond the JFET input range is possible because of an auxiliary bipolar input stage that functions with input voltages up to the positive supply. The amplifiers operate as if they have a rail-to-rail input and exhibit no phase reversal behavior for common-mode voltages within the power supply.

With voltage noise of 7 nV/√Hz and −88 dBc distortion for 1 MHz 2 V p-p signals, the AD8065/AD8066 are a great choice for high resolution data acquisition systems. Their low noise, sub-pA input current, precision offset, and high speed make them superb preamps for fast photodiode applications. The speed and output drive capability of the AD8065/AD8066 also make them useful in video applications.

CLOSED-LOOP FREQUENCY RESPONSE

The AD8065/AD8066 are classic voltage feedback amplifiers with an open-loop frequency response that can be approximated as the integrator response shown in Figure 53. Basic closed-loop frequency response for inverting and noninverting configurations can be derived from the schematics shown.

R

F

NONINVERTING CLOSED-LOOP FREQUENCY RESPONSE

Solving for the transfer function

where f

V V

O

I

crossover

2

=

()

crossover

F

2

G

is the frequency where the amplifier’s open-loop

+

G

crossover

RRf

F

RfsRR

××π++

G

gain equals 0 db

At dc

V

O

V

I

RR

F

=

G

R

G

Closed-loop −3 dB frequency

R

ff

crossover

−

3dB

G

×=

+

RR

F

G

INVERTING CLOSED-LOOP FREQUENCY RESPONSE

Rf

crossover

2

R

G

+

F

RR

×

crossover

G

F

RfRRs

××π++

G

2

()

F

G

R

F

−=

R

G

At dc

V

O

=

V

I

V

O

V

I

Closed-loop −3 dB frequency

ff

×=

crossover

−

3dB

R

F

R

G

A

V

E

V

I

80

60

40

OPEN-LOOP GAIN (A) (dB)

20

0

0.01 100

Figure 53. Open-Loop Gain vs. Frequency and Basic Connections

V

O

A = (2π×

0.1 101 FREQUENCY (MHz)

Rev. E | Page 18 of 28

f

crossover

)/s

R

V

G

I

V

A

E

f

crossover

= 65MHz

V

O

02916-E-053

AD8065/AD8066

The closed-loop bandwidth is inversely proportional to the noise gain of the op amp circuit, (

R

+ RG )/RG. This simple

F

model is accurate for noise gains above 2. The actual bandwidth of circuits with noise gains at or below 2 will be higher than those predicted with this model due to the influence of other poles in the frequency response of the real op amp.

R

F

R

G

V

I

+VOS–

I

A

b

R

S

Figure 54. Voltage Feedback Amplifier DC Errors

–

I

b

+

V

O

02916-E-054

Figure 54 shows a voltage feedback amplifier’s dc errors. For both inverting and noninverting configurations

()

O

RIerrorV

×=

b

The voltage error due to

RR

+

⎛ ⎜

S

⎝

I

and Ib– is minimized if RS = R

b+

⎞

F

G

⎟

R

G

⎠

+×−

F

b

−+

VRI

OS

RR

+

⎛ ⎜

⎝

⎞

F

G

⎟

R

G

⎠

|| R

F

G

(though with the AD8065 input currents at less than 20 pA over temperature, this is likely not a concern). To include common-

V

mode and power supply rejection effects, total

can be

OS

modeled as

nom

V

PSR

VV

OSOS

V

is the offset voltage specified at nominal conditions,

OS

nom

∆V

is the change in power supply from nominal conditions,

S

PSR is the power supply rejection, ∆V

common-mode voltage from nominal conditions, and

CMS

++=

CMR

is the change in

CM

CMR

ΔΔ

V

is the common-mode rejection.

WIDEBAND OPERATION

Figure 42 through Figure 44 show the circuits used for wideband characterization for gains of +1, +2, and −1. Source impedance at the summing junction ( in the amplifier’s loop response with the amplifier’s input capacitance of 6.6 pF. This can cause peaking and ringing if the time constant formed is too low. Feedback resistances of 300 Ω to 1 kΩ are recommended, since they will not unduly load down the amplifier and the time constant formed will not be too low. Peaking in the frequency response can be compensated for with a small capacitor (C

) in parallel with the feedback

F

resistor, as illustrated in Figure 12. This shows the effect of different feedback capacitances on the peaking and bandwidth for a noninverting G = +2 amplifier.

R

|| RG) will form a pole

F

For the best settling times and the best distortion, the impedances at the AD8065/AD8066 input terminals should be matched. This minimizes nonlinear common-mode capacitive effects that can degrade ac performance.

Actual distortion performance depends on a number of variables:

• The closed-loop gain of the application

• Whether it is inverting or noninverting

• Amplifier loading

• Signal frequency and amplitude

• Board layout

Also see Figure 16 to Figure 20. The lowest distortion will be obtained with the AD8065 used in low gain inverting applications, since this eliminates common-mode effects. Higher closed-loop gains result in worse distortion performance.

INPUT PROTECTION

The inputs of the AD8065/AD8066 are protected with back-toback diodes between the input terminals as well as ESD diodes to either power supply. This results in an input stage with picoamps of input current that can withstand up to 1500 V ESD events (human body model) with no degradation.

Excessive power dissipation through the protection devices will destroy or degrade the performance of the amplifier. Differential voltages greater than 0.7 V will result in an input current of approximately (| in series with the inputs. For input voltages beyond the positive supply, the input current will be approximately (

0.7)/

R

. Beyond the negative supply, the input current will be

I

about (

V

− VEE + 0.7)/RI. If the inputs of the amplifier are to be

I

subjected to sustained differential voltages greater than 0.7 V or to input voltages beyond the amplifier power supply, input current should be limited to 30 mA by an appropriately sized input resistor (

(| V+–V

RI>

FOR LARGE | V

V

I

V

− V−| 0.7 V)/RI, where RI is the resistance

+

R

) as shown in Figure 55.

I

| – 0.7V)

–

30mA

|

+–V–

AD8065

R

I

Figure 55. Current Limiting Resistor

V

(V

I–VEE

>

R

I

30mA

(V

I–VEE

R

>

I

30mA FOR V SUPPLY VOLTAGES

V

O

− VCC −

I

– 0.7V)

+ 0.7V)

BEYOND

I

02916-E-055

Rev. E | Page 19 of 28

AD8065/AD8066

THERMAL CONSIDERATIONS

With 24 V power supplies and 6.5 mA quiescent current, the AD8065 dissipates 156 mW with no load. The AD8066 dissipates 312 mW. This can lead to noticeable thermal effects, especially in the small SOT-23-5 (thermal resistance of 160°C/W). V maximum drift of 17 µV/°C, so it can change up to 0.425 mV due to warm-up effects for an AD8065/AD8066 in a SOT-23-5 package on 24 V.

I

increases by a factor of 1.7 for every 10°C rise in temperature.

b

I

will be close to 5 times higher at 24 V supplies as opposed to a

b

single 5 V supply.

Heavy loads will increase power dissipation and raise the chip junction temperature as described in the Maximum Power Dissipation section. Care should be taken to not exceed the rated power dissipation of the package.

INPUT AND OUTPUT OVERLOAD BEHAVIOR

The AD8065/AD8066 have internal circuitry to guard against phase reversal due to overdriving the input stage. A simplified schematic of the input stage, including the input-protection diodes and antiphase reversal circuitry, is shown in Figure 56.

temperature drift is trimmed to guarantee a

OS

The circuit is arranged such that when the input commonmode voltage exceeds a certain threshold, the input JFET pair’s bias current will turn OFF, and the bias current of an auxiliary NPN pair will turn ON, taking over control of the amplifier. When the input common-mode voltage returns to a viable operating value, the FET stage turns back ON, the NPN stage turns OFF, and normal operation resumes.

The NPN pair can sustain operation with the input voltage up to the positive supply, so this is a pseudo rail-to-rail input stage. For operation beyond the FET stage’s common-mode limit, the amplifier’s V 160 µV, standard deviation of 820 µV), and I

will change to the NPN pair’s offset (mean of

OS

will increase to the

b

NPN pair’s base current up to 45 µA (see Figure 32).

Switchback, or recovery time, is about 100 ns, see Figure 27.

The output transistors of the rail-to-rail output stage have circuitry to limit the extent of their saturation when the output is overdriven. This helps output recovery time. Output recovery from a 0.5 V output overdrive on a ±5 V supply is shown in Figure 24.

Rev. E | Page 20 of 28

AD8065/AD8066

LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS

POWER SUPPLY BYPASSING

Power supply pins are actually inputs and care must be taken so that a noise-free stable dc voltage is applied. The purpose of bypass capacitors is to create low impedances from the supply to ground at all frequencies, thereby shunting or filtering most of the noise.

Decoupling schemes are designed to minimize the bypassing impedance at all frequencies with a parallel combination of capacitors. 0.1 µF (X7R or NPO) chip capacitors are critical and should be as close as possible to the amplifier package. The 4.7 µF tantalum capacitor is less critical for high frequency bypassing, and, in most cases, only one is needed per board, at the supply inputs.

R1

GROUNDING

A ground plane layer is important in densely packed PC boards to spread the current minimizing parasitic inductances. However, an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design. The length of the current path is directly proportional to the magnitude of parasitic inductances and therefore the high frequency impedance of the path. High speed currents in an inductive ground return will create an unwanted voltage noise.

V

CC

R5

TO REST OF AMP

V

THRESHOLD

V

N

Q2 Q5

D1

R6

R3

Q1 Q6

D3 D4

S

R2 R8

I

Figure 56. Simplified Input Stage

D2

Q4

Q3

R4

T1

R7

I

T2

S

–V

VBIAS

V

P

Q7

EE

02916-E-056

Rev. E | Page 21 of 28

AD8065/AD8066

V

The length of the high frequency bypass capacitor leads is most critical. A parasitic inductance in the bypass grounding will work against the low impedance created by the bypass capacitor. Place the ground leads of the bypass capacitors at the same physical location. Because load currents flow from the supplies as well, the ground for the load impedance should be at the same physical location as the bypass capacitor grounds. For the larger value capacitors, which are effective at lower frequencies, the current return path distance is less critical.

LEAKAGE CURRENTS

Poor PC board layout, contaminants, and the board insulator material can create leakage currents that are much larger than the input bias current of the AD8065/AD8066. Any voltage differential between the inputs and nearby runs will set up leakage currents through the PC board insulator, for example, 1 V/100 GΩ = 10 pA. Similarly, any contaminants on the board can create significant leakage (skin oils are a common problem). To significantly reduce leakage, put a guard ring (shield) around the inputs and input leads that are driven to the same voltage potential as the inputs. This way there is no voltage potential between the inputs and surrounding area to set up any leakage currents. For the guard ring to be completely effective, it must be driven by a relatively low impedance source and should completely surround the input leads on all sides, above and below, using a multilayer board.

INPUT CAPACITANCE

Along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. A few pF of capacitance will reduce the input impedance at high frequencies, in turn increasing the amplifier’s gain, causing peaking of the frequency response or even oscillations, if severe enough. It is recommended that the external passive components connected to the input pins be placed as close as possible to the inputs to avoid parasitic capacitance. The ground and power planes must be kept at a small distance from the input pins on all layers of the board.

OUTPUT CAPACITANCE

To a lesser extent, parasitic capacitances on the output can cause peaking and ringing of the frequency response. There are two methods to effectively minimize their effect.

• As shown in Figure 57, put a small value resistor (R

series with the output to isolate the load capacitor from the amp’s output stage. A good value to choose is 20 Ω (see Figure 10).

• Increase the phase margin with higher noise gains or add a

pole with a parallel resistor and capacitor from −IN to the output.

) in

S

Another effect that can cause leakage currents is the charge absorption of the insulator material itself. Minimizing the amount of material between the input leads and the guard ring will help to reduce the absorption. Also, low absorption materials, such as Teflon® or ceramic, could be necessary in some instances.

I

PHOTO

C

S

V

B

RSH= 1011Ω

CF+C

Figure 58. Wideband Photodiode Preamp

AD8065

I

Figure 57. Output Isolation Resistor

RS= 20Ω

V

O

C

L

02916-E-057

C

F

R

F

C

M

C

D

C

M

S

R

F

V

O

02916-E-058

Rev. E | Page 22 of 28

AD8065/AD8066

INPUT-TO-OUTPUT COUPLING

In order to minimize capacitive coupling between the inputs and output, the output signal traces should not be parallel with the inputs.

The preamp’s output noise over frequency is shown in Figure 59.

f

=

1

2πRF(CF+CS+CM+2CD)

1

WIDEBAND PHOTODIODE PREAMP

Figure 58 shows an I/V converter with an electrical model of a photodiode. The basic transfer function is where

×

RI

PHOTO

=

V

where

OUT

I

+

1

is the output current of the photodiode, and the

PHOTO

parallel combination of

The stable bandwidth attainable with this preamp is a function of

R

, the gain bandwidth product of the amplifier, and the total

F

capacitance at the amplifier’s summing junction, including and the amplifier input capacitance. produce a pole in the amplifier’s loop transmission that can result in peaking and instability. Adding loop transmission, which compensates for the pole’s effect and reduces the signal bandwidth. It can be shown that the signal bandwidth resulting in a 45° phase margin ( the expression

f

()

45

where f resistor, and C

is the amplifier crossover frequency, RF is the feedback

CR

is the total capacitance at the amplifier summing

S

junction (amplifier + photodiode + board parasitics).

The value of C

C

F

that produces f

F

The frequency response in this case will show about 2 dB of peaking and 15% overshoot. Doubling C bandwidth in half will result in a flat frequency response, with about 5% transient overshoot.

Table 5. RMS Noise Contributions of Photodiode Preamp

Contributor Expression

RF (×2)

Amp to f1

Amp (f2 – f1)

Amp to (past f2)

F

RsC

FF

R

and CF set the signal bandwidth.

F

C

S

R

and the total capacitance

F

C

creates a 0 in the

F

f

) is defined by

(45)

f

CR

××π=2

F

S

can be shown to be

(45)

C

S

fR

××π=2

CRF

and cutting the

F

57142 .fRkT

××××

2

F

fVEN ×

1

+++

2

CCCC

VEN

S

×

C

F

S

C

F

DFM

+++

2

CCCC

FDM

1

f

=

2

2πRFC

F

f

=

3

RF NOISE

VOLTAGE NOISE (nV/ Hz)

f

1

VEN

f

2

NOISE DUE TO AMPLIFIER

Figure 59. Photodiode Voltage Noise Contributions

CR

(CS+CM+2CD+CF)/C

VEN (CF+CS+CM+ 2CD)/C

FREQUENCY (Hz)

F

f

3

F

02916-E-059

The pole in the loop transmission translates to a 0 in the amplifier’s noise gain, leading to an amplification of the input voltage noise over frequency. The loop transmission 0 introduced by C

limits the amplification. The noise gain

F

bandwidth extends past the preamp signal bandwidth and is eventually rolled off by the decreasing loop gain of the amplifier. Keeping the input terminal impedances matched is recommended to eliminate common-mode noise peaking effects, which will add to the output noise.

Integrating the square of the output voltage noise spectral density over frequency and then taking the square root allows users to obtain the total rms output noise of the preamp. Table 5 summarizes approximations for the amplifier and feedback and source resistances. Noise components for an example preamp

= 50 kΩ, CS = 15 pF, and CF = 2 pF (bandwidth of about

with R

F

1.6 MHz) are also listed.

RMS Noise with R C

= 15 pF, CS = 15 pF

S

= 50 kΩ,

F

64.5 µV

2.4 µV

31 µV

ff

−×

12

260 µV

57.1

××

f

3

270 µV (Total)

Rev. E | Page 23 of 28

AD8065/AD8066

()(

)

V

CC

4.7µF

1

/

2

AD8066

RF = 500Ω

1

/

2

AD8066

0.1µF

V

EE

RF = 500Ω

V

CC

0.1µ F

V

EE

R

S1

V

N

R

G

R

S2

V

P

Figure 60. High Speed Instrumentation Amplifier

HIGH SPEED JFET INPUT INSTRUMENTATION AMPLIFIER

Figure 60 shows an example of a high speed instrumentation amplifier with high input impedance using the AD8065/AD8066. The dc transfer function is

10001

+

()

OUT

⎛

VVV

−=

⎜

PN

⎝

For G = +1, it is recommended that the feedback resistors for the two preamps be set to a low value (for instance 50 Ω for 50 Ω source impedance). The bandwidth for G = +1 will be 50 MHz. For higher gains, the bandwidth will be set by the preamp, equaling

3dB

−

Common-mode rejection of the inamp will be primarily determined by the match of the resistor ratios R1:R2 to R3:R4. It can be estimated

⎞ ⎟

R

G

⎠

RRfInamp ××=

2/

GCR

F

2.2pF

R2

500Ω

V

CC

4.7µF

4.7µ F

V

O

02916-E-060

500Ω

AD8065

2.2pF

0.1µF

0.1µ F

V

EE

R1

R3

R4

500Ω

R

|| 0.5(RG). This is the value to be used for matching purposes.

F

VIDEO BUFFER

The output current capability and speed of the AD8065 make it useful as a video buffer, shown in Figure 61.

The G = +2 configuration compensates for the voltage division of the signal due to the signal termination. This buffer maintains 0.1 dB flatness for signals up to 7 MHz, from low amplitudes up to 2 V p-p (Figure 7). Differential gain and phase have been measured to be 0.02% and 0.028° at ±5 V supplies.

+V

S

4.7µ F

75Ω

AD8065

–V

S

0.1µ F

2.2pF

249Ω

+ V

I

–

+

V

O

–

()

δ−δ

V

O

=

V

CM

The summing junction impedance for the preamps is equal to

21

()

211

δδ+

499Ω

Figure 61. Video Buffer

02916-E-061

Rev. E | Page 24 of 28

AD8065/AD8066

Y

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARIT

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

85

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

BSC

6.20 (0.2440)

5.80 (0.2284)

41

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

Figure 62. 8-Lead Standard Small Outline Package Narrow Body [SOIC]

(R-8)

Dimensions shown in millimeters (inches)

× 45°

3.00

BSC

85

3.00 BSC

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10 COMPLIANT TO JEDEC STANDARDS MO-187AA

BSC

4

SEATING PLANE

4.90

1.10 MAX

0.23

0.08

8° 0°

0.80

0.60

0.40

Figure 64. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

1.60 BSC

1.30

1.15

0.90

0.15MAX

2.90 BSC

4 5

2.80 BSC

1

PIN 1

COMPLIANT TO JEDEC STANDARDS MO-178AA

1.90

BSC

3

2

0.95 BSC

0.50

0.30

1.45 MAX

SEATING PLANE

0.22

0.08 10°

5° 0°

Figure 63. 5-Lead Small Outline Transistor Package [SOT-23]

(RT-5)

Dimensions shown in millimeters

0.60

0.45

0.30

Rev. E | Page 25 of 28

AD8065/AD8066

ORDERING GUIDE

Model Temperature Range Package Description Package Outline Branding

AD8065AR −40°C to +85°C 8-Lead SOIC R-8 AD8065AR-REEL −40°C to +85°C 8-Lead SOIC R-8 AD8065AR-REEL7 −40°C to +85°C 8-Lead SOIC R-8 AD8065ART-REEL −40°C to +85°C 5-Lead SOT-23 RT-5 HRA AD8065ART-R2 −40°C to +85°C 5-Lead SOT-23 RT-5 HRA AD8065ART-REEL7 −40°C to +85°C 5-Lead SOT-23 RT-5 HRA AD8066AR −40°C to +85°C 8-Lead SOIC R-8 AD8066AR-REEL −40°C to +85°C 8-Lead SOIC R-8 AD8066AR-REEL7 −40°C to +85°C 8-Lead SOIC R-8 AD8066ARZ1 −40°C to +85°C 8-Lead SOIC R-8 AD8066ARZ-REEL1 −40°C to +85°C 8-Lead SOIC R-8 AD8066ARZ-REEL71 −40°C to +85°C 8-Lead SOIC R-8 AD8066ARM −40°C to +85°C 8-Lead MSOP RM-8 HIB AD8066ARM-REEL −40°C to +85°C 8-Lead MSOP RM-8 HIB AD8066ARM-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 HIB

1

Z = Pb-free part.

Rev. E | Page 26 of 28

AD8065/AD8066

NOTES

Rev. E | Page 27 of 28

AD8065/AD8066

NOTES

C02916-0-2/04(E)

Rev. E | Page 28 of 28

Datasheet AD8065 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

APPLICATIONS

CONNECTION DIAGRAMS

TABLE OF CONTENTS

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

MAXIMUM POWER DISSIPATION

OUTPUT SHORT CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

SOIC-8 Pinout

THEORY OF OPERATION

CLOSED-LOOP FREQUENCY RESPONSE

NONINVERTING CLOSED-LOOP FREQUENCY RESPONSE

INVERTING CLOSED-LOOP FREQUENCY RESPONSE

WIDEBAND OPERATION

INPUT PROTECTION

THERMAL CONSIDERATIONS

INPUT AND OUTPUT OVERLOAD BEHAVIOR

LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS

POWER SUPPLY BYPASSING

GROUNDING

LEAKAGE CURRENTS

INPUT CAPACITANCE

OUTPUT CAPACITANCE

INPUT-TO-OUTPUT COUPLING

WIDEBAND PHOTODIODE PREAMP

HIGH SPEED JFET INPUT INSTRUMENTATION AMPLIFIER

VIDEO BUFFER

OUTLINE DIMENSIONS

ORDERING GUIDE