Datasheet AD8057 Datasheet (Analog Devices)

Low Cost, High Performance

Voltage Feedback, 325 MHz Amplifiers

AD8057/AD8058

FEATURES
Low Cost Single (AD8057) and Dual (AD8058)
High Speed

325 MHz –3 dB Bandwidth (G = +1)
1000 V/␮s Slew Rate
Gain Flatness 0.1 dB to 28 MHz

Low Noise

7 nV/√Hz

Low Power

5.4 mA/Amplifier Typical Supply Current @ 5 V

Low Distortion

–85 dBc @ 5 MHz, R

= 1 k⍀

L

Wide Supply Range from 3 V to 12 V
Small Packaging

AD8057 Available in SOIC-8 and SOT-23-5
AD8058 Available in SOIC-8 and MSOP

APPLICATIONS
Imaging
DVD/CD
Photodiode Preamp
A-to-D Driver
Professional Cameras
Filters

GENERAL DESCRIPTION

The AD8057 (single) and AD8058 (dual) are very high perfor­mance amplifiers with a very low cost. The balance between
cost and performance make them ideal for many applications.
The AD8057 and AD8058 will reduce the need to qualify a
variety of specialty amplifiers.

The AD8057 and AD8058 are voltage feedback amplifiers with
the bandwidth and slew rate normally found in current feedback
amplifiers. The AD8057 and AD8058 are low power amplifiers
having low quiescent current and a wide supply range from 3 V
to 12 V. They have noise and distortion performance required
for high end video systems as well as dc performance parameters
rarely found in high speed amplifiers.

The AD8057 and AD8058 are available in standard SOIC
packaging as well as tiny SOT-23-5 (AD8057) and MSOP
(AD8058) packages. These amplifiers are available in the indus­trial temperature range of –40°C to +85°C.

CONNECTION DIAGRAMS (TOP VIEW)

RT-5 (SOT-23-5)

1

2

S

3

(Not to Scale)

AD8057

V

OUT

–V

+IN

+V

5

S

4

–IN

R-8 (SOIC)

1

NC

2

–IN

3

+IN

AD8057

4

S

(Not to Scale)

NC = NO CONNECT

RM-8 (MSOP)

R-8 (SOIC)

OUT1

–IN1

+IN1

–V

5

4

3

2

1

0

GAIN (dB)

–1

–2

–3

–4

–5

1 100010

S

G = +10

AD8058

1

2

3

4

(Not to Scale)

G = +5

FREQUENCY (MHz)

8

7

5

6

100

+V

S

OUT2

–IN2

+IN2

G = +1

G = +2

Figure 1. Small Signal Frequency Response

8

NC

7

+V

S

6

V

OUT

5

NC–V

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

(@ TA = 25ⴗC, VS = ⴞ5 V, RL = 100 ⍀, RF = 0 ⍀, Gain = +1,

AD8057/AD8058–SPECIFICATIONS

unless otherwise noted.)

AD8057/AD8058

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth G = +1, VO = 0.2 V p-p 325 MHz

G = –1, V
G = +1, V

Bandwidth for 0.1 dB Flatness G = +1, V

= 0.2 V p-p 95 MHz

O

= 2 V p-p 175 MHz

O

= 0.2 V p-p 30 MHz

O

Slew Rate G = +1, VO = 2 V Step, RL = 2 kΩ 850 V/µs

G = +1, V

= 4 V Step, RL = 2 kΩ 1150 V/µs

O

Settling Time to 0.1% G = +2, VO = 2 V Step 30 ns

NOISE/HARMONIC PERFORMANCE

Total Harmonic Distortion f

SFDR f = 5 MHz, V
Third Order Intercept f = 5 MHz, V

= 5 MHz, VO = 2 V p-p, RL = 1 kΩ –85 dBc

C

f

= 20 MHz, VO = 2 V p-p, RL = 1 kΩ –62 dBc

C

= 2 V p-p, RL = 150 Ω –68 dB

O

= 2 V p-p –35 dBm

O

Crosstalk, Output to Output f = 5 MHz, G = +2 –60 dB
Input Voltage Noise f = 100 kHz 7 nV/√Hz
Input Current Noise f = 100 kHz 0.7 pA/√Hz
Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.01 %

NTSC, G = +2, R

Differential Phase Error NTSC, G = +2, R

NTSC, G = +2, R

= 1 kΩ 0.02 %

L

= 150 Ω 0.15 Degree

L

= 1 kΩ 0.01 Degree

L

Overload Recovery VIN = 200 mV p-p, G = +1 30 ns

DC PERFORMANCE

Input Offset Voltage 15mV

T

MIN

to T

MAX

2.5 mV

Input Offset Voltage Drift 3 µV/°C
Input Bias Current 0.5 2.5 µA

T

MIN

to T

MAX

3.0 µA

Input Offset Current ±0.75 µA
Open-Loop Gain V

= ±2.5 V, RL = 2 kΩ 50 55 dB

O

VO = ±2.5 V, RL = 150 Ω 50 52 dB

INPUT CHARACTERISTICS

Input Resistance 10 MΩ
Input Capacitance +Input 2 pF
Input Common-Mode Voltage Range R

= 1 kΩ –4.0 +4.0 V

L

Common-Mode Rejection Ratio VCM = ±2.5 V 48 60 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 2 kΩ –4.0 +4.0 V

= 150 Ω±3.9 V

R

L

Capacitive Load Drive 30% Overshoot 30 pF

POWER SUPPLY

Operating Range ±5.0 V
Quiescent Current for AD8057 6.0 7.5 mA
Quiescent Current for AD8058 14.0 15 mA
Power Supply Rejection Ratio VS = ±5 V to ± 1.5 V 54 59 dB

Specifications subject to change without notice.

REV. B–2–

AD8057/AD8058

SPECIFICATIONS

(@ TA = 25ⴗC, VS = 5 V, RL = 100 ⍀, RF = 0 ⍀, Gain = +1, unless otherwise noted.)

AD8057/AD8058

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth G = +1, V

= 0.2 V p-p 300 MHz

O

G = +1, VO = 2 V p-p 155 MHz
Bandwidth for 0.1 dB Flatness V
Slew Rate G = +1, V

= 0.2 V p-p 28 MHz

O

= 2 V Step, RL = 2 kΩ 700 V/µs

O

Settling Time to 0.1% G = +2, VO = 2 V Step 35 ns

NOISE/HARMONIC PERFORMANCE

Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ –75 dBc

= 20 MHz, VO = 2 V p-p, RL = 1 kΩ –54 dBc

f

C

Crosstalk, Output to Output f = 5 MHz, G = +2 –60 dB
Input Voltage Noise f = 100 kHz 7 nV/√Hz
Input Current Noise f = 100 kHz 0.7 pA/√Hz
Differential Gain Error NTSC, G = +2, R

NTSC, G = +2, R
Differential Phase Error NTSC, G = +2, R

= 150 Ω 0.05 %

L

= 1 kΩ 0.05 %

L

= 150 Ω 0.10 Degree

L

NTSC, G = +2, RL = 1 kΩ 0.02 Degree

DC PERFORMANCE

Input Offset Voltage 15mV

T

MIN

to T

MAX

2.5 mV

Input Offset Voltage Drift 3 µV/°C
Input Bias Current 0.5 2.5 µA

T

MIN

to T

MAX

3.0 µA

Input Offset Current 0.75 µA
Open-Loop Gain V

= ±1.25 V, RL = 2 kΩ to Midsupply 50 55 dB

O

VO = ±1.25 V, RL = 150 Ω to Midsupply 45 52 dB

INPUT CHARACTERISTICS

Input Resistance 10 MΩ
Input Capacitance +Input 2 pF
Input Common-Mode Voltage Range R

= 1 kΩ±0.9 to ±3.4 V

L

Common-Mode Rejection Ratio VCM = ±2.5 V 48 60 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 2 kΩ 0.9 to 4.1 V

= 150 Ω 1.2 to 3.8 V

R

L

Capacitive Load Drive 30% Overshoot 30 pF

POWER SUPPLY

Operating Range 5.0 V
Quiescent Current for AD8057 5.4 7.0 mA
Quiescent Current for AD8058 13.5 14 mA
Power Supply Rejection Ratio 54 58 dB

Specifications subject to change without notice.

REV. B

–3–

AD8057/AD8058

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (+VS to –VS) . . . . . . . . . . . . . . . . . . . . . 12.6 V

Internal Power Dissipation

2

1

SOIC Package (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 W

SOT-23-5 Package (RT) . . . . . . . . . . . . . . . . . . . . . . . 0.5 W

MSOP Package (RM) . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 4.0 V

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . .Observe Power Derating Curves

Storage Temperature Range (R) . . . . . . . . . –65°C to +125°C

Operating Temperature Range (A Grade) . . . –40°C to +85°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for device in free air:
8-Lead SOIC Package: ␪JA = 160°C/W
5-Lead SOT-23-5 Package: ␪JA = 240°C/W
8-Lead MSOP Package: ␪JA = 200°C/W

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8057/AD8058 is limited by the associated rise in junction
temperature. Exceeding a junction temperature of 175°C for an
extended period can result in device failure. While the AD8057/
AD8058 is internally short-circuit protected, this may not be
sufficient to guarantee that the maximum junction temperature
(150°C) is not exceeded under all conditions.

To ensure proper operation, it is necessary to observe the maxi­mum power derating curves.

2.0

1.5

8-LEAD SOIC

8-LEAD MSOP

1.0

0.5

MAXIMUM POWER DISSIPATION (W)

0
–50 80–40

–30 –20 –10010 20 30 40 50 60 70

SOT-23-5

AMBIENT TEMPERATURE (ⴗC)

TJ = 150ⴗC

90

Figure 2. Plot of Maximum Power Dissipation vs.
Temperature

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8057AR –40°C to +85°C 8-Lead Narrow Body SOIC R-8 Standard
AD8057ACHIPS –40°C to +85°CDie Waffle Pak N/A
AD8057AR-REEL –40°C to +85°C 8-Lead SOIC, 13" Reel R-8 Standard
AD8057AR-REEL7 –40°C to +85°C 8-Lead SOIC, 7" Reel R-8 Standard
AD8057ART-R2 –40°C to +85°C 5-Lead SOT-23 RT-5 H7A
AD8057ART-REEL –40°C to +85°C 5-Lead SOT-23, 13" Reel RT-5 H7A
AD8057ART-REEL7 –40°C to +85°C 5-Lead SOT-23, 7" Reel RT-5 H7A
AD8057ARTZ-REEL7* –40°C to +85°C 5-Lead SOT-23, 7" Reel RT-5 H7A
AD8058AR –40°C to +85°C 8-Lead Narrow Body SOIC R-8 Standard
AD8058ACHIPS –40°C to +85°CDie Waffle Pak N/A
AD8058AR-REEL –40°C to +85°C 8-Lead SOIC, 13" Reel R-8 Standard
AD8058AR-REEL7 –40°C to +85°C 8-Lead SOIC, 7" Reel R-8 Standard
AD8058ARZ-REEL7* –40°C to +85°C 8-Lead SOIC, 7" Reel R-8 Standard
AD8058ARM –40°C to +85°C 8-Lead MSOP RM-8 H8A
AD8058ARM-REEL –40°C to +85°C 8-Lead MSOP, 13" Reel RM-8 H8A
AD8058ARM-REEL7 –40°C to +85°C 8-Lead MSOP, 7" Reel RM-8 H8A
AD8058ARMZ-REEL7* –40°C to +85°C 8-Lead MSOP, 7" Reel RM-8 H8A

*Lead free

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8057/AD8058 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. B–4–

4.5

–40 85–30 –20 –10 0 10 20 304050607080

TEMPERATURE (ⴗC)

0.0

–3.5

–5.0

VOLTS

–0.5

–3.0

–4.0

–4.5

–1.5

–2.5

–1.0

–2.0

–5V SWING RL = 150⍀

–2.5V SWING RL = 150⍀

–1.5V SWING RL = 150⍀

TEMPERATURE (ⴗC)

6

–2

–6

–40 –30

V

OS

(mV)

–20 –10

0

10 20 30 40 50 60 70 80

–4

2

0

4

VOS @ ⴞ5V

V

OS

@ ⴞ1.5V

TEMPERATURE (ⴗC)

3.5

1.5

0
–40 –30

A

VOL

(mV/V)

–20 –10

0

10 20 30 40 50 60 70 80

0.5

2.5

2.0

3.0

A

VOL

@ ⴞ2.5V

A

VOL

@ ⴞ5V

85

1.0

(+) OUTPUT

4.0
VOLTAGE

3.5

3.0

2.5

2.0

1.5

OUTPUT VOLTAGE (V)

1.0

0.5

0

10 100k100

ABS (–)
OUTPUT

LOAD RESISTANCE (⍀)

1k 10k

Typical Performance Characteristics–AD8057/AD8058

TPC 1. Output Swing vs. Load Resistance

–3.0

–3.5

–4.0

–4.5

–5.0

(mA)

–5.5

SUPPLY

–6.0

–I

–6.5

–7.0

–7.5

–8.0

–40 85–30 –20 –10 0 10 20 304050607080

TPC 2. –I

5.0

4.5

+5V SWING RL = 150⍀

4.0

3.5

3.0

2.5

VOLTS

2.0

1.5

1.0

REV. B

0.5

0.0

–4085–30

TPC 3. Positive Output Voltage Swing vs. Temperature

–I

SUPPLY

TEMPERATURE ( C)

SUPPLY

+2.5V SWING RL = 150⍀

+1.5V SWING RL = 150⍀

–20 –10

10 20 30 40 50 60 70 80

0

TEMPERATURE (ⴗC)

–I

@ ⴞ1.5V

SUPPLY

@ ⴞ5V

vs. Temperature

TPC 4. Negative Output Voltage Swing vs. Temperature

TPC 5. VOS vs. Temperature

TPC 6. Open-Loop Gain vs. Temperature

–5–

AD8057/AD8058

0.00

–0.10

–0.20

–0.30

–0.40

(␮A)

B

I

–0.50

–0.60

–0.70

–0.80

–40 85–30 –20 –10 0 10 20 30 40 50 60 70 80

+IB @ ⴞ5V

+IB @ ⴞ2.5V

–IB @ ⴞ5V

–IB @ ⴞ1.5V

–IB @ ⴞ2.5V

TEMPERATURE (

+IB @ ⴞ1.5V

C)

TPC 7. Input Bias Current vs. Temperature

4

3

PSRR @ ⴞ1.5V ⴞ5V

2

+V

S

4.7␮F

0.01␮F

HP8130A

PULSE

GENERATOR

= 1ns

T

R/TF

V

IN

50

⍀

0.001␮F

AD8057/58

0.01␮F

0.001␮F

–V

S

4.7␮F

V

OUT

1k

⍀

TPC 10. Test Circuit G = +1, RL = 1 kΩ for TPCs 11 and 12

100mV

20mV/

DIV

PSRR (mV/V)

1

0

–4085–30 –20 –10

0

–10

–20

–30

PSRR (dB)

–40

–50

–60

0.1

10 20 30 40 50 60 70 80

0

TEMPERATURE ( C)

TPC 8. PSRR vs. Temperature

–PSRR VS = ⴞ2.5V

+PSRR VS = ⴞ2.5V

10 100

FREQUENCY (MHz)

TPC 9. ±PSRR vs. Frequency

–100mV

4ns/DIV

TPC 11. Small Signal Step Response G = +1,

= 1 kΩ, VS = ±5 V

R

L

5V

1V/DIV

–5V

10001

4ns/DIV

TPC 12. Large Signal Step Response G = +1,
RL = 1 kΩ, VS = ±5.0 V

REV. B–6–

1k⍀

+V

S

4.7␮F

0.01␮F

HP8130A

PULSE

GENERATOR

= 1ns

T

R/TF

V

1k⍀

IN

50⍀

0.001␮F

AD8057/58

0.01␮F

0.001␮F

–V

S

4.7␮F

V

OUT

1k⍀

TPC 13. Test Circuit G = –1, RL = 1 kΩ for TPCs 14 and 15

100mV

20mV/

DIV

0V

–100mV

TPC 14. Small Signal Step Response G = –1, RL = 1 k

4ns/DIV

Ω

AD8057/AD8058

5

4

3

2

1

0

GAIN (dB)

–1

–2

–3

–4

–5

1 100010

G = +10

G = +5

FREQUENCY (MHz)

TPC 16. Small Signal Frequency Response,
V

= 0.2 V p-p

OUT

5

4

3

2

1

0

GAIN (dB)

–1

–2

–3

–4

–5

1 100010

G = +10

G = +5

FREQUENCY (MHz)

TPC 17. Large Signal Frequency Response, V

G = +1

G = +2

100

G = +1

G = +2

100

= 2 V p-p

OUT

5V

1V/DIV

–5V

4ns/DIV

TPC 15. Large Signal Step Response G = –1, RL = 1 k

REV. B

5

4

3

2

1

0

GAIN (dB)

–1

–2

–3

–4

–5

1 100010

Ω

TPC 18. Large Signal Frequency Response

G = –5

G = –10

G = –2

G = –1

FREQUENCY (MHz)

100

–7–

AD8057/AD8058

0.5

0.4

0.3

0.2

0.1

0.0

GAIN (dB)

–0.1

–0.2

–0.3

–0.4

–0.5

1 100010

TPC 19. 0.1 dB Flatness G = +2

–50

–60

–70

–80

–90

DISTORTION (dBc)

–100

FREQUENCY (MHz)

THD

SECOND

THIRD

100

V

OUT

G = +2

= 1.0k⍀

R

L

= 1.0k⍀

R

F

= 0.2V

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

RISE TIME AND FALL TIME (ns)

0.5

0.0
0

FALL TIME

V

OUT

RISE TIME

(V p-p)

TPC 22. Rise Time and Fall Time vs. V

= 1 kΩ, RF = 0

R

L

5

4

3

2

1

RISE TIME AND FALL TIME (ns)

Ω

RISE TIME

FALL TIME

, G = +1,

OUT

412 3

–110

0.1 1001
FREQUENCY (MHz)

10

TPC 20. Distortion vs. Frequency, RL = 150

–40

–50

20MHz

–60

DISTORTION (dBc)

–70

–80

0.0 4.00.4

0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6

TPC 21. Distortion vs. V

5MHz

V

(V p-p)

OUT

@ 20 MHz, 5 MHz,

OUT

RL = 150 Ω, VS = ±5.0 V

0

0

Ω

TPC 23. Rise Time and Fall Time vs. V
RL = 100 Ω, RF = 402

V

0.4%

0.3%

0.2%

0.1%

0.0%

–0.1%

–0.2%

–0.3%

–0.4%

OUT

0102030405060

23

V

(V p-p)

OUT

Ω

= –1V TO + 1V OR +1V TO –1V

TIME (ns)

G = +2

RL = 100⍀/1k⍀

, G = +2,

OUT

41

TPC 24. Settling Time

REV. B–8–

AD8057/AD8058

VS = ⴞ2.5V
RL = 1k⍀
G = +1

2.5V

500mV/

DIV

INPUT SIGNAL

OUTPUT RESPONSE

0V

20ns/DIV

TPC 25. Input Overload Recovery, VS = ±2.5 V

VS = ⴞ5.0V

= 1k⍀

R

L

G = +1

INPUT SIGNAL 5V

5.0V

1V/DIV

OUTPUT SIGNAL = 4.0V

1.8V

200mV/

DIV

OUTPUT SIGNAL 1.7V

INPUT SIGNAL = 0.6V

20ns/DIV

VS = ⴞ2.5V
R1 = 1k⍀
G = +4

TPC 28. Output Overload Recovery, VS = ±2.5 V

4.5V

500mV/

DIV

VS = ⴞ5.0V
R1 = 1k⍀
G = +4

0V

20ns/DIV

TPC 26. Output Overload Recovery, VS = ±5.0 V

0

–10

–20

–30

–40

CMRR (dB)

–50

–60

–70

0.1 1001
FREQUENCY (MHz)

10

TPC 27. CMRR vs. Frequency

20ns/DIV 37ns

TPC 29. Output Overload Recovery, VS = ±5.0 V

0

–20

–40

–60

CROSSTALK (dB)

–80

–100

–120

0.1 1

SIDE B DRIVEN

FREQUENCY (MHz)

SIDE A DRIVEN

10 100

TPC 30. Crosstalk (Output-to-Output) vs. Frequency

REV. B

–9–

AD8057/AD8058

DIFFERENTIAL GAIN (%)

0.00 –0.00–0.00–0.00 –0.000.00 –0.000.00 –0.00–0.00 –0.00

0.015

0.010

0.005

0.000

–0.005

–0.010

–0.015

DIFFERENTIAL PHASE (Degrees)

0.00 0.130.070.00 0.090.02 0.100.03 0.110.05 0.12

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.00

–0.02

1st 11th6th2nd 7th3rd 8th4th 9th5th 10th

a.

DIFFERENTIAL GAIN (%)

0.00 –0.010.000.00 0.000.00 0.000.01 –0.000.01 –0.01

0.015

0.010

0.005

0.000

–0.005

–0.010

–0.015

DIFFERENTIAL PHASE (Degrees)

0.00 –0.01`–0.000.00 –0.010.00 –0.01–0.00 –0.01–0.00 –0.01

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.00

–0.02

1st 11th6th2nd 7th3rd 8th4th 9th5th 10th

b.

VS = ⴞ5.0V

= 150⍀

R

L

VS = ⴞ5.0V

= 150⍀

R

L

VS = ⴞ5.0V

= 1k⍀

R

L

VS = ⴞ5.0V

= 1k⍀

R

L

DIFFERENTIAL GAIN (%)

0.00 –0.04–0.01–0.00 –0.01–0.00 –0.01–0.01 –0.02–0.01 –0.03

0.01

0.00

–0.01

–0.02

–0.03

–0.04

–0.05

DIFFERENTIAL PHASE (Degrees)

0.00 0.130.090.01 0.110.03 0.120.05 0.120.07 0.13

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.00

–0.02

1st 11th6th2nd 7th3rd 8th4th 9th5th 10th

a.

DIFFERENTIAL GAIN (%)

0.00 –0.05–0.010.01 –0.02–0.00 –0.02–0.01 –0.03–0.01 –0.04

0.01

0.00

–0.01

–0.02

–0.03

–0.04

–0.05

DIFFERENTIAL PHASE (Degrees)

0.00 –0.02–0.00–0.00 –0.000.00 –0.000.00 –0.01–0.00 –0.01

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.00

–0.02

1st 11th6th2nd 7th3rd 8th4th 9th5th 10th

b.

VS = +5V

= 150⍀

R

L

VS = +5V

= 150⍀

R

L

VS = +5V

= 1k⍀

R

L

VS = +5V

= 1k⍀

R

L

TPC 31. Differential Gain and Differential Phase

Ω

One Back Terminated Load (150

) (Video Op

Amps Only)

180

135

90

45

PHASE (Degrees)

0

–45

–90

0.01 10000.1

110100

FREQUENCY (MHz)

80

60

40

20

0

–20

TPC 32. Open-Loop Gain and Phase vs. Frequency

OPEN-LOOP GAIN (dB)

TPC 33. Differential Gain and Differential Phase,

= 150 Ω, b. RL = 1 k

a. R

L

100

10

(nV/ Hz)

NOISE

V

1

0.1
10 100M100

1k 10k 100k

Ω

FREQUENCY (Hz)

1M 10M

TPC 34. Voltage Noise vs. Frequency

REV. B–10–

AD8057/AD8058

–2.5V

R

G

50k⍀

V

IN

= 200mV p-p

AD8058

0.1␮F 10␮F

0.1␮F

10␮F

+2.5V

R

F

C

L

R

S

V

OUT

FET PROBE

100

10

(pA/ Hz)

NOISE

I

1

0.1
10 100M100

1k 10k 100k

FREQUENCY (Hz)

1M 10M

TPC 35. Current Noise vs. Frequency

APPLICATIONS
Driving Capacitive Loads

When driving a capacitive load, most op amps will exhibit over­shoot in their pulse response.

Figure 3 shows the relationship between the capacitive load
that results in 30% overshoot and the closed-loop gain of an
AD8058. It can be seen that, under the Gain = +2 condition,
the device is stable with capacitive loads of up to 69 pF.

In general, to minimize peaking or to ensure device stability for
larger values of capacitive loads, a small series resistor, R

, can

S

be added between the op amp output and the load capacitor,

, as shown in Figure 4.

C

L

For the setup shown in Figure 4, the relationship between R

S

and CL was empirically derived and is shown in Table I.

100

10

(⍀)

OUT

Z

1

0.1

0.1 10001

10 100

FREQUENCY (MHz)

TPC 36. Output Impedance vs. Frequency

Table I. Recommended Value for Resistors RS, RF, RG vs.

Capacitive Load, C

Gain R

F

, Which Results in 30% Overshoot

L

R

CL w/RS = 0 Ω CL w/RS = 2.4 Ω

G

(Ω)(Ω) (pF) (pF)

1 100 11 13
2 100 100 51 69
3 100 50 104 153
4 100 33.2 186 270
5 100 25 245 500
10 100 11 870 1580

500

400

300

(pF)

L

C

200

RS = 2.4⍀

100

= 0⍀

R

S

0

152

Figure 3. Capacitive Load Drive vs. Closed-Loop Gain

REV. B

34

CLOSED-LOOP GAIN

–11–

Figure 4. Capacitive Load Drive Circuit

+ OVERSHOOT

29.0%

200mV

100mV

–100mV

–200mV

100mV/DIV

50ns/DIV

Figure 5. Typical Pulse Response with CL = 65 pF,
Gain = +2, and V

= ±2.5 V

S

AD8057/AD8058

Video Filter

Some composite video signals that are derived from a digital
source contain some clock feedthrough that can cause problems
with downstream circuitry. This clock feedthrough is usually at
27 MHz, which is a standard clock frequency for both NTSC
and PAL video systems. A filter that passes the video band and
rejects frequencies at 27 MHz can be used to remove these
frequencies from the video signal.

Figure 6 shows a circuit that uses an AD8057 to create a single
5 V supply, 3-pole Sallen-Key filter. This circuit uses a single
RC pole in front of a standard 2-pole active section. To shift the
dc operating point to midsupply, ac coupling is provided by R4,
R5, and C4.

C2

680pF

R

F

1k⍀

+5V

7

4

0.1␮F+10␮F

6

R1

200⍀

R2

499⍀

C1
100pF

R3

49.9⍀

C3
36pF

C4

0.1␮F

+5V

R4
10k⍀

R5
10k⍀

2

AD8057

3

Figure 6. Low-Pass Filter for Video

Figure 7 shows a frequency sweep of this filter. The response is
down 3 dB at 5.7 MHz, so it passes the video band with little
attenuation. The rejection at 27 MHz is 42 dB, which provides
more than a factor of 100 in suppression of the clock compo­nents at this frequency.

Differential A-to-D Driver

As system supply voltages are dropping, many ADCs provide
differential analog inputs to increase the dynamic range of the
input signal while still operating on a low supply voltage. Differ­ential driving can also reduce second and other even-order
distortion products.

Analog Devices offers an assortment of 12- and 14-bit high
speed converters that have differential inputs and can be run
from a single 5 V supply. These include the AD9220, AD9221,
AD9223, AD9224, and AD9225 at 12 bits, and the AD9240,
AD9241, and AD9243 at 14 bits. Although these devices can
operate over a range of common-mode voltages at their analog
inputs, they work best when the common-mode voltage at the
input is at the midsupply or 2.5 V.

Op amp architectures that require upwards of 2 V of headroom
at the output have significant problems when trying to drive
such ADCs while operating with a 5 V positive supply. The low
headroom output design of the AD8057 and AD8058 make
them ideal for driving these types of ADCs.

The AD8058 can be used to make a dc-coupled, single-ended­to-differential driver for one of these ADCs. Figure 8 is a
schematic of such a circuit for driving an AD9225, 12-bit,
25 MSPS ADC.

1k⍀

+5V

+

10␮F

0.1␮F

3

AD8058

2

8

1

1k⍀

50⍀

1k⍀

V

IN

0V

1k⍀

0.1␮F

VINA

+2.5V

+

10␮F

+5V

REF

10

0

–10

–20

–30

–40

–50

–60

LOG MAGNITUDE (dB)

–70

–80

–90

100k 100M

1M 10M

FREQUENCY (Hz)

Figure 7. Video Filter Response

AD9225

6

AD8058

5

–5V

1k⍀

10␮F

+

50⍀

VINB

7

4

0.1␮F

1k⍀

1k⍀

1k⍀

Figure 8. Schematic Circuit for Driving AD9225

In this circuit, one of the op amps is configured in the inverting
mode, while the other is in the noninverting mode. However, to
provide better bandwidth matching, each op amp is configured
for a noise gain of +2. The inverting op amp is configured for a
gain of –1, while the noninverting op amp is configured for a
gain of +2. Each of these produces a noise gain of +2, which is
only determined by the inverse of the feedback ratio. The input
signal to the noninverting op amp is divided by 2 in order to
normalize its level and make it equal to the inverting output.

REV. B–12–

AD8057/AD8058

For 0 V input, the outputs of the op amps want to be at 2.5 V,
which is the midsupply level of the ADCs. This is accomplished by
first taking the 2.5 V reference output of the ADC and divid­ing it by two by a pair of 1 kΩ resistors. The resulting 1.25 V is
applied to each op amp’s positive input. This voltage is then
multiplied by the gain of +2 of the op amps to provide a 2.5 V
level at each output.

The assumption for this circuit is that the input signal is bipolar
with respect to ground and the circuit must be dc-coupled. This
implies the existence of a negative supply elsewhere in the sys­tem. This circuit uses –5 V as the negative supply for the AD8058.

If the AD8058 negative supply were tied to ground, there would
be a problem at the input of the noninverting op amp. The
input common-mode voltage can only go to within 1 V of the
negative rail. Since this circuit requires that the positive inputs
operate with a 1.25 V bias, there is not enough room to swing
this voltage in the negative direction. The inverting stage does

not have this problem because its common-mode input voltage
remains fixed at 1.25 V. If dc coupling is not required, various
ac coupling techniques can be used to eliminate this problem.

Layout

The AD8057 and AD8058 are high speed op amps and should
be used in a board layout that follows standard high speed design
rules. All the signal traces should be as short and direct as pos­sible. In particular, the parasitic capacitance on the inverting
input of each device should be kept to a minimum to avoid
excessive peaking and other undesirable performance.

The power supplies should be bypassed very close to the power
pins of the package with 0.1 µF in parallel with a larger, approxi-
mately 10 µF tantalum capacitor. These capacitors should be
connected to a ground plane that is either on an inner layer or
fills the area of the board that is not used for other signals.

REV. B

–13–

AD8057/AD8058

OUTLINE DIMENSIONS

8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

3.00

BSC

3.00
BSC

PIN 1

0.15

0.00

COPLANARITY

0.10

85

1

0.65 BSC

0.38

0.22

COMPLIANT TO JEDEC STANDARDS MO-187AA

4

SEATING
PLANE

4.90

BSC

1.10 MAX

0.23

0.08

8ⴗ
0ⴗ

5-Lead Small Outline Transistor Package [SOT-23]

Dimensions shown in millimeters

0.80

0.60

0.40

(RT-5)

8-Lead Standard Small Outline Package [SOIC]

(R-8)

Dimensions shown in millimeters and (inches)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

85

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

BSC

6.20 (0.2440)

5.80 (0.2284)

41

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

ⴗ

8

ⴗ

0

1.27 (0.0500)

0.40 (0.0157)

ⴛ

ⴗ

45

1.60 BSC

1.30

1.15

0.90

0.15 MAX

2.90 BSC

4 5

2.80 BSC

1 3

2

PIN 1

COMPLIANT TO JEDEC STANDARDS MO-178AA

1.90
BSC

0.50

0.30

0.95 BSC

1.45 MAX

SEATING
PLANE

0.22

0.08
10ⴗ

5ⴗ
0ⴗ

0.60

0.45

0.30

REV. B–14–

AD8057/AD8058

Revision History

Location Page

8/03—Data Sheet changed from REV. A to REV. B.

Renumbered Figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Change to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

REV. B

–15–

C01064–0–8/03(B)

–16–