Datasheet AD8051 Datasheet (Analog Devices)

Low Cost, High Speed

8

7

6

5

1

2

3

4

NC

–IN

+IN

NC

+V

S

V

OUT

NC–V

S

AD8051

NC = NO CONNECT

1

2

3

5

4

–IN+IN

+V

S

V

OUT

AD8051

+–

–V

S

V+

+IN B

OUT B

OUT D

+IN D

Vⴚ

+IN C

OUT C

AD8054

+IN A

OUT A

ⴚIN A

ⴚIN B ⴚIN C

ⴚIN D

1

2

3

4

5

6

7

14

13

12

11

10

9

8

a

FEATURES
Low Cost Single (AD8051), Dual (AD8052), and Quad

(AD8054)
Voltage Feedback Architecture
Fully Specified at +3 V, +5 V, and ⴞ5 V Supplies
Single-Supply Operation

Output Swings to Within 25 mV of Either Rail

Input Voltage Range: –0.2 V to +4 V; V
High Speed and Fast Settling on 5 V:

110 MHz –3 dB Bandwidth (G = +1) (AD8051/AD8052)

150 MHz –3 dB Bandwidth (G = +1) (AD8054)

145 V/␮s Slew Rate

50 ns Settling Time to 0.1%
Small Packaging

AD8051 Available in SOT-23-5

AD8052 Available in MSOP-8

AD8054 Available in TSSOP-14
Good Video Specifications (G = +2)

Gain Flatness of 0.1 dB to 20 MHz; R

0.03% Differential Gain Error; RL = 1 k⍀

0.03ⴗ Differential Phase Error; RL = 1 k⍀

Low Distortion

–80 dBc Total Harmonic @ 1 MHz, R
Outstanding Load Drive Capability

Drives 45 mA, 0.5 V from Supply Rails (AD8051/AD8052)

Drives 50 pF Capacitive Load (G = +1) (AD8051/AD8052)
Low Power of 2.75 mA/Amplifier (AD8054)
Low Power of 4.4 mA/Amplifier (AD8051/AD8052)

APPLICATIONS
Coax Cable Drivers
Active Filters
Video Switchers
A/D Driver
Professional Cameras
CCD Imaging Systems
CD/DVD ROMs

= +5 V

S

= 150 ⍀

L

= 100 ⍀

L

Rail-to-Rail Amplifiers

AD8051/AD8052/AD8054

PIN CONNECTIONS

(Top Views)

R-8 (SOIC)

SOT-23-5 (RT)

R-8, MSOP (RM)

AD8052

1

OUT1

–

2

–IN1

+IN1

–V

+

3

4

S

R-14, TSSOP-14 (RU-14)

8

+V

S

7

OUT

6

–IN2

–
+

+IN2

5

GENERAL DESCRIPTION

The AD8051 (single), AD8052 (dual), and AD8054 (quad) are
low cost, voltage feedback, high speed amplifiers designed to
operate on +3 V, +5 V, or ±5 V supplies. They have true single­supply capability with an input voltage range extending 200 mV
below the negative rail and within 1 V of the positive rail.

Despite their low cost, the AD8051/AD8052/AD8054 provide
excellent overall performance and versatility. The output voltage
swing extends to within 25 mV of each rail, providing the maxi­mum output dynamic range with excellent overdrive recovery.

REV. F

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD8051/AD8052/AD8054

This makes the AD8051/AD8052/AD8054 useful for video
electronics, such as cameras, video switchers, or any high speed
portable equipment. Low distortion and fast settling make them
ideal for active filter applications.

The AD8051/AD8052/AD8054 offer low power supply current
and can operate on a single 3 V power supply. These features
are ideally suited for portable and battery-powered applications
where size and power are critical.

The wide bandwidth and fast slew rate on a single +5 V supply
make these amplifiers useful in many general-purpose, high
speed applications where dual power supplies of up to ±6 V and
single supplies from +3 V to +12 V are needed.

All of this low cost performance is offered in an 8-lead SOIC, as
well as a tiny SOT-23-5 package (AD8051), an MSOP package
(AD8052), and a TSSOP-14 (AD8054). The AD8051 and
AD8052 in the SOIC-8 and RM packages, and the AD8054 in
the RN-14 and RU packages are available in the extended tem­perature range of –40°C to +125°C.

5.0

4.5
VS = +5V

G = –1

4.0
R

= 2k⍀

F

R

3.5

3.0

2.5

2.0

(THD ⱕ 0.5%) – V

1.5

1.0

0.5

PEAK-TO-PEAK OUTPUT VOLTAGE SWING

= 2k⍀

L

0

FREQUENCY – MHz

500.1 1 10

Figure 1. Low Distortion Rail-to-Rail Output Swing

REV. F–2–

AD8051/AD8052/AD8054

SPECIFICATIONS

(@ TA = 25ⴗC, VS = 5 V, RL = 2 k⍀ to 2.5 V, unless otherwise noted.)

AD8051A/AD8052A AD8054A

Parameter Conditions Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth G = +1, V

G = –1, +2, V

Bandwidth for 0.1 dB Flatness G = +2, V

R
R

= 0.2 V p-p 70 110 80 150 MHz

O

= 0.2 V p-p 50 60 MHz

O

= 0.2 V p-p,

O

= 150 Ω to 2.5 V,

L

= 806 Ω for AD8051A/

F

AD8052A 20 MHz

= 200 Ω for AD8054A 12 MHz

R

F

Slew Rate G = –1, V
Full Power Response G = +1, V

= 2 V Step 100 145 140 170 V/µs

O

= 2 V p-p 35 45 MHz

O

Settling Time to 0.1% G = –1, VO = 2 V Step 50 40 ns

NOISE/DISTORTION PERFORMANCE

Total Harmonic Distortion* f

= 5 MHz, VO = 2 V p-p, G = +2 –67 –68 dB

C

Input Voltage Noise f = 10 kHz 16 16 nV/√Hz
Input Current Noise f = 10 kHz 850 850 fA/√Hz
Differential Gain Error (NTSC) G = +2, R

R

Differential Phase Error (NTSC) G = +2, R

R

= 150 Ω to 2.5 V 0.09 0.07 %

L

= 1 kΩ to 2.5 V 0.03 0.02 %

L

= 150 Ω to 2.5 V 0.19 0.26 Degrees

L

= 1 kΩ to 2.5 V 0.03 0.05 Degrees

L

Crosstalk f = 5 MHz, G = +2 –60 –60 dB

DC PERFORMANCE

Input Offset Voltage 1.7 10 1.7 12 mV

T

MIN–TMAX

25 30 mV

Offset Drift 10 15 µV/°C
Input Bias Current 1.4 2.5 2 4.5 µA

T

MIN–TMAX

3.25 4.5 µA

Input Offset Current 0.1 0.75 0.2 1.2 µA
Open-Loop Gain R

= 2 kΩ to 2.5 V 86 98 82 98 dB

L

T

MIN–TMAX

= 150 Ω to 2.5 V 76 82 74 82 dB

R

L

T

MIN–TMAX

96 96 dB

78 78 dB

INPUT CHARACTERISTICS

Input Resistance 290 300 kΩ
Input Capacitance 1.4 1.5 pF
Input Common-Mode Voltage Range –0.2 to +4 –0.2 to +4 V
Common-Mode Rejection Ratio VCM = 0 V to 3.5 V 72 88 70 86 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing R

Output Current V

= 10 kΩ to 2.5 V 0.015 to 4.985 0.03 to 4.975 V

L

= 2 kΩ to 2.5 V 0.1 to 4.9 0.025 to 4.975 0.125 to 4.875 0.05 to 4.95 V

R

L

= 150 Ω to 2.5 V 0.3 to 4.625 0.2 to 4.8 0.55 to 4.4 0.25 to 4.65 V

R

L

= 0.5 V to 4.5 V 45 30 mA

OUT

T

MIN–TMAX

45 30 mA

Short-Circuit Current Sourcing 80 45 mA

Sinking 130 85 mA

Capacitive Load Drive G = +1 (AD8051/AD8052) 50 pF

G = +2 (AD8054) 40 pF

POWER SUPPLY

Operating Range 3 12 3 12 V
Quiescent Current/Amplifier 4.4 5 2.75 3.275 mA
Power Supply Rejection Ratio ⌬VS = ±1 V 70 80 68 80 dB

OPERATING TEMPERATURE RANGE

RT –40 +85 °C
RM, R-8, RU, R-14 –40 +125 –40 +125 °C

*Refer to TPC 13.

Specifications subject to change without notice.

REV. F

–3–

AD8051/AD8052/AD8054

SPECIFICATIONS

(@ TA = 25ⴗC, VS = 3 V, RL = 2 k⍀ to 1.5 V, unless otherwise noted.)

AD8051A/AD8052A AD8054A

Parameter Conditions Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth G = +1, V

G = –1, +2, V

Bandwidth for 0.1 dB Flatness G = +2, V

R
R

R
Slew Rate G = –1, V
Full Power Response G = +1, V
Settling Time to 0.1% G = –1, VO = 2 V Step 55 55 ns

= 0.2 V p-p 70 110 80 135 MHz

O

= 0.2 V p-p 50 65 MHz

O

= 0.2 V p-p,

O

= 150 Ω to 2.5 V,

L

= 402 Ω for AD8051A/AD8052A 17 MHz

F

= 200 Ω for AD8054A 10 MHz

F

= 2 V Step 90 135 110 150 V/µs

O

= 1 V p-p 65 85 MHz

O

NOISE/DISTORTION PERFORMANCE

Total Harmonic Distortion* f

Input Voltage Noise f = 10 kHz 16 16 nV/√Hz

= 5 MHz, VO = 2 V p-p,

C

G = –1, R

= 100 Ω to 1.5 V –47 –48 dB

L

Input Current Noise f = 10 kHz 600 600 fA/√Hz
Differential Gain Error (NTSC) G = +2, V

R

= 150 Ω to 1.5 V, 0.11 0.13 %

L

R

= 1 kΩ to 1.5 V 0.09 0.09 %

Differential Phase Error (NTSC) G = +2, V

Crosstalk f = 5 MHz, G = +2 –60 –60 dB

L

R

= 150 Ω to 1.5 V 0.24 0.3 Degrees

L

R

= 1 kΩ to 1.5 V 0.10 0.1 Degrees

L

CM

CM

= 1 V

= 1 V

DC PERFORMANCE

Input Offset Voltage 1.6 10 1.6 12 mV

T
Offset Drift 10 15 µV/°C

MIN–TMAX

25 30 mV

Input Bias Current 1.3 2.6 2 4.5 µA

T
Input Offset Current 0.15 0.8 0.2 1.2 µA
Open-Loop Gain R

MIN–TMAX

= 2 kΩ 80 96 80 96 dB

L

T

MIN–TMAX

R

= 150 Ω 74 82 72 80 dB

L

T

MIN–TMAX

94 94 dB

76 76 dB

3.25 4.5 µA

INPUT CHARACTERISTICS

Input Resistance 290 300 kΩ
Input Capacitance 1.4 1.5 pF
Input Common-Mode Voltage Range –0.2 to +2 –0.2 to +2 V
Common-Mode Rejection Ratio VCM = 0 V to 1.5 V 72 88 70 86 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing R

Output Current V

Short-Circuit Current Sourcing 60 30 mA

= 10 kΩ to 1.5 V 0.01 to 2.99 0.025 to 2.98 V

L

R

= 2 kΩ to 1.5 V 0.075 to 2.9 0.02 to 2.98 0.1 to 2.9 0.35 to 2.965 V

L

R

= 150 Ω to 1.5 V 0.2 to 2.75 0.125 to 2.875 0.35 to 2.55 0.15 to 2.75 V

L

= 0.5 V to 2.5 V 45 25 mA

OUT

T

MIN–TMAX

45 25 mA

Sinking 90 50 mA
Capacitive Load Drive G = +1 (AD8051/AD8052) 45 pF

G = +2 (AD8054) 35 pF

POWER SUPPLY

Operating Range 3 12 3 12 V
Quiescent Current/Amplifier 4.2 4.8 2.625 3.125 mA
Power Supply Rejection Ratio ⌬VS = 0.5 V 68 80 68 80 dB

OPERATING TEMPERATURE RANGE

RT –40 +85 °C

RM, R-8, RU, R-14 –40 +125 –40 +125 °C

*Refer to TPC 13.

Specifications subject to change without notice.

REV. F–4–

AD8051/AD8052/AD8054

SPECIFICATIONS

(@ TA = 25ⴗC, VS = ⴞ5 V, RL = 2 k⍀ to Ground, unless otherwise noted.)

AD8051A/AD8052A AD8054A

Parameter Conditions Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth G = +1, V

G = –1, +2, V

Bandwidth for 0.1 dB Flatness G = +2, V

= 0.2 V p-p 70 110 85 160 MHz

O

= 0.2 V p-p 50 65 MHz

O

= 0.2 V p-p,

O

RL = 150 Ω,

= 1.1 kΩ for

R

F

AD8051A/AD8052A 20 MHz

= 200 Ω for AD8054A 15 MHz

R

F

Slew Rate G = –1, V
Full Power Response G = +1, V

= 2 V Step 105 170 150 190 V/µs

O

= 2 V p-p 40 50 MHz

O

Settling Time to 0.1% G = –1, VO = 2 V Step 50 40 ns

NOISE/DISTORTION PERFORMANCE

Total Harmonic Distortion f

= 5 MHz, VO = 2 V p-p, G = +2 –71 –72 dB

C

Input Voltage Noise f = 10 kHz 16 16 nV/√Hz
Input Current Noise f = 10 kHz 900 900 fA/√Hz
Differential Gain Error (NTSC) G = +2, R

R

Differential Phase Error (NTSC) G = +2, R

R

= 150 Ω 0.02 0.06 %

L

= 1 kΩ 0.02 0.02 %

L

= 150 Ω 0.11 0.15 Degrees

L

= 1 kΩ 0.02 0.03 Degrees

L

Crosstalk f = 5 MHz, G = +2 –60 –60 dB

DC PERFORMANCE

Input Offset Voltage 1.8 11 1.8 13 mV

T

MIN–TMAX

27 32 mV

Offset Drift 10 15 µV/°C
Input Bias Current 1.4 2.6 2 4.5 µA

T

MIN–TMAX

3.5 4.5 µA

Input Offset Current 0.1 0.75 0.2 1.2 µA
Open-Loop Gain R

= 2 kΩ 88 96 84 96 dB

L

T

MIN–TMAX

= 150 Ω 78 82 76 82 dB

R

L

T

MIN–TMAX

96 96 dB

80 80 dB

INPUT CHARACTERISTICS

Input Resistance 290 300 kΩ
Input Capacitance 1.4 1.5 pF
Input Common-Mode Voltage Range –5.2 to +4 –5.2 to +4 V
Common-Mode Rejection Ratio VCM = –5 V to +3.5 V 72 88 70 86 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing R

Output Current V

= 10 kΩ –4.98 to +4.98 –4.97 to +4.97 V

L

= 2 kΩ –4.85 to +4.85 –4.97 to +4.97 –4.8 to +4.8 –4.9 to +4.9 V

R

L

= 150 Ω –4.45 to +4.3 –4.6 to +4.6 –4.0 to +3.8 –4.5 to +4.5 V

R

L

= –4.5 V to +4.5 V 45 30 mA

OUT

T

MIN–TMAX

45 30 mA

Short-Circuit Current Sourcing 100 60 mA

Sinking 160 100 mA

Capacitive Load Drive G = +1 (AD8051/AD8052) 50 pF

G = +2 (AD8054) 40 pF

POWER SUPPLY

Operating Range 3 12 3 12 V
Quiescent Current/Amplifier 4.8 5.5 2.875 3.4 mA
Power Supply Rejection Ratio ⌬VS = ±1 V 68 80 68 80 dB

OPERATING TEMPERATURE RANGE

RT –40 +85 °C
RM, RN-8, RU, R-14 –40 +125 –40 +125 °C

Specifications subject to change without notice.

REV. F

–5–

AD8051/AD8052/AD8054

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V

Internal Power Dissipation

2

1

Small Outline Package (RN) Observe Power Derating Curves

SOT-23-5 Package . . . . . . . Observe Power Derating Curves

MSOP Package . . . . . . . . . Observe Power Derating Curves

TSSOP-14 Package . . . . . . Observe Power Derating Curves

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 2.5 V

Output Short-Circuit Duration

. . . . . . . . . . . . . . . . . .Observe Power Derating Curves

Storage Temperature Range (RN) . . . . . . . . –65°C to +150°C

Operating Temperature Range (A Grade) . . –40°C to +125°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for device in free air:
8-Lead SOIC: ␪JA = 125°C/W
5-Lead SOT-23-5: ␪JA = 180°C/W
8-Lead MSOP: ␪JA = 150°C/W
14-Lead SOIC: ␪JA = 90°C/W
14-Lead TSSOP: ␪JA = 120°C/W

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8051/AD8052/AD8054 is limited by the associated rise in
junction temperature. The maximum safe junction temperature

for plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit may cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package. Exceeding a junction temperature of 175°C for
an extended period can result in device failure.

While the AD8051/AD8052/AD8054 are internally short-circuit
protected, this may not be sufficient to guarantee that the maxi­mum junction temperature (150°C) is not exceeded under all
conditions. To ensure proper operation, it is necessary to observe
the maximum power derating curves.

2.5

–35 –15

SOIC-14

SOIC-8

SOT-23-5

15 35 55 75 95 115

5

AMBIENT TEMPERATURE – ⴗC

2.0

TSSOP-14

1.5

1.0

MSOP-8

0.5

MAXIMUM POWER DISSIPATION – W

0

–55

Figure 2. Plot of Maximum Power Dissipation vs.
Temperature for AD8051/AD8052/AD8054

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8051/AD8052/AD8054 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

REV. F–6–

ORDERING GUIDE

AD8051/AD8052/AD8054

Temperature Package Package

Model Range Descriptions Options

1

Branding

AD8051AR –40°C to +125°C 8-Lead SOIC R-8
AD8051AR-REEL –40°C to +125°C 13" Tape and Reel R-8
AD8051AR-REEL7 –40°C to +125°C 7" Tape and Reel R-8
AD8051ARZ
AD8051ARZ-REEL

2

–40°C to +85°C 8-Lead SOIC R-8

2

–40°C to +85°C 13" Tape and Reel R-8

AD8051ARZ-REEL72–40°C to +85°C 7" Tape and Reel R-8
AD8051ART-REEL –40°C to +85°C 13" Tape and Reel RT-5 H2A
AD8051ART-REEL7 –40°C to +85°C 7" Tape and Reel RT-5 H2A
AD8051ART-R2 –40°C to +85°C 7" Tape and Reel RT-5 H2A
AD8051ARTZ-R2
AD8051ARTZ-REEL

2

–40°C to +85°C 7" Tape and Reel RT-5 H2A

2

–40°C to +85°C 13" Tape and Reel RT-5 H2A

AD8051ARTZ-REEL72–40°C to +85°C 7" Tape and Reel RT-5 H2A
AD8052AR –40°C to +125°C 8-Lead SOIC R-8

AD8052AR-REEL –40°C to +125°C 13" Tape and Reel R-8
AD8052AR-REEL7 –40°C to +125°C 7" Tape and Reel R-8
AD8052ARZ
AD8052ARZ-REEL
AD8052ARZ-REEL7

2

–40°C to +125°C 8-Lead SOIC R-8

2

–40°C to +125°C 13" Tape and Reel R-8

2

–40°C to +125°C 7" Tape and Reel R-8
AD8052ARM –40°C to +125°C 8-Lead MSOP RM-8 H4A
AD8052ARM-REEL –40°C to +125°C 13" Tape and Reel RM-8 H4A
AD8052ARM-REEL7 –40°C to +125°C 7" Tape and Reel RM-8 H4A
AD8052ARMZ-REEL72–40°C to +125°C 7" Tape and Reel RM-8 H4A

AD8054AR –40°C to +125°C 14-Lead SOIC R-14
AD8054AR-REEL –40°C to +125°C 13" Tape and Reel R-14
AD8054AR-REEL7 –40°C to +125°C 7" Tape and Reel R-14
AD8054ARZ
AD8054ARZ-REEL
AD8054ARZ-REEL7

2

–40°C to +125°C 14-Lead SOIC R-14

2

–40°C to +125°C 13" Tape and Reel R-14

2

–40°C to +125°C 7" Tape and Reel R-14
AD8054ARU –40°C to +125°C 14-Lead TSSOP RU-14
AD8054ARU-REEL –40°C to +125°C 13" Tape and Reel RU-14
AD8054ARU-REEL7 –40°C to +125°C 7" Tape and Reel RU-14
AD8054ARUZ
AD8054ARUZ-REEL

2

–40°C to +125°C 14-Lead TSSOP RU-14

2

–40°C to +125°C 13" Tape and Reel RU-14
AD8054ARUZ-REEL72–40°C to +125°C 7" Tape and Reel RU-14

NOTES

1

R = Small Outline; RM = MSOP; RT = SOT-23; RU = TSSOP.

2

Z = Pb-free part.

REV. F

–7–

AD8051/AD8052/AD8054

–Typical Performance Characteristics

3

2

1

0

–1

–2

–3

VS = +5V

–4

GAIN AS SHOWN

NORMALIZED GAIN – dB

R

–5

R
V

–6

–7

0.1 1 10 100

AS SHOWN

F

= 2k⍀

L

= 0.2V p-p

O

G = +10
R

= 2k⍀

F

G = +2
R

= 2k⍀

F

G = +5
R

= 2k⍀

F

FREQUENCY – MHz

G = +1

= 0

R

F

500

TPC 1. AD8051/AD8052 Normalized Gain vs.
Frequency; VS = +5 V

3

2

1

0

–1

–2

VS AS SHOWN
G = +1

GAIN – dB

–3

= 2k⍀

R

L

= 0.2V p-p

V

O

–4

–5

–6

–7

0.1 500110100
FREQUENCY – MHz

VS = +3V

VS = ⴞ5V

VS = +5V

TPC 2. AD8051/AD8052 Gain vs. Frequency
vs. Supply

5

VS = +5V

4

GAIN AS SHOWN

3

AS SHOWN

R

F

= 5k⍀

R

L

2

= 0.2V p-p

V

O

1

0

–1

–2

–3

NORMALIZED GAIN – dB

–4

–5

–6

–7

100k

1M

G = +10
R

= 2k⍀

F

G = +5
R

= 2k⍀

F

FREQUENCY – Hz

G = +2
R

= 2k⍀

F

10M 100M

G = +1
R

= 0

F

500M

TPC 4. AD8054 Normalized Gain vs. Frequency;
VS = +5 V

6

5

G = +1
R

4

C

3

V

2

1

GAIN – dB

0

–1

–2

–3

–4

100k

= 2k⍀

L

= 5pF

L

= 0.2V p-p

O

1M 10M 100M

FREQUENCY – Hz

+3V

+5V

ⴞ5V

ⴞ5V

+3V

+5V

500M

TPC 5. AD8054 Gain vs. Frequency vs. Supply

3

2

1

0

–1

–2

GAIN – dB

–3

VS = +5V

–4

G = +1

= 2k⍀

R

L

–5

= 0.2V p-p

V

O

TEMPERATURE AS SHOWN

–6

–7

0.1
FREQUENCY – MHz

–40ⴗC

+85ⴗC

+25ⴗC

500110100

TPC 3. AD8051/AD8052 Gain vs. Frequency vs.
Temperature

4

3

2

1

0

VS = +5V

–1

GAIN – dB

= 2k⍀ TO 2.5V

R

L

–2

C

= 5pF

L

G = +1

–3

V

= 0.2V p-p

O

–4

–5

110100

FREQUENCY – MHz

+85ⴗC

+25ⴗC

–40ⴗC

TPC 6. AD8054 Gain vs. Frequency vs.
Temperature

500

REV. F–8–

AD8051/AD8052/AD8054

g

80

40

–10

70

60

50

30

20

10

0

–20

30k 100k 1M 10M 100M

GAIN

PHASE

45ⴗ PHASE
MARGIN

VS = +5V
R

L

= 2k⍀

C

L

= 5pF

FREQUENCY – Hz

180

135

90

45

0

500M

OPEN-LOOP GAIN – dB

PHASE MARGIN – Degrees

6.3

6.2

6.1

6.0

5.9

5.8

0.1

VS = +5V
G = +2

= 150⍀

R

L

= 806⍀

R

F

= 0.2V p-p

V

O

110100

FREQUENCY – MHz

5.7

5.6

GAIN FLATNESS – dB

5.5

5.4

5.3

TPC 7. AD8051/AD8052 0.1 dB Gain Flatness vs.
Frequency; G = +2

9

VS = ⴞ5V
V

= 4V p-p

O

VS = +5V
V

= 2V p-p

O

8

7

6

5

4

GAIN – dB

3

VS AS SHOWN

2

G = +2

= 2k⍀

R

L

1

= 2k⍀

R

F

AS SHOWN

V

O

0

–1

0.1 500110100
FREQUENCY – MHz

TPC 8. AD8051/AD8052 Large Signal Frequency
Response; G = +2

6.3

6.2

6.1

6.0

5.9

5.8

VS = +5V

= 200⍀

R

5.7

5.6

GAIN FLATNESS – dB

5.5

5.4

5.3

F

= 150⍀

R

L

G = +2

= 0.2V p-p

V

O

1 10010

FREQUENCY – MHz

TPC 10. AD8054 0.1 dB Gain Flatness vs.
Frequency; G = +2

9

= 4V p-p

VS = +5V
V

= 2V p-p

O

8

7

6

5

4

GAIN – dB

3

VS AS SHOWN

2

G = +2

= 2k⍀

R

L

1

= 2k⍀

R

F

AS SHOWN

V

0

O

–1

0.1 500110100

VS = ⴞ5V
V

O

FREQUENCY – MHz

TPC 11. AD8054 Large Signal Frequency
Response; G = +2

80

70

60

50

40

30

20

10

OPEN-LOOP GAIN – dB

0

–10

REV. F

–20

0.01 5000.1 1 10 100

TPC 9. AD8051/AD8052 Open-Loop Gain and
Phase vs. Frequency

GAIN

PHASE

FREQUENCY – MHz

VS = +5V
R

= 2k⍀

L

50ⴗ PHASE
MARGIN

0

rees

–45

–90

–135

–180

PHASE MARGIN – De

–9–

TPC 12. AD8054 Open-Loop Gain and Phase
Margin vs. Frequency

AD8051/AD8052/AD8054

ⴚ20

VO = 2V p-p

ⴚ30

ⴚ40

VS = +5V, G = +1

ⴚ50

R

= 100⍀

L

ⴚ60

ⴚ70

ⴚ80

ⴚ90

TOTAL HARMONIC DISTORTION – dBc

ⴚ100

ⴚ110

12345

VS = +5V, G = +2

= 2k⍀, RL = 100⍀

R

F

VS = +5V, G = +2

= 2k⍀, RL = 2k⍀

R

F

FUNDAMENTAL FREQUENCY – MHz

VS = +3V, G = ⴚ1
R

= 2k⍀, RL = 100⍀

F

VS = +5V, G = +1

= 2k⍀

R

L

678910

TPC 13. Total Harmonic Distortion

ⴚ30

ⴚ40

ⴚ50

ⴚ60

ⴚ70

ⴚ80

ⴚ90

ⴚ100

ⴚ110

WORST HARMONIC – dBc

ⴚ120

ⴚ130

ⴚ140

0 5.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

10MHz

5MHz

1MHz

OUTPUT VOLTAGE – V p-p

VS = +5V

= 2k⍀

R

L

G = +2

TPC 14. Worst Harmonic vs. Output Voltage

4.5

1000

VS = +5V

Hz

100

10

VOLTAGE NOISE – nA/

1

10

1k

10k

FREQUENCY – Hz

100k

1M

TPC 16. Input Voltage Noise vs. Frequency

100

VS = +5V

10

1

CURRENT NOISE – pA/ Hz

0.1
10

1k

10k

FREQUENCY – Hz

100k

1M

TPC 17. Input Current Noise vs. Frequency

10M100

10M100

0.10
NTSC SUBSCRIBER (3.58MHz)

0.08

0.06

0.04

0.02

0.00

ⴚ

0.02

DIFFERENTIAL

DIFFERENTIAL

VS = +5, G = +2

GAIN ERROR – %

ⴚ

0.04

= 2k⍀, RL AS SHOWN

R

F

ⴚ0.06

0

10 6020 7030 8040 90

0.10

0.05

0.00

ⴚ0.05
ⴚ0.10

ⴚ0.15

VS = +5, G = +2

= 2k⍀, RL AS SHOWN

R

ⴚ0.20

F

ⴚ0.25

PHASE ERROR – Degrees

0

50

RL = 1k⍀

MODULATING RAMP LEVEL – IRE

RL = 150

RL = 1k

RL = 150⍀

⍀

⍀

TPC 15. AD8051/AD8052 Differential Gain and
Phase Errors

100

10050106020 7030 8040 90

0.10
NTSC SUBSCRIBER (3.58MHz)

0.05

0.00

GAIN – %

–0.05

VS = +5, G = +2

DIFFERENTIAL

R

F

–0.10

1st 6th2nd 7th3rd 8th4th 9th5th 10th 11th

0.3

0.2

0.1

0.0
VS = +5, G = +2

–0.1

R

DIFFERENTIAL

F

–0.2

PHASE – Degrees

R

L

–0.3

1st 6th2nd 7th3rd 8th4th 9th5th 10th 11th

= 2k⍀, RL AS SHOWN

= 2k⍀,
AS SHOWN

MODULATING RAMP LEVEL – IRE

RL = 1k⍀

RL = 150⍀

RL = 1k⍀

RL = 150⍀

TPC 18. AD8054 Differential Gain and
Phase Errors

REV. F–10–

AD8051/AD8052/AD8054

INPUT STEP – V p-p

60

0

40

30

20

10

50

70

0.5 21 1.5

SETTLING TIME TO 0.1%

ⴚ

ns

AD8051/AD8052

AD8054

VS = ⴙ5V
G = ⴚ1

R

L

= 2k

⍀

–10

VS = +5V

–20

R

= 2k⍀

F

= 2k⍀

R

L

–30

V

= 2V p-p

O

–40

–50

–60

–70

CROSSTALK – dB

–80

–90

–100

0.1
FREQUENCY – MHz

500110100

TPC 19. AD8052 Crosstalk (Output-to-Output) vs.
Frequency

0

VS = +5V

–10

–20

–30

–40

–50

–60

CMRR – dB

–70

–80

–90

–100

0.03 500

0.1 1 10 100
FREQUENCY – MHz

TPC 20. CMRR vs. Frequency

–10

–20

–30

–40

–50

–60

–70

CROSSTALK – dB

–80

–90

–100

–110

0.1

RL = 100⍀

RL = 1k⍀

110

FREQUENCY – MHz

VS = ⴞ5V
R

= 1k⍀

F

RL = AS SHOWN
VO = 2V p-p

100

500

TPC 22. AD8054 Crosstalk (Output-to-Output) vs.
Frequency

20

VS = +5V

10

0

–10

–20

–30

–40

PSRR – dB

–50

–60

–70

–80

–PSRR

+PSRR

1 50010 1000.10.01

FREQUENCY – MHz

TPC 23. PSRR vs. Frequency

100

31

10

3.1

1

0.31

0.1

OUTPUT RESISTANCE – ⍀

0.031

0.01

REV. F

0.1 1 10 100 500

TPC 21. Closed-Loop Output Resistance vs.
Frequency

VS = ⴙ5V

G = ⴙ1

FREQUENCY – MHz

TPC 24. Settling Time vs. Input Step

–11–

AD8051/AD8052/AD8054

1.00

0.90

0.80

0.70

0.60

0.50

0.40

0.30

0.20

0.10

OUTPUT SATURATION VOLTAGE – V

0

06551015202530354045 50 5560

VOH = +85ⴗC

VOH = +25ⴗC

VOH = –40ⴗC

LOAD CURRENT – mA

VOL = –40ⴗC

VS = +5V

VOL = +85ⴗC

VOL = +25ⴗC

70 75 80 85

TPC 25. AD8051/AD8052 Output Saturation
Voltage vs. Load Current

100

RL = 2k⍀

90

RL = 150⍀

80

1.000
VS = +5V

0.875

0.750

0.625

0.500

0.375

0.250

0.125

OUTPUT SATURATION VOLTAGE – V

0.00
0303691215 18 21 24 27

+5V – VOH (–40ⴗC)

LOAD CURRENT – mA

+5V – VOH (+125ⴗC)

+5V – VOH (+25ⴗC)

VOL (–40ⴗC)

VOL (+125ⴗC)

VOL (+25ⴗC)

TPC 27. AD8054 Output Saturation Voltage vs.
Load Current

OPEN-LOOP GAIN – dB

70

VS = +5V

60

0 5.0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

OUTPUT VOLTAGE – V

TPC 26. Open-Loop Gain vs. Output Voltage

REV. F–12–

AD8051/AD8052/AD8054

5

1.50

VOLTS

Figure 3. 100 mV Step Response, G = +1

2.60

2.50

VOLTS

2.40

20ns

Figure 4. AD8051/AD8052 200 mV Step
Response; VS = +5 V, G = +1

2.5

VOLTS

Figure 6. Output Swing; G = –1, RL = 2 k

2.55

2.50

VOLTS

2.45

Ω

Figure 7. AD8054 100 mV Step Response;
VS = +5 V, G = +1

4.5

3.5

2.5

VOLTS

1.5

0.5

500mV

20ns

Figure 5. Large Signal Step Response; VS = +5 V, G = +2

4

3

2

1

VOLTS

ⴚ1

ⴚ2

ⴚ3

ⴚ4

Figure 8. Large Signal Step Response;
VS = ±5 V, G = +1

REV. F

–13–

AD8051/AD8052/AD8054

Overdrive Recovery

Overdrive of an amplifier occurs when the output and/or input
range is exceeded. The amplifier must recover from this overdrive
condition. As shown in Figure 9, the AD8051/AD8052/AD8054
recovers within 60 ns from negative overdrive and within 45 ns
from positive overdrive.

2.60

2.55

2.50

VOLTS

2.45

2.40

VOLTS

Figure 9. Overdrive Recovery

Driving Capacitive Loads

Consider the AD8051/AD8052 in a closed-loop gain of +1 with
+V

= 5 V and a load of 2 kΩ in parallel with 50 pF. Figures 10

S

and 11 show its frequency and time domain responses, respec­tively, to a small-signal excitation. The capacitive load drive of
the AD8051/AD8052/AD8054 can be increased by adding a
low value resistor in series with the load. Figures 12 and 13
show the effect of a series resistor on the capacitive drive for
varying voltage gains. As the closed-loop gain is increased, the
larger phase margin allows for larger capacitive loads with less
peaking. Adding a series resistor with lower closed-loop gains
accomplishes the same effect. For large capacitive loads, the
frequency response of the amplifier will be dominated by the
roll-off of the series resistor and the load capacitance.

8

6

4

2

0

ⴚ2

GAIN – dB

ⴚ4

VS = +5V

ⴚ6

G = +1
R

= 2k⍀

L

ⴚ8

C

= 50pF

L

V

= 200mV p-p

O

ⴚ10

0.1 1 10 100
FREQUENCY – MHz

500

Figure 10. AD8051/AD8052 Closed-Loop
Frequency Response: C

= 50 pF

L

Figure 11. AD8051/AD8052 200 mV Step
Response: C

10000

VS = +5V
ⱕ 30%

OVERSHOOT

1000

100

CAPACITIVE LOAD ⴚ pF

10

1

162

= 50 pF

L

RS = 3⍀

⍀

RS = 0

R

R

G

F

V

IN

100mV STEP

⍀

50

345

– V/V

A

CL

R

S

V

OUT

C

L

Figure 12. AD8051/AD8052 Capacitive Load Drive
vs. Closed-Loop Gain

1000

VS = +5V
ⱕ 30%

OVERSHOOT

RS = 10⍀

R

50⍀

RS = 0⍀

R

G

F

R

S

V

OUT

C

L

100

CAPACITIVE LOAD – pF

10

162 345

V

IN

100mV STEP

ACL – V/V

Figure 13. AD8054 Capacitive Load Drive vs.
Closed-Loop Gain

Circuit Description

The AD8051/AD8052/AD8054 is fabricated on the Analog Devices
proprietary eXtra-Fast Complementary Bipolar (XFCB) process,
which enables the construction of PNP and NPN transistors
with similar f

s in the 2 GHz to 4 GHz region. The process is

T

dielectrically isolated to eliminate the parasitic and latch-up

REV. F–14–

AD8051/AD8052/AD8054

problems caused by junction isolation. These features allow the
construction of high frequency, low distortion amplifiers with
low supply currents. This design uses a differential output input
stage to maximize bandwidth and headroom (see Figure 14).
The smaller signal swings required on the first stage outputs (nodes
SIP, SIN) reduce the effect of nonlinear currents due to junction
capacitances and improve the distortion performance. This
design achieves harmonic distortion of –80 dBc @ 1 MHz into
100 Ω with V

= 2 V p-p (Gain = +1) on a single 5 V supply.

OUT

The inputs of the device can handle voltages from –0.2 V below
the negative rail to within 1 V of the positive rail. Exceeding
these values will not cause phase reversal; however, the input
ESD devices will begin to conduct if the input voltages exceed
the rails by greater than 0.5 V. During this overdrive condition,
the output stays at the rail.

The rail-to-rail output range of the AD8051/AD8052/AD8054
is provided by a complementary common-emitter output stage.
High output drive capability is provided by injecting all output
stage predriver currents directly into the bases of the output
devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by
I8 and I5, along with a common-mode feedback loop (not shown).
This circuit topology allows the AD8051/AD8052 to drive 45 mA
of output current and allows the AD8054 to drive 30 mA of
output current with the outputs within 0.5 V of the supply rails.

V

VINP

VINN

V

CC

R26

Q4

R2

R15

Q1

Q13

Q2

C7

EE

Q40

R5

V

SIP

I10

R39

Q5

EE

SIN

Q11

Q3

R21

I2 I3

Q22

R3

Q25

Q39

Q51

R27

R23

Q7

Q21 Q27

Q24 Q47

I7

Q50

Q31

Q23

I11

I9

Q36

I5

V

EE

C3

V

OUT

C9

Q8

I8

V

CC

Figure 14. AD8051/AD8052 Simplified Schematic

APPLICATIONS
Layout Considerations

The specified high speed performance of the AD8051/AD8052/
AD8054 requires careful attention to board layout and compo­nent selection. Proper RF design techniques and low parasitic
component selection are necessary.

The PCB should have a ground plane covering all unused portions
of the component side of the board to provide a low impedance
path. The ground plane should be removed from the area near
the input pins to reduce parasitic capacitance.

Chip capacitors should be used for supply bypassing. One end
should be connected to the ground plane and the other within
3 mm of each power pin. An additional large (4.7 µF to 10 µF)
tantalum electrolytic capacitor should be connected in parallel,
but not necessarily so close, to supply current for fast, large
signal changes at the output.

The feedback resistor should be located close to the inverting
input pin to keep the parasitic capacitance at this node to a

minimum. Parasitic capacitance of less than 1 pF at the inverting
input can significantly affect high speed performance.

Stripline design techniques should be used for long signal traces
(greater than about 25 mm). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly
terminated at each end.

Active Filters

Active filters at higher frequencies require wider bandwidth
op amps to work effectively. Excessive phase shift produced by
lower frequency op amps can significantly impact active filter
performance.

Figure 15 shows an example of a 2 MHz biquad bandwidth
filter that uses three op amps of an AD8054. Such circuits are
sometimes used in medical ultrasound systems to lower the
noise bandwidth of the analog signal before A/D conversion.

Note that the unused amplifier’s inputs should be tied to
ground.

R6

1k⍀

C1

50pF

8

13

12

BAND-PASS
FILTER OUTPUT

14

R2

2k⍀

R1

3k⍀

V

IN

2

3

1

AD8054

2k⍀

R4

2k⍀

R3

6

5

AD8054

2k⍀

7

C2

50pF

R5

9

10

AD8054

Figure 15. 2 MHz Biquad Band-Pass Filter Using AD8054

The frequency response of the circuit is shown in Figure 16.

0

ⴚ10

ⴚ20

GAIN – dB

ⴚ30

ⴚ40

10k 100M100k 1M 10M

FREQUENCY – Hz

Figure 16. Frequency Response of 2 MHz Band­Pass Biquad Filter

A/D and D/A Applications

Figure 17 is a schematic showing the AD8051 used as a driver for
an AD9201, a 10-bit 20 MSPS dual A/D converter. This converter
is designed to convert I and Q signals in communications systems.
In this application, only the I channel is being driven. The I chan­nel is enabled by applying a logic HIGH to SELECT, Pin 13.

The AD8051 is running from a dual supply and is configured
for a gain of +2. The input signal is terminated in 50 Ω and the

REV. F

–15–

AD8051/AD8052/AD8054

0.33␮F

50⍀

+5V

AD8051

0.1␮F

10␮F

0.01␮F

22⍀

1k⍀

22⍀

0.1␮F

0.1␮F

1k⍀

ⴚ5V

0.1␮F

10␮F

ⴙ5V

10␮F

10␮F 0.1␮F

1k⍀

0.1␮F

Figure 17. AD8051 Driving an AD9201, a 10-Bit 20 MSPS A/D Converter

output is 2 V p-p, which is the maximum input range of the
AD9201. The 22 Ω series resistor limits the maximum current
that flows and helps to lower the distortion of the A/D.

The AD9201 has differential inputs for each channel. These are
designated the A and B inputs. The B inputs of each channel are
connected to VREF (Pin 22), which supplies a positive reference
of 2.5 V. Each of the B inputs has a small low-pass filter that also
helps to reduce distortion.

The output of the op amp is ac-coupled into INA-I (Pin 16)
via two parallel capacitors to provide good high frequency and
low frequency coupling. The 1 kΩ resistor references the signal
to VREF that is applied to INB-I. Thus, INA-I swings both
positive and negative with respect to the bias voltage applied
to INB-I.

22⍀

0.1␮F

10pF

10pF

0.1␮F10␮F

0.1␮F10␮F0.1␮F

SLEEP

INA-I

INB- I

AD9201

REFT-I

REFB- I

AVSS

REFSENSE

VREF

AVDD

REFB-Q

REFT-Q

CLK

SELECT

ⴙV

DD

D9

DATA OUT

D8

D7

D6

D5

D4

D3

D2

D1

D0

22⍀

22⍀

10pF

10pF

INB-Q

INA-Q

CHIP–SELECT

DVDD

DVSS

ⴙ5V

10␮F0.1␮F

With the sampling clock running at 20 MSPS, the A/D output
was analyzed with a digital analyzer. Two input frequencies
were used, 1 MHz and 9.5 MHz, which is just short of the
Nyquist frequency. These signals were well filtered to minimize
any harmonics.

Figure 18 shows the FFT response of the A/D for the case of
a 1 MHz analog input. The SFDR is –71.66 dB and the A/D is
producing 8.8 ENOB (effective number of bits). When the analog
frequency was raised to 9.5 MHz, the SFDR was reduced to
–60.18 dB and the A/D operated with 8.46 ENOBs as shown in
Figure 19. The inclusion of the AD8051 in the circuit did not
worsen the distortion performance of the AD9201.

10

FUND

0

ⴚ10

ⴚ20

ⴚ30

ⴚ40

ⴚ50

ⴚ60

AMPLITUDE – dB

ⴚ70

ⴚ80

ⴚ90

ⴚ100

ⴚ110

ⴚ120

0 12345678910

2ND

3RD

4TH

5TH

FREQUENCY – MHz

7TH

6TH

9TH

8TH

Figure 18. FFT Plot for AD8051 Driving the AD9201
at 1 MHz

PART# 0

FFTSIZE 8192

FCLK

FUND

VIN

THD

SNR

SINAD

ENOB

SFDR

2ND

3RD

4TH

5TH

6TH

7TH

8TH

9TH

20.0MHz

998.5kHz

ⴚ0.51dB

ⴚ68.13

54.97

54.76

8.80

71.66

ⴚ74.53

ⴚ76.06

ⴚ76.35

ⴚ79.05

ⴚ80.36

ⴚ75.08

ⴚ88.12

ⴚ77.87

10

0

ⴚ10

ⴚ20

ⴚ30

ⴚ40

ⴚ50

2ND

ⴚ60

AMPLITUDE – dB

ⴚ70

6TH

ⴚ80

ⴚ90

ⴚ100

ⴚ110

ⴚ120

012345678910

4TH

8TH

7TH

–

FUND

3RD

Figure 19. FFT Plot for AD8051 Driving the AD9201
at 9.5 MHz

PART#

FFTSIZE 8192

FCLK

FUND

VIN

THD

SNR

SINAD

ENOB

SFDR

2ND

3RD

4TH

5TH

6TH

7TH

8TH

9TH

REV. F–16–

0

20.0MHz

9.5MHz

ⴚ0.44dB

ⴚ57.08

54.65

52.69

8.46

60.18

ⴚ60.18

ⴚ60.23

ⴚ82.01

ⴚ78.83

ⴚ81.28

ⴚ77.28

ⴚ84.54

ⴚ92.78

AD8051/AD8052/AD8054

Sync Stripper

Synchronizing pulses are sometimes carried on video signals so
as not to require a separate channel to carry the synchronizing
information. However, for some functions, such as A/D conversion,
it is not desirable to have the sync pulses on the video signal.
These pulses reduce the dynamic range of the video signal and
do not provide any useful information for such a function.

A sync stripper removes the synchronizing pulses from a video
signal while passing all the useful video information. Figure 20
shows a practical single-supply circuit that uses only a single
AD8051. It is capable of directly driving a reverse terminated
video line.

VIDEO WITHOUT SYNC

+

R2

1k⍀

0.1␮F

10␮F

100⍀

GROUND

TO A/D

V

BLANK

GROUND

VIDEO WITH SYNC

V

IN

(OR 2 ⴛ V

+0.8V

+0.4V

AD8051

R1
1k⍀

BLANK

+3V OR +5V

)

Figure 20. Sync Stripper

The video signal plus sync is applied to the noninverting input
with the proper termination. The amplifier gain is set to 2 via
the two 1 kΩ resistors in the feedback circuit. A bias voltage
must be applied to R1 so that the input signal has the sync pulses
stripped at the proper level.

The blanking level of the input video pulse is the desired place
to remove the sync information. This level is multiplied by 2 by
the amplifier. This level must be at ground at the output for the
sync stripping action to take place. Since the gain of the ampli­fier from the input of R1 to the output is –1, a voltage equal to
2 × V

must be applied to make the blanking level come

BLANK

out at ground.

Single-Supply Composite Video Line Driver

Many composite video signals have their blanking level at ground
and have video information that is both positive and negative.
Such signals require dual-supply amplifiers to pass them. However,
by ac level shifting, a single-supply amplifier can be used to
pass these signals. The following complications may arise from
such techniques.

Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capacity than their (bounded)
peak-to-peak amplitude after they are ac-coupled. As a worst case,
the dynamic signal swing will approach twice the peak-to-peak
value. The two conditions that define the maximum dynamic swing
requirements are a signal that is mostly low but goes high with a

duty cycle that is a small fraction of a percent, and the other
extreme defined by the opposite condition.

The worst case of composite video is not quite this demanding.
One bounding condition is a signal that is mostly black for an
entire frame but has a white (full amplitude) minimum width
spike at least once in a frame.

The other extreme is for a full white video signal. The blanking
intervals and sync tips of such a signal have negative-going
excursions in compliance with the composite video specifications.
The combination of horizontal and vertical blanking intervals
limit such a signal to being at the highest (white) level for a
maximum of about 75% of the time.

As a result of the duty cycles between the two extremes presented
above, a 1 V p-p composite video signal that is multiplied by a
gain of +2 requires about 3.2 V p-p of dynamic voltage swing at
the output for an op amp to pass a composite video signal of
arbitrarily varying duty cycle without distortion.

Some circuits use a sync tip clamp to hold the sync tips at a relatively
constant level to lower the amount of dynamic signal swing
required. However, these circuits can have artifacts such as sync
tip compression unless they are driven by a source with a very
low output impedance. The AD8051/AD8052/AD8054 have
adequate signal swing when running on a single 5 V supply to handle
an ac-coupled composite video signal.

The input to the circuit in Figure 21 is a standard composite
(1 V p-p) video signal that has the blanking level at ground. The
input network level shifts the video signal by means of ac coupling.
The noninverting input of the op amp is biased to half of the
supply voltage.

The feedback circuit provides unity gain for the dc-biasing of
the input and provides a gain of 2 for any signals that are in the
video bandwidth. The output is ac-coupled and terminated to
drive the line.

The capacitor values were selected for providing minimum tilt
or field time distortion of the video signal. These values would
be required for video that is considered to be studio or broadcast
quality. However, if a lower consumer grade of video, sometimes
referred to as consumer video, is all that is desired, the values and
the cost of the capacitors can be reduced by as much as a factor
of five with minimum visible degradation in the picture.

+5V

4.99k⍀

+

1k⍀

10k⍀

R

G

10␮F

AD8051

220␮F

R

1k⍀

0.1␮F

F

+

1000␮F

+

0.1␮F

10␮F

R

75⍀

BT

V

OUT

R

L

75⍀

COMPOSITE

VIDEO

IN

75⍀

R

T

4.99k⍀

47␮F

+

Figure 21. Single-Supply Composite Video Line Driver

REV. F

–17–

AD8051/AD8052/AD8054

OUTLINE DIMENSIONS

14-Lead Standard Small Outline Package [SOIC]

Narrow Body

(R-14)

Dimensions shown in millimeters and (inches)

8.75 (0.3445)

8.55 (0.3366)

4.00 (0.1575)

3.80 (0.1496)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

14

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.10

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-012AB

8

6.20 (0.2441)

7

5.80 (0.2283)

SEATING
PLANE

1.75 (0.0689)

1.35 (0.0531)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

8ⴗ
0ⴗ

1.27 (0.0500)

0.40 (0.0157)

ⴛ 45ⴗ

5-Lead Small Outline Transistor Package [SOT-23]

(RT-5)

Dimensions shown in millimeters

2.90 BSC

4 5

0.50

0.30

2.80 BSC

0.95 BSC

1.45 MAX

SEATING
PLANE

0.22

0.08
10ⴗ

5ⴗ
0ⴗ

1.60 BSC

1.30

1.15

0.90

0.15 MAX

1 3

2

PIN 1

1.90
BSC

COMPLIANT TO JEDEC STANDARDS MO-178AA

0.60

0.45

0.30

8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

3.00
BSC

85

3.00
BSC

1

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187AA

BSC

4

SEATING
PLANE

4.90

1.10 MAX

0.23

0.08

8ⴗ
0ⴗ

0.80

0.60

0.40

8-Lead Standard Small Outline Package [SOIC]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

85

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

BSC

6.20 (0.2440)

5.80 (0.2284)

41

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8ⴗ
0ⴗ

1.27 (0.0500)

0.40 (0.0157)

ⴛ 45ⴗ

REV. F–18–

AD8051/AD8052/AD8054

OUTLINE DIMENSIONS

14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

5.10

5.00

4.90

1.05

1.00

0.80

4.50

4.40

4.30

PIN 1

14

0.65
BSC

0.15

0.05

COMPLIANT TO JEDEC STANDARDS MO-153AB-1

0.30

0.19

8

6.40

BSC

71

1.20
MAX

SEATING
PLANE

0.20

0.09

COPLANARITY

0.10

ⴗ

8

ⴗ

0

0.75

0.60

0.45

REV. F

–19–

AD8051/AD8052/AD8054

Revision History

Location Page

9/04—Data Sheet changed from REV. E to REV. F.

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Changes to Figure 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3/04—Data Sheet changed from REV. D to REV. E.

Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2/03—Data Sheet changed from REV. C to REV. D.

Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1/03—Data Sheet changed from REV. B to REV. C.

Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Changes to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

C01062–0–9/04(F)

–20–

REV. F