Datasheet AD8042AR-REEL7, AD8042AR-REEL, AD8042AR, AD8042AN, AD8042ACHIPS Datasheet (Analog Devices)

OUT1

–IN1

+IN1

–V

S

OUT2

+V

S

–IN2

+IN2

1

2

3

4

8

7

6

5

AD8042

Dual 160 MHz

a

FEATURES
Single AD8041 and Quad AD8044 also Available
Fully Specified at +3 V, +5 V, and ⴞ5 V Supplies
Output Swings to Within 30 mV of Either Rail
Input Voltage Range Extends 200 mV Below Ground
No Phase Reversal with Inputs 0.5 V Beyond Supplies
Low Power of 5.2 mA per Amplifier
High Speed and Fast Settling on +5 V:

160 MHz –3 dB Bandwidth (G = +1)
200 V/␮s Slew Rate
39 ns Settling Time to 0.1%

Good Video Specifications (R

Gain Flatness of 0.1 dB to 14 MHz

0.02% Differential Gain Error

0.04ⴗ Differential Phase Error

Low Distortion

–64 dBc Worst Harmonic @ 10 MHz

Drives 50 mA 0.5 V from Supply Rails

APPLICATIONS
Video Switchers
Distribution Amplifiers
A/D Driver
Professional Cameras
CCD Imaging Systems
Ultrasound Equipment (Multichannel)

PRODUCT DESCRIPTION

The AD8042 is a low power voltage feedback, high speed am-

plifier designed to operate on +3 V, +5 V or ±5 V supplies. It

has true single supply capability with an input voltage range
extending 200 mV below the negative rail and within 1 V of the
positive rail.

5V

2.5V

0V

1V

Figure 1. Output Swing: Gain = –1, VS = +5 V

= 150 ⍀, G = +2)

L

G = 1
RL = 2kV TO +2.5V

1ms

Rail-to-Rail Amplifier

AD8042

CONNECTION DIAGRAM

8-Lead Plastic DIP and SOIC

The output voltage swing extends to within 30 mV of each rail,
providing the maximum output dynamic range. Additionally, it
features gain flatness of 0.1 dB to 14 MHz while offering differ-

ential gain and phase error of 0.04% and 0.06° on a single +5 V

supply. This makes the AD8042 useful for professional video
electronics such as cameras, video switchers or any high speed
portable equipment. The AD8042’s low distortion and fast
settling make it ideal for buffering single supply, high speed
A-to-D converters.

The AD8042 offers low power supply current of 12 mA max
and can run on a single +3.3 V power supply. These features are
ideally suited for portable and battery powered applications
where size and power are critical.

The wide bandwidth of 160 MHz along with 200 V/µs of slew

rate on a single +5 V supply make the AD8042 useful in many
general purpose, high speed applications where single supplies

from +3.3 V to +12 V and dual power supplies of up to ±6 V

are needed. The AD8042 is available in 8-lead plastic DIP and
SOIC.

15

VS = +5V

12

G = +1
C

= 5pF

L

9

= 2kV TO 2.5V

R

L

6
3

0

–3
–6

CLOSED–LOOP GAIN – dB

–9
–12

–15

1 10 100 500

Figure 2. Frequency Response

FREQUENCY – MHz

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD8042–SPECIFICATIONS

(@ TA = +25ⴗC, VS = +5 V, RL = 2 k⍀ to 2.5 V, unless otherwise noted)

AD8042A

Parameter Conditions Min Typ Max Units

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth, V
Bandwidth for 0.1 dB Flatness G = +2, R
Slew Rate G = –1, V
Full Power Response V
Settling Time to 1% G = –1, V

< 0.5 V p-p G = +1 125 160 MHz

O

= 2 V p-p 30 MHz

O

= 150 Ω. RF = 200 Ω 14 MHz

L

= 2 V Step 130 200 V/µs

O

= 2 V Step 26 ns

O

Settling Time to 0.1% 39 ns

NOISE/DISTORTION PERFORMANCE

Total Harmonic Distortion f

= 5 MHz, VO = 2 V p-p, G = +2, R

C

= 1 kΩ –73 dB

L

Input Voltage Noise f = 10 kHz 15 nV/√Hz
Input Current Noise f = 10 kHz 700 fA/√Hz

Differential Gain Error (NTSC, 100 IRE) G = +2, R

G = +2, R

Differential Phase Error (NTSC, 100 IRE) G = +2, R

G = +2, R

Worst Case Crosstalk f = 5 MHz, R

= 150 Ω to 2.5 V 0.04 0.06 %

L

= 75 Ω to 2.5 V 0.04 %

L

= 150 Ω to 2.5 V 0.06 0.12 Degrees

L

= 75 Ω to 2.5 V 0.24 Degrees

L

= 150 Ω to 2.5 V –63 dB

L

DC PERFORMANCE

Input Offset Voltage 39mV

T

MIN–TMAX

12 mV

Offset Drift 12 µV/°C
Input Bias Current 1.2 3.2 µA

T

MIN–TMAX

4.8 µA

Input Offset Current 0.2 0.5 µA

Open-Loop Gain R

= 1 kΩ 90 100 dB

L

T

MIN–TMAX

90 dB

INPUT CHARACTERISTICS

Input Resistance 300 kΩ

Input Capacitance 1.5 pF
Input Common-Mode Voltage Range –0.2 to 4 V
Common-Mode Rejection Ratio VCM = 0 V to 3.5 V 68 74 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing R

Output Voltage Swing: R
Output Voltage Swing: R

Output Current T

= 10 kΩ to 2.5 V 0.03 to 4.97 V

L

= 1 kΩ to 2.5 V 0.10 to 4.9 0.05 to 4.95 V

L

= 50 Ω to 2.5 V 0.4 to 4.4 0.36 to 4.45 V

L

MIN

to T

MAX, VOUT

= 0.5 V to 4.5 V 50 mA

Short Circuit Current Sourcing 90 mA

Sinking 100 mA

Capacitive Load Drive G = +1 20 pF

POWER SUPPLY

Operating Range 312V
Quiescent Current (Per Amplifier) 5.2 6 mA
Power Supply Rejection Ratio VS– = 0 V to –1 V, or VS+ = +5 V to +6 V 72 80 dB

OPERATING TEMPERATURE RANGE –40 +85 °C

Specifications subject to change without notice.

REV. A–2–

AD8042

SPECIFICATIONS

Parameter Conditions Min Typ Max Units

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth, V
Bandwidth for 0.1 dB Flatness G = +2, R
Slew Rate G = –1, V
Full Power Response V
Settling Time to 1% G = –1, V
Settling Time to 0.1% 45 ns

NOISE/DISTORTION PERFORMANCE

Total Harmonic Distortion f

Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 10 kHz 500 fA/√Hz

Differential Gain Error (NTSC, 100 IRE) G = +2, R

Differential Phase Error (NTSC, 100 IRE) G = +2, R

Worst Case Crosstalk f = 5 MHz, R

DC PERFORMANCE

Input Offset Voltage 39mV

Offset Drift 12 µV/°C
Input Bias Current 1.2 3.2 µA

Input Offset Current 0.2 0.6 µA

Open-Loop Gain R

INPUT CHARACTERISTICS

Input Resistance 300 kΩ

Input Capacitance 1.5 pF
Input Common-Mode Voltage Range –0.2 to 2 V
Common-Mode Rejection Ratio VCM = 0 V to 1.5 V 66 74 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing R

Output Voltage Swing: R
Output Voltage Swing: R

Output Current T
Short Circuit Current Sourcing 50 mA

Capacitive Load Drive G = +1 17 pF

POWER SUPPLY

Operating Range 312V
Quiescent Current (Per Amplifier) 5.0 6 mA
Power Supply Rejection Ratio VS– = 0 V to –1 V, or VS+ = +3 V to +4 V 68 80 dB

OPERATING TEMPERATURE RANGE 0 +70 °C

Specifications subject to change without notice.

(@ TA = +25ⴗC, VS = +3 V, RL = 2 k⍀ to 1.5 V, unless otherwise noted)

AD8042A

< 0.5 V p-p G = +1 120 140 MHz

O

= 2 V p-p 25 MHz

O

= 5 MHz, VO = 2 V p-p, G = –1, R

C

R

= 75 Ω to 1.5 V, Input V

L

R

= 75 Ω to 1.5 V, Input V

L

T

MIN–TMAX

T

MIN–TMAX

= 1 kΩ 90 100 dB

L

T

MIN–TMAX

= 10 kΩ to 1.5 V 0.03 to 2.97 V

L

= 1 kΩ to 1.5 V 0.1 to 2.9 0.05 to 2.95 V

L

= 50 Ω to 1.5 V 0.3 to 2.6 0.25 to 2.65 V

L

MIN

Sinking 70 mA

= 150 Ω, RF = 200 Ω 11 MHz

L

= 2 V Step 120 170 V/µs

O

= 1 V Step 30 ns

O

= 100 Ω –56 dB

L

= 150 Ω to 1.5 V, Input V

L

= 150 Ω to 1.5 V, Input V

L

= 1 kΩ to 1.5 V –68 dB

L

CM

CM

= 1 V 0.10 %

CM

= 1 V 0.10 %

= 1 V 0.12 Degrees

CM

= 1 V 0.27 Degrees

90 dB

to T

MAX, VOUT

= 0.5 V to 2.5 V 50 mA

12 mV

4.8 µA

REV. A –3–

AD8042–SPECIFICATIONS

(@ TA = +25ⴗC, VS = ⴞ5 V, RL = 2 k⍀ to 0 V, unless otherwise noted)

AD8042A

Parameter Conditions Min Typ Max Units

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth, V
Bandwidth for 0.1 dB Flatness G = +2, R
Slew Rate G = –1, V
Full Power Response V
Settling Time to 1% G = –1, V

< 0.5 V p-p G = +1 125 170 MHz

O

= 2 V p-p 35 MHz

O

= 150 Ω, RF = 200 Ω 18 MHz

L

= 2 V Step 145 225 V/µs

O

= 2 V Step 22 ns

O

Settling Time to 0.1% 32 ns

NOISE/DISTORTION PERFORMANCE

Total Harmonic Distortion f

= 5 MHz, VO = 2 V p-p, G = +2, R

C

= 1 kΩ –78 dB

L

Input Voltage Noise f = 10 kHz 15 nV/√Hz
Input Current Noise f = 10 kHz 700 fA/√Hz

Differential Gain Error (NTSC, 100 IRE) G = +2, R

G = +2, R

Differential Phase Error (NTSC, 100 IRE) G = +2, R

G = +2, R

Worst Case Crosstalk f = 5 MHz, R

= 150 Ω 0.02 0.05 %

L

= 75 Ω 0.02 %

L

= 150 Ω 0.04 0.10 Degrees

L

= 75 Ω 0.12 Degrees

L

= 150 Ω –63 dB

L

DC PERFORMANCE

Input Offset Voltage 3 9.8 mV

T

MIN–TMAX

14 mV

Offset Drift 12 µV/°C
Input Bias Current 1.2 3.2 µA

T

MIN–TMAX

4.8 µA

Input Offset Current 0.2 0.6 µA

Open-Loop Gain R

= 1 kΩ 90 94 dB

L

T

MIN–TMAX

86 dB

INPUT CHARACTERISTICS

Input Resistance 300 kΩ

Input Capacitance 1.5 pF
Input Common-Mode Voltage Range –5.2 to 4 V
Common-Mode Rejection Ratio VCM = –5 V to 3.5 V 66 74 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing R

Output Voltage Swing: R
Output Voltage Swing: R

Output Current T

= 10 kΩ –4.97 to +4.97 V

L

= 1 kΩ –4.8 to +4.8 –4.9 to +4.9 V

L

= 50 Ω –4 to +3.2 –4.2 to +3.5 V

L

MIN

to T

MAX, VOUT

= –4.5 V to 4.5 V 50 mA

Short Circuit Current Sourcing 100 mA

Sinking 100 mA

Capacitive Load Drive G = +1 25 pF

POWER SUPPLY

Operating Range 312V
Quiescent Current (Per Amplifier) 67mA
Power Supply Rejection Ratio VS– = –5 V to –6 V, or VS+ = +5 V to +6 V 68 80 dB

OPERATING TEMPERATURE RANGE

Specifications subject to change without notice.

–40 +85 °C

REV. A–4–

AD8042

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12.6 V

Internal Power Dissipation

2

1

Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . 1.3 Watts

Small Outline Package (R) . . . . . . . . . . . . . . . . . . 0.9 Watts

Input Voltage (Common Mode) . . . . . . . . . . . . . . ±V

± 0.5 V

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±3.4 V

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves

Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for the device in free air:

8-Lead Plastic DIP Package: θJA = 90°C/W
8-Lead SOIC Package: θJA = 155°C/W

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8042 is limited by the associated rise in junction tempera­ture. The maximum safe junction temperature for plastic encap­sulated devices is determined by the glass transition temperature

of the plastic, approximately +150°C. Exceeding this limit tem-

porarily may cause a shift in parametric performance due to a
change in the stresses exerted on the die by the package.

Exceeding a junction temperature of +175°C for an extended

period can result in device failure.

While the AD8042 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction

temperature (+150°C) is not exceeded under all conditions.

To ensure proper operation, it is necessary to observe the
maximum power derating curves.

2.0
8-LEAD PLASTIC-DIP PACKAGE

TJ = +1508C

1.5

1.0

0.5

MAXIMUM POWER DISSIPATION – Watts

0
–50 90–40 –30 –20 –10 0 10 20 30 50 60 70 8040

8-LEAD SOIC PACKAGE

AMBIENT TEMPERATURE – 8C

Figure 3. Maximum Power Dissipation vs. Temperature

ORDERING GUIDE

Supply Temperature Package Package

Model Voltages Range Description Option

AD8042AN +5 V, ±5 V –40°C to +85°C 8-Lead Plastic DIP N-8
AD8042AN +3 V 0°C to +70°C 8-Lead Plastic DIP N-8
AD8042AR +5 V, ±5 V –40°C to +85°C 8-Lead Plastic SOIC SO-8
AD8042AR +3 V 0°C to +70°C 8-Lead Plastic SOIC SO-8
AD8042AR-REEL –40°C to +85°C 13" Tape and REEL SO-8
AD8042AR-REEL7 –40°C to +85°C 7" Tape and REEL SO-8
AD8042ACHIPS –40°C to +85°CDie

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8042 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. A –5–

AD8042–Typical Performance Characteristics

LOAD RESISTANCE – V

100

70

95

90

85

80

75

0 2000250 500 750 1000 1250 1500 1750

VS = +5V
T = +258C

OPEN-LOOP GAIN – dB

OUTPUT VOLTAGE – Volts

100

70

40

90

80

60

50

050.5 1 1.5 2 2.5 3 3.5 4 4.5

RL = 500V TO 2.5V

VS = +5V

RL = 50V TO 2.5V

OPEN-LOOP GAIN – dB

100

90

80

70

60

50

40

FREQUENCY

30

20

10

0

–6 6–5 –4 –3 –2 –1 0 1 2 3 4 5

VS = +5V
T = +258C
140 PARTS, SIDE A & B
MEAN = –1.52mV
STD DEVIATION = 1.15
SAMPLE SIZE = 280
(140 AD8042S)

V

– mV

Figure 4. Typical Distribution of V

30

VS = +5V

25

20

15

FREQUENCY

10

5

0

–18 –4–16

–14 –12 0–8 –6 –2

V

MEAN = –12.6mV/8C
STD DEV = 2.02mV/8C
SAMPLE SIZE = 60

–10
DRIFT – mV/8C

OS

Figure 7. Open-Loop Gain vs. RL to +2.5 V

100

98

96

94

92

90

OPEN-LOOP GAIN – dB

88

86

–40 –20 0 20 40 60 80

VS = +5V
RL = 1kV

TEMPERATURE – 8C

INPUT BIAS CURRENT – mA

Figure 5. VOS Drift Over –40°C to +85°C

0

–0.2

–0.4
–0.6

–0.8

–1

–1.2

–1.4

–1.6

–1.8

–2

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

TEMPERATURE – 8C

V
V

Figure 6. IB vs. Temperature

= +5V

S
CM

Figure 8. Open-Loop Gain vs. Temperature

= 0V

90

Figure 9. Open-Loop Gain vs. Output Voltage

–6– REV. A

300

MODULATING RAMP LEVEL – IRE

0.04

0.03

0 10030

0.02

0.00

0.01

20

60 70 80 9010 40 50

–0.01

DIFFERENTIAL

PHASE ERROR – deg

0.01

0.03

0.02

0

0.04

–0.01

0.05

DIFFERENTIAL

GAIN ERROR – %

NTSC Subcarrier (3.579 MHz)

RL = 150V

VS = 65V

G = +2

RL = 150V TO 2.5V

VS = +5V

G = +2

RL = 150V

VS = 65V
G = +2

RL = 150V TO 2.5V

VS = +5V
G = +2

0.6

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2
–0.3
–0.4

1 10 100 500

NORMALIZED GAIN – dB

FREQUENCY – MHz

14MHz

VS = +5V
G = +2

R

F

= 200V

R

L

= 150V TO 2.5V

√

100

30

10

3

INPUT VOLTAGE NOISE – nV/ Hz

1

AD8042

10 100

1k 10k 100k

FREQUENCY – Hz

Figure 10. Input Voltage Noise vs. Frequency

–30

–40

–50

–60

–70

–80

–90

TOTAL HARMONIC DISTORTION – dBc

–100

1103

VS = +5V, AV = +2,
R

= 100V TO 2.5V

L

VS = +5V, AV = +1,
R

= 100V TO 2.5V

L

VS = +5V, AV = +1,
R

2456789

FUNDAMENTAL FREQUENCY – MHz

Figure 11. Total Harmonic Distortion

–30

–40

–50

–60

–70

–80

REV. A –7–

–90

WORST HARMONIC – dBc

–100

–110

0.0 5.01.5

1.0 3.0 3.5 4.0 4.5

0.5 2.0 2.5
OUTPUT VOLTAGE – V p-p

Figure 12. Worst Harmonic vs. Output Voltage

VS = +3V, AV = –1,
R

L

= 1kV TO 2.5V

L

1M 10M 100M 1G

= 100V TO 1.5V

VS = +5V, AV = +2,
R

= 1kV TO 2.5V

L

10MHz

5MHz

1MHz

VS = +5V, G = +2,
RL = 1kV TO 2.5V

Figure 13. Differential Gain and Phase Errors

Figure 14. 0.1 dB Gain Flatness

120
100

80

60

40
20

0

OPEN–LOOP GAIN – dB

–20

–40
–60
–80

0.01 0.1

PHASE

GAIN

110

FREQUENCY – MHz

VS = +5V
G = +2

R

= 200V

F

RL = 150V TO 2.5V

100

Figure 15. Open-Loop Gain and Phase
vs. Frequency

500

45

0
–45
–90
–135

–180

–225
–270

PHASE– Degrees

0.5 2
BIPOLAR INPUT STEP – V

1 1.5

SETTING TIME – ns

35

60

50

40

30

20

25

G = –1
R

L

= 2kV TO MIDPOINT

C

L

= 5pF

VS = +3V, 0.1%

45

55

VS = +3V, 1%

VS = +5V, 0.1%

VS = 65V, 0.1%

VS = +5V, 1%

VS = 65V, 1%

–10

–40

–60

–80

0

–20
–30

–50

–70

–90

1M 10M 100M

100k

10k

COMMON MODE REJECTION – dB

FREQUENCY – Hz

V

s

= +5V

IN

CM

OUT

1.02kV

TEST CIRCUIT:

1.02kV

1.02kV

1.02kV

500M

AD8042–Typical Performance Characteristics

10

VS = +5V

8

G = +1

= 5pF

C

L

6

RL = 2kV TO 2.5V

4

2
0

–2
–4

CLOSED–LOOP GAIN – dB

–6
–8

–10

1 10 100 500

FREQUENCY – MHz

T = –408C

T = +858C

T = +258C

Figure 16. Closed-Loop Frequency Response
vs. Temperature

12

G = +1

10

CL = 5pF
R

= 2kV

L

8

6

4
2

0

–2

CLOSED–LOOP GAIN – dB

–4

–6
–8

1 10 100 500

V

= +3V

S

R

& C

L

L

VS = +5V
R

& C

L

L

FREQUENCY – MHz

Figure 17. Closed-Loop Frequency Response vs. Supply

100

VS = +5V

10

G = +1

1

0.1

OUTPUT RESISTANCE – V

0.01

0.01 0.1

Figure 18. Output Resistance vs. Frequency

R

BT

V

OUT

RBT = 50V

110

FREQUENCY – MHz

TO 1.5V

TO 2.5V

RBT = 0

100

V

= 65V

S

500

Figure 19. Settling Time

Figure 20. CMRR vs. Frequency

0.80
VS = +5V

0.70

0.60

0.50

0.40

0.30

0.20

OUTPUT SATURATION VOLTAGE – V

0.10

0

050

+5V – V

(+1258C)

OH

+5V – V

+5V – V

535

10 15 20 25 30 40 45

(+258C)

OH

(–558C)

OH

LOAD CURRENT – mA

+V

+V
+V

OL
OL
OL

Figure 21. Output Saturation Voltage vs. Load Current

–8–

(+1258C)
(+258C)
(–558C)

REV. A

AD8042

0 200

LOAD CAPACITANCE – pF

20 120

% OVERSHOOT

50

40

30

10

0

40 60 80 100 160140 180

20

VS = +5V
V

OUT

= 100mV STEP

G = +2

G = +3

0

–1

–2

–3
–4

1 10 100 500

NORMALIZED GAIN – dB

FREQUENCY – MHz

V

S

= +5V

R

F

= 2kV

RL = 2kV TO +2.5V

G = +10

G = +2

G = +5

1

2

3

4

5

6

G = +2
R

F

= 200V

–70

–80

–90

–100
–110

0.1 10 100 200

CROSSTALK – dB

FREQUENCY – MHz

–60

–50

–40

–30

–20

–10

1

V

OUT

1

V

OUT

2

, RL = 1kV TO +2.5V

V

OUT

2

V

OUT

1

, RL = 1kV TO +2.5V

, RL = 150V TO +2.5V

V

OUT

1

V

OUT

2

V

S

= +5V

V

IN

= 0.6V p-p

G = +2
R

F

= 1kV

V

OUT

2

V

OUT

1

, RL = 150V TO +2.5V

12

11.5

11

10.5

10

9.5

SUPPLY CURRENT – mA

9

8.5

8
–40

–20 –10

–30

010 30 6020 50 70

TEMPERATURE – 8C

VS = 65V

VS = +5V

VS = +3V

40

Figure 22. Supply Current vs. Temperature

VS = +5V

0

–10

–20

–30

– dB

–40

–50

PSRR

–60

–70

–80

–90

10k

–PSRR

100k

+PSRR

1M 10M 100M

FREQUENCY – Hz

90

80

Figure 25. % Overshoot vs. Load Capacitance

500M

Figure 23. PSRR vs. Frequency

10

9
8

7
6
5

4
3

OUTPUT VOLTAGE – V p-p

2

REV. A –9–

1
0

0.1

Figure 24. Output Voltage Swing vs. Frequency

1.0 10.0
FREQUENCY – MHz

Figure 26. Frequency Response vs. Closed-Loop Gain

VS = 65V
RL = 2kV
G = –1

100.0

Figure 27. Crosstalk (Output-to-Output) vs. Frequency

AD8042–Typical Performance Characteristics

+2.6V

+2.5V

+2.4V

AV = +1
V

S

= +5V

V

IN

= 100mV p-p

R

L

= 1kV TO 2.5V

C

L

= 5pF

10ns

25mV

5V

4V

3V

2V

1V

0V

0.5V

4.770V

0.160V

VS = +5V
G = –1
R

= 150V TO +2.5V

L

200ms

Figure 28a. Output Swing with Load Reference to Supply
Midpoint

5V

4V

3V

2V

1V

0V

4.59V

0.5V

VS= +5V
G = –1
R

= 150V TO GND

L

0.035V

200ms

Figure 30. 100 mV Pulse Response, VS = +5 V

G = –1

= 2kV TO +1.5V

R

3V

1.5V

0V

0.5V

L

1ms

Figure 28b. Output Swing with Load Reference to Negative
Supply

4.5V

3.5V

2.5V

1.5V

0.5V

AV = +2

= +5V

V

S

= 5pF

C

L

R

= 1kV TO +2.5V

L

= 1V p-p

V

IN

10ns0.5V

Figure 29. One Volt Pulse Response, VS = +5 V

Figure 31. Rail-to-Rail Output Swing, VS = +3 V

V

= 100mV p-p

+1.6V

+1.5V

+1.4V

25mV

IN

= 1kV TO 1.5V

R

L

= +3V

V

S

C

= 5pF

L

= +1V

A

V

10ns

Figure 32. 100 mV Pulse Response, VS = +3 V

–10– REV. A

AD8042

1000

10

100

12 5

CAPACITIVE LOAD – pF

CLOSED-LOOP GAIN – V/V

34

R

S

C

L

VS = +5V
200mV STEP WITH 30% OVERSHOOT

RS = 20V

RS = 5V

RS = 0

Overdrive Recovery

Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this over­drive condition. As shown in Figure 33, the AD8042 recovers
within 30 ns from negative overdrive and within 25 ns from
positive overdrive.

Circuit Description

The AD8042 is fabricated on Analog Devices’ proprietary
eXtra-Fast Complementary Bipolar (XFCB) process which
enables the construction of PNP and NPN transistors with
similar f
cally isolated to eliminate the parasitic and latch-up problems
caused by junction isolation. These features allow the construc­tion of high frequency, low distortion amplifiers with low supply
currents. This design uses a differential output input stage to
maximize bandwidth and headroom (see Figure 34). The
smaller signal swings required on the first stage outputs (nodes
S1P, S1N) reduce the effect of nonlinear currents due to
junction capacitances and improve the distortion performance.
With this design harmonic distortion of better than –77 dB

@ 1 MHz into 100 Ω with V

single 5 volt supply is achieved.

V

CC

Q13

VINP
VINN

V

EE

The AD8042’s rail-to-rail output range is provided by a
complementary common-emitter output stage. High output
drive capability is provided by injecting all output stage
predriver currents directly into the bases of the output devices
Q8 and Q36. Biasing of Q8 and Q36 is accomplished by I8 and
I5, along with a common-mode feedback loop (not shown).

+5V

+2.5V

0V

VS = +5V

= +5V p-p

V

IN

G = +2

= 1kV TO +2.5V

R

1V

L

50ns

Figure 33. Overdrive Recovery

s in the 2 GHz–4 GHz region. The process is dielectri-

T

= 2 V p-p (Gain = +2) on a

OUT

I1

R2R15

Q17

C7

I10

R26 R39

Q4

Q2

Q40

R5

SIP

Q5

V

EE

Q3

R21

SIN

Q11

R3

I2 I3

Q22

Q31

Q23

I9

Q36

I5

V

EE

C3

V

OUT

C9

Q8

I8

V

CC

Q51

Q21

R23

Q50

Q39

R27

Q27

Q47

Q25

Q7

Q24

I7

Figure 34. AD8042 Simplified Schematic

This circuit topology allows the AD8042 to drive 40 mA of
output current with the outputs within 0.5 V of the supply rails.

On the input side, the device can handle voltages from 0.2 V
below the negative rail to within 1.2 V of the positive rail. Ex­ceeding these values will not cause phase reversal; however, the
input ESD devices will begin to conduct if the input voltages
exceed the rails by greater than 0.5 V.

DRIVING CAPACITIVE LOADS

The capacitive load drive of the AD8042 can be increased by
adding a low valued resistor in series with the load. Figure 35
shows the effects of a series resistor on capacitive drive for vary­ing voltage gains. As the closed-loop gain is increased, the larger
phase margin allows for larger capacitive loads with less over­shoot. Adding a series resistor with lower closed-loop gains
accomplishes this same effect. For large capacitive loads, the
frequency response of the amplifier will be dominated by the
roll-off of the series resistor and capacitive load.

Figure 35. Capacitive Load Drive vs. Closed-Loop Gain

Single Supply Composite Video Line Driver

The two op amps of an AD8042 can be configured as a single
supply dual line driver for composite video. The wide signal
swing of the AD8042 enables this function to be performed
without using any type of clamping or dc restore circuit which
can cause signal distortion.

Figure 36 shows a schematic for a circuit that is driven by a
single composite video source that is ac coupled, level shifted
and applied to both + inputs of the two amplifiers. Each op amp

provides a separate 75 Ω composite video output. To obtain

single supply operation, ac coupling is used throughout. The
large capacitor values are required to ensure that there is mini­mal tilting of the video signals due to their low frequency
(30 Hz) signal content. The circuit shown was measured to have

a differential gain of 0.06% and a differential phase of 0.06°.
The input is terminated in 75 Ω and ac coupled via C

IN

to a
voltage divider that provides the dc bias point to the input.
Setting the optimal bias point requires some understanding of
the nature of composite video signals and the video performance
of the AD8042.

REV. A –11–

AD8042

+5V

COMPOSITE

VIDEO

IN

75V

4.99kV

10kV

10mF

R

1kV

4.99kV

G

3
2

R
1kV

220mF

5

6

220mF

8

1

R

F

1kV

G

7

4

R

F

1kV

0.1µF

1000mF

0.1mF

1000mF

0.1mF

10mF

75V

75V

75V

COAX

R

T

R

T

R

L

75V

R

L

75V

V

OUT

V

OUT

Figure 36. Single Supply Composite Video Line Driver
Using AD8042

Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capability than their peak-to­peak amplitude after ac coupling. As a worst case, the dynamic
signal swing required will approach twice the peak-to-peak
value. The two bounding cases are for a duty cycle that is mostly
low, but occasionally goes high at a fraction of a percent duty
cycle and vice versa.

Composite video is not quite this demanding. One bounding
extreme is for a signal that is mostly black for an entire frame,
but has a white (full intensity), minimum width spike at least
once per frame.

The other extreme is for a video signal that is full white every­where. The blanking intervals and sync tips of such a signal will
have negative going excursions in compliance with composite
video specifications. The combination of horizontal and vertical
blanking intervals limit such a signal to being at its highest level
(white) for only about 75% of the time.

As a result of the duty cycle variations between the two extremes
presented above, a 1 V p-p composite video signal that is multi­plied by a gain of two requires about 3.2 V p-p of dynamic volt­age swing at the output for an op amp to pass a composite video
signal of arbitrary duty cycle without distortion.

Some circuits use a sync tip clamp along with ac coupling to
hold the sync tips at a relatively constant level in order to lower
the amount of dynamic signal swing required. However, these
circuits can have artifacts like sync tip compression unless they
are driven by sources with very low output impedance.

The AD8042 not only has ample signal swing capability to
handle the dynamic range required without using a sync tip
clamp, but also has good video specifications like differential
gain and differential phase when buffering these signals in an
ac-coupled configuration.

To test this, the differential gain and differential phase were
measured for the AD8042 while the supplies were varied. As the
lower supply is raised to approach the video signal, the first
effect to be observed is that the sync tips become compressed
before the differential gain and differential phase are adversely
affected. Thus, there must be adequate swing in the negative
direction to pass the sync tips without compression.

As the upper supply is lowered to approach the video, the differ­ential gain and differential phase were not significantly adversely
affected until the difference between the peak video output and
the supply reached 0.6 V. Thus, the highest video level should
be kept at least 0.6 V below the positive supply rail.

Taking the above into account, it was found that the optimal
point to bias the noninverting input is at 2.2 V dc. Operating at
this point, the worst case differential gain is measured at 0.06%

and the worst case differential phase is 0.06°.

The ac coupling capacitors used in the circuit at first glance
appear quite large. A composite video signal has a lower fre­quency band edge of 30 Hz. The resistances at the various ac
coupling points—especially at the output—are quite small. In
order to minimize phase shifts and baseline tilt, the large value
capacitors are required. For video system performance that is
not to be of the highest quality, the value of these capacitors can
be reduced by a factor of up to five with only a slightly observ­able change in the picture quality.

Single-Ended-to-Differential Driver

Using a cross-coupled single-ended-to-differential converter, the
AD8042 makes a good general purpose differential line driver.
This can be used for applications such as driving category 5
twisted pair wire which is becoming common for data communi­cations in buildings. Figure 37 shows a configuration for a cir­cuit that performs this function that can be used for video
transmission over a differential pair or various data communica­tion purposes.

10mF

0.1mF

R

V

IN

AD8042

1kV

49.9V

100V

IN

3

AMP1

2

R

B

1kV

6

AMP2

5

R

1kV

R

1kV

–5V

R

F

8

A

A

7

4

1kV

1

R

B

1kV

0.1mF

60.4V

60.4V

10mF

50m

121V

V

OUT

Figure 37. Single-Ended-to-Differential Twisted Pair Line
Driver

REV. A–12–

Each of the AD8042’s op amps is configured as a unity gain

AD9220

VINA

V

IN

B

CAPT

CAPB
V

REF

SENSE
CML

CLK

19

27

25

14
13

12
11

10

9
8

7
6
5
4
3

2

+5V

0.1mF

DV

DD

AV

DD

AV

DD

REFCOM

DV

SSAVSSAVSS

16

28

15

26

OTR
BIT1

BIT2
BIT3

BIT4
BIT5

BIT6
BIT7
BIT8

BIT9

BIT10
BIT11

BIT12

CLOCK

1

0.1mF

0.1mF

18
17
22

10/16

8

3

2

6

5

7

4

+5V

1

AD8042

2.49kV 0.1mF

1kV

V

IN

1kV

1kV

1kV

1kV

1kV

0.1mF

+5V

+5V

0.1mF

2.49kV

0.1mF

0.1mF

+5V

0.1mF

+5V

0.1mF

VERTICAL SCALE – 15dB/DIV

1

4

9

7

2

3

6

8

5

FUND FRQ 1000977
SMPL FRQ 10000000

THD –82.00
SNR 71.13
SINAD 70.79
SFDR –86.74

2nd –88.34
3rd –86.74
4th –99.26
5th –90.67

6th –99.47
7th –91.16
8th –97.25
9th –91.61

HARMONICS (dBc)

follower by the feedback resistors (R
also drives the other as a unity gain inverter via the two R

). Each op amp output

A

B

s,

creating a totally symmetrical circuit.

If the + input to Amp 2 is grounded and a small positive signal
is applied to the + input of Amp 1, the output of Amp 1 will be
driven to saturation in the positive direction and the input of
Amp 2 driven to saturation in the negative direction. This is
similar to the way a conventional op amp behaves without any
feedback.

If a resistor (R

) is connected from the output of Amp 2 to the

F

+ input of Amp 1, negative feedback is provided which closes
the loop. An input resistor (R

) will make the circuit look like a

I

conventional inverting op amp configuration with differential
outputs.

The gain of this circuit from input to either output will be ±R

. Or the single-ended-to-differential gain will be 2 × R

R

I

F/RI.

/

F

This gives the circuit the advantage of being able to adjust its
gain by changing a single resistor.

The cable has a characteristic impedance of about 120 Ω. Each
driver output is back terminated with a pair of 60.4 Ω resistors
to make the source look like 120 Ω. The receive end is termi­nated with 121 Ω, and the signal is measured differentially with

a pair of scope probes. One channel on the oscilloscope is in­verted and then the signals are added.

The scope photo in Figure 38 shows a 10 MHz, 2 V p-p input
signal driving the circuit with 50 m of category 5 twisted pair
wire.

1V

100

90

V

IN

200mV

50ns

AD8042

Figure 39. AD8042 Differential Driver for the AD9220
12-Bit, 10 MSPS A/D Converter

The circuit was tested with a 1 MHz input signal and clocked at
10 MHz. An FFT response of the digital output is shown in
Figure 40.

Pin 5 is biased at 2.5 V by the voltage divider and bypassed.
This biases each output at 2.5 V. V
going positive makes VINA go positive and VINB go in the nega­tive direction. The opposite happens for a negative going V

is ac coupled such that V

IN

IN

.

IN

Single Supply Differential A/D Driver

The single-ended-to-differential converter circuit is also useful
as a differential driver for video speed, single-ended, differential
input A/D converters. Figure 39 is a schematic that shows such
a circuit differentially driving an AD9220, a 12-bit, 10 MSPS
A/D converter.

REV. A –13–

V

OUT

10

0%

Figure 38. Differential Driver Frequency Response

200mV

Figure 40. FFT of AD9220 Output When Driven by AD8042

AD8042

HDSL Line Driver

HDSL or high-bit-rate digital subscriber line is becoming popu­lar as a means to provide data communication at DS1 rates
(1.544 MBPS) over moderate distances via conventional tele­phone twisted pair wires. In these systems, the transceiver at the
customer’s end is sometimes powered via the twisted pair from a
power source at the central office. It is sometimes required to
raise the dc voltage of the power source to compensate for IR
drops in long lines or lines with narrow gauge wires.

Because of this, it is highly desirable to keep the power con­sumption of the customer’s transceiver as low as possible. One
means to realize significant power savings is to run the trans-

ceiver from a ±5 V supply instead of the more conventional
±12 V.

The high output swing and current drive capability of the
AD8042 make it ideally suited to this application. Figure 41
shows a circuit for the analog portion of an HDSL transceiver
using the AD8042 as the line driver.

2kV

V

IN

232V

0.001mF

2kV

6
5

2
3

3kV

1/2

AD8042

3kV

1/2

AD8042

912V

0.0027mF

2kV

0.001mF

7

1

2kV

2718AF
93DJ39

14

10 5

27

96

34V

2kV

ATT

2kV

2
3

2kV

1

1/4

AD8044

V

OUT

249V

V

REC

Layout Considerations

The specified high speed performance of the AD8042 requires
careful attention to board layout and component selection.
Proper RF design techniques and low-pass parasitic component
selection are necessary.

The PCB should have a ground plane covering all unused por­tions of the component side of the board to provide a low im­pedance path. The ground plane should be removed from the
area near the input pins to reduce the stray capacitance.

Chip capacitors should be used for the supply bypassing.
One end should be connected to the ground plane and the
other within 1/8 inch of each power pin. An additional large

(0.47 µF–10 µF) tantalum electrolytic capacitor should be con-

nected in parallel, but not necessarily so close, to supply current
for fast, large signal changes at the output.

The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the in­verting input will significantly affect high speed performance.

Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a

characteristic impedance of 50 Ω or 75 Ω and be properly termi-

nated at each end.

Figure 41. HDSL Line Driver

REV. A–14–

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead Plastic DIP

(N-8)

AD8042

PIN 1

0.165±0.01

(4.19±0.25)

0.125
(3.18)

MIN

PIN 1

0.0098 (0.25)

0.0040 (0.10)

8

1

0.018±0.003
(0.46±0.08)

0.0500

5

0.25

(6.35)

4

0.39 (9.91) MAX

0.10

(2.54)

BSC

0.033
(0.84)
NOM

0.035±0.01
(0.89±0.25)

0.18±0.03
(4.57±0.76)

SEATING
PLANE

8-Lead Plastic SOIC

(SO-8)

8

1

0.1968 (5.00)

0.1890 (4.80)

(1.27)

BSC

5

4

0.0192 (0.49)

0.0138 (0.35)

0.1574 (4.00)

0.1497 (3.80)

0.2440 (6.20)

0.2284 (5.80)

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0075 (0.19)

0.31

(7.87)

0.30 (7.62)

0.011±0.003
(0.28±0.08)

15°

0°

0.0196 (0.50)

0.0099 (0.25)

8°
0°

REF

x 45°

0.0500 (1.27)

0.0160 (0.41)

C2082a–0–9/99

REV. A –15–

PRINTED IN U.S.A.