Datasheet AD8041AR, AD8041AN, AD8041-EB, AD8041AR-REEL7, AD8041AR-REEL Datasheet (Analog Devices)

CONNECTION DIAGRAM

8-Lead DIP and SOIC

ⴙV

S

DISABLE

1

2

3

4

8

7

6

5

NC = NO CONNECT

NC

NC

OUTPUT

–INPUT

ⴙINPUT

–V

S

AD8041

(Top View)

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

a

160 MHz Rail-to-Rail

Amplifier with Disable

AD8041*

FEATURES

Fully Specified for +3 V, +5 V, and ⴞ5 V Supplies
Output Swings Rail to Rail
Input Voltage Range Extends 200 mV Below Ground
No Phase Reversal with Inputs 1 V Beyond Supplies
Disable/Power-Down Capability
Low Power of 5.2 mA (26 mW on 5 V)
High Speed and Fast Settling on 5 V:

160 MHz –3 dB Bandwidth (G = +1)
160 V/␮s Slew Rate
30 ns Settling Time to 0.1%

Good Video Specifications (R

L

= 150 ⍀, G = +2)

Gain Flatness of 0.1 dB to 30 MHz

0.03% Differential Gain Error

0.03ⴗ Differential Phase Error

Low Distortion

–69 dBc Worst Harmonic @ 10 MHz

Outstanding Load Drive Capability

Drives 50 mA 0.5 V from Supply Rails

Cap Load Drive of 45 pF

APPLICATIONS

Power Sensitive High Speed Systems
Video Switchers
Distribution Amplifiers
A/D Driver
Professional Cameras
CCD Imaging Systems
Ultrasound Equipment (Multichannel)
Single-Supply Multiplexer

PRODUCT DESCRIPTION

The AD8041 is a low power voltage feedback, high-speed ampli­fier designed to operate on +3 V, +5 V, or ±5 V supplies. It has
true single supply capability with an input voltage range extending
200 mV below the negative rail and within 1 V of the positive rail.

5V

2.5V

0V

200ns

1V

Figure 1. Output Swing: G = –1, VS = 5 V

The output voltage swing extends to within 50 mV of each rail,
providing the maximum output dynamic range. Additionally, it
features gain flatness of 0.1 dB to 30 MHz while offering differ­ential gain and phase error of 0.03% and 0.03° on a single 5 V
supply. This makes the AD8041 ideal for professional video
electronics such as cameras, video switchers or any high-speed
portable equipment. The AD8041’s low distortion and fast settling
make it ideal for buffering high-speed A-to-D converters.

The AD8041 has a high-speed disable feature useful for mul­tiplexing or for reducing power consumption (1.5 mA). The
disable logic interface is compatible with CMOS or open­collector logic. The AD8041 offers low power supply current of

5.8 mA max and can run on a single 3 V power supply. These
features are ideally suited for portable and battery powered
applications where size and power are critical.

The wide bandwidth of 160 MHz along with 160 V/µs of slew
rate on a single 5 V supply make the AD8041 useful in many
general purpose high-speed applications where dual power
supplies of up to ±6 V and single supplies from 3 V to 12 V are
needed. The AD8041 is available in 8-lead plastic DIP and
SOIC over the industrial temperature range of –40°C to +85°C.

FREQUENCY – MHz

VS = 5V
G = +2

R

F

= 400⍀

0

100

NORMALIZED GAIN – dB

80

60

40

20

0

2

1

–2

–1

–8

–7

–6

–5

–4

–3

Figure 2. Frequency Response: G = +2, VS = 5 V

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

*Protected under U.S. Patent No. 5,537,079.

AD8041–SPECIFICATIONS

REV. A

–2–

(@ TA = 25ⴗC, VS = 5 V, RL = 2 k⍀ to 2.5 V, unless otherwise noted.)

AD8041A

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth, V

O

< 0.5 V p-p G = +1 130 160 MHz

Bandwidth for 0.1 dB Flatness G = +2, R

L

= 150 Ω 30 MHz

Slew Rate G = –1, V

O

= 2 V Step 130 160 V/µs

Full Power Response V

O

= 2 V p-p 24 MHz

Settling Time to 0.1% G = –1, V

O

= 2 V Step 35 ns

Settling Time to 0.01% 55 ns

NOISE/DISTORTION PERFORMANCE

Total Harmonic Distortion f

C

= 5 MHz, VO = 2 V p-p, G = +2, RL = 1 kΩ –72 dB

Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 10 kHz 600 fA/√Hz
Differential Gain Error (NTSC) G = +2, R

L

= 150 Ω to 2.5 V 0.03 %

G = +2, R

L

= 75 Ω to 2.5 V 0.01 %

Differential Phase Error (NTSC) G = +2, R

L

= 150 Ω to 2.5 V 0.03 Degrees

G = +2, RL = 75 Ω to 2.5 V 0.19 Degrees

DC PERFORMANCE

Input Offset Voltage 27mV

T

MIN

to T

MAX

8mV

Offset Drift 10 µV/°C
Input Bias Current 1.2 3.2 µA

T

MIN

to T

MAX

3.5 µA

Input Offset Current 0.2 0.5 µA
Open-Loop Gain R

L

= 1 kΩ 86 95 dB

T

MIN

to T

MAX

90 dB

INPUT CHARACTERISTICS

Input Resistance 160 kΩ
Input Capacitance 1.8 pF
Input Common-Mode Voltage Range –0.2 to +4 V
Common-Mode Rejection Ratio VCM = 0 V to 3.5 V 74 80 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing: R

L

= 10 kΩ 0.05 to 4.95 V

Output Voltage Swing: R

L

= 1 kΩ 0.35 to 4.75 0.1 to 4.9 V

Output Voltage Swing: R

L

= 50 Ω 0.4 to 4.4 0.3 to 4.5 V

Output Current V

OUT

= 0.5 V to 4.5 V 50 mA

Short Circuit Current Sourcing 90 mA

Sinking 150 mA

Capacitive Load Drive G = +1 45 pF

POWER SUPPLY

Operating Range 312V
Quiescent Current 5.2 5.8 mA
Quiescent Current (Disabled) 1.4 1.7 mA
Power Supply Rejection Ratio VS = 0, +5 V, ±1 V 72 80 dB

DISABLE CHARACTERISTICS V

O

= 2 V p-p @ 10 MHz, G = +2

Turn-Off Time R

F

= RL = 2 kΩ 120 ns

Turn-On Time R

F

= RL = 2 kΩ 230 ns

Off Isolation (Pin 8 Tied to –V

S

)R

L

= 100 Ω, f = 5 MHz, G = +2, RF = 1 kΩ 70 dB

Off Voltage (Device Disabled) <V

S

– 2.5 V

On Voltage (Device Enabled) Open or +V

S

V

Specifications subject to change without notice.

REV. A

–3–

AD8041

SPECIFICATIONS

(@ TA = 25ⴗC, VS = 3 V, RL = 2 k⍀ to 1.5 V, unless otherwise noted)

AD8041A

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth, V

O

< 0.5 V p-p G = +1 120 150 MHz

Bandwidth for 0.1 dB Flatness G = +2, R

L

= 150 Ω 25 MHz

Slew Rate G = –1, V

O

= 2 V Step 120 150 V/µs

Full Power Response V

O

= 2 V p-p 20 MHz

Settling Time to 0.1% G = –1, V

O

= 2 V Step 40 ns

Settling Time to 0.01% 55 ns

NOISE/DISTORTION PERFORMANCE

Total Harmonic Distortion f

C

= 5 MHz, VO = 2 V p-p, G = –1, RL = 100 Ω –55 dB

Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 10 kHz 600 fA/√Hz
Differential Gain Error (NTSC) G = +2, R

L

= 150 Ω to 1.5 V, Input VCM = 1 V 0.07 %

Differential Phase Error (NTSC) G = +2, RL = 150 Ω to 1.5 V, Input VCM = 1 V 0.05 Degrees

DC PERFORMANCE

Input Offset Voltage 27mV

T

MIN

to T

MAX

8mV

Offset Drift 10 µV/°C
Input Bias Current 1.2 3.2 µA

T

MIN

to T

MAX

3.5 µA

Input Offset Current 0.2 0.6 µA
Open-Loop Gain R

L

= 1 kΩ 85 94 dB

T

MIN

to T

MAX

89 dB

INPUT CHARACTERISTICS

Input Resistance 160 kΩ
Input Capacitance 1.8 pF
Input Common-Mode Voltage Range –0.2 to +2 V
Common-Mode Rejection Ratio VCM = 0 V to 1.5 V 72 80 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing: R

L

= 10 kΩ 0.05 to 2.95 V

Output Voltage Swing: R

L

= 1 kΩ 0.45 to 2.7 0.1 to 2.9 V

Output Voltage Swing: R

L

= 50 Ω 0.5 to 2.6 0.25 to 2.75 V

Output Current V

OUT

= 0.5 V to 2.5 V 50 mA

Short Circuit Current Sourcing 70 mA

Sinking 120 mA

Capacitive Load Drive G = +1 40 pF

POWER SUPPLY

Operating Range 312V
Quiescent Current 5.0 5.6 mA
Quiescent Current (Disabled) 1.3 1.5 mA
Power Supply Rejection Ratio VS = 0, +3 V, ±0.5 V 68 80 dB

DISABLE CHARACTERISTICS V

O

= 2 V p-p @ 10 MHz, G = +2

Turn-Off Time R

F

= RL = 2 kΩ 90 ns

Turn-On Time R

F

= RL = 2 kΩ 170 ns

Off Isolation (Pin 8 Tied to –V

S

)R

L

= 100 Ω, f = 5 MHz, G = +2, RF = 1 kΩ 70 dB

Off Voltage (Device Disabled) <V

S

– 2.5 V

On Voltage (Device Enabled) Open or +V

S

V

Specifications subject to change without notice.

AD8041A

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth, V

O

< 0.5 V p-p G = +1 140 170 MHz

Bandwidth for 0.1 dB Flatness G = +2, R

L

= 150 Ω 32 MHz

Slew Rate G = –1, V

O

= 2 V Step 140 170 V/µs

Full Power Response V

O

= 2 V p-p 26 MHz

Settling Time to 0.1% G = –1, V

O

= 2 V Step 30 ns

Settling Time to 0.01% 50 ns

NOISE/DISTORTION PERFORMANCE

Total Harmonic Distortion f

C

= 5 MHz, VO = 2 V p-p, G = +2, RL = 1 kΩ –77 dB

Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 10 kHz 600 fA/√Hz
Differential Gain Error (NTSC) G = +2, R

L

= 150 Ω 0.02 %

G = +2, R

L

= 75 Ω 0.02 %

Differential Phase Error (NTSC) G = +2, R

L

= 150 Ω 0.03 Degrees

G = +2, RL = 75 Ω 0.10 Degrees

DC PERFORMANCE

Input Offset Voltage 27mV

T

MIN

to T

MAX

8mV

Offset Drift 10 µV/°C
Input Bias Current 1.2 3.2 µA

T

MIN

to T

MAX

3.5 µA

Input Offset Current 0.2 0.6 µA
Open-Loop Gain R

L

= 1 kΩ 90 99 dB

T

MIN

to T

MAX

95 dB

INPUT CHARACTERISTICS

Input Resistance 160 kΩ
Input Capacitance 1.8 pF
Input Common-Mode Voltage Range –5.2 to +4 V
Common-Mode Rejection Ratio VCM = –5 V to +3.5 V 72 80 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing: R

L

= 10 kΩ –4.95 to +4.95 V

Output Voltage Swing: R

L

= 1 kΩ –4.45 to +4.6 –4.8 to +4.8 V

Output Voltage Swing: R

L

= 50 Ω –4.3 to +3.2 –4.5 to +3.8 V

Output Current V

OUT

= –4.5 V to +4.5 V 50 mA

Short Circuit Current Sourcing 100 mA

Sinking 160 mA

Capacitive Load Drive G = +1 50 pF

POWER SUPPLY

Operating Range 312V
Quiescent Current 5.8 6.5 mA
Quiescent Current (Disabled) 1.6 2.2 mA
Power Supply Rejection Ratio VS = –5 V, +5 V, ±1 V 68 80 dB

DISABLE CHARACTERISTICS V

O

= 2 V p-p @ 10 MHz, G = +2

Turn-Off Time R

F

= 2 kΩ 120 ns

Turn-On Time R

F

= 2 kΩ 320 ns

Off Isolation (Pin 8 Tied to –V

S

)R

L

= 100 Ω, f = 5 MHz, G = +2, RF = 1 kΩ 70 dB

Off Voltage (Device Disabled) <V

S

– 2.5 V

On Voltage (Device Enabled) Open or +V

S

Specifications subject to change without notice.

(@ TA = 25ⴗC, VS = ⴞ5 V, RL = 2 k⍀ to 0 V, unless otherwise noted)

REV. A

–4–

AD8041–SPECIFICATIONS

AD8041

REV. A

–5–

ABSOLUTE MAXIMUM RATINGS

1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V

Internal Power Dissipation

2

Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . 1.3 Watts

Small Outline Package (R) . . . . . . . . . . . . . . . . . . 0.9 Watts

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± V

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±3.4 V

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves

Storage Temperature Range N, R . . . . . . . . –65°C to +125°C

Operating Temperature Range (A Grade) . . . –40°C to +85°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for the device in free air:

8-Lead Plastic DIP Package: θJA = 90°C/W.
8-Lead SOIC Package: θJA = 155°C/W.

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8041 is limited by the associated rise in junction temperature.
The maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Exceeding this limit temporarily
may cause a shift in parametric performance due to a change in

the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can result
in device failure.

While the AD8041 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction tem­perature (150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves.

MAXIMUM POWER DISSIPATION – Watts

AMBIENT TEMPERATURE – ⴗC

2.0

1.5

0

–50 90–40 –30 –20 –10 0 102030 506070 8040

1.0

0.5

8-LEAD PLASTIC DIP PACKAGE

8-LEAD SOIC PACKAGE

TJ = 150ⴗC

Figure 3. Maximum Power Dissipation vs. Temperature

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8041 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Temperature Package Package

Model Range Description Options

AD8041AN –40°C to +85°C 8-Lead Plastic DIP N-8
AD8041AR –40°C to +85°C 8-Lead Plastic SOIC SO-8
AD8041AR-REEL –40°C to +85°C 13" Tape and Reel SO-8
AD8041AR-REEL7 –40°C to +85°C 7" Tape and Reel SO-8
AD8041-EB Evaluation Board
5962-9683901MPA* –55°C to +125°C 8-Lead Cerdip Q-8

*Refer to official DSCC drawing for tested specifications.

WARNING!

ESD SENSITIVE DEVICE

VOS – mV

30

15

0

25

20

10

5

–66–5 –4 –3 –2 –1012345

NUMBER OF PARTS IN BIN

VS = ⴞ2.5V
T

A

= 25ⴗC
91 PARTS
MEAN = +0.21
STD DEVIATION = 1.47

TPC 1. Typical Distribution of V

OS

VOS DRIFT – ␮V/ ⴗC

0.20

0.15

0

–10 10–7.5

PROBABILITY DENSITY

–5 –2.5 0 2.5 5 7.5

0.10

0.05

MEAN = 0.02␮V/ ⴗC
STD DEV = 2.87␮V/ ⴗC
SAMPLE SIZE = 45

TPC 2. VOS Drift Over –40°C to +85°C

TEMPERATURE – ⴗC

2

1.5

0

–45 85–35 –25 –15 –5 5 15 25 35 45 55 65 75

1

0.5

INPUT BIAS CURRENT – ␮A

VS = 5V
V

CM

= 0V

TPC 3. IB vs. Temperature

–6–

REV. A

AD8041–Typical Performance Characteristics

LOAD RESISTANCE – ⍀

100

70

95

90

85

80

75

0 2000250 500 750 1000 1250 1500 1750

VS = 5V
T

A

= 25ⴗC

OPEN-LOOP GAIN – dB

TPC 4. Open-Loop Gain vs. RL to 25°C

TEMPERATURE – ⴗC

100

97

85

–60 –40 –20 0 20 40 60 80 100 120

94

91

88

OPEN-LOOP GAIN – dB

VS = 5V
R

L

= 1k⍀ TO 2.5V

TPC 5. Open-Loop Gain vs. Temperature

OUTPUT VOLTAGE – Volts

100

70

40

90

80

60

50

050.5 1 1.5 2 2.5 3 3.5 4 4.5

RL = 500⍀ TO 2.5V

VS = 5V

RL = 50⍀ TO 2.5V

OPEN-LOOP GAIN – dB

TPC 6. Open-Loop Gain vs. Output Voltage

AD8041

REV. A

–7–

FREQUENCY – Hz

200

150

0

100

50

10 100k100

INPUT VOLTAAGE NOISE – nV/

Hz

1k 10k

TPC 7. Input Voltage Noise vs. Frequency

FUNDAMENTAL FREQUENCY – MHz

–30

–40

–100

1102

TOTAL HARMONIC DISTORTION – dBc

–60

–70

–80

–90

–50

3456789

VS = 3V, AV = –1,
R

L

= 100⍀ TO 1.5V

VS = 5V, AV = 1,
R

L

= 1k⍀ TO 2.5V

VS = 5V, AV = 2,
R

L

= 100⍀ TO 2.5V

VS = 5V, AV = 2,
R

L

= 1k⍀ TO 2.5V

VS = 5V, AV = 1,
R

L

= 100⍀ TO 2.5V

TPC 8. Total Harmonic Distortion

OUTPUT VOLTAGE – V

PP

0 1.50.5 1 2

2.5

3 3.5 4 4.5 5

WORST HARMONIC – dBc

–140

–30

–40

–50

–70

–100

–80

–90

–60

–110

–120

–130

10MHz

5MHz

1MHz

VS = 5V
R

L

= 2k⍀ TO 2.5V

G = +2

TPC 9. Worst Harmonic vs. Output Voltage

DIFF PHASE – Degrees

DIFF GAIN – %

11th1st 6th2nd 3rd

4th

5th 7th 8th 9th

10th

–0 .005

0.015

0.005

0.025

0.020

0.010

0.000

0.030

–0 .010

0.035
VS = 5V
G = +2
R

L

= 150⍀ TO 2.5V

11th1st 6th2nd 3rd 4th 5th 7th 8th 9th 10th

VS = ±5V
G = +2

R

L

= 150⍀

–0 .005

0.015

0.005

0.025

0.020

0.010

0.000

0.030

–0 .010

0.035

VS = 5V
G = +2

R

L

= 150⍀ TO 2.5V

VS = ±5V
G = +2

R

L

= 150⍀

DC OUTPUT LEVEL – 100 IRE MAX

TPC 10. Differential Gain and Phase Errors

FREQUENCY – MHz

6.5

6.4

5.5

6.3

6.2

6.1

6.0

5.9

5.8

5.7

5.6

1 50010

100

32.4MHz

VS = 5V
G = +2

R

L

= 150⍀ TO 2.5V

R

F

= 402⍀

CLOSED-LOOP GAIN – dB

TPC 11. 0.1 dB Gain Flatness

–10

40

30

60

0

50

10

20

80

90

70

OPEN-LOOP GAIN – dB

–180

0

–90

90

180

270

PHASE – ⴗC

360

450

–270

–360

–450

5000.1

0.01

10010

FREQUENCY – MHz

VS = 5V
R

L

= 2k⍀ TO 2.5V

C

L

= 5pF TO 2.5V

PHASE

GAIN

TPC 12. Open-Loop Gain and Phase vs. Frequency

FREQUENCY – MHz

5

4

–5

3

2

1

0

–1

–2

–3

–4

1 50010 100

VS = 5V
R

L

= 2k⍀ TO 2.5V
CL = 5pF
G = +1

T = +125ⴗC

T = +25ⴗC

T = –55ⴗC

CLOSED-LOOP GAIN – dB

TPC 13. Closed-Loop Frequency Response
vs. Temperature

FREQUENCY – MHz

5

4

–5

3

2

1

0

–1

–2

–3

–4

1 50010 100

G = +1
R

L

= 2k⍀
C

L

= 5pF

VS = 3V
R

L

& CL TO 1.5V

VS = ⴞ5V

CLOSED-LOOP GAIN – dB

VS = 5V
R

L

& CL TO 2.5V

TPC 14. Closed-Loop Frequency Response vs. Supply

FREQUENCY – MHz

100

10

1

0.1

0.01

1 50010 1000.1

0.01

G = +1
V

S

= 5V

OUTPUT RESISTANCE – ⍀

TPC 15. Output Resistance vs. Frequency

REV. A

–8–

INPUT STEP – Volts p-p

TIME – ns

50

40

10

0.5 21 1.5

30

20

VS = 3V, 0.1%

VS = ⴞ5V, 0.1%

VS = 3V, 1%

VS = ⴞ5V, 1%

G = –1

TPC 16. Settling Time vs. Input Step

FREQUENCY – MHz

–10

–40

–60

–80

–100

–20

–30

–50

–70

–90

–110

1 50010 1000.1

0.01

CMRR – dB

VS = +3V AND ⴞ5V

TPC 17. CMRR vs. Frequency

LOAD CURRENT – mA

OUTPUT SATURATION VOLTAGE – mV

1000

10

0

0.001 0.01

100

0.1 1 10

100

V

OL

, –55ⴗC

+

5

V

– V

OH

,

+

12

5

ⴗC

V

OL

, +125ⴗC

VS = 5V

+5V

– V

O

H

,

–55ⴗC

TPC 18. Output Saturation Voltage vs. Load Current

AD8041–Typical Performance Characteristics

AD8041

REV. A

–9–

TEMPERATURE – ⴗC

8

5

2
–60 –40 –20 0 20 40 60 80 100 120

SUPPLY CURRENT – mA

7

6

4

3

VS = 5V

VS = ⴞ5V

VS = 3V

TPC 19. Supply Current vs. Temperature

FREQUENCY – MHz

40

–20

–60

–100

–140

20

0

–40

–80

–120

–160

1 50010 1000.1

0.01

PSRR – dB

VS = 5V

–PSRR

+PSRR

TPC 20. PSRR vs. Frequency

10

9

0

6

3

2

1

8

7

4

5

V

OUT

p-p – Volts

FREQUENCY – MHz

VS = ⴞ5V
RL = 2k⍀

0.1 10001 10 100

TPC 21. Output Voltage Swing vs. Frequency

SERIES RESISTANCE –

⍀

90

10

80

50

40

30

20

70

60

0

06010 20 30 40 50

V

IN

100k

⍀

R

SERIES

C

LOAD

1k

⍀

20ⴗ PHASE
MARGIN

45ⴗ PHASE
MARGIN

VS = 5V

CAPACITIVE LOAD – pF

TPC 22. Capacitive Load vs. Series Resistance

FREQUENCY – MHz

5

4

–5

NORMALIZED OUTPUT – dB

3

2

1

0

–1

–2

–3

–4

1 50010 100

G = 2

G = 10

G = 5

G = 2,
R

F

= 402

⍀

VS = 5V
R

L

= 5k⍀ TO 2.5V

R

F

= 2k

⍀

TPC 23. Frequency Response vs. Closed-Loop Gain

1.600V

1.550V

1.500V

1.450V

1.400V

1.425V

1.475V

1.525V

1.575V

10ns

50mV

V

I

N

= 0.1V p-p

R

L

=

2k⍀

VS = 3V

G = +1

TPC 24. Pulse Response, VS = 3 V

AD8041–Typical Performance Characteristics

–10–

REV.

A

5V

4V

3V

2V

1V

0V

200␮s

1V

0.111V MIN

RL = 150⍀ TO 2.5V

4.840V MAX

TPC 25a.

5V

4V

3V

2V

1V

0V

200␮s

1V

RL = 150⍀ TO GND

4.741V MAX

0.043V MIN

TPC 25b.
TPC 25a-b. Output Swing vs. Load Reference Voltage,
VS = 5 V, G = –1

4.5V

3.5V

2.5V

1.5V

0.5V

40ns1V

VS = 5V

G = +2
R

L

= 2k⍀

V

IN

= 1V p-p

TPC 26. One Volt Step Response, VS = 5 V, G = +2

2.6V

2.55V

2.5V

2.45V

2.4V

VS = 5V

G = +1
R

L

= 2k⍀

V

L

= 5pF

40ns

50mV

TPC 27. 100 mV Step Response, VS = 5 V, G = +1

3V

2.5V

2V

1.5V

1V

0.5V

0V

2␮s

500mV

VIN = 3V p-p
f = 0.1MHz
R

L

= 2k⍀

V

S

= 3V

G = –1

TPC 28. Output Swing, VS = 3 V, VIN = 3 V p-p

3V

2.5V

2V

1.5V

1V

0.5V

0V

2␮s

500mV

VIN = 2.8V p-p
f = 0.8MHz
R

L

= 2k⍀

V

S

= 3V

G = –1

TPC 29. Output Swing, VS = 3 V, VIN = 2.8 V p-p

AD8041

REV. A

–11–

Overdrive Recovery

Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this over­drive condition. As shown in Figure 4, the AD8041 recovers
within 50 ns from negative overdrive and within 25 ns from
positive overdrive.

5V

2.5V

0V

40ns50mV

OUTPUT

INPUT

G = +2
V

S

= 5V

Figure 4. Overdrive Recovery

Circuit Description

The AD8041 is fabricated on Analog Devices’ proprietary
eXtra-Fast Complementary Bipolar (XFCB) process which
enables the construction of PNP and NPN transistors with similar
f

T

s in the 2 GHz–4 GHz region. The process is dielectrically
isolated to eliminate the parasitic and latch-up problems caused
by junction isolation. These features allow the construction of
high frequency, low distortion amplifiers with low supply currents.
This design uses a differential output input stage to maximize
bandwidth and headroom (see Figure 5). The smaller signal
swings required on the first stage outputs (nodes S1P, S1N) reduce
the effect of nonlinear currents due to junction capacitances and
improve the distortion performance. With this design harmonic
distortion of better than –85 dB @ 1 MHz into 100 Ω with V

OUT

=

2 V p-p (Gain = +2) on a single 5 volt supply is achieved.

The complementary common-emitter design of the output stage
provides excellent load drive without the need for emitter followers,
thereby improving the output range of the device considerably
with respect to conventional op amps. High output drive capa­bility is provided by injecting all output stage predriver currents
directly into the bases of the output devices Q8 and Q36. Bias­ing of Q8 and Q36 is accomplished by I8 and I5, along with a
common-mode feedback loop (not shown). This circuit topology
allows the AD8041 to drive 50 mA of output current with the
outputs within 0.5 V of the supply rails.

On the input side, the device can handle voltages from –0.2 V
below the negative rail to within 1.2 V of the positive rail. Exceed­ing these values will not cause phase reversal; however, the input
ESD devices will begin to conduct if the input voltages exceed
the rails by greater than 0.5 V.

A “Nested Integrator” topology is used in the AD8041 (see
small-signal schematic shown in Figure 6). The output stage
can be modeled as an ideal op amp with a single-pole response
and a unity-gain frequency set by transconductance g

m2

and

capacitor C9. R1 is the output resistance of the input stage; g

m

is the input transconductance. C7 and C9 provide Miller com­pensation for the overall op amp. The unity gain frequency will
occur at g

m

/C9. Solving the node equations for this circuit yields:

V

Vi

A

sR C A s

g

C

OUT

m

=

++×











+











0

19 21 1

3

1

2

([( )])

where A0 = gmg

m2

R2 R1 (Open-Loop Gain of Op Amp)

A2 = g

m2

R2 (Open-Loop Gain of Output Stage)

The first pole in the denominator is the dominant pole of the
amplifier, and occurs at about 180 Hz. This equals the input
stage output impedance R1 multiplied by the Miller-multiplied
value of C9. The second pole occurs at the unity-gain bandwidth
of the output stage, which is 250 MHz. This type of architecture
allows more open-loop gain and output drive to be obtained
than a standard two-stage architecture would allow.

Output Impedance

The low frequency open-loop output impedance of the common
emitter output stage used in this design is approximately 6.5 kΩ.
While this is significantly higher than a typical emitter follower
output stage, when connected with feedback the output imped­ance is reduced by the open-loop gain of the op amp. With
110 dB of open-loop gain the output impedance is reduced to
less than 0.1 Ω. At higher frequencies the output impedance will
rise as the open-loop gain of the op amp drops; however, the out­put also becomes capacitive due to the integrator capacitors C9
and C3. This prevents the output impedance from ever becoming
excessively high (see TPC 15), which can cause stability prob­lems when driving capacitive loads. In fact, the AD8041 has
excellent cap-load drive capability for a high-frequency op amp.
TPC 22 demonstrates that the AD8041exhibits a 45° margin
while driving a 20 pF direct capacitive load. In addition, run­ning the part at higher gains will also improve the capacitive
load drive capability of the op amp.

SIN

R21

R3

V

EE

Q11

Q3

I10

R26 R39

Q5

Q4

Q40

I7

R2R15

Q13

Q17

R5

C7

Q2

SIP

Q22

Q7

Q21

Q24

R23

R27

I2 I3

I1

Q51

Q25 Q50

Q39

Q47

Q27

Q31

Q23

I9

I5

V

EE

V

CC

I8

Q36

Q8

V

OUT

C3

C9

V

CC

VINP

V

IN

N

V

EE

Figure 5. AD8041 Simplified Schematic

REV. A

–12–

AD8041

R2

C3

g

m2

V

OUT

R1

C9

g

m

Vi

S1N

S1P

C7

R1

gmVi

Figure 6. Small Signal Schematic

Disable Operation

The AD8041 has an active-low disable pin, which can be used
to three-state the output of the part and also lower its supply
current. If the disable pin is left floating, the part is enabled and
will perform normally. If the disable pin is pulled to 2.5 V (min)
below the positive supply, output of the AD8041 will be disabled
and the nominal supply current will drop to less than 1.6 mA.
For best isolation, the disable pin should be pulled to as low a
voltage as possible; ideally, the negative supply rail.

The disable pin on the AD8041 allows it to be configured as an 2:1
mux as shown in Figure 7 and can be used to switch many types of
high speed signals. Higher order multiplexers can also be built.
The break-before-make switching time is approximately 50 ns to
disable the output and 300 ns to enable the output.

6

4

7

3

2

AD8041

330⍀

50⍀

10␮F

5V

330⍀

8

6

4

7

3

2

AD8041

330⍀

50⍀

10␮F

5V

330⍀

8

13

12 11

10

74HC04

50⍀

G = +2

G = +2

CH0

5MHz

CH1

10MHz

Figure 7. 2:1 Multiplexer

10

0%

100

90

200ns

1V

VS = 5V

Figure 8. 2:1 Multiplexer Performance

Single Supply A/D Conversion

Figure 9 shows the AD8041 driving the analog inputs of the
AD9050 in a dc coupled system with single-ended signals. All
components are powered from a single 5 V supply. The AD820
is used to offset the ground referenced input signal to the level
required by the AD9050. The AD8041 is used to add in the offset
with the ground referenced input signal and buffer the input to
AD9050. The nominal input range of the AD9050 is 2.8 V

0.1␮F

5V

AD8041

2.8V – 3.8V

3.3V

5V

AD9050

10

9

1k⍀

V

IN

–0.5V TO +0.5V

1k⍀1k⍀

0.1␮F
5V

AD820

1k⍀

Figure 9. 10-Bit, 40 MSPS A/D Conversion

and 3.8 V (1 V p-p centered at 3.3 V). This circuit provides
40 MSPS analog-to-digital conversion on just 330 mW of power
while delivering 10-bit performance.

0

–10

–100

–60

–70

–80

–90

–40

–50

–30

–20

F1 = 4.9MHz
FUNDAMENTAL = 0.6dB
2nd HARMONIC = 66.9dB
3rd HARMONIC = 74.7dB
SNR = 55.2dB
NOISE FLOOR = – 86.1dB
ENCODE FREQUENCY = 40MHz

Figure 10. FFT Output of Circuit in Figure 9

AD8041

REV. A

–13–

APPLICATIONS
RGB Buffer

The AD8041 can provide buffering of RGB signals that include
ground while operating from a single 3 V or 5 V supply.

The signals that drive an RGB monitor are usually supplied by
current output DACs that operate from a 5 V only supply. These
can triple DACs like the ADV7120 and ADV7122 from Analog
Devices or integrate into the graphics controller IC as in most
PCs these days.

During the horizontal blanking interval the currents output from
the DACs go to zero and the RGB signals are pulled to ground
via the termination resistors. If more than one RGB monitor is
desired, it cannot simply be connected in parallel because it will
provide an additional termination. Therefore, buffering must be
provided before connecting a second monitor.

Since the RGB signals include ground as part of their dynamic
output range, it has previously been required to use a dual sup­ply op amp to provide this buffering. In some systems this is the
only component that requires a negative supply so it can be
quite inconvenient to incorporate this multiple monitor feature.

Figure 11 shows a schematic of one channel of a single supply
gain-of-two buffer for driving a second RGB monitor. No cur­rent is required when the amplifier output is at ground. The
termination resistor at the monitor helps pull the output down
at low voltage levels.

6

4

7

3

2

AD8041

1k⍀

75⍀

10␮F

8

75⍀

R, G OR B

NC

0.1␮F

1k⍀

PRIMARY RGB

MONITOR

75⍀

SECOND RGB

MONITOR

3V OR 5V

Figure 11. Single Supply RGB Buffer

Figure 12 is an oscilloscope photo of the circuit in Figure 11
operating from a 3 V supply and driven by the Blue signal of a
color bar pattern. Note that the input and output are at ground
during the horizontal blanking interval. The RGB signals are
specified to output a maximum of 700 mV peak. The output of
the AD8041 is 1.4 V with the termination resistors providing a
divide-by-two. The Red and Green signals can be buffered in
the same manner with duplication of this circuit.

V

IN

GND

GND

V

OUT

10

0%

100

90

5␮s500mV

500mV

Figure 12. 3 V, RGB Buffer

Single Supply Composite Video Line Driver

Figure 13 shows a schematic of a single supply gain-of-two
composite video line driver. Since the sync tips of a composite
video signal extend below ground, the input must be ac coupled
and shifted positively to provide signal swing during these nega­tive excursions in a single supply configuration.

The input is terminated in 75 Ω and ac coupled via C

IN

to a
voltage divider that provides the dc bias point to the input.
Setting the optimal bias point requires some understanding of
the nature of composite video signals and the video performance
of the AD8041.

Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capability than their peak-to­peak amplitude after ac coupling. As a worst case, the dynamic
signal swing required will approach twice the peak-to-peak value.
The two bounding cases are for a duty cycle that is mostly low,
but occasionally goes high at a fraction of a percent duty cycle
and vice versa.

Composite video is not quite this demanding. One bounding
extreme is for a signal that is mostly black for an entire frame,
but has a white (full intensity), minimum width spike at least
once per frame.

The other extreme is for a video signal that is full white every­where. The blanking intervals and sync tips of such a signal will
have negative going excursions in compliance with composite
video specifications. The combination of horizontal and vertical
blanking intervals limit such a signal to being at its highest level
(white) for only about 75% of the time.

As a result of the duty cycle variations between the two extremes
presented above, a 1 V p-p composite video signal that is multi­plied by a gain of two requires about 3.2 V p-p of dynamic voltage
swing at the output for an op amp to pass a composite video
signal of arbitrary duty cycle without distortion.

Some circuits use a sync tip clamp along with ac coupling to
hold the sync tips at a relatively constant level in order to lower
the amount of dynamic signal swing required. However, these
circuits can have artifacts like sync tip compression unless they
are driven by sources with very low output impedance.

6

4

7

3

2

AD8041

R

F

1k⍀

10k⍀

10␮F

5V

75⍀

COMPOSITE

VIDEO IN

NC

0.1␮F

R

T

75⍀

8

1000␮F

0.1␮F

4.99k⍀

10␮F

4.99k⍀

47␮F

R

G

1k⍀

220␮F

75⍀

COAX

R

L

75⍀

V

OUT

Figure 13. Single Supply Composite Video Line Driver

The AD8041 not only has ample signal swing capability to
handle the dynamic range required without using a sync tip
clamp, but also has good video specifications like differential
gain and differential phase when buffering these signals in an ac
coupled configuration.

REV. A

–14–

AD8041

To test this, the differential gain and differential phase were
measured for the AD8041 while the supplies were varied. As the
lower supply is raised to approach the video signal, the first effect
to be observed is that the sync tips become compressed before
the differential gain and differential phase are adversely affected.
Thus, there must be adequate swing in the negative direction to
pass the sync tips without compression.

As the upper supply is lowered to approach the video, the differ­ential gain and differential phase were not significantly adversely
affected until the difference between the peak video output and
the supply reached 0.6 V. Thus, the highest video level should
be kept at least 0.6 V below the positive supply rail.

Taking the above into account, it was found that the optimal
point to bias the noninverting input is at 2.2 V dc. Operating at
this point, the worst case differential gain is measured at 0.06%
and the worst case differential phase is 0.06°.

The ac coupling capacitors used in the circuit at first glance
appear quite large. A composite video signal has a lower fre­quency band edge of 30 Hz. The resistances at the various ac
coupling points—especially at the output—are quite small. In
order to minimize phase shifts and baseline tilt, the large value
capacitors are required. For video system performance that is
not to be of the highest quality, the value of these capacitors can
be reduced by a factor of up to five with only a slightly observ­able change in the picture quality.

Sync Stripper

Some RGB monitor systems use only three cables total and
carry the synchronizing signals along with the Green (G) signal
on the same cable. The sync signals are pulses that go in the
negative direction from the blanking level of the G signal.

In some applications like prior to digitizing component video
signals with A/D converters, it is desirable to remove or strip the
sync portion from the G signal. Figure 14 is a schematic of a
circuit using the AD8041 running on a single 5 V supply that
performs this function.

AD8041

R2

1k⍀

10␮F

0.1␮F

0.8V

(2X V

BLANK

)

5V

75⍀

V

IN

75⍀

75⍀

(MONITOR)

R1

1k⍀

7

6

3

2

4

GREEN W/SYNC

V

BLANK

+0.4

GROUND

GREEN W/OUT SYNC

GROUND

Figure 14. Single Supply Sync Stripper

Referring to Figure 15, the Green plus sync signal is output
from an ADV7120, a single supply triple video DAC. Because
the DAC is single supply, the lowest level of the sync tip is at
ground or slightly above. The AD8041 is set for a gain of two to
compensate for the divide by two of the output terminations.

10

0%

100

90

10␮s

500mV

500mV

Figure 15. Single Supply Sync Stripper

The reference voltage for R1 should be twice the dc blanking
level of the G signal. If the blanking level is at ground and the
sync tip is negative as in some dual supply systems, then R1 can
be tied to ground. In either case, the output will have the sync
removed and have the blanking level at ground.

Layout Considerations

The specified high-speed performance of the AD8041 requires
careful attention to board layout and component selection.
Proper RF design techniques and low-pass parasitic component
selection are necessary.

The PCB should have a ground plane covering all unused portions
of the component side of the board to provide a low impedance
path. The ground plane should be removed from the area near
the input pins to reduce the stray capacitance.

Chip capacitors should be used for the supply bypassing (see
Figure 16). One end should be connected to the ground plane
and the other within 1/8 inch of each power pin. An additional
large (0.47 µF–10 µF) tantalum electrolytic capacitor should be
connected in parallel, but not necessarily so close, to supply
current for fast, large signal changes at the output.

The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the inverting
input will significantly affect high-speed performance.

Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly termi­nated at each end.

AD8041

REV. A

–15–

V+

IN

OUT

V–

GND

VCH

1

VCL

SO NONINVERTER

1

ANALOG
DEVICES

Figure 17. Evaluation Board Silkscreen (Top)

Evaluation Board

An evaluation board for the AD8041 is available which has been
carefully laid out and tested to demonstrate that the specified high­speed performance of the device can be realized. For ordering
information, please refer to the ordering guide.

The layout of the evaluation board can be used as shown or
can serve as a guide for a board layout.

6

8

7

3

2

AD8041

10␮F

0.1␮F

10k⍀

V

IN

R

O

75⍀

4

1000␮F

0.1␮F

4.99k⍀

10␮F

4.99k⍀

47␮F

R

G

1k⍀

220␮F

10␮F 0.1␮F

ENABLE

–V

TP1

TP3

TP2

TP4

R

F

1k⍀

J2

J1

J3

J4

J5

R

T

75⍀

+V

Figure 16. Noninverting Configurations for Evaluation
Boards

Figure 18. Board Layout (Component Side)

Figure 19. Board Layout (Back Side)

Table I. Recommended Component Values

AD8041A

Gain

Component +1 +2 +2 +5 +10

R

F

0 Ω 2kΩ 400 Ω 2kΩ 2kΩ

R

G

2kΩ 400 Ω 500 Ω 220 Ω

R

O

(Nominal) 75 Ω 75 Ω 75 Ω 75 Ω 75 Ω

R

T

(Nominal) 75 Ω 75 Ω 75 Ω 75 Ω 75 Ω

Small Signal BW (MHz)

V

S

= 5 V 160 67 72 20 9

0.1 dB Bandwidth (MHz)

VS = 5 V 7 32

REV. A

–16–

AD8041

8-Lead Plastic DIP

(N-8)

0.011±0.003
(0.28±0.08)

0.30 (7.62)

REF

15°

0°

0.10

(2.54)

BSC

SEATING
PLANE

0.035±0.01
(0.89±0.25)

0.18±0.03

(4.57±0.76)

0.033
(0.84)

NOM

0.018±0.003
(0.46±0.08)

0.125

(3.18)

MIN

0.165±0.01

(4.19±0.25)

0.39 (9.91) MAX

PIN 1

4

58

1

0.25

(6.35)

0.31

(7.87)

C01058–0–4/01(A)

PRINTED IN U.S.A.

8-Lead Plastic SOIC

(SO-8)

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

8ⴗ
0ⴗ

0.0196 (0.50)

0.0099 (0.25)

ⴛ 45ⴗ

85

41

0.1968 (5.00)

0.1890 (4.80)

0.2440 (6.20)

0.2284 (5.80)

PIN 1

0.1574 (4.00)

0.1497 (3.80)

0.0500 (1.27)
BSC

0.0688 (1.75)

0.0532 (1.35)

SEATING

PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

AD8041–Revision History

Location Page

Data Sheet changed from REV. 0 to REV. A.

Specifications changed DISABLE CHARACTERISTICS, Off Voltage (Device Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

8-Lead Ceramic DIP

(Q-8)

1

4

85

0.310 (7.87)

0.220 (5.59)

PIN 1

0.005 (0.13)
MIN

0.055 (1.4)
MAX

0.100 (2.54)
BSC

15°

0°

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

SEATING
PLANE

0.200 (5.08)
MAX

0.405 (10.29) MAX

0.150
(3.81)
MIN

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

0.070 (1.78)

0.030 (0.76)

0.060 (1.52)

0.015 (0.38)