Datasheet AD8038, AD8039 Datasheet (ANALOG DEVICES)

Low Power, 350 MHz

–V

FEATURES

Low power: 1 mA supply current/amp
High speed

350 MHz, −3 dB bandwidth (G = +1)

425 V/μs slew rate
Low cost
Low noise

8 nV/√Hz @ 100 kHz

600 fA/√Hz @ 100 kHz
Low input bias current: 750 nA maximum
Low distortion

−90 dB SFDR @ 1 MHz

−65 dB SFDR @ 5 MHz
Wide supply range: 3 V to 12 V
Small packaging: 8-lead SOT-23, 5-lead SC70, and 8-lead SOIC

APPLICATIONS

Battery-powered instrumentation
Filters
A/D drivers
Level shifting
Buffering
Photo multipliers

Voltage Feedback Amplifiers

AD8038/AD8039

FUNCTIONAL BLOCK DIAGRAM

AD8038

NC

1

–IN

2

+IN

3

4

S

NC = NO CONNECT

Figure 1. 8-lead SOIC (R)

OUT

–V

+IN

AD8038

1

2

S

3

V

Figure 2. 5-Lead SC70 (KS)

AD8039

1

V

OUT1

2

–IN1

+IN1

3

–V

4

S

NC = NO CONNECT

Figure 3. 8-Lead SOIC (R) and 8-Lead SOT-23 (RJ)

DISABLE

8

+V

7

V

6

NC

5

5

4

8

7

6

5

OUT

S

+V

–IN

+V

V

OUT2

–IN2

+IN2

2951-001

S

2951-002

S

02951-003

GENERAL DESCRIPTION

The AD8038 (single) and AD8039 (dual) amplifiers are high speed
(350 MHz) voltage feedback amplifiers with an exceptionally low
quiescent current of 1.0 mA/amplifier typical (1.5 mA maximum).
The AD8038 single amplifier in the 8-lead SOIC package has a
disable feature. Despite being low power and low cost, the amplifier
provides excellent overall performance. Additionally, it offers a
high slew rate of 425 V/µs and a low input offset voltage of 3 mV
maximum.

The Analog Devices, Inc., proprietary XFCB process allows low
noise operation (8 nV/√Hz and 600 fA/√Hz) at extremely low
quiescent currents. Given a wide supply voltage range (3 V to 12 V),
wide bandwidth, and small packaging, the AD8038 and AD8039
amplifiers are designed to work in a variety of applications
where power and space are at a premium.

The AD8038 and AD8039 amplifiers have a wide input common­mode range of 1 V from either rail and swing to within 1 V of each
rail on the output. These amplifiers are optimized for driving
capacitive loads up to 15 pF. If driving larger capacitive loads, a small
series resistor is needed to avoid excessive peaking or overshoot.

The AD8039 amplifier is available in a 8-lead SOT-23 package,
and the single AD8038 is available in both an 8-lead SOIC and a
5-lead SC70 package. These amplifiers are rated to work over
the industrial temperature range of −40°C to +85°C.

24

G = +10

21

18

15

G = +5

12

9

G = +2

GAIN (dB)

6

3

G = +1

0

–3

–6

FREQUENCY (MHz)

Figu re 4. Small Signal Frequency Response for Various Gains,

V

= 500 mV p-p, VS = ±5 V

OUT

10000.1 1 10 100

2951-004

Rev. G

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2002–2009 Analog Devices, Inc. All rights reserved.

AD8038/AD8039

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

Maximum Power Dissipation ..................................................... 5

Output Short Circuit .................................................................... 5

ESD Caution .................................................................................. 5

Typical Performance Characteristics ............................................. 6

Layout, Grounding, and Bypassing Considerations .................. 13

REVISION HISTORY

8/09—Rev. F to Rev. G

Changes to Applications Section and General Description

Section ................................................................................................ 1

Changes to Disable Section and Grounding Section ................. 13

Changes to Low Power ADC Driver Section and Low Power

Active Video Filter Section ............................................................ 14

Updated Outline Dimensions ....................................................... 15

Changes to Ordering Guide .......................................................... 16

8/04—Rev. E to Rev. F

Changes to Figure 4 ........................................................................ 10

8/03—Rev. D to Rev. E

Change to TPC 34............................................................................. 8

7/03—Rev. C to Rev. D

Changes to Ordering Guide ............................................................ 4

Updated TPC 35 Caption ................................................................ 8

6/03—Rev. B to Rev. C

Updated Connection Diagrams ...................................................... 1

Updated Ordering Guide ................................................................. 4

Updated Outline Dimensions ....................................................... 11

Disable ......................................................................................... 13

Power Supply Bypassing ............................................................ 13

Grounding ................................................................................... 13

Input Capacitance ...................................................................... 13

Output Capacitance ................................................................... 13

Input-to-Output Coupling ........................................................ 13

Applications Information .............................................................. 14

Low Power ADC Driver ............................................................ 14

Low Power Active Video Filter ................................................. 14

Outline Dimensions ....................................................................... 15

Ordering Guide .......................................................................... 16

5/02—Rev. A to Rev. B

Add Part Number AD8038 ............................................... Universal

Changes to Product Title .................................................................. 1

Changes to Features .......................................................................... 1

Changes to Product Description ..................................................... 1

Changes to Connection Diagram .................................................... 1

Update to Specifications ................................................................... 2

Update to Maximum Power Dissipation ........................................ 4

Update to Output Short Circuit ....................................................... 4

Update to Ordering Guide ............................................................... 4

Change to Figure 2 ............................................................................ 4

Change to TPC 2 ............................................................................... 5

Change to TPC 18 ............................................................................. 6

Change to TPC 27 ............................................................................. 7

Change to TPC 29 ............................................................................. 8

Change to TPC 30 ............................................................................. 8

Change to TPC 31 ............................................................................. 8

Added TPC 36 .................................................................................... 8

Added TPC 37 .................................................................................... 9

Edits to Low Power Active Video Filter ....................................... 10

Change to Figure 4 ......................................................................... 10

4/02—Rev. 0 to Rev. A

Changes to Features .......................................................................... 1

Update Specifications ................................................................... 2, 3

Edits to TPC 19 .................................................................................. 7

Rev. G | Page 2 of 16

AD8038/AD8039

SPECIFICATIONS

TA = 25°C, VS = ±5 V, RL = 2 kΩ, Gain = +1, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, VO = 0.5 V p-p 300 350 MHz
G = +2, VO = 0.5 V p-p 175 MHz
G = +1, VO = 2 V p-p 100 MHz
Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 45 MHz
Slew Rate G = +1, VO = 2 V step, RL = 2 kΩ 400 425 V/µs
Overdrive Recovery Time G = +2, 1 V overdrive 50 ns
Settling Time to 0.1% G = +2, VO = 2 V step 18 ns

NOISE/HARMONIC PERFORMANCE

SFDR

Second Harmonic fC = 1 MHz, VO = 2 V p-p, RL = 2 kΩ −90 dBc
Third Harmonic fC = 1 MHz, VO = 2 V p-p, RL = 2 kΩ −92 dBc
Second Harmonic fC = 5 MHz, VO = 2 V p-p, RL = 2 kΩ −65 dBc

Third Harmonic fC = 5 MHz, VO = 2 V p-p, RL = 2 kΩ −70 dBc
Crosstalk, Output-to-Output (AD8039) f = 5 MHz, G = +2 −70 dB
Input Voltage Noise f = 100 kHz 8 nV/√Hz
Input Current Noise f = 100 kHz 600 fA/√Hz

DC PERFORMANCE

Input Offset Voltage 0.5 3 mV
Input Offset Voltage Drift 4.5 µV/°C
Input Bias Current 400 750 nA
Input Bias Current Drift 3 nA/°C
Input Offset Current ±25 nA
Open-Loop Gain VO = ±2.5 V 70 dB

INPUT CHARACTERISTICS

Input Resistance 10 MΩ
Input Capacitance 2 pF
Input Common-Mode Voltage Range RL = 1 kΩ ±4 V
Common-Mode Rejection Ratio VCM = ±2.5 V 61 67 dB

OUTPUT CHARACTERISTICS

DC Output Voltage Swing RL = 2 kΩ, saturated output ±4 V
Capacitive Load Drive 30% overshoot, G = +2 20 pF

POWER SUPPLY

Operating Range 3.0 12 V
Quiescent Current per Amplifier 1.0 1.5 mA
Power Supply Rejection Ratio −Supply −71 −77 dB

+Supply −64 −70 dB
POWER-DOWN DISABLE1

Turn-On Time 180 ns
Turn-Off Time 700 ns
Disable Voltage—Part is Off +VS − 4.5 V
Disable Voltage—Part is On +VS − 2.5 V
Disabled Quiescent Current 0.2 mA
Disabled In/Out Isolation f = 1 MHz −60 dB

1

Only available in AD8038 8-lead SOIC package.

Rev. G | Page 3 of 16

AD8038/AD8039

TA = 25°C, VS = 5 V, RL = 2 kΩ to VS/2, Gain = +1, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, VO = 0.2 V p-p 275 300 MHz
G = +2, VO = 0.2 V p-p 150 MHz
G = +1, VO = 2 V p-p 30 MHz
Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 45 MHz
Slew Rate G = +1, VO = 2 V step, RL = 2 kΩ 340 365 V/µs
Overdrive Recovery Time G = +2, 1 V overdrive 50 ns
Settling Time to 0.1% G = +2, VO = 2 V step 18 ns

NOISE/HARMONIC PERFORMANCE

SFDR

Second Harmonic fC = 1 MHz, VO = 2 V p-p, RL = 2 kΩ −82 dBc
Third Harmonic fC = 1 MHz, VO = 2 V p-p, RL = 2 kΩ −79 dBc
Second Harmonic fC = 5 MHz, VO = 2 V p-p, RL = 2 kΩ −60 dBc

Third Harmonic fC = 5 MHz, VO = 2 V p-p, RL = 2 kΩ −67 dBc
Crosstalk, Output-to-Output f = 5 MHz, G = +2 −70 dB
Input Voltage Noise f = 100 kHz 8 nV/√Hz
Input Current Noise f = 100 kHz 600 fA/√Hz

DC PERFORMANCE

Input Offset Voltage 0.8 3 mV
Input Offset Voltage Drift 3 V/°C
Input Bias Current 400 750 nA
Input Bias Current Drift 3 nA/°C
Input Offset Current ±30 nA
Open-Loop Gain VO = ±2.5 V 70 dB

INPUT CHARACTERISTICS

Input Resistance 10 MΩ
Input Capacitance 2 pF
Input Common-Mode Voltage Range RL = 1 kΩ 1.0 − 4.0 V
Common-Mode Rejection Ratio VCM = ±1 V 59 65 dB

OUTPUT CHARACTERISTICS

DC Output Voltage Swing RL = 2 kΩ, saturated output 0.9 − 4.1 V
Capacitive Load Drive 30% overshoot 20 pF

POWER SUPPLY

Operating Range 3 12 V
Quiescent Current per Amplifier 0.9 1.5 mA
Power Supply Rejection Ratio −65 −71 dB

POWER-DOWN DISABLE1

Turn-On Time 210 ns
Turn-Off Time 700 ns
Disable Voltage—Part is Off +VS − 4.5 V
Disable Voltage—Part is On +VS − 2.5 V
Disabled Quiescent Current 0.2 mA
Disabled In/Out Isolation f = 1 MHz −60 dB

1

Only available in AD8038 8-lead SOIC package.

Rev. G | Page 4 of 16

AD8038/AD8039

ABSOLUTE MAXIMUM RATINGS

2.0

Table 3.

Parameter Rating

Supply Voltage 12.6 V

Power Dissipation See Figure 5

Common-Mode Input Voltage ±VS

Differential Input Voltage ±4 V

Storage Temperature Range −65°C to +125°C

Operating Temperature Range −40°C to +85°C

Lead Temperature (Soldering, 10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8038/AD8039

package is limited by the associated rise in junction temperature

(T

) on the die. The plastic encapsulating the die locally reaches

J

the junction temperature. At approximately 150°C, which is the

glass transition temperature, the plastic changes its properties.

Even temporarily exceeding this temperature limit may change

the stresses that the package exerts on the die, permanently

shifting the parametric performance of the AD8038/AD8039.

Exceeding a junction temperature of 175°C for an extended

time can result in changes in the silicon devices, potentially

causing failure.

The still-air thermal properties of the package and PCB (θ

ambient temperature (T

package (P

) determine the junction temperature of the die.

D

), and total power dissipated in the

A

The junction temperature can be calculated as

T

= TA + (PD × θJA)

J

The power dissipated in the package (P

) is the sum of the

D

quiescent power dissipation and the power dissipated in the

package due to the load drive for all outputs. The quiescent power

is the voltage between the supply pins (V

quiescent current (I

). Assuming the load (RL) is referenced to

S

midsupply, then the total drive power is V

) multiplied by the

S

/2 × I

S

, some of which

OUT

is dissipated in the package and some in the load (V

The difference between the total drive power and the load

power is the drive power dissipated in the package.

P

= quiescent power + (total drive power − load power)

D

P

= [VS × IS] + [(VS/2) × (V

D

OUT/RL

)] − [V

OUT

2

/RL]

OUT

× I

JA

OUT

),

).

1.5

1.0

0.5

MAXIMUM POWER DISSIPATION (W)

0

–55

Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

RMS output voltages should be considered. If RL is referenced to
V

, as in single-supply operation, then the total drive power is

S−

V

× I

. If the rms signal levels are indeterminate, consider the

S

OUT

worst case, when V

= (VS × IS) + (VS/4)2/RL

P

D

In single-supply operation with R
is V

= VS /2.

OUT

Airflow increases heat dissipation, effectively reducing θ
addition, more metal directly in contact with the package leads
from metal traces, throughholes, ground, and power planes reduce
the θ

. Care must be taken to minimize parasitic capacitances at

JA

the input leads of high speed op amps as discussed in the
Layout, Grounding, and Bypassing Considerations section.

Figure 5 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(125°C/W), 5-lead SC70 (210°C/W), and 8-lead SOT-23
(160°C/W) packages on a JEDEC standard 4-layer board.
θ

values are approximations.

JA

OUTPUT SHORT CIRCUIT

Shorting the output to ground or drawing excessive current
from the AD8038/AD8039 will likely cause a catastrophic failure.

ESD CAUTION

SOIC-8

SOT-23-8

SC70-5

–25 5 35 65 95 125

AMBIENT TEMPERATURE (°C)

= VS /4 for RL to midsupply

OUT

referenced to VS−, worst case

L

JA

. In

02951-005

Rev. G | Page 5 of 16

AD8038/AD8039

TYPICAL PERFORMANCE CHARACTERISTICS

Default Conditions: ±5 V, CL = 5 pF, G = +2, RG = RF = 1 kΩ, RL = 2 kΩ, VO = 2 V p-p, Frequency = 1 MHz, TA = 25°C.

24

G = +10

21

18

G = +5

15

12

9

G = +2

GAIN (dB)

6

3

G = +1

0

–3

–6

1 100

10

FREQUENCY ( MHz)

Figure 6. Small Signal Frequency Response for Various Gains,

= 500 mV p-p

V

OUT

7

V

= ±5V

S

VS = ±1.5V

= ±2.5V

V

S

6

5

4

10000.1

2951-006

7

6

5

4

3

GAIN (dB)

2

1

0

RL = 500Ω

R

L

FREQUE NCY (MHz)

RL = 2kΩ

= 1kΩ

Figure 9. Small Signal Frequency Response for Various RL,

= 5 V, V

V

S

8

7

6

5

= 500 mV p-p

OUT

RL = 2kΩ

RL = 500Ω

10000.1 1 10010

2951-009

3

GAIN (dB)

2

1

0

FREQUENCY ( MHz)

Figure 7. Small Signal Frequency Response for Various Supplies,

= 500 mV p-p

V

OUT

7

6

5

4

3

GAIN (dB)

2

1

0

FREQUENCY ( MHz)

R

L

= 500Ω

= 1kΩ

R

L

R

= 2kΩ

L

Figure 8. Small Signal Frequency Response for Various RL,

= ±5 V, V

V

S

= 500 mV p-p

OUT

4

GAIN (dB)

3

2

1

10000.1 1 10010

02951-007

0

0.1 1 10010

FREQUENCY ( MHz)

RL = 1kΩ

2951-010

Figure 10. Large Signal Frequency Response for Various RL,

= 3 V p-p, VS = 5 V

V

OUT

8

7

6

5

4

GAIN (dB)

3

2

1

10000.1 1 10010

02951-008

0

0.1 1 10010

FREQUENCY (MHz)

RL = 2kΩ

RL = 500Ω

RL = 1kΩ

02951-011

Figure 11. Large Signal Frequency Response for Various RL,

V

= 4 V p-p, VS = ±5 V

OUT

Rev. G | Page 6 of 16

AD8038/AD8039

–

5

4

3

2

1

0

GAIN (dB)

–1

–2

–3

–4

–5

CL = 15pF

CL = 10pF

CL = 5pF

FREQUENCY ( MHz)

Figure 12. Small Signal Frequency Response for Various CL,

= 500 mV p-p, VS = ±5 V, G = +1

V

OUT

7

5

3

1

GAIN (dB)

–1

CL = 15pF

CL = 10pF

CL = 5pF

80

70

60

50

40

30

20

10

OPEN-LOOP GAIN (dB)

0

–10

–20

1000110010

2951-012

0.01

0.1

PHASE

GAIN

1 10 100 1000

FREQUENCY (MHz)

Figure 15. Open-Loop Gain and Phase, VS = ±5 V

9

6

–40°C

3

GAIN (dB)

0

+85°C

180

135

90

45

PHASE (Degrees)

0

–45

+25°C

02951-015

–3

–5

FREQUENCY ( MHz)

1000110010

Figure 13. Small Signal Frequency Response for Various CL,

= 500 mV p-p, VS = 5 V, G = +1

V

OUT

2

V

= 200mV

1

0

–1

–2

GAIN (dB)

–3

–4

–5

–6

0.1

FREQUENCY ( MHz)

V

V

V

OUT

OUT

OUT

OUT

= 1V

= 500mV

= 2V

10001 10010

Figure 14. Frequency Response for Various Output Voltage Levels

–3

0.1 1 10 100 1000

RL = 500Ω HD2

R

= 2kΩ HD2

L

= ±5 V, V

V

S

FREQUENCY (M Hz)

= ±5 V, V

S

5432678

FREQUENCY (M Hz)

OUT

= 2 V p-p

OUT

R

= 2kΩ HD3

L

= 2 V p-p, G = +2

9

02951-013

Figure 16. Frequency Response vs. Temperature,

Gain = +2, V

50

–55

–60

–65

–70

–75

–80

HARMONIC DIS TORTION (dBc)

–85

–90

02951-014

Figure 17. Harmonic Distortion vs. Frequency for Various Loads,

RL = 500Ω HD3

1

02951-016

10

02951-017

Rev. G | Page 7 of 16

AD8038/AD8039

–

–

–

–

–

45

–50

HARMONIC DIS TORTION ( dBc)

–55

–60

–65

–70

–75

–80

–85

–90

= 500Ω HD3

R

L

15432 678910

= 500Ω HD2

R

L

= 2kΩ HD2

R

L

FREQUENCY ( MHz)

= 2kΩ HD3

R

L

Figure 18. Harmonic Distortion vs. Frequency for Various Loads,

HARMONIC DIS TORTION (dBc)

–60

–70

–80

–90

50

V

G = +1 HD2

G = +2 HD2

= 5 V, V

S

= 2 V p-p, G = +2

OUT

G = +2 HD3

G = +1 HD3

02951-018

40

–50

10MHz HD3

–60

–70

HARMONIC DIS TORTION (dBc)

–80

–90

–100

1

1MHz HD2

234

AMPLITUDE (V p-p)

Figure 21. Harmonic Distortion vs. V

= ±5 V, G = +2

V

S

HARMONIC DIS TORTION ( dBc)

45

–55

–65

–75

–85

10MHz HD2

10MHz HD3

5MHz HD2

5MHz HD3

1MHz HD3

1MHz HD2

10MHz HD2

5MHz HD2

5MHz HD3

1MHz HD3

Amplitude for Various Frequencies,

OUT

2951-021

–100

15432 678910

FREQUENCY (MHz)

Figure 19. Harmonic Distortion vs. Frequency for Various Gains,

= ±5 V, V

V

S

50

–60

–70

–80

HARMONIC DIS TORTION (dBc)

–90

–100

15432 678910

G = +1 HD2

G = +2 HD2

G = +1 HD3

F

Q

E

R

= 2 V p-p

OUT

G = +2 HD3

Y

C

N

E

U

)

z

H

M

(

Figu re 20. Harmonic Distortion vs. Frequency for Various Gains,

= 5 V, V

V

S

= 2 V p-p

OUT

–95

1.0

02951-019

1.5 2.0 2.5 3.0

AMPLITUDE (V p-p)

02951-022

Figure 22. Harmonic Distortion vs. Amplitude for Various Frequencies,

= 5 V, G = +2

V

S

1000

100

10

VOLTAGE NOIS E (nV/ Hz)

1

10

FREQUENCY (Hz)

02951-020

Figure 23. Input Voltage Noise vs. Frequency

10M100k1k100 10k 100M1M

02951-023

Rev. G | Page 8 of 16

AD8038/AD8039

√

100k

C

= 25pF WITH

L

R

= 19.6Ω

10k

Hz)

SNUB

NOISE (fA/

1k

100

10

100

1k 10k 100k 1M

FREQUENCY ( Hz)

Figure 24. Input Current Noise vs. Frequency

= 500Ω

R

L

RL = 2kΩ

50mV/DIV 5ns/ DIV

02951-025

Figure 25. Small Signal Transient Response for Various RL, VS = 5 V

CL = 5pF

CL = 10pF

50mV/DIV 5ns/DIV

02951-024

02951-027

Figure 27. Small Signal Transient Response for Various CL, VS = 5 V

CL = 25pF WITH
R

= 19.6Ω

SNUB

CL = 5pF

CL = 10pF

50mV/DIV 5ns/DIV

02951-028

Figure 28. Small Signal Transient Response for Various CL, VS = ±5 V

R

= 500Ω

L

Figure 26. Small Signal Transient Response for Various RL, VS = ±5 V

RL = 2kΩ

50mV/DIV 5ns/DIV

02951-026

Rev. G | Page 9 of 16

RL = 500Ω

2.5V

500mV/DIV 5ns/DIV

RL = 2kΩ

02951-029

Figure 29. Large Signal Transient Response for Various RL, VS = 5 V

AD8038/AD8039

RL = 2kΩ

RL = 500Ω

1V/DIV 5ns/DIV

02951-030

Figure 30. Large Signal Transient Response for Various RL, VS = ±5 V

CL = 25pF

CL = 5pF

2.5V

IN

OUT

2V/DIV

50ns/DIV

Figure 33. Input Overdrive Recovery, Gain = +1

IN

OUT

02951-033

500mV/DIV

5ns/DIV

02951-031

Figure 31. Large Signal Transient Response for Various CL, VS = 5 V

CL = 10pF

CL = 5pF

500mV/DIV

5ns/DIV

02951-032

Figure 32. Large Signal Transient Response for Various CL, VS = ±5 V

INPUT 1V/DIV
OUTPUT 2V/DIV

Figure 34. Output Overdrive Recovery, Gain = +2

2mV/DIV

ERROR

+0.1%

–0.1%

0

t = 0

V

0.5V/DIV 5ns/DIV

VOLTAGE

IN

Figure 35. 0.1% Settling Time V

50ns/DIV

= 2 V p-p

OUT

VS = ±5V
G = +2

= 2V p-p

V

OUT

02951-034

02951-035

Rev. G | Page 10 of 16

AD8038/AD8039

–

–

10

–20

–30

–40

CROSSTALK (dB)

–50

–60

–70

–80

–90

–100

SIDE B

SIDE A

FREQUENCY ( MHz)

Figure 36. AD8039 Crosstalk, VIN = 1 V p-p, Gain = +1

10

–20

–30

–40

–50

CMRR (dB)

–60

–70

–80

1 100010 100

VS = +5V VS = ±5V

FREQUENCY (MHz )

Figure 37. CMRR vs. Frequency, VIN = 1 V p-p

1000

10000.1 1 10 100

2951-036

02951-037

10

0

–10

–20

–30

–40

PSRR (dB)

–50

–60

–70

–80

–90

–PSRR

+PSRR

FREQUENCY ( MHz)

Figure 39. PSRR vs. Frequency

9

8

7

6

5

(p-p)

4

OUT

V

3

2

1

0

0 100 200 300 400 500

V

V

R

= ±5V

S

= +5V

S

LOAD

(Ω)

Figure 40. Output Swing vs. Load Resistance

1.25

10000.10.01 1 10 100

02951-039

02951-040

100

10

IMPEDANCE Ω)

1

VS = ±5V

= +5V

V

0.1

S

10000.10.01 1 10 100

FREQUENCY (M Hz)

02951-038

Figure 38. Output Impedance vs. Frequency

1.00

0.75

0.50

SUPPLY CURRENT (mA)

0.25

0

012

246810

SUPPLY VOLTAGE (V)

02951-041

Figure 41. AD8038 Supply Current vs. Supply Voltage

Rev. G | Page 11 of 16

AD8038/AD8039

A

0

–10

–20

–30

–40

TION (dB)

–50

ISOL

–60

–70

–80

–90

0.1 10 1001

FREQUENCY ( MHz)

Figure 42. AD8038 Input-Output Isolation (G = +2, R

1000

= 2 kΩ, VS = ±5 V)

L

02951-042

Rev. G | Page 12 of 16

AD8038/AD8039

LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS

DISABLE

The AD8038 in the 8-lead SOIC package provides a disable

feature. This feature disables the input from the output (see

Figure 42 for input-output isolation) and reduces the quiescent

current from typically 1 mA to 0.2 mA. When the

node is pulled below 4.5 V from the positive supply rail, the part

becomes disabled. To enable the part, the

to be pulled to greater than (V

– 2.5).

S

DISABLE

DISABLE

node needs

POWER SUPPLY BYPASSING

Power supply pins are actually inputs, and care must be taken

so that a noise-free stable dc voltage is applied. The purpose of

bypass capacitors is to create low impedances from the supply

to ground at all frequencies, thereby shunting or filtering a

majority of the noise.

Decoupling schemes are designed to minimize the bypassing

impedance at all frequencies with a parallel combination of

capacitors. The 0.01 µF or 0.001 F (X7R or NPO) chip capacitors

are critical and should be placed as close as possible to the

amplifier package. Larger chip capacitors, such as 0.1 F

capacitors, can be shared among a few closely spaced active

components in the same signal path. A 10 F tantalum capacitor

is less critical for high frequency bypassing and, in most cases,

only one per board is needed at the supply inputs.

GROUNDING

A ground plane layer is important in densely packed PC boards

to spread the current minimizing parasitic inductances. However,

an understanding of where the current flows in a circuit is critical

to implementing effective high speed circuit design. The length

of the current path is directly proportional to the magnitude of

parasitic inductances and, therefore, the high frequency impedance

of the path. High speed currents in an inductive ground return

create an unwanted voltage noise.

The length of the high frequency bypass capacitor leads is most

critical. A parasitic inductance in the bypass grounding works

against the low impedance created by the bypass capacitor. Because

load currents flow from the supplies as well, the ground for the

load impedance should be at the same physical location as the

bypass capacitor grounds. For the larger value capacitors, which

are intended to be effective at lower frequencies, the current

return path distance is less critical.

INPUT CAPACITANCE

Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground. A
few picofarads of capacitance reduces the input impedance at
high frequencies, in turn increasing the gain of the amplifiers,
causing peaking of the frequency response, or even oscillations
if severe enough. It is recommended that the external passive
components that are connected to the input pins be placed as
close as possible to the inputs to avoid parasitic capacitance.
The ground and power planes must be kept at a distance of at
least 0.05 mm from the input pins on all layers of the board.

OUTPUT CAPACITANCE

To a lesser extent, parasitic capacitances on the output can cause
peaking of the frequency response. Two methods to minimize
this effect include the following:

• Put a small value resistor in series with the output to isolate

the load capacitor from the output stage of the amplifier, see
Figure 12, Figure 13, Figure 27, and Figure 28.

• Increase the phase margin with higher noise gains or add

a pole with a parallel resistor and capacitor from −IN to
the output.

INPUT-TO-OUTPUT COUPLING

The input and output signal traces should not be parallel to
minimize capacitive coupling between the inputs and outputs,
avoiding any positive feedback.

Rev. G | Page 13 of 16

AD8038/AD8039

APPLICATIONS INFORMATION

LOW POWER ADC DRIVER

1kΩ

+5V

0.1µF 10µF

1kΩ

V

IN

0V

1kΩ

8

3

2

1

1kΩ

AD8039

1kΩ

1kΩ

1kΩ

6

5

–5V

7

4

10µF

0.1µF

1kΩ

Figure 43. Schematic to Drive AD9203 with the AD8039

The AD9203 is a low power (125 mW on a 5 V supply), 40 MSPS
10-bit converter. As such, the low power, high performance
AD8039 is an appropriate amplifier choice to drive it.

In low supply voltage applications, differential analog inputs
are needed to increase the dynamic range of the ADC inputs.
Differential driving can also reduce second and other even-order
distortion products. The AD8039 can be used to make a dc­coupled, single-ended-to-differential driver for driving these
ADCs. Figure 43 is a schematic of such a circuit for driving the
AD9203, 10-bit, 40 MSPS ADC.

The AD9203 works best when the common-mode voltage at the
input is at the midsupply or 2.5 V. The output stage design of
the AD8039 makes it ideal for driving these types of ADCs.

In this circuit, one of the op amps is configured in the inverting
mode, and the other is in the noninverting mode. However, to
provide better bandwidth matching, each op amp is configured
for a noise gain of +2. The inverting op amp is configured for a
gain of −1, and the noninverting op amp is configured for a gain
of +2. Each has a very similar ac response. The input signal to
the noninverting op amp is divided by 2 to normalize its voltage
level and make it equal to the inverting output.

The outputs of the op amps are centered at 2.5 V, which is the
midsupply level of the ADC. This is accomplished by first taking
the 2.5 V reference output of the ADC and dividing it by 2 with
a pair of 1 k resistors. The resulting 1.25 V is applied to the
positive input of each op amp. This voltage is then multiplied by
the gain of the op amps to provide a 2.5 V level at each output.

2.5V

0.1µF 10 µF

50Ω

VINP

50Ω

VINN

3V

REF

AD9203

02951-043

LOW POWER ACTIVE VIDEO FILTER

Some composite video signals derived from a digital source
contain clock feedthrough that can limit picture quality. Active
filters made from op amps can be used in this application, but
they consume 25 mW to 30 mW for each channel. In power­sensitive applications, this can be too much, requiring the use
of passive filters that can create impedance matching problems
when driving any significant load.

The AD8038 can be used to make an effective low-pass active
filter that consumes one-fifth of the power consumed by an
active filter made from an op amp. Figure 44 shows a circuit
that uses a AD8038 with ±2.5 V supplies to create a three-pole
Sallen-Key filter. This circuit uses a single RC pole in front of a
standard 2-pole active section.

R

680pF

+2.5V

R3

R2

R1

200Ω

V

IN

R4

49.9Ω

499Ω

C1
100pF

49.9Ω

C3
33pF

AD8038

–2.5V

Figure 44. Low-Pass Filter for Video

Figure 45 shows the frequency response of this filter. The
response is down 3 dB at 6 MHz; therefore, it passes the video
band with little attenuation. The rejection at 27 MHz is 45 dB,
which provides more than a factor of 100 in suppression of the
clock components at this frequency.

10

0

–10

–20

–30

GAIN (dB)

–40

–50

–60

0.1

110

FREQUENCY (MHz)

Figure 45. Video Filter Response

1Ω

0.1µF

0.1µF

F

10µF

V

OUT

R5
75Ω

10µF

100

02951-045

02951-044

Rev. G | Page 14 of 16

AD8038/AD8039

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLL ING DIMENSI ONS ARE IN MILLIMETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-A A

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 46. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

2.20

2.00

1.80

1.35

1.25

1.15

PIN 1

1.00

0.90

0.70

0

.

1

0

M

A

X

0.10 COPLANARITY

123

0.30

0.15

COMPLIANT TO JEDEC STANDARDS MO-203-AA

45

0.65 BSC

2.40

2.10

1.80

1.10

0.80

SEATING
PLANE

0.40

0.10

0.22

0.08

0.46

0.36

0.26

Figure 47. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-5)

Dimensions shown in millimeters

Rev. G | Page 15 of 16

AD8038/AD8039

0

0

1.70

1.60

1.50

PIN 1

INDICATOR

1.30

1.15

0.90

.15 MAX
.05 MIN

3.00

2.90

2.80

76

8

1234

COMPLIANT TO JEDEC ST ANDARDS MO-178-BA

1.95
BSC

5

0.38 MAX

0.22 MIN

0.65 BSC

1.45 MAX

0.95 MIN

3.00

2.80

2.60

SEATING
PLANE

0.22 MAX

0.08 MIN

8°

0.60

4°

BSC

0°

0.60

0.45

0.30

121608-A

Figure 48. 8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8038AR −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8038AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8038AR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8038ARZ
AD8038ARZ-REEL
AD8038ARZ-REEL7
AD8038AKSZ-R2
AD8038AKSZ-REEL
AD8038AKSZ-REEL7

1

−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8

1

−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8

1

−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8

1

−40°C to +85°C 5-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-5 H1C

1

−40°C to +85°C 5-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-5 H1C

1

−40°C to +85°C 5-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-5 H1C
AD8039AR −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8039AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8039AR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8039ARZ
AD8039ARZ-REEL
AD8039ARZ-REEL7

1

−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8

1

−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8

1

−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8039ART-R2 −40°C to +85°C 8-Lead Small Outline Transistor Package [SOT-23] RJ-8
AD8039ART-REEL −40°C to +85°C 8-Lead Small Outline Transistor Package [SOT-23] RJ-8
AD8039ART-REEL7 −40°C to +85°C 8-Lead Small Outline Transistor Package [SOT-23] RJ-8
AD8039ARTZ-R2
AD8039ARTZ-REEL
AD8039ARTZ-REEL7

1

Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked..

1

−40°C to +85°C 8-Lead Small Outline Transistor Package [SOT-23] RJ-8 HYA#

1

−40°C to +85°C 8-Lead Small Outline Transistor Package [SOT-23] RJ-8 HYA#

1

−40°C to +85°C 8-Lead Small Outline Transistor Package [SOT-23] RJ-8 HYA#

HYA
HYA
HYA

©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02951-0-8/09(G)

Rev. G | Page 16 of 16