Page 1
–4 –3 –2 –1 0 1 2 3 4
4
3
2
1
0
–1
–2
–3
–4
INPUT VOLTAGE – Volts
OUTPUT VOLTAGE – Volts
VL = –3V
VL = –2V
VL = –1V
VH = 1V
VH = 2V
VH = 3V
AD8036
1
2
3
4
8
7
6
5
AD8036/
AD8037
NC
–INPUT
+INPUT
–V
S
+V
S
OUTPUT
(Top View)
NC = NO CONNECT
V
L
V
H
Low Distortion, Wide Bandwidth
a
Voltage Feedback Clamp Amps
AD8036/AD8037
FEATURES
Superb Clamping Characteristics
3 mV Clamp Error
1.5 ns Overdrive Recovery
Minimized Nonlinear Clamping Region
240 MHz Clamp Input Bandwidth
ⴞ3.9 V Clamp Input Range
Wide Bandwidth AD8036 AD8037
Small Signal 240 MHz 270 MHz
Large Signal (4 V p-p) 195 MHz 190 MHz
Good DC Characteristics
2 mV Offset
10 V/ⴗC Drift
Ultralow Distortion, Low Noise
–72 dBc typ @ 20 MHz
4.5 nV/√Hz Input Voltage Noise
High Speed
Slew Rate 1500 V/s
Settling 10 ns to 0.1%, 16 ns to 0.01%
ⴞ3 V to ⴞ5 V Supply Operation
APPLICATIONS
ADC Buffer
IF/RF Signal Processing
High Quality Imaging
Broadcast Video Systems
Video Amplifier
Full Wave Rectifier
and large-signal bandwidths and ultralow distortion. The
AD8036 achieves –66 dBc at 20 MHz, and 240 MHz smallsignal and 195 MHz large-signal bandwidths. The AD8036 and
AD8037’s recover from 2× clamp overdrive within 1.5 ns.
These characteristics position the AD8036/AD8037 ideally for
driving as well as buffering flash and high resolution ADCs.
In addition to traditional output clamp amplifier applications,
the input clamp architecture supports the clamp levels as additional inputs to the amplifier. As such, in addition to static dc
clamp levels, signals with speeds up to 240 MHz can be applied
to the clamp pins. The clamp values can also be set to any
value within the output voltage range provided that V
that V
AD8037 can be used in nontraditional applications such as a
full-wave rectifier, a pulse generator, or an amplitude modula-
PRODUCT DESCRIPTION
The AD8036 and AD8037 are wide bandwidth, low distortion
clamping amplifiers. The AD8036 is unity gain stable. The
AD8037 is stable at a gain of two or greater. These devices allow the designer to specify a high (V
) and low (VCL) output
CH
clamp voltage. The output signal will clamp at these specified
tor. These novel applications are only examples of some of the
diverse applications which can be designed with input clamps.
The AD8036 is offered in chips, industrial (–40°C to +85°C)
and military (–55°C to +125°C) package temperature ranges
and the AD8037 in industrial. Industrial versions are available
in plastic DIP and SOIC; MIL versions are packaged in cerdip.
levels. Utilizing a unique patent pending CLAMPIN™ input
clamp architecture, the AD8036 and AD8037 offer a 10× im-
provement in clamp performance compared to traditional output clamping devices. In particular, clamp error is typically
3 mV or less and distortion in the clamp region is minimized.
This product can be used as a classical op amp or a clamp amplifier where a high and low output voltage are specified.
The AD8036 and AD8037, which utilize a voltage feedback architecture, meet the requirements of many applications which
previously depended on current feedback amplifiers. The
AD8036 and AD8037 exhibit an exceptionally fast and accurate
pulse response (16 ns to 0.01%), extremely wide small-signal
CLAMPIN is a trademark of Analog Devices, Inc.
FUNCTIONAL BLOCK DIAGRAM
8-Lead Plastic DIP (N), Cerdip (Q),
and SO Packages
is greater
. Due to these clamp characteristics, the AD8036 and
L
H
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Figure 1. Clamp DC Accuracy vs. Input Voltage
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
Page 2
AD8036/AD8037–SPECIFICATIONS
(±VS = ±5 V; R
ELECTRICAL CHARACTERISTICS
Parameter Conditions Min Typ Max Min Typ Max Units
DYNAMIC PERFORMANCE
Bandwidth (–3 dB)
Small Signal V
Large Signal
1
Bandwidth for 0.1 dB Flatness V
Slew Rate, Average +/– V
Rise/Fall Time V
Settling Time
To 0.1% V
To 0.01% V
HARMONIC/NOISE PERFORMANCE
2nd Harmonic Distortion 2 V p-p; 20 MHz, R
3rd Harmonic Distortion 2 V p-p; 20 MHz, R
3rd Order Intercept 25 MHz +46 +41 dBm
Noise Figure R
Input Voltage Noise 1 MHz to 200 MHz 6.7 4.5 nV√Hz
Input Current Noise 1 MHz to 200 MHz 2.2 2.1 pA√Hz
Average Equivalent Integrated
Input Noise Voltage 0.1 MHz to 200 MHz 95 60 µV rms
Differential Gain Error (3.58 MHz) R
Differential Phase Error (3.58 MHz) R
Phase Nonlinearity DC to 100 MHz 1.1 1.1 Degree
CLAMP PERFORMANCE
Clamp Voltage Range
2
Clamp Accuracy 2× Overdrive, V
Clamp Nonlinearity Range
Clamp Input Bias Current (V
3
or VL) 8036, V
H
Clamp Input Bandwidth (–3 dB) V
Clamp Overshoot 2× Overdrive, V
Overdrive Recovery 2× Overdrive 1.5 1.3 ns
4,
R
DC PERFORMANCE
Input Offset Voltage
5
= 150 Ω
L
Offset Voltage Drift ±10 ± 10 µV/°C
Input Bias Current 410 39µA
Input Offset Current 0.3 3 0.1 3 µA
Common-Mode Rejection Ratio V
Open-Loop Gain V
INPUT CHARACTERISTICS
Input Resistance 500 500 kΩ
Input Capacitance 1.2 1.2 pF
Input Common-Mode Voltage Range ±2.5 ± 2.5 V
OUTPUT CHARACTERISTICS
Output Voltage Range, R
= 150 Ω±3.2 ±3.9 ± 3.2 ±3.9 V
L
Output Current 70 70 mA
Output Resistance 0.3 0.3 Ω
Short Circuit Current 240 240 mA
POWER SUPPLY
Operating Range ±3.0 ±5.0 ±6.0 ±3.0 ±5.0 ±6.0 V
Quiescent Current 20.5 21.5 18.5 19.5 mA
Power Supply Rejection Ratio T
NOTES
1
See Max Ratings and Theory of Operation sections of data sheet.
2
See Max Ratings.
3
Nonlinearity is defined as the voltage delta between the set input clamp voltage (VH or VL) and the voltage at which V
4
Measured at AV = 50.
5
Measured with respect to the inverting input.
ations subject to change without notice.
Specific
OUT
8036, V
OUT
8036, R
OUT
OUT
V
OUT
OUT
OUT
R
L
R
L
S
L
L
VCH or V
T
MIN–TMAX
T
MIN–TMAX
CH
T
MIN–TMAX
T
MIN–TMAX
T
MIN–TMAX
CM
OUT
T
MIN–TMAX
T
MIN–TMAX
MIN–TMAX
otherwise noted)
≤ 0.4 V p-p 150 240 200 270 MHz
= 2.5 V p-p; 8037, V
OUT
≤ 0.4 V p-p
= 140 Ω; 8037, RF = 274 Ω 130 130 MHz
F
= 4 V Step, 10–90% 900 1200 1100 1500 V/µs
= 0.5 V Step, 10–90% 1.4 1.2 ns
= 4 V Step, 10–90% 2.6 2.2 ns
= 2 V Step 10 10 ns
= 2 V Step 16 16 ns
= 100 Ω –59 –52 –52 –45 dBc
= 500 Ω –66 –59 –72 –65 dBc
= 500 Ω –72 –65 –80 –73 dBc
= 50 Ω 18 14 dB
= 150 Ω 0.05 0.09 0.02 0.04 %
= 150 Ω 0.02 0.04 0.02 0.04 Degree
CL
H, L
or V
CL
= ±2 V 66 90 70 90 dB
= ±2.5 V 48 55 54 60 dB
L
= 100 Ω –68 –61 –70 –63 dBc
L
= +2 V, V
CH
= ±1 V; 8037, V
= 2 V p-p 150 240 180 270 MHz
or VCL = 2 V p-p 1 5 1 5 %
CH
= 100 Ω; A
LOAD
= +1 (AD8036); AV = +2 (AD8037), VH, VL open, unless
V
AD8036A AD8037A
= 3.5 V p-p 160 195 160 190 MHz
OUT
±3.3 ±3.9 ±3.3 ± 3.9 V
= –2 V ±3 ± 10 ±3 ±10 mV
CL
±20 ±20 mV
100 100 mV
= ±0.5 V ±40 ±60 ±50 ± 70 µA
H, L
±80 ±90 µA
27 27mV
11 10 mV
15 15 µA
55µA
40 46 dB
25 24 mA
50 60 56 66
starts deviating from VIN (see Figure 73).
OUT
d
B
REV. A–2–
Page 3
AD8036/AD8037
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Voltage Swing × Bandwidth Product . . . . . . . . . . . 350 V-MHz
|V
|V
Internal Power Dissipation
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 6.3 V
H–VIN
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤ 6.3 V
L–VIN
2
Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . . 1.3 Watts
Small Outline Package (SO) . . . . . . . . . . . . . . . . . . 0.9 Watts
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±1.2 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range N, R . . . . . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Lead Plastic DIP: θJA = 90°C/W
8-Lead SOIC: θJA = 155°C/W
8-Lead Cerdip: θJA = 110°C/W.
METALIZATION PHOTO
Dimensions shown in inches and (mm).
Connect Substrate to –V
–IN
2
V
.
S
+V
H
8
S
7
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by these devices is limited by the associated rise in junction temperature.
The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature
of the plastic, approximately +150°C. Exceeding this limit tem-
porarily may cause a shift in parametric performance due to a
change in the stresses exerted on the die by the package. Exceed-
ing a junction temperature of +175°C for an extended period can
result in device failure.
While the AD8036 and AD8037 are internally short circuit protected, this may not be sufficient to guarantee that the maxi-
mum junction temperature (+150°C) is not exceeded under all
conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
2.0
1.5
1.0
0.5
MAXIMUM POWER DISSIPATION – Watts
0
–50 80
–40
8-LEAD PLASTIC DIP
PACKAGE
8-LEAD SOIC
PACKAGE
010–10–20–30 20 30 40 50 60 70 90
AMBIENT TEMPERATURE – 8C
TJ = +1508C
0.046
(1.17)
OUT
6
Figure 2. Plot of Maximum Power Dissipation vs.
Temperature
ORDERING GUIDE
45
3
+IN –V
S
0.050 (1.27)
–IN
2
8036
AD8036
V
L
V
H
87
+V
S
Model Range Description Option
AD8036AN –40°C to +85°C Plastic DIP N-8
AD8036AR –40°C to +85°C SOIC SO-8
AD8036AR-REEL –40°C to +85°C 13" Tape and Reel SO-8
AD8036AR-REEL7 –40°C to +85°C 7" Tape and Reel SO-8
AD8036ACHIPS –40°C to +85°CDie
Temperature Package Package
AD8036-EB Evaluation Board
5962-9559701MPA –55°C to +125°C Cerdip Q-8
0.046
(1.17)
OUT
6
AD8037AN –40°C to +85°C Plastic DIP N-8
AD8037AR –40°C to +85°C SOIC SO-8
AD8037AR-REEL –40°C to +85°C 13" Tape and Reel SO-8
AD8037AR-REEL7 –40°C to +85°C 7" Tape and Reel SO-8
AD8037ACHIPS –40°C to +85°CDie
AD8037-EB Evaluation Board
3
45
+IN –V
S
0.050 (1.27)
8037
AD8037
V
L
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A –3–
Page 4
AD8036/AD8037
+V
S
RL = 100V
–V
S
49.9V
V
IN
R
F
130V
V
OUT
0.1mF
10mF
AD8036
0.1mF
10mF
PULSE
GENERATOR
TR/T
F
= 350ps
+V
H
V
L
0.1mF
0.1mF
AD8036–Typical Characteristics
R
F
10mF
S
0.1mF
0.1mF
10mF
S
PULSE
GENERATOR
TR/T
= 350ps
F
V
IN
49.9V
130V
+V
AD8036
–V
V
RL = 100V
OUT
Figure 3. Noninverting Configuration, G = +1
Figure 4. Large Signal Transient Response; VO = 4 V p-p,
G = +1, R
= 140
F
Ω
Figure 6. Noninverting Clamp Configuration, G = +1
Figure 7. Clamped Large Signal Transient Response (2
Overdrive); VO = 2 V p-p, G = +1, RF = 140 Ω, VH = +1 V,
V
= –1 V
L
×
Figure 5. Small Signal Transient Response; VO = 400 mV
p-p, G = +1, R
F
= 140
Ω
Figure 8. Clamped Small Signal Transient Response
(2
×
Overdrive); VO = 400 mV p-p, G = +1, RF = 140 Ω,
V
= +0.2 V, VL = –0.2 V
H
REV. A–4–
Page 5
AD8037–Typical Characteristics
R
IN
+V
S
RL = 100V
–V
S
49.9V
V
IN
R
F
100V
V
OUT
0.1mF
10mF
AD8037
0.1mF
10mF
PULSE
GENERATOR
TR/T
F
= 350ps
+V
H
V
L
0.1mF
0.1mF
R
F
PULSE
GENERATOR
TR/T
= 350ps
F
+V
R
IN
10mF
S
0.1mF
AD8036/AD8037
V
IN
100V
49.9V
AD8037
–V
S
0.1mF
10mF
V
RL = 100V
OUT
Figure 9. Noninverting Configuration, G = +2
Figure 10. Large Signal Transient Response; VO = 4 V p-p,
G = +2, R
= RIN = 274
F
Ω
Figure 12. Noninverting Clamp Configuration, G = +2
Figure 13. Clamped Large Signal Transient Response
(2
×
Overdrive); VO = 2 V p-p, G = +2, RF = RIN = 274 Ω,
V
= +0.5 V, VL = –0.5 V
H
Figure 11. Small Signal Transient Response;
V
REV. A –5–
= 400 mV p-p, G = +2, RF = RIN = 274
O
Ω
Figure 14. Clamped Small Signal Transient Response
(2
×
Overdrive); VO = 400 mV p-p, G = +2, RF = R
V
= +0.1 V, VL = –0.1 V
H
= 274 Ω,
IN
Page 6
AD8036/AD8037
VALUE OF FEEDBACK RESISTOR (RF) – V
–3dB BANDWIDTH – MHz
20 24040 200 2201801601401201008060
R PACKAGE
R
F
130V
AD8036
VS = 65V
R
L
= 100V
GAIN = +1
R
L
49.9V
N PACKAGE
400
350
300
250
200
OUTPUT – dB
1M
FREQUENCY – Hz
10M
100M 1G
250V
RF = 50V
TO
250V
BY
50V
50V
VS = 65V
V
O
= 2.5V
p-p
R
L
= 100V
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
FREQUENCY – Hz
GAIN – dB
1M 10M
100M 1G
100k
VS = 65V
V
O
= 300mV
p-p
RL = 100V
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
140V
V
H
100V
VL (VIN)
(VO)
1V
AD8036
AD8036–Typical Characteristics
2
1
0
–1
–2
–3
GAIN – dB
–4
–5
–6
–7
–8
1M
VO = 300mV p-p
V
= 65V
S
= 100V
R
L
10M
102V
49.9V
FREQUENCY – Hz
100M 1G
200V
140V
Figure 15. AD8036 Small Signal Frequency Response,
G = +1
0.2
0.1
–0.1
–0.2
–0.3
GAIN – dB
–0.4
–0.5
–0.6
–0.7
–0.8
Figure 16. AD8036 0.1 dB Flatness, N Package (for R
Package Add 20
90
80
70
60
50
40
30
Figure 17. AD8036 Open-Loop Gain and Phase Margin vs.
Frequency, R
20
OPEN -LOOP GAIN – dB
10
–10
–20
0
VO = 300mV p-p
V
= 65V
S
= 100V
R
L
1M
0
10k 100k 10M1M
= 100
L
10M
Ω
to RF)
GAIN
Ω
140V
130V
FREQUENCY – Hz
FREQUENCY – Hz
158V
150V
100M 1G
PHASE
100M 1G
100
80
60
40
20
0
–20
–40
–60
PHASE MARGIN – Degrees
–80
–100
–120
Figure 18. AD8036 Small Signal –3 dB Bandwidth vs. R
Figure 19. AD8036 Large Signal Frequency Response,
G = +1
Figure 20. AD8036 Clamp Input Bandwidth, VH, V
L
REV. A–6–
F
Page 7
–30
DIFF GAIN – %
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
DIFF PHASE – Degrees
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
0.04
0.02
0.00
–0.02
–0.04
0.04
0.02
0.00
–0.02
–0.04
0.06
–0.06
SETTLING TIME – ns
0 5 10 15 20 25 30 35 40 45
ERROR – %
–0.05
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0.03
0.04
0.05
SETTLING TIME - ms
0 2 4 6 8 10 12 14 16 18
ERROR – %
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
–50
–70
VO = 2V p-p
= 65V
V
S
= 500V
R
L
G = +1
AD8036/AD8037
–90
–110
HARMONIC DISTORTION – dBc
–130
100k 100M10M1M10k
2ND HARMONIC
3RD HARMONIC
FREQUENCY – Hz
Figure 21. AD8036 Harmonic Distortion vs. Frequency,
R
= 500
L
Ω
–30
VO = 2V p-p
V
= 65V
S
RL = 100V
–50
G = +1
–70
–90
HARMONIC DISTORTION – dBc
–110
–130
100k 100M10M1M10k
FREQUENCY – Hz
2ND HARMONIC
3RD HARMONIC
Figure 24. AD8036 Differential Gain and Phase Error,
G = +1, R
= 150 Ω, F = 3.58 MHz
L
Figure 22. AD8036 Harmonic Distortion vs. Frequency,
R
= 100
L
Figure 23. AD8036 Third Order Intercept vs. Frequency
REV. A –7–
Ω
60
50
40
INTERCEPT – +dBm
30
20
10
20 40 8060
FREQUENCY – MHz
100
Figure 25. AD8036 Short-Term Settling Time to 0.01%, 2 V
Step, G = +1, R
= 100
L
Ω
Figure 26. AD8036 Long-Term Settling Time, 2 V Step,
G = +1, R
= 100
L
Ω
Page 8
AD8036/AD8037
RF = 475V
RF = 75V
TO
475V
BY
100V
VO = 3.5 V p-p
V
S
= 65V
R
L
= 100V
RF = 75V
1M
FREQUENCY – Hz
10M 100M 1G
GAIN – dB
–2
–1
0
1
2
3
4
5
6
7
8
FREQUENCY – Hz
GAIN – dB
VS = 65V
V
O
= 300mV p-p
R
L
= 100V
274V
V
H
100V
AD8037
VL (VIN)
(VO)
1V
274V
100k 1M 10M 100M 1G
–2
–1
0
1
2
3
4
5
6
7
8
AD8037–Typical Characteristics
8
7
6
5
4
3
GAIN – dB
2
1
0
–1
–2
1M
VO = 300mV p-p
V
= 65V
S
= 100V
R
L
10M 100M 1G
FREQUENCY – Hz
475
374
274
174
350
300
250
200
–3dB BANDWIDTH – MHz
150
VS = 65V
= 100V
R
L
GAIN = +2
R PACKAGE
100 550500450400350300250200150
R
IN
100V
49.9V
N PACKAGE
VALUE OF RF,RIN – V
AD8037
R
F
R
L
Figure 27. AD8037 Small Signal Frequency Response,
G = +2
0.2
0.1
0
1M
VO = 3.00mV p-p
V
= 65V
S
= 100V
R
L
10M
249
224
FREQUENCY – Hz
100M 1G
–0.1
–0.2
–0.3
GAIN – dB
–0.4
–0.5
–0.6
–0.7
–0.8
Figure 28. AD8037 0.1 dB Flatness, N Package
(for R Package Add 20
65
60
55
50
45
40
35
30
25
20
15
10
OPEN -LOOP GAIN – dB
5
0
–5
–10
Figure 29. AD8037 Open-Loop Gain and Phase Margin
vs. Frequency, R
–15
10k 100k 1G100M10M1M
= 100
L
Ω
FREQUENCY – Hz
Ω
to RF)
GAIN
301
274
PHASE
100
50
0
–50
–100
–150
PHASE MARGIN – Degrees
–200
–250
Figure 30. AD8037 Small Signal –3 dB Bandwidth
vs. R
, R
F
IN
Figure 31. AD8037 Large Signal Frequency Response,
G = +2
Figure 32. AD8037 Clamp Input Bandwidth, VH, V
L
REV. A–8–
Page 9
–30
DIFF GAIN – %
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
DIFF PHASE – Degrees
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
0.03
0.02
0.01
0.00
–0.01
–0.02
–0.03
0.03
0.02
0.01
0.00
–0.01
–0.02
–0.03
SETTLING TIME – ns
0 5 10 15 20 25 30 35 40 45
ERROR – %
–0.05
–0.04
–0.03
–0.02
–0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
SETTLING TIME – ms
0 2 4 6 8 10 12 14 16 18
ERROR – %
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
–50
–70
–90
AD8036/AD8037
VO = 2V p-p
VS = 65V
RL = 500V
G = +2
2ND HARMONIC
HARMONIC DISTORTION – dBc
–110
–130
100k
FREQUENCY – Hz
3RD HARMONIC
10M1M10k
100M
Figure 33. AD8037 Harmonic Distortion vs. Frequency,
R
= 500
L
Ω
–30
VO = 2V p-p
–50
VS = 65V
RL = 100V
G = +2
–70
–90
HARMONIC DISTORTION – dBc
–110
–130
100k
2ND HARMONIC
3RD HARMONIC
FREQUENCY – Hz
10M1M10k
100M
Figure 36. AD8037 Differential Gain and Phase Error
G = +2, R
= 150 Ω, F = 3.58 MHz
L
Figure 34. AD8037 Harmonic Distortion vs. Frequency,
R
= 100
L
Figure 35. AD8037 Third Order Intercept vs. Frequency
REV. A –9–
Ω
60
50
40
INTERCEPT – +dBm
30
20
10
20 40 8060
FREQUENCY – MHz
100
Figure 37. AD8037 Short-Term Settling Time to 0.01%,
2 V Step, G = +2, R
= 100
L
Ω
Figure 38. AD8037 Long-Term Settling Time 2 V Step,
R
= 100
L
Ω
Page 10
AD8036/AD8037–Typical Characteristics
100 100k10k1k10
FREQUENCY – Hz
VS = 65V
INPUT NOISE VOLTAGE – nV/ Hz
17
15
13
11
9
7
5
3
80
70
60
50
40
30
20
10
0
75
65
55
45
35
25
15
5
10k 100k 1G100M10M1M
FREQUENCY – Hz
PSRR – dB
–PSRR
+PSRR
100
90
80
70
60
50
40
30
20
100k 1G100M10M1M
FREQUENCY – Hz
CMRR – dB
VS = 65V
DVCM = 1V
RL = 100V
32
28
24
20
16
12
INPUT NOISE VOLTAGE – nV/ Hz
8
4
100 10k1k10
FREQUENCY – Hz
Figure 39. AD8036 Noise vs. Frequency
80
75
70
65
+PSRR
60
55
50
45
40
35
PSRR – dB
30
25
20
15
10
5
0
10k 100k 1G100M10M1M
–PSRR
FREQUENCY – Hz
VS = 65V
100k
Figure 42. AD8037 Noise vs. Frequency
100
90
80
70
60
CMRR – dB
50
40
30
20
100k 1G100M10M1M
Figure 40. AD8036 PSRR vs. Frequency
VS = 65V
DVCM = 1V
RL = 100V
FREQUENCY – Hz
Figure 41. AD8036 CMRR vs. Frequency
Figure 43. AD8037 PSRR vs. Frequency
Figure 44. AD8037 CMRR vs. Frequency
REV. A–10–
Page 11
AD8036/AD8037
1400
1300
1200
1100
1000
900
800
700
600
500
400
–60 –40 –20 0 20 40 60 80 100 120 140
–A
OL
+A
OL
–A
OL
+A
OL
AD8036
AD8037
JUNCTION TEMPERATURE – 8C
OPEN -LOOP GAIN – V/ V
–60 –40 –20 0 20 40 60 80 100 120 140
PSRR – dB
JUNCTION TEMPERATURE – 8C
–PSRR
AD8037
AD8036
AD8037
AD8036
+PSRR
+PSRR
–PSRR
74
72
70
68
66
64
62
60
15 25 35 45 55 65 75 85 95
CMRR – dB
JUNCTION TEMPERATURE – 8C
DV
CM
= 2V
96
95
94
93
92
91
90
89
88
1k
VS = 65V
G = +1
300M
– V
R
OUT
0.01
100
0.1
10
1
0.1M
1.0M 100M
FREQUENCY – Hz
10M
Figure 45. AD8036 Output Resistance vs. Frequency
1k
VS = 65V
G = +2
– V
R
OUT
100
10
1
Figure 48. Open-Loop Gain vs. Temperature
0.1
0.01
0.1M
1.0M 100M
FREQUENCY – Hz
10M
Figure 46. AD8037 Output Resistance vs. Frequency
4.2
4.1
4.0
3.9
3.8
3.7
OUTPUT SWING – Volts
3.6
3.5
3.4
–60 –40 –20 0 20 40 60 80 100 120 140
JUNCTION TEMPERATURE – 8C
Figure 47. AD8036/AD8037 Output Swing vs. Temperature
REV. A –11–
+V
OUT
–V
OUT
+V
OUT
–V
OUT
300M
Figure 49. PSRR vs. Temperature
RL=150
RL= 50
Figure 50. AD8036/AD8037 CMRR vs. Temperature
Page 12
AD8036/AD8037–Typical Characteristics
–60 –40 –20 0 20 40 60 80 100 120 140
JUNCTION TEMPERATURE – 8C
AD8037
AD8036
AD8036
SHORT CIRCUIT CURRENT – mA
AD8037
SINK
SOURCE
270
260
250
240
230
220
210
200
INPUT OFFSET VOLTAGE – mV
COUNT
3 WAFER LOTS
COUNT = 853
FREQ. DIST
48
44
40
36
32
28
24
20
16
12
8
4
0
–4.5 –4.0 –3.5 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5
24
23
22
21
20
19
SUPPLY CURRENT – mA
18
17
–60 –40 –20 0 20 40 60 80 100 120 140
JUNCTION TEMPERATURE – 8C
AD8036, VS = 66V
AD8037, VS = 66V
AD8036, VS = 65V
AD8037, VS = 65V
Figure 51. Supply Current vs. Temperature
–2.50
–2.25
–2.00
–1.75
VS = 65V
–1.50
–1.25
–1.00
INPUT OFFSET VOLTAGE – mV
–0.75
AD8037
AD8036
VS = 66V
VS = 66V
VS = 65V
Figure 54. Short Circuit Current vs. Temperature
4.5
4.0
3.5
3.0
2.5
INPUT BIAS CURRENT – mA
2.0
AD8036
AD8037
–IB
+IB
–IB
+IB
–0.50
–60 –40 –20 0 20 40 60 80 100 120 140
JUNCTION TEMPERATURE – 8C
Figure 52. Input Offset Voltage vs. Temperature
44
3 WAFER LOTS
40
COUNT = 632
36
32
28
24
20
COUNT
16
12
8
4
0
–6–5–4–3–2–101234
Figure 53. AD8036 Input Offset Voltage Distribution
INPUT OFFSET VOLTAGE – mV
FREQ. DIST
1.5
–60 –40 –20 0 20 40 60 80 100 120 140
JUNCTION TEMPERATURE – 8C
Figure 55. Input Bias Current vs. Temperature
Figure 56. AD8037 Input Offset Voltage Distribution
REV. A–12–
Page 13
0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0
–80
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
ABSOLUTE VALUE OF OUTPUT VOLTAGE – Volts
HARMONIC DISTORTION – dBc
VH +1V +0.5V
V
L
–1V –0.5V
G +1V +2V
AD8036 AD8037
AD8037 3RD
HARMONIC
AD8036 3RD
HARMONIC
AD8036 2ND
HARMONIC
AD8037 2ND
HARMONIC
–5 –4 –3 –2 –1 0 1 2 3 4 5
INPUT CLAMP VOLTAGE (V
H,VL
) – Volts
I
BH
I
BL
POSITIVE IBH, IBL DENOTES
CURRENT FLOW INTO
CLAMP INPUTS VH, V
L
CLAMP INPUT BIAS CURRENT – mA
80
60
40
20
0
–20
–40
–60
–80
REF
+2V
+1V
0V
Clamp Characteristics–AD8036/AD8037
20
15
VCL =
VCL =
–3V
10
5
0
–5
–10
INPUT ERROR VOLTAGE – mV
–15
–20
–3 –2 –1 0 1 2 3
VCL =
–2V
–1V
OUTPUT VOLTAGE – Volts
AD8036, ACL = +1
AD8037, A
AD8036
AD8037
V
=
VCH =
CH
+1V
+2V
= +2
CL
V
=
CH
+3V
Figure 57. Input Error Voltage vs. Clamped Output
Voltage
20
15
10
5
VH = + 1V
V
= – 1V
L
Figure 60. Harmonic Distortion as Output Approaches
Clamp Voltage; V
= 2 V p-p, RL = 100 ⍀, f = 20 MHz
O
0
–5
NONLINEARITY – mV
–10
–15
–20
INPUT VOLTAGE A
Figure 58. AD8036/AD8037 Nonlinearity Near Clamp
Voltage
+2V
+1V
Figure 59. AD8036 Clamp Overdrive (2X) Recovery
REV. A –13–
REF
– Volts
V
1.0–0.8–1.0 0.80.60.40.20.0–0.2–0.4–0.6
Figure 61. AD8036/AD8037 Clamp Input Bias Current vs.
Input Clamp Voltage
0V
Figure 62. AD8037 Clamp Overdrive (2X) Recovery
Page 14
AD8036/AD8037–Clamp Characteristics
0 5 10 15 20 25 30 35 40
SETTLING TIME – ns
ERROR – %
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0 5 10 15 20 25 30 35 40
SETTLING TIME – ns
ERROR – %
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.3
0.2
0.1
0
–0.1
ERROR – %
–0.2
–0.3
–0.4
–0.5
0 102030405060708090
SETTLING TIME – ns
Figure 63. AD8036 Clamp Settling (0.1%), VH = +1 V,
V
= –1 V, 2× Overdrive
L
0.5
0.4
0.3
0.2
0.1
0
–0.1
ERROR – %
–0.2
–0.3
–0.4
–0.5
0 5 10 15 20 25 30 35 40
SETTLING TIME – ns
0.5
0.4
0.3
0.2
0.1
0
–0.1
ERROR – %
–0.2
–0.3
–0.4
–0.5
0 102030405060708090
SETTLING TIME – ns
Figure 66. AD8037 Clamp Settling (0.1%), VH = +0.5 V,
V
= –0.5 V, 2× Overdrive
L
Figure 64. AD8036 Clamp Recovery Settling Time (High),
from +2
×
Overdrive to 0 V
0.5
0.4
0.3
0.2
0.1
0
–0.1
ERROR – %
–0.2
–0.3
–0.4
–0.5
0 5 10 15 20 25 30 35 40
SETTLING TIME – ns
Figure 65. AD8036 Clamp Recovery Settling Time (Low),
from –2
×
Overdrive to 0 V
Figure 67. AD8037 Clamp Recovery Settling Time (High),
from +2
×
Overdrive to 0 V
Figure 68. AD8037 Clamp Recovery Settling Time (Low),
from –2
×
Overdrive to 0 V
REV. A–14–
Page 15
AD8036/AD8037
R
L
1kV
R
F
R
IN
R
SERIES
C
L
AD8036/
AD8037
R
IN
THEORY OF OPERATION
General
The AD8036 and AD8037 are wide bandwidth, voltage feedback clamp amplifiers. Since their open-loop frequency response follows the conventional 6 dB/octave roll-off, their gain
bandwidth product is basically constant. Increasing their
closed-loop gain results in a corresponding decrease in small signal bandwidth. This can be observed by noting the bandwidth
specification, between the AD8036 (gain of 1) and AD8037
(gain of 2). The AD8036/AD8037 typically maintain 65 degrees of phase margin. This high margin minimizes the effects
of signal and noise peaking.
While the AD8036 and AD8037 can be used in either an inverting or noninverting configuration, the clamp function will only
work in the noninverting mode. As such, this section shows connections only in the noninverting configuration. Applications
that require an inverting configuration will be discussed in the
Applications section. In applications that do not require clamping, Pins 5 and 8 (respectively V
and VH) may be left floating.
L
See Input Clamp Amp Operation and Applications sections
otherwise.
Feedback Resistor Choice
The value of the feedback resistor is critical for optimum performance on the AD8036 (gain +1) and less critical as the gain increases. Therefore, this section is specifically targeted at the
AD8036.
At minimum stable gain (+1), the AD8036 provides optimum
dynamic performance with R
= 140 Ω. This resistor acts only
F
as a parasitic suppressor against damped RF oscillations that
can occur due to lead (input, feedback) inductance and parasitic
capacitance. This value of R
provides the best combination of
F
wide bandwidth, low parasitic peaking, and fast settling time.
In fact, for the same reasons, a 100–130 Ω resistor should be
placed in series with the positive input for other AD8036 noninverting configurations. The correct connection is shown in
Figure 69.
+V
S
R
F
G = 1+
R
G
100 - 130V
V
IN
R
TERM
AD8036/
AD8037
10mF
V
H
V
L
0.1mF
0.1mF
10mF
V
OUT
R
F
This estimation loses accuracy for gains of +2/–1 or lower due
to the amplifier’s damping factor. For these “low gain” cases,
the bandwidth will actually extend beyond the calculated value
(see Closed-Loop BW plots, Figures 15 and 27).
Pulse Response
Unlike a traditional voltage feedback amplifier, where the slew
speed is dictated by its front end dc quiescent current and gain
bandwidth product, the AD8036 and AD8037 provide “on demand” current that increases proportionally to the input “step”
signal amplitude. This results in slew rates (1200 V/µs) compa-
rable to wideband current feedback designs. This, combined
with relatively low input noise current (2.1 pA/√Hz), gives the
AD8036 and AD8037 the best attributes of both voltage and
current feedback amplifiers.
Large Signal Performance
The outstanding large signal operation of the AD8036 and
AD8037 is due to a unique, proprietary design architecture.
In order to maintain this level of performance, the maximum
350 V-MHz product must be observed, (e.g., @ 100 MHz,
≤ 3.5 V p-p).
V
O
Power Supply and Input Clamp Bypassing
Adequate power supply bypassing can be critical when optimizing the performance of a high frequency circuit. Inductance in
the power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors
(typically greater than 1 µF) will be required to provide the best
settling time and lowest distortion. A parallel combination of at
least 4.7 µF, and between 0.1 µF and 0.01 µF, is recommended.
Some brands of electrolytic capacitors will require a small series
damping resistor ≈4.7 Ω for optimum results.
When the AD8036 and AD8037 are used in clamping mode,
and V
and a dc voltage is connected to clamp inputs V
H
, a 0.1 µF
L
bypassing capacitor is required between each input pin and
ground in order to maintain stability.
Driving Capacitive Loads
The AD8036 and AD8037 were designed primarily to drive
nonreactive loads. If driving loads with a capacitive component
is desired, the best frequency response is obtained by the addition of a small series resistance as shown in Figure 70. The accompanying graph shows the optimum value for R
SERIES
vs.
capacitive load. It is worth noting that the frequency response of
the circuit when driving large capacitive loads will be dominated
by the passive roll-off of R
6 pF or less, no R
is necessary.
SERIES
and CL. For capacitive loads of
SERIES
–V
S
R
G
Figure 69. Noninverting Operation
For general voltage gain applications, the amplifier bandwidth
can be closely estimated as:
ω
f
≅
3 dB
REV. A –15–
2π 1+
O
R
F
R
G
Figure 70. Driving Capacitive Loads
Page 16
AD8036/AD8037
A
B
C
S1
R
F
140V
A B C
0 1 0
1 0 0
0 0 1
S1
V
IN
> V
H
VL ≤ VIN ≤ V
H
V
IN
< V
L
–V
IN
+V
IN
V
H
V
L
V
OUT
+1
+1
+1
C
H
C
L
A1
A2
+1
40
30
– V
SERIES
R
20
Operation of the AD8036 for negative input voltages and negative clamp levels on V
ling S1. Since the comparators see the voltage on the +V
as their common reference level, then the voltage V
defined as “High” or “Low” with respect to +V
is set to zero volts, VH is open, and VL is +1 V, compara-
if V
IN
will switch S1 to “C,” so the AD8036 will buffer the
tor C
L
voltage on V
and ignore +VIN.
L
is similar, with comparator CL control-
L
. For example,
IN
pin
IN
and VL are
H
The performance of the AD8036 and AD8037 closely matches
the ideal just described. The comparator’s threshold extends
from 60 mV inside the clamp window defined by the voltages on
V
and VH to 60 mV beyond the window’s edge. Switch S1 is
L
10
0 5 10 15 20 25
Figure 71. Recommended R
CL– pF
vs. Capacitive Load
SERIES
INPUT CLAMPING AMPLIFIER OPERATION
The key to the AD8036 and AD8037’s fast, accurate clamp and
amplifier performance is their unique patent pending CLAMPIN
input clamp architecture. This new design reduces clamp errors
by more than 10× over previous output clamp based circuits, as
well as substantially increasing the bandwidth, precision and
versatility of the clamp inputs.
Figure 72 is an idealized block diagram of the AD8036 connected as a unity gain voltage follower. The primary signal path
comprises A1 (a 1200 V/µs, 240 MHz high voltage gain, differ-
ential to single-ended amplifier) and A2 (a G = +1 high current
gain output buffer). The AD8037 differs from the AD8036 only
in that A1 is optimized for closed-loop gains of two or greater.
The CLAMPIN section is comprised of comparators C
, which drive switch S1 through a decoder. The unity-gain
C
L
buffers in series with +V
, VH, and VL inputs isolate the input
IN
H
and
pins from the comparators and S1 without reducing bandwidth
or precision.
The two comparators have about the same bandwidth as A1
(240 MHz), so they can keep up with signals within the useful
bandwidth of the AD8036. To illustrate the operation of the
CLAMPIN circuit, consider the case where V
+1 V, V
is open, and the AD8036 is set for a gain of +1, by
L
is referenced to
H
implemented with current steering, so that A1’s +input makes a
continuous transition from say, V
to VH as the input voltage
IN
traverses the comparator’s input threshold from 0.9 V to 1.0 V
= 1.0 V.
for V
H
The practical effect of these nonidealities is to soften the
transition from amplification to clamping modes, without compromising the absolute clamp limit set by the CLAMPIN circuit. Figure 73 is a graph of V
vs. VIN for the AD8036 and a
OUT
typical output clamp amplifier. Both amplifiers are set for G =
+1 and V
The worst case error between V
= +1 V.
H
(ideally clamped) and V
OUT
OUT
(actual) is typically 18 mV times the amplifier closed-loop gain.
This occurs when V
and/or below this limit, V
equals VH (or VL). As VIN goes above
IN
will settle to within 5 mV of the
OUT
ideal value.
In contrast, the output clamp amplifier’s transfer curve typically
will show some compression starting at an input of 0.8 V, and
can have an output voltage as far as 200 mV over the clamp
limit. In addition, since the output clamp in effect causes the
amplifier to operate open loop in clamp mode, the amplifier’s
output impedance will increase, potentially causing additional
errors.
The AD8036’s and AD8037’s CLAMPIN input clamp architecture works only for noninverting or follower applications and,
since it operates on the input, the clamp voltage levels V
, and input error limits will be multiplied by the amplifier’s
V
L
H
and
connecting its output back to its inverting input through the rec-
ommended 140 Ω feedback resistor. Note that the main signal
path always operates closed loop, since the CLAMPIN circuit
only affects A1’s noninverting input.
If a 0 V to +2 V voltage ramp is applied to the AD8036’s +V
for the connection just described, V
should track +VIN per-
OUT
fectly up to +1 V, then should limit at exactly +1 V as +V
IN
IN
con-
tinues to +2 V.
In practice, the AD8036 comes close to this ideal behavior. As
the +V
high limit comparator C
put of C
practically by about 18 mV), C
from “A” to “B” reference level. Since the + input of A1 is now
connected to V
AD8036’s output voltage. In short, the AD8036 is now operating as a unity-gain buffer for the V
V
input voltage ramps from zero to 1 V, the output of the
IN
. When +VIN just exceeds V
L
, for VH > 1 V, will be faithfully reproduced at V
H
starts in the off state, as does the out-
H
, further increases in +VIN have no effect on the
H
(ideally, by say 1 µV,
IN
changes state, switching S1
H
input, as any variation in
H
OUT
.
Figure 72. AD8036/AD8037 Clamp Amp System
REV. A–16–
Page 17
AD8036/AD8037
+5V
R
F
140V
–5V
130V
V
H
V
L
V
IN
V
OUT
0.1mF
10mF
0.1mF
AD8036
0.1mF10mF
V
H
0.1mF
V
L
+5V
R
F
274V
–5V
100V
V
H
V
L
V
IN
V
OUT
0.1mF
10mF
0.1mF
AD8037
0.1mF10mF
V
H
0.1mF
V
L
R
G
274V
49.9V
closed-loop gain at the output. For instance, to set an output
limit of ±1 V for an AD8037 operating at a gain of 3.0, V
would need to be set to +0.333 V and –0.333 V, respectively.
V
L
and
H
The only restriction on using the AD8036’s and AD8037’s
+V
, VL, VH pins as inputs is that the maximum voltage differ-
IN
ence between +V
and VH or VL should not exceed 6.3 V, and
IN
Clamping with Gain
Figure 75 shows an AD8037 configured for a noninverting gain
of two. The AD8037 is used in this circuit since it is compensated for gains of two or greater and provides greater bandwidth. In this case, the high clamping level at the output will
all three voltages be within the supply voltage range. For example, if V
Figure 73. Output Clamp Error vs. Input Clamp Error
AD8036/AD8037 APPLICATIONS
The AD8036 and AD8037 use a unique input clamping circuit
to perform the clamping function. As a result, they provide the
clamping function better than traditional output clamping devices and provide additional flexibility to perform other unique
is set at –3 V, then VIN should not exceed +3.3 V.
L
1.6
1.4
OUT
1.2
CLAMP ERROR – 25mV
AD8036
1.0
AD8036
OUTPUT VOLTAGE – V
0.8
0.6
0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
OUTPUT CLAMP AMP
INPUT VOLTAGE – +V
CLAMP ERROR – >200mV
OUTPUT CLAMP
IN
Figure 74. Unity Gain Noninverting Clamp
occur at 2 × V
. The equations governing the output clamp levels in cir-
2 × V
L
and the low clamping level at the output will be
H
cuits configured for noninverting gain are:
V
= G × V
where: V
CH
V
= G × V
CL
is the high output clamping level
CH
is the low output clamping level
V
CL
H
L
G is the gain of the amplifier configuration
is the high input clamping level (Pin 8)
V
H
is the low input clamping level (Pin 5)
V
*Amplifier offset is assumed to be zero.
L
applications.
There are, however, some restrictions on circuit configurations;
and some calculations need to be performed in order to figure
the clamping level, as a result of clamping being performed at
the input stage.
The major restriction on the clamping feature of the AD8036/
AD8037 is that clamping occurs only when using the amplifiers
in the noninverting mode. To clamp in an inverting circuit, an
additional inverting gain stage is required. Another restriction is
that V
voltage range of the amplifier (±3.9 V). V
and V
be greater than VL, and that each be within the output
H
can go above ground as long as VH is kept higher than VL.
L
can go below ground
H
Unity Gain Clamping
The simplest circuit for calculating the clamp levels is a unity
gain follower as shown in Figure 74. In this case, the AD8036
Figure 75. Gain of Two Noninverting Clamp
should be used since it is compensated for noninverting unity
gain.
This circuit will clamp at an upper voltage set by V
applied to Pin 8) and a lower voltage set by V
plied to Pin 5).
REV. A –17–
(the voltage
H
(the voltage ap-
L
Page 18
AD8036/AD8037
+5V
806V
V
H
AD8037
V
L
+5V
–5V
0.1mF10mF
–2V to 0V
0.1mF
301V
10mF
R2
1N5712
49.9V
CLAMPING
RANGE
–2.1V to +0.1V
0.1mF
AD9002
V
= –2V TO 0V
IN
SUBSTRATE
DIODE
–5.2V
100V
0.1mF
49.9V
100V
806V
100V
0.1mF
–5V
10µF
0.1mF
+5V
AD780
V
2.5V
0.1mF
–0.5V to +0.5V
IN
750V
R1
499V
R3
Figure 76. Gain of Two, Noninverting with Offset AD8037 Driving an AD9002—8-Bit, 125 MSPS A/D Converter
Clamping with an Offset
Some op amp circuits are required to operate with an offset
voltage. These are generally configured in the inverting mode
where the offset voltage can be summed in as one of the inputs.
Since AD8036/AD8037 clamping does not function in the inverting mode, it is not possible to clamp with this configuration.
Figure 76 shows a noninverting configuration of an AD8037
that provides clamping and also has an offset.␣ The circuit shows
the AD8037 as a driver for an AD9002, an 8-bit, 125 Msps
A/D converter and illustrates some of the considerations for using an AD8037 with offset and clamping.
The analog input range of the AD9002 is from ground to –2 V.
The input should not go more than 0.5 V outside this range in
order to prevent disruptions to the internal workings of the A/D
and to avoid drawing excess current. These requirements make
the AD8037 a prime candidate for signal conditioning.
When an offset is added to a noninverting op amp circuit, it is
fed in through a resistor to the inverting input. The result is that
the op amp must now operate at a closed-loop gain greater than
unity. For this circuit a gain of two was chosen which allows the
use of the AD8037. The feedback resistor, R2, is set at 301 Ω
for optimum performance of the AD8037 at a gain of two.
There is an interaction between the offset and the gain, so some
calculations must be performed to arrive at the proper values for
R1 and R3. For a gain of two the parallel combination of resistors R1 and R3 must be equal to the feedback resistor R2. Thus
R1 × R3/R1 + R3 = R2 = 301 Ω
The reference used to provide the offset is the AD780 whose
output is 2.5 V. This must be divided down to provide the 1 V
offset desired. Thus
2.5 V × R1/(R1 + R3) = 1 V
When the two equations are solved simultaneously we get R1 =
499 Ω and R3 = 750 Ω (using closest 1% resistor values in all
cases). This positive 1 V offset at the input translates to a –1 V
offset at the output.
The usable input signal swing of the AD9002 is 2 V p-p. This is
centered about the –1 V offset making the usable signal range
from 0 V to –2 V. It is desirable to clamp the input signal so
that it goes no more than 100 mV outside of this range in either
direction. Thus, the high clamping level should be set at +0.1 V
and the low clamping level should be set at –2.1 V as seen at the
input of the AD9002 (output of AD8037).
Because the clamping is done at the input stage of the AD8037,
the clamping level as seen at the output is affected by not only
the gain of the circuit as previously described, but also by the
offset. Thus, in order to obtain the desired clamp levels, V
H
must be biased at +0.55 V while VL must be biased at –0.55 V.
The clamping levels as seen at the output can be calculated by
the following:
V
= V
CH
VCL = V
Where V
is the offset voltage that appears at the output.
OFF
The resistors used to generate the voltages for V
+ G × V
OFF
+ G × V
OFF
H
L
and VL should
H
be kept to a minimum in order to reduce errors due to clamp
bias current. This current is dependent on V
and VL (see Fig-
H
ure 61) and will create a voltage drop across whatever resistance
is in series with each clamp input. This extra error voltage is
multiplied by the closed-loop gain of the amplifier and can be
substantial, especially in high closed-loop gain configurations. A
0.1 µF bypass capacitor should be placed between input clamp
and VL and ground to ensure stable operation.
pins V
H
The 1N5712 Schottky diode is used for protection from forward
biasing the substrate diode in the AD9002 during power-up
transients.
Programmable Pulse Generator
The AD8036/AD8037’s clamp output can be set accurately and
has a well controlled flat level. This along with wide bandwidth
and high slew rate make them very well suited for programmable
level pulse generators.
Figure 77 is a schematic for a pulse generator that can directly
accept TTL generated timing signals for its input and generate
pulses at the output up to 24 V p-p with 2500 V/µs slew rate.
The output levels can be programmed to anywhere in the range
–12 V to +12 V.
REV. A–18–
Page 19
TTL
INPUT
FULL WAVE
RECTIFIED
OUTPUT
LOWER
CLAMPING
LEVEL WITH
NO NEG INPUT
OUTPUT
LOWER
CLAMPING
LEVEL
–1 3 INPUT
AD8036/AD8037
V
H
0.1mF
200V
IN
100V
1.3kV
–15V
0.1mF
274V
+5V
+15V
AD811
–15V
V
H
AD8037
V
L
V
L
–5V
0.1mF
0.1mF10mF
10mF
274V
100V
150V
Figure 77. Programmable Pulse Generator
0.1mF
0.1mF10mF
604V
10mF
PULSE
OUT
VH 3 10
V
3 10
L
The circuit uses an AD8037 operating at a gain of two with an
AD811 to boost the output to the ±12 V range. The AD811 was
chosen for its ability to operate with ±15 V supplies and its high
slew rate.
R1 and R2 act as a level shifter to make the TTL signal levels be
approximately symmetrical above and below ground. This ensures that both the high and low logic levels will be clamped by
the AD8037. For well controlled signal levels in the output
pulse, the high and low output levels should result from the
clamping action of the AD8037 and not be controlled by either
the high or low logic levels passing through a linear amplifier.
For good rise and fall times at the output pulse, a logic family
with high speed edges should be used.
The high logic levels are clamped at two times the voltage at V
,
H
while the low logic levels are clamped at two times the voltage
. The output of the AD8037 is amplified by the AD811
at V
L
operating at a gain of 5. The overall gain of 10 will cause the
high output level to be 10 times the voltage at V
output level to be 10 times the voltage at V
H
.
L
, and the low
High Speed, Full-Wave Rectifier
The clamping inputs are additional inputs to the input stage of
the op amp. As such they have an input bandwidth comparable
to the amplifier inputs and lend themselves to some unique
functions when they are driven dynamically.
Figure 78 is a schematic for a full-wave rectifier, sometimes
called an absolute value generator. It works well up to 20 MHz
and can operate at significantly higher frequencies with some
degradation in performance. The distortion performance is significantly better than diode based full-wave rectifiers, especially
at high frequencies.
+5V
100V
V
H
AD8037
V
L
R
V
274V
IN
R
274V
F
G
0.1mF10mF
0.1mF
–5V
10mF
V
OUT = VIN
Figure 78. Full-Wave Rectifier
The circuit is configured as an inverting amplifier with a gain
of one. The input drives the inverting amplifier and also directly
drives V
ing input, V
, the lower level clamping input. The high level clamp-
L
, is left floating and plays no role in this circuit.
H
When the input is negative, the amplifier acts as a regular unitygain inverting amplifier and outputs a positive signal at the same
amplitude as the input with opposite polarity. V
is driven nega-
L
tive by the input, so it performs no clamping action, because the
positive output signal is always higher than the negative level
driving V
.
L
When the input is positive, the output result is the sum of two
separate effects. First, the inverting amplifier multiplies the input by –1 because of its unity-gain inverting configuration. This
effectively produces an offset as explained above, but with a dynamic level that is equal to –1 times the input.
Second, although the positive input is grounded (through 100 Ω),
the output is clamped at two times the voltage applied to V
(a
L
positive, dynamic voltage in this case). The factor of two is because the noise gain of the amplifier is two.
The sum of these two actions results in an output that is equal
to unity times the input signal for positive input signals, see Figure 79. For a input/output scope photo with an input signal of
20 MHz and amplitude ±1 V, see Figure 80.
Figure 79.
REV. A –19–
Page 20
AD8036/AD8037
Figure 80. Full-Wave Rectifier Scope
Thus for either positive or negative input signals, the output is
unity times the absolute value of the input signal. The circuit
can be easily configured to produce the negative absolute value
of the input by applying the input to V
The circuit can get to within about 40 mV of ground during the
time when the input crosses zero. This voltage is fixed over a
wide frequency range and is a result of the switching between
the conventional op amp input and the clamp input. But because there are no diodes to rapidly switch from forward to reverse bias, the performance far exceeds that of diode based full
wave rectifiers.
The 40 mV offset mentioned can be removed by adding an off-
set to the circuit. A 27.4 kΩ input resistor to the inverting input
will have a gain of 0.01, while changing the gain of the circuit by
only 1%. A plus or minus 4 V dc level (depending on the polarity of the rectifier) into this resistor will compensate for the
offset.
Full wave rectifiers are useful in many applications including
AM signal detection, high frequency ac voltmeters and various
arithmetic operations.
Amplitude Modulator
In addition to being able to be configured as an amplitude demodulator (AM detector), the AD8037 can also be configured
as an amplitude modulator as shown in Figure 81.
instead of VL.
H
The modulation signal is applied to both the input of a unity
gain inverting amplifier and to V
is biased at +0.5 V dc.
V
H
, the lower clamping input.
L
To understand the circuit operation, it is helpful to first consider a simpler circuit. If both V
and VH were dc biased at
L
–0.5 V and the carrier and modulation inputs driven as above,
the output would be a 2 V p-p square wave at the carrier frequency riding on a waveform at the modulating frequency. The
inverting input (modulation signal) is creating a varying offset to
the 2 V p-p square wave at the output. Both the high and low
levels clamp at twice the input levels on the clamps because the
noise gain of the circuit is two.
When V
is driven by the modulation signal instead of being
L
held at a dc level, a more complicated situation results. The resulting waveform is composed of an upper envelope and a lower
envelope with the carrier square wave in between. The upper
and lower envelope waveforms are 180° out of phase as in a
typical AM waveform.
The upper envelope is produced by the upper clamp level being
offset by the waveform applied to the inverting input. This offset
is the opposite polarity of the input waveform because of the
inverting configuration.
The lower envelope is produced by the sum of two effects. First,
it is offset by the waveform applied to the inverting input as in
the case of the simplified circuit above. The polarity of this offset is in the same direction as the upper envelope. Second, the
output is driven in the opposite direction of the offset at twice
the offset voltage by the modulation signal being applied to V
.
L
This results from the noise gain being equal to two, and since
there is no inversion in this connection, it is opposite polarity
from the offset.
The result at the output for the lower envelope is the sum of
these two effects, which produces the lower envelope of an amplitude modulated waveform. See Figure 82.
V
+5V
H
–5V
0.1mF10mF
0.1mF
10mF
AM OUT
CARRIER IN
MODULATION IN
100V
R
274V
V
H
AD8037
V
L
R
F
G
274V
Figure 81. Amplitude Modulator
The positive input of the AD8037 is driven with a square wave
of sufficient amplitude to produce clamping action at both the
high and low levels. This is the higher frequency carrier signal.
Figure 82. AM Waveform
The depth of modulation can be modified in this circuit by
changing the amplitude of the modulation signal. This changes
the amplitude of the upper and lower envelope waveforms.
The modulation depth can also be changed by changing the dc
bias applied to V
. In this case the amplitudes of the upper and
H
lower envelope waveforms stay constant, but the spacing between them changes. This alters the ratio of the envelope amplitude to the amplitude of the overall waveform.
REV. A–20–
Page 21
Layout Considerations
IN
R
O
1kV
V
OUT
0.1mF
AD8036/
AD8037
V
H
0.1mF
V
L
R
S
–V
S
+V
S
–V
S
+V
S
R
G
R
F
1kV
–V
S
+V
S
R
T
NONINVERTING CONFIGURATION
C5
10mF
+V
S
–V
S
C3
0.1mF
C1
0.01mF
C6
10mF
C4
0.1mF
C2
0.01mF
OPTIONAL
SUPPLY BYPASSING
The specified high speed performance of the AD8036 and
AD8037 requires careful attention to board layout and component selection. Proper RF design techniques and low pass parasitic component selection are mandatory.
The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. The ground plane should be removed from the
area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply and input clamp bypassing (see Figure 83). One end should be connected to the
ground plane and the other within 1/8 inch of each power and
clamp pin. An additional large (0.47 µF–10 µF) tantalum elec-
trolytic capacitor should be connected in parallel, though not
necessarily so close, to supply current for fast, large signal
changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the inverting input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50 Ω or 75 Ω and be properly termi-
nated at each end.
Evaluation Board
An evaluation board for both the AD8036 and AD8037 is available that has been carefully laid out and tested to demonstrate
that the specified high speed performance of the device can be
realized. For ordering information, please refer to the Ordering
Guide.
The layout of the evaluation board can be used as shown or
serve as a guide for a board layout.
AD8036/AD8037
Figure 83. Noninverting Configurations for Evaluation
Boards
Component +1 +2 +10 +100 +2 +10 +100
R
F
R
G
(Nominal) 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω
R
O
R
REV. A –21–
S
(Nominal) 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω 49.9 Ω
R
T
Small Signal BW (MHz) 240 90 10 1.3 275 21 3
Table I.
AD8036A AD8037A
Gain Gain
140 Ω 274 Ω 2 kΩ 2 kΩ 274 Ω 2 kΩ 2 kΩ
274 Ω 221 Ω 20.5 Ω 274 Ω 221 Ω 20.5 Ω
130 Ω 100 Ω 100 Ω 100 Ω 100 Ω 100 Ω 100 Ω
Page 22
AD8036/AD8037
Figure 84. Evaluation Board Silkscreen (Top)
Figure 85. Evaluation Board Silkscreen (Bottom)
Figure 86. Board Layout (Solder Side)
Figure 87. Board Layout (Component Side)
REV. A–22–
Page 23
PIN 1
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.1574 (4.00)
0.1497 (3.80)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N Package)
0.430 (10.92)
0.348 (8.84)
8
0.100 (2.54)
5
0.280 (7.11)
14
BSC
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
SEATING
PLANE
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
8-Lead Plastic SOIC
(SO Package)
0.1 968 (5.00)
0.1 890 (4.80)
85
0.2440 (6.20)
0.2284 (5.80)
41
0.195 ( 4.95)
0.115 (2.93)
AD8036/AD8037
C1980a–0–9/99
PIN 1
0.0098 (0.25)
0.0040 (0.10)
SEATING
PIN 1
0.200.(5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.0500 (1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
PLANE
0.005 (0.13)
MIN
85
1
0.100 (2.54) BSC
0.405 (10.29) MAX
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
0.0688 (1.75)
0.0532 (1.35)
8-Lead Cerdip
(Q Package)
0.055 (1.4)
MAX
0.310 (7.87)
0.220 (5.59)
4
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.320 (8.13)
0.290 (7.37)
15°
0°
0.0196 (0.50)
0.0099 (0.25)
88
0.0500 (1.27)
08
0.0160 (0.41)
0.015 (0.38)
0.008 (0.20)
3 458
PRINTED IN U.S.A.
REV. A –23–
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