Datasheet AD8033 Datasheet (Analog Devices)

Low Cost, 80 MHz

0.01 1001.0 10
FREQUENCY – MHz

21

18

–9

15

12

9

6

3

0

–3

–6

24

GAIN – dB

G = +5

1000

G = +1

VO = 200mV p-p

G = +10

G = +2

G = –1

a

FEATURES
FET Input Amplifier

1 pA Typical Input Bias Current
Very Low Cost
High Speed

80 MHz, –3 dB Bandwidth (G = +1)

80 V/␮s Slew Rate (G = +2)
Low Noise

√

11 nV/

0.6 fA/

Wide Supply Voltage Range

5 V to 24 V
Low Offset Voltage, 1 mV Typical
Single-Supply and Rail-to-Rail Output
High Common-Mode Rejection Ratio –100 dB
Low Power

3.3 mA/Amplifier Typical Supply Current
No Phase Reversal
Small Packaging

SOIC-8, SOT-23-8, and SC70

APPLICATIONS
Instrumentation
Filters
Level Shifting
Buffering

Hz (f = 100 kHz)

√

Hz (f = 100 kHz)

CONNECTION DIAGRAMS

SOIC-8 (R)

AD8033

1

NC

–IN

27

36

+IN

–V

45

S

8

NC

+V

V

NC

SOIC-8 and SOT-23-8 (RT)

V

OUT1

–IN1

+IN1

–V

S

FastFET

™

Op Amps

AD8033/AD8034

SC70 (KS)

AD8033

1

V

OUT

–V

S

OUT

AD8034

1

27

36

45

2

S

34

+IN

8

+V

S

V

OUT2

–IN2

+IN2

+V

5

S

–IN

GENERAL DESCRIPTION

The AD8033/AD8034 FastFET amplifiers are voltage feedback
amplifiers with FET inputs, offering ease of use and excellent
performance. The AD8033 is a single amplifier and the
AD8034 is a dual amplifier. The AD8033/AD8034 FastFET
op amps in ADI’s proprietary XFCB process offer significant
performance improvements over other low cost FET amps, such as
low noise (11 nV/
bandwidth and 80 V/µs slew rate).

With a wide supply voltage range from 5 V to 24 V and fully
operational on a single supply, the AD8033/AD8034 amplifiers
will work in more applications than similarly priced FET
input amps.
outputs for added versatility.

Despite their low cost, the amplifiers provide excellent overall
performance. They offer high common-mode rejection of
–100 dB, low input offset voltage of 2 mV max, and low noise
of 11 nV/

The
quiescent

√

AD8033/AD8034

40 mA of load current.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

√

Hz and 0.6 fA/√Hz) and high speed (80 MHz

In addition, the

Hz.

AD8033/AD8034

have rail-to-rail

amplifiers only draw 3.3 mA/amplifier of

current while having the capability of delivering up to

Figure 1. Small Signal Frequency Response

The AD8033 is available in small packages: SOIC-8 and SC70.
The AD8034 is also available in small packages: SOIC-8 and
SOT-23-8. They are rated to work over the industrial temperature
range of –40°C to +85°C without a premium over commercial
grade products.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD8033/AD8034–SPECIFICATIONS

(TA = 25ⴗC, VS = ⴞ5 V, RL = 1 k⍀, Gain = +2, unless otherwise noted.)

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth G = +1, VO = 0.2 V p-p 65 80 MHz

G = +2, V
G = +2, V

= 0.2 V p-p 30 MHz

O

= 2 V p-p 21 MHz

O

Input Overdrive Recovery Time –6 V to +6 V Input 135 ns
Output Overdrive Recovery Time –3 V to +3 V Input, G = +2 135 ns
Slew Rate (25% to 75%) G = +2, V
Settling Time to 0.1% G = +2, V

= 4 V Step 55 80 V/µs

O

= 2 V Step 95 ns

O

G = +2, VO = 8 V Step 225 ns

NOISE/HARMONIC PERFORMANCE

Distortion f

Second Harmonic R

Third Harmonic R

= 1 MHz, VO = 2 V p-p

C

= 500 Ω –82 dBc

L

= 1 kΩ –85 dBc

R

L

= 500 Ω –70 dBc

L

R

= 1 kΩ –81 dBc

L

Crosstalk, Output-to-Output f = 1 MHz, G = +2 –86 dB
Input Voltage Noise f = 100 kHz 11 nV/√Hz
Input Current Noise f = 100 kHz 0.7 fA/√Hz

DC PERFORMANCE

Input Offset Voltage VCM = 0 V 12mV

– T

T

MIN

MAX

Input Offset Voltage Match 2.5 mV
Input Offset Voltage Drift 4 27 µV/

3.5 mV

o

C

Input Bias Current 1.5 11 pA

T

MIN

– T

MAX

50 pA

Open-Loop Gain VO = ±3 V 89 92 dB

INPUT CHARACTERISTICS

Common-Mode Input Impedance 1000||2.3 GΩ||pF
Differential Input Impedance 1000||1.7 GΩ||pF
Input Common-Mode Voltage Range

FET Input Range –5.0 to +2.2 V
Usable Input Range –5.0 to +5.0 V

Common-Mode Rejection Ratio VCM = (–3 V to +1.5 V) –89 –100 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing ±4.75 ±4.95 V
Output Short Circuit Current 40 mA
Capacitive Load Drive 30% Overshoot, G = +1, 35 pF

VO = 400 mV p-p

POWER SUPPLY

Operating Range 5 24 V
Quiescent Current per Amplifier 3.3 3.5 mA
Power Supply Rejection Ratio VS = ±2 V –90 –100 dB

Specifications subject to change without notice.

REV. B–2–

AD8033/AD8034

SPECIFICATIONS

(TA = 25ⴗC, VS = 5 V, RL = 1 k⍀, Gain = +2, unless otherwise noted.)

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth G = +1, VO = 0.2 V p-p 70 80 MHz

G = +2, V
G = +2, V

= 0.2 V p-p 32 MHz

O

= 2 V p-p 21 MHz

O

Input Overdrive Recovery Time –3 V to +3 V Input 180 ns
Output Overdrive Recovery Time –1.5 V to +1.5 V Input, G = +2 200 ns
Slew Rate (25% to 75%) G = +2, V

= 4 V Step 55 70 V/µs

O

Settling Time to 0.1% G = +2, VO = 2 V Step 100 ns

NOISE/HARMONIC PERFORMANCE

Distortion fC = 1 MHz, VO = 2 V p-p

Second Harmonic R

Third Harmonic R

= 500 Ω –80 dBc

L

= 1 kΩ –84 dBc

R

L

= 500 Ω –70 dBc

L

= 1 kΩ –80 dBc

R

L

Crosstalk, Output to Output f = 1 MHz, G = +2 –86 dB
Input Voltage Noise f = 100 kHz 11 nV/√Hz
Input Current Noise f = 100 kHz 0.7 fA/√Hz

DC PERFORMANCE

Input Offset Voltage VCM = 0 V 1 2.0 mV

– T

T

MIN

MAX

Input Offset Voltage Match 2.5 mV
Input Offset Voltage Drift 4 30 µV/

3.5 mV

o

C

Input Bias Current 110pA

T

MIN

– T

MAX

50 pA

Open-Loop Gain VO = 0 V to 3 V 87 92 dB

INPUT CHARACTERISTICS

Common-Mode Input Impedance 1000||2.3 GΩ||pF
Differential Input Impedance 1000||1.7 GΩ||pF
Input Common-Mode Voltage Range

FET Input Range 0 to 2.0 V
Usable Input Range 0 to 5.0 V

Common-Mode Rejection Ratio VCM = 1.0 V to 2.5 V –80 –100 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 1 kΩ

0.16 to 4.83 0.04 to 4.95

V
Output Short Circuit Current 30 mA
Capacitive Load Drive 30% Overshoot, G = +1, 25 pF

VO = 400 mV p-p

POWER SUPPLY

Operating Range 5 24 V
Quiescent Current per Amplifier 3.3 3.5 mA
Power Supply Rejection Ratio VS = ±1 V –80 –100 dB

Specifications subject to change without notice.

REV. B

–3–

AD8033/AD8034

SPECIFICATIONS

(TA = 25ⴗC, VS = ⴞ12 V, RL = 1 k⍀, Gain = +2, unless otherwise noted.)

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth G = +1, VO = 0.2 V p-p 65 80 MHz

G = +2, V
G = +2, V

= 0.2 V p-p 30 MHz

O

= 2 V p-p 21 MHz

O

Input Overdrive Recovery Time –13 V to +13 V Input 100 ns
Output Overdrive Recovery Time –6.5 V to +6.5 V Input, G = +2 100 ns
Slew Rate (25% to 75%) G = +2, V
Settling Time to 0.1% G = +2, V

= 4 V Step 55 80 V/µs

O

= 2 V Step 90 ns

O

G = +2, VO = 10 V Step 225 ns

NOISE/HARMONIC PERFORMANCE

Distortion f

Second Harmonic R

Third Harmonic R

= 1 MHz, VO = 2 V p-p

C

= 500 Ω –80 dBc

L

= 1 kΩ –82 dBc

R

L

= 500 Ω –70 dBc

L

= 1 kΩ –82 dBc

R

L

Crosstalk, Output to Output f = 1 MHz, G = +2 –86 dB
Input Voltage Noise f = 100 kHz 11 nV/√Hz
Input Current Noise f = 100 kHz 0.7 fA/√Hz

DC PERFORMANCE

Input Offset Voltage V

= 0 V 1 2.0 mV

CM

– T

T

MIN

MAX

3.5 mV

Input Offset Voltage Match 2.5 mV
Input Offset Voltage Drift 4 24 µV/
Input Bias Current 2 12 pA

– T

T

MIN

MAX

50 pA

Open-Loop Gain VO = ±8 V 88 96 dB

INPUT CHARACTERISTICS

Common-Mode Input Impedance 1000||2.3 GΩ||pF
Differential Input Impedance 1000||1.7 GΩ||pF
Input Common-Mode Voltage Range

FET Input Range –12.0 to +9.0 V
Usable Input Range –12.0 to +12.0 V

Common-Mode Rejection Ratio VCM = ±5 V –92 –100 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing ±11.52 ± 11.84 V
Output Short Circuit Current 60 mA
Capacitive Load Drive 30% Overshoot; G = +1 35 pF

POWER SUPPLY

Operating Range 5 24 V
Quiescent Current per Amplifier 3.3 3.5 mA
Power Supply Rejection Ratio VS = ±2 V –85 –100 dB

Specifications subject to change without notice.

o

C

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . See Figure 2

Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . 26.4 V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 1.4 V

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +125°C

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

REV. B–4–

AD8033/AD8034

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8033/AD8034
packages is limited by the associated rise in junction temperature

) on the die. The plastic that encapsulates the die will locally

(T

J

reach the junction temperature. At approximately 150°C, which is
the glass transition temperature, the plastic will change its proper­ties. Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently shifting
the parametric performance of the AD8033/AD8034. Exceeding a
junction temperature of 175°C for an extended period of time can
result in changes in silicon devices, potentially causing failure.

The still-air thermal properties of the package and PCB (
ambient temperature (T
package (P

) determine the junction temperature of the die.

D

), and the total power dissipated in the

A

),

JA

The junction temperature can be calculated as follows

TT

=+ ×()P θ

AD AJJ

The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the package
due to the load drive for all outputs. The quiescent power is the
voltage between the supply pins (VS) times the quiescent current (IS).
Assuming the load (R
drive power is VS/2  I
package and some in the load (V

) is referenced to midsupply, then the total

L

some of which is dissipated in the

OUT,

OUT

 I

). The difference

OUT

between the total drive power and the load power is the drive
power dissipated in the package:

P Quiescent Power Total Drive Power Load Power

=+(–)

D

PVI V V R V R

=×

[]

DSS S OUT L OUT L

+

()

[]

×

//–/2

()

2

[]

RMS output voltages should be considered. If RL is referenced
to V

, as in single-supply operation, then the total drive power

S–

 I

is V

S

OUT

.

If the rms signal levels are indeterminate, consider the worst
case, when V

= VS/4 for RL to midsupply:

OUT

PVI V R

=×

()

DSS S L

+

//4

()

2

Airflow will increase heat dissipation, effectively reducing 
Also, more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes will reduce
the JA. Care must be taken to minimize parasitic capacitances at
the input leads of high speed op amps as discussed in the Layout,
Grounding, and Bypassing Considerations section.

Figure 2 shows the maximum safe power dissipation in the
package versus the ambient temperature for the SOIC-8 (125°C/W),
SC70
standard 4-layer board.

OUTPUT SHORT CIRCUIT

Shorting the output to ground or drawing excessive current for
the AD8033/AD8034 will likely cause catastrophic failure.

In single-supply operation with RL referenced to VS–, worst case

= VS/2.

is V

OUT

2.0

1.5

SOT-23-8

1.0

SC70-5

0.5

MAXIMUM POWER DISSIPATION – W

0.0
–60 –40 –20 0 20 40 60 80 100

SOIC-8

AMBIENT TEMPERATURE – C

Figure 2. Maximum Power Dissipation vs.
Temperature for a Four-Layer Board

(210°C/W),

and SOT-23-8 (160°C/W) packages on a JEDEC



values are approximations.

JA

.

JA

ORDERING GUIDE

Model Temperature Range

AD8033AR +85ºC 8-Lead SOIC R-8
AD8033AR-REEL +85ºC 8-Lead SOIC R-8
AD8033AR-REEL7 +85ºC 8-Lead SOIC R-8
AD8033AKS-REEL +85ºC 5-Lead SC70 KS-5 H3B
AD8033AKS-REEL7
AD8034AR
AD8034AR-REEL7
AD8034AR-REEL
AD8034ART-REEL +85ºC 8-Lead SOT-23 RT-8
AD8034ART -REEL7 +85ºC 8-Lead SOT-23 HZA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8033/AD8034 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–40ºC to
–40ºC to

–40ºC to

–40ºC to
–40ºC to
–40ºC to
–40ºC to
–40ºC to
–40ºC to
–40ºC to

+85ºC 5-Lead SC70 KS-5 H3B
+85ºC 8-Lead SOIC R-8
+85ºC 8-Lead SOIC R-8
+85ºC 8-Lead SOIC R-8

REV. B

Description

–5–

Package Outline

RT-8

WARNING!

Package

Branding

Information

HZA

ESD SENSITIVE DEVICE

AD8033/AD8034–Typical Performance Characteristics

Default Conditions: ⴞ5 V, CL = 5 pF, RL = 1 k⍀, Temperature = 25ⴗC

24

G = +10

21

18

G = +5

15

12

9

G = +2

6

GAIN – dB

3

0

–3

–6

–9

0.01 1001.0 10
FREQUENCY – MHz

G = –1

VO = 200mV p-p

G = +1

TPC 1. Small Signal Frequency Response for
Various Gains

1

0

–1

–2

–3

GAIN – dB

–4

–5

G = +1
VO = 200mV p-p

–6

0.1 100110
FREQUENCY – MHz

VS = +5V

VS = ⴞ5V

VS = ⴞ12V

TPC 2. Small Signal Frequency Response for
Various Supplies (See Test Circuit 1)

1000

8

G = +2

7

V

= 0.2V p-p

6

5

4

GAIN – dB

3

2

1

0

0.1 100110

V

= 1V p-p

OUT

= 4V p-p

V

OUT

V

= 2V p-p

OUT

FREQUENCY – MHz

OUT

TPC 4. Frequency Response for Various Output
Amplitudes (See Test Circuit 2)

8

7

6

5

4

GAIN – dB

3

2

G = +2

1

VO = 200mV p-p

0

0.1 100110
FREQUENCY – MHz

VS = ⴞ5V

V

S

VS = +5V

= ⴞ12V

TPC 5. Small Signal Frequency Response for
Various Supplies (See Test Circuit 2)

2

G = +1

1

0

–1

–2

GAIN – dB

–3

–4

–5

–6

0.1 1001

= 2V p-p

V

OUT

= ⴞ5V

V

S

= +5V

V

S

FREQUENCY – MHz

= ⴞ12V

V

10

S

TPC 3. Large Signal Frequency Response for
Various Supplies (See Test Circuit 1)

7

6

5

4

3

GAIN – dB

2

1

G = +2
VO = 2V p-p

0

0.1 100110

VS = ⴞ5V

= +5V

V

S

FREQUENCY – MHz

VS = ⴞ12V

TPC 6. Large Signal Frequency Response for
Various Supplies (See Test Circuit 2)

REV. B–6–

AD8033/AD8034

8

C

C

R

L

SNUB

L

= 100pF

= 25⍀

= 100pF

C

= 33pF

L

C

= 2pF

L

VO = 200mV p-p

6

G = +1

4

2

0

GAIN – dB

–2

–4

–6

0.1 100110
FREQUENCY – MHz

TPC 7. Small Signal Frequency Response for
Various C

9

8

7

6

5

4

GAIN – dB

3

2

VO = 200mV p-p
R

1

G = +2

0

0.1 100110

(See Test Circuit 1)

LOAD

= 3k⍀

F

CF = 0pF

CF = 1.5pF

C

= 2pF

F

FREQUENCY – MHz

CF = 1pF

10

9

8

7

6

5

4

GAIN – dB

3

G = +2

2

VO = 200mV p-p

1

0

0.1 100110

C

= 100pF

L

C

= 51pF

L

C

= 33pF

L

C

= 2pF

L

FREQUENCY – MHz

TPC 10. Small Signal Frequency Response for
Various C

8

VO = 200mV p-p
G = +2

7

6

5

4

GAIN – dB

3

2

1

0

0.1 100110

(See Test Circuit 2)

LOAD

RL = 500⍀

FREQUENCY – MHz

RL = 1k⍀

TPC 8. Small Signal Frequency Response for
Various RF/CF (See Test Circuit 2)

100

VO = 200mV p-p

10

G = +2

1

IMPEDANCE – ⍀

0.1

0.01
100 1k 10k 100k 1M 10M 100M

FREQUENCY – Hz

TPC 9. Output Impedance vs. Frequency
(See Test Circuits 4 and 7)

REV. B

G = +1

–7–

TPC 11. Small Signal Frequency Response for
Various R

100

80

60

40

GAIN – dB

20

0

–20

100 10M1k 10k 100k 1M 100M

(See Test Circuit 2)

LOAD

PHASE

FREQUENCY – Hz

VS = ⴞ12V

GAIN

TPC 12. Open-Loop Response

180

150

120

90

PHASE – Degrees

60

30

0

AD8033/AD8034

–40

–50

–60

–70

–80

–90

DISTORTION – dBc

–100

–110

–120

G = +2

HD3 RL = 1k⍀

HD2 R

= 1k⍀

L

0.1 1 5

FREQUENCY – MHz

HD2 R

HD3 RL = 500⍀

= 500⍀

L

TPC 13. Harmonic Distortion vs. Frequency for
Various Loads (See Test Circuit 2)

–40

G = +2

–50

–60

–70

–80

HD2 VS = 5V

–90

DISTORTION – dBc

–100

–110

–120

0.1 5

HD2 V

FREQUENCY – MHz

= 24V

S

1

HD3 VS = 5V

HD3 VS = 24V

TPC 14. Harmonic Distortion vs. Frequency for
Various Supply Voltages (See Test Circuit 2)

–40

–50

–60

–70

–80

HD3 G = +2

–90

DISTORTION – dBc

–100

–110

–120

0.1 51

HD2 G = +1

HD2 G = +2

HD3 G = +1

FREQUENCY – MHz

TPC 16. Harmonic Distortion vs. Frequency for
Various Gains

–20

–30

–40

–50

HD3 VO = 20V p-p

–60

–70

–80

–90

DISTORTION – dBc

–100

–110

–120

0.1 51

HD3 VO = 10V p-p

HD2 VO = 2V p-p

FREQUENCY – MHz

HD2 VO = 20V p-p

HD2 VO = 10V p-p

HD3 VO = 2V p-p

TPC 17. Harmonic Distortion vs. Frequency for
Various Amplitudes (See Test Circuit 2), VS = 24 V

1000

Hz

100

NOISE – nV/

10

10 10M100 1k 10k 100k 1M 100M

FREQUENCY – Hz

TPC 15. Voltage Noise

80

70

60

VS = +5V

NEGATIVE SIDE

50

40

30

PERCENT OVERSHOOT

20

10

0

10 30 50 70 90 110

VS = ⴞ5V

VS = +5V

POSITIVE SIDE

CAP LOAD – pF

POSITIVE SIDE

VS = ⴞ5V

NEGATIVE SIDE

TPC 18. Capacitive Load vs. Percent Overshoot
G = +1 (See Test Circuit 1)

REV. B–8–

AD8033/AD8034

G = +1

25mV/DIV

20ns/DIV

TPC 19. Small Signal Transient Response 5 V
(See Test Circuit 1)

VO = 20V p-p

VO = 8V p-p

VO = 2V p-p

G = +1

38pF

80mV/DIV

15pF

80ns/DIV

TPC 22. Small Signal Transient Response ±5 V
(See Test Circuit 1)

VO = 20V p-p

VO = 8V p-p

VO = 2V p-p

3V/DIV

320ns/DIV

TPC 20. Large Signal Transient Response G = +1
(See Test Circuit 1)

G = –1

1.5V/DIV

V

IN

V

OUT

350ns/DIV

TPC 21. Output Overdrive Recovery (See Test Circuit 3)

3V/DIV

320ns/DIV

TPC 23. Large Signal Transient Response G = +2
(See Test Circuit 2)

G = +1

1.5V/DIV

V

OUT

V

IN

350ns/DIV

TPC 24. Input Overdrive Recovery (See Test Circuit 1)

REV. B

–9–

AD8033/AD8034

t

= 0

VIN = 1V

V

OUT

– 2V

VIN = 1V

IN

+0.1%

–0.1%

t

= 0

+0.1%

V

OUT

– 2V

IN

–0.1%

2mV/DIV

1.5␮s/DIV

TPC 25. Long-Term Settling Time

0

–5

–10

–15

–20

– pA

b

I

–25

–30

–35

–40

20 8525 30 35 40 45 50 55 60 65 70 75 80

TEMPERATURE – ⴗC

–I

b

+I

b

TPC 26. Ib vs. Temperature

BJT INPUT RANGE

42

36

30

24

= ␮A

18

b

12

6

0

FET INPUT RANGE

10

5
0

–5

–10

– pA I

b

I

–15
–20
–25
–30

–12 –10 –8 –6 –4 –2 024681012

+I

b

–I

b

COMMON-MODE VOLTAGE – V

–I

b

+I

b

2mV/DIV

20ns/DIV

TPC 28. 0.1% Short-Term Settling Time

7.0

6.9

6.8

6.7

6.6

6.5

6.4

6.3

6.2

QUIESCENT CURRENT – mA

6.1

6.0

5.9
–40 –20

VS = ⴞ12V

VS = ⴞ5V

VS = +5V

020406080

TEMPERATURE – ⴗC

TPC 29. Quiescent Supply Current vs. Tempera-

for Various Supply Voltages

ture

4.0

3.5

3.0

2.5

2.0

1.5

1.0

.50

NORMALIZED OFFSET – mV

0

–.50

–1.0

–14 12–12

VS = ⴞ5V

–10 –8 –6 –4 –2 0 2 4 6 8 10

COMMON-MODE VOLTAGE – V

VS = +5V

VS = ⴞ12V

14

TPC 27. Input Bias Current vs. Common-Mode
Voltage Range

TPC 30. Input Offset Voltage vs. Common­Mode Voltage

REV. B–10–

AD8033/AD8034

FREQUENCY – MHz

–40

–70

–100

0.1

CROSSTALK – dB

50

–80

–90

–60

–50

110

SOIC A/B

SOIC B/A

SOT-23 B/A

SOT-23 A/B

–20

–30

–40

–50

CMRR – dB

–60

–70

–80

0.1 1 10 50

FREQUENCY – MHz

TPC 31. CMRR vs. Frequency (See Test Circuit 7)

1.0

0.8

VCC Ð V

0.6

OH

105

100

95

90

85

80

75

OPEN-LOOP GAIN – dB

70

65

60

–12

RL = 500

⍀

RL = 1k

⍀

OUTPUT VOLTAGE – V

RL = 2k

⍀

12–10 –8 –6 –4 –2 0 2 4 6 8 10

TPC 34. Open-Loop Gain vs. Output Voltage for
Various R

LOAD

0.4

VOL Ð V

I

LOAD

EE

– mA

OUTPUT SATURATION – V

0.2

0

0305

10 15 20 25

TPC 32. Output Saturation Voltage vs. Load Current

0

–10

–20

–30

–40

–50

PSRR – dB

–60

–70

–80

–90

–100

0.0001 1000.001 0.01 0.1 1 10

TPC 33. PSRR vs. Frequency (See Test Circuits 6 and 8)

–PSRR

+PSRR

FREQUENCY – MHz

TPC 35. Crosstalk (See Test Circuit 9)

180

150

120

90

FREQUENCY

60

30

0

–1.5 –1.0 –0.5 0 0.5 1.0 1.5

VOS – mV

TPC 36. Initial Offset

REV. B

–11–

AD8033/AD8034

V

CC

V

EE

1␮F

+

10nF

AD8033/AD8034

10nF

1␮F

+

V

SINE

0.2V

p-p

+

–

1k⍀

1k⍀

V

OUT

V

OUT

1.2V/DIV

TPC 37. G = +1 Response VS = ± 5 V

Test Circuits

V

IN

49.9⍀

V

IN

V

CC

1␮F

+

10nF

R

SNUB

AD8033/AD8034

10nF

+

1␮F

V

EE

Test Circuit 1. G = +1

976⍀

C

LOAD

1␮s/DIV

49.9⍀

1.2V/DIV

V

IN

1␮s/DIV

TPC 38. G = +2 Response VS = ± 5 V

C

F

1k⍀

V

OUT

V

IN

499⍀

49.9⍀

1k⍀

R

F

V

CC

1␮F

+

10nF

AD8033/AD8034

10nF

+

1␮F

V

EE

R

SNUB

976⍀

C

LOAD

49.9⍀

V

OUT

Test Circuit 2. G = +2

V

IN

1k⍀

499⍀

1k⍀

V

CC

1␮F

+

10nF

976⍀

AD8033/AD8034

10nF

+

1␮F

V

EE

Test Circuit 3. G = –1

49.9⍀

V

CC

1␮F

+

10nF

V

OUT

AD8033/AD8034

10nF

1␮F

V

EE

V

SINE

0.2V

+

Test Circuit 4. Output Impedance
G = +1

p-p

+

–

Test Circuit 5. Output Impedance

G = +2

REV. B–12–

AD8033/AD8034

V

IN

49.9

1V p-p

+

V

AC

CC

49.9⍀

AD8033/AD8034

10nF

+

1␮F

V

EE

Test Circuit 6. Positive PSRR

⍀

1k

⍀

⍀

1k

⍀

1k

⍀

1k

V

CC

1␮F

+

10nF

10nF

1␮F

V

EE

Test Circuit 7. CMRR

V

–

CC

V

OUT

976

AD8033/AD8034

+

V

CC

1␮F

+

10nF

V

AD8033/AD8034

1V p-p
–

V

EE

+

V

AC

EE

49.9⍀

OUT

Test Circuit 8. Negative PSRR

1k⍀1k⍀

V

EE

–

TO PORT 1

+

V

⍀

49.9

V

OUT

⍀

IN

–

50⍀

TO PORT 2

1k⍀

499⍀

B

+

V

CC

V

EE

+

A

–

V

CC

1k⍀

499⍀

1k⍀1k⍀

Test Circuit 9. Crosstalk

REV. B

–13–

AD8033/AD8034

THEORY OF OPERATION

The incorporation of JFET devices into Analog Devices’ high
voltage XFCB process has given the performance ability to
design the AD8033/AD8034. The AD8033/AD8034 are voltage
feedback rail-to-rail output amplifiers with FET inputs and a
bipolar-enhanced common-mode input range. The use of JFET
devices in high speed amplifiers extends the application

space
into both low input bias current as well as low distortion high
bandwidth areas.

Using N-channel JFETs and a folded cascade input topology, the
common-mode input level operates from 0.2 V below the negative
rail to within 3.0 V of the positive rail. Cascading of the
ensures low input bias current over the entire common-

input stage

mode range
as well as CMRR and PSRR specifications that are above 90 dB.
Additionally, long-term settling issues that normally occur with
high supply voltages are minimized as a result of the cascading.

Output Stage Drive and Capacitive Load Drive

The common emitter output stage adds rail-to-rail output perfor-

and is compensated to drive 35 pF (30% overshoot G = +1).

mance
Additional capacitance can be driven if a small snub resistor is
put in series with the capacitive load, effectively decoupling the
load from the output stage, as shown in TPC 7. The output

can source and sink 20 mA of current within 500 mV of the

stage

rails and 1 mA within 100 mV of the supply rails.

supply

Input Overdrive

An additional feature of the AD8033/AD8034 is a bipolar
input pair that adds rail-to-rail common-mode input perfor­mance specifically for applications that cannot tolerate phase
inversion problems.

Under normal common-mode operation, the bipolar input pair
is kept reversed, maintaining Ib at less than 1 pA. When the

common mode comes within 3.0 V of the positive supply

input
rail, I1 turns off and I4 turns on,

+VS

supplying tail current to the

bipolar pair Q25 and Q27. With this configuration, the inputs
can be
inversion (see Figure 3).

As a result of entering the bipolar mode of operation, an offset and
input bias current shift will occur. See TPCs 27 and 30
re-entering the JFET common-mode range, the amplifier will
recover in approximately 100 ns (refer to TPC 24 for input
overload
tection diodes
input bias current.
rails, series input resistance should be included to limit the input
bias current to less than 10 mA.

Input Impedance

The input capacitance of the
with the feedback network, resulting in peaking and ringing
overall response. The equivalent impedance of the feedback
network should be kept small enough to ensure that the parasitic
pole falls well beyond the –3 dB bandwidth of the gain configura­tion being used. If larger impedance values are desired, the
amplifier can be compensated by placing a small capacitor in
parallel with the feedback resistor. TPC 8 shows the improvement
in frequency response by including a small feedback capacitor
with high feedback resistance values.

Thermal Considerations

Because the AD8034 operates at up to ±12 V supplies in the small
SOT-23-8 package (160°C/W), power dissipation can easily exceed
package limitations, resulting in permanent shifts in device
characteristics and even failure. Likewise, high supply voltages can
cause an increase in junction temperature even with light loads,
resulting in an input bias current and offset drift penalty. The input
bias current will double for every 10°C shown in TPC 26. Refer
to the Maximum Power Dissipation section for an estimation of
die temperature based on load and supply voltage.

driven beyond the positive supply rail without any phase

. After

behavior). Above and below the supply rails, ESD pro-

activate, resulting in an exponentially increasing

If the inputs are to be driven well beyond the

AD8033/AD8034

will form a pole

in the

VTH

–VS

–IN

Q9

R14

Q7

R3

+

V2

–

Q4

Q13

+IN

J2

D5

R7

Q11

Q29

I3

Q1

Q14

VCC

Q28

R8

+

V4

–

V

OUT

R2

Q6

D4

J1

I1 I4

Q25

I2

Q27

Figure 3. Simplified AD8033/AD8034 Input Stage

REV. B–14–

AD8033/AD8034

LAYOUT, GROUNDING, AND BYPASSING
CONSIDERATIONS
Bypassing

Power supply pins are actually inputs, and care must be taken
so that a noise-free stable dc voltage is applied. The purpose of
bypass capacitors is to create low impedances from the supply to
ground at all frequencies, thereby shunting or filtering a majority
of the noise. Decoupling schemes are designed to minimize the
bypassing impedance at all frequencies with a parallel combination
of capacitors. 0.01 µF or 0.001 µF (X7R or NPO) chip capacitors
are critical and should be placed as close as possible to the
amplifier package. Larger chip capacitors, such as the 0.1 µF
capacitor, can be shared among a few closely spaced active
components in the same signal path. The 10 µF tantalum capacitor
is less critical for high frequency bypassing, and in most cases,
only one per board is needed at the supply inputs.

Grounding

A ground plane layer is important in densely packed PC boards

in
order to spread the current, thereby minimizing parasitic induc­tances. However,
a circuit is critical

an understanding of where the current flows in

to implementing effective high speed circuit
design. The length of the current path is directly proportional to
the magnitude of
frequency impedance
inductive ground return will
length of the high frequency

the parasitic inductances, and thus the high

of the path. High speed currents in an

create unwanted voltage noise. The

bypass capacitor leads is most critical.
A parasitic inductance in the bypass grounding will work against
the low impedance created by the bypass capacitor. Place the
ground leads of the bypass capacitors at the same physical location.

Because load currents flow from the supplies as well, the ground
for the load impedance should be at the same physical location
as the bypass capacitor grounds. For the larger value capacitors
that are intended to be effective at lower frequencies, the current
return path distance is less critical.

Leakage Currents

Poor PC board layout, contaminants, and the board insulator
material can create leakage currents that are much larger than the
input bias currents of the
between the inputs and nearby runs will set up leakage

AD8033/AD8034

. Any voltage differen

tial

currents

through the PC board insulator, for example, 1 V/100 GΩ = 10 pA.
Similarly, any contaminants on the board can create significant
leakage (skin oils are a common problem).
leakages, put a guard ring (shield) around

To significantly reduce

the inputs and input

leads that are driven to the same voltage potential as the
This way there is no voltage potential between the inputs
surrounding area to set up any leakage currents. For the guard

inputs.

and

ring
to be completely effective, it must be driven by a relatively low
impedance source and should
leads on all sides, above, and below

completely surround the input

using a multilayer board.

Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the amount
of material between the
to reduce the absorption.

®

Teflon

Input Capacitance

or ceramic may be necessary in some instances.

input leads and the guard ring will help

Also, low absorption materials such as

Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
A few pF of capacitance will reduce the input impedance at high
frequencies, in turn increasing the amplifiers’ gain and causing

of the overall response or even oscillations if severe

peaking
enough. It is recommended that the external passive components
that are connected to the input pins be placed as close as possible
to the inputs to avoid parasitic capacitance. The ground and power
planes must be kept at a distance of at least 0.05 mm from the
input pins on all layers of the board.

APPLICATIONS
High Speed Peak Detector

The low input bias current and high bandwidth of the AD8033/
AD8034 make the parts ideal for a fast settling, low leakage peak
detector. The classic fast-low leakage topology with a diode in
the output is limited to 1.4 V p-p max in the case of the
AD8033/AD8034 because of the protection diodes across the
inputs, as depicted in Figure 4.

AD8033/

V

IN

~1.4V p-p MAX

Figure 4. High Speed Peak Detector with Limited Input Range

AD8034

V

OUT

REV. B

–15–

AD8033/AD8034

Using the
constructed

AD8033/AD8034

, a unity gain peak detector can be

that will capture a 300 ns pulse while still taking
advantage of the AD8033/AD8034’s low input bias current and
wide common-mode input range, as shown in Figure 5.

Using two amplifiers, the difference between the peak and the
current input level is forced across R2 instead of either amplifier’s
input pins. In the event of a rising pulse, the first amplifier
compensates for the drop across D2 and D3, forcing the voltage
Node 3 equal to Node 1. D1 is off and the voltage drop across

at

R2
is zero. Capacitor C3 speeds up the loop by providing the charge
required by the first amplifier’s input capacitance, helping to
maintain a minimal voltage drop across R2 in the sampling mode.
A negative going edge results in D2 and D3 turning off and D1
turning on, closing the loop around the first amplifier and forcing

– VIN across R2. R4 makes the voltage across D2 zero,

V

OUT

minimizing leakage current and kickback from D3 from affecting
the voltage across C2.

The rate of the incoming edge must be limited so that the output
of the first amplifier does not overshoot the peak value of V

IN

before the second amplifier’s output can provide negative feedback
at the first amplifier’s summing junction. This is accomplished
with the combination of R1 and C1, which allows the voltage at
Node 1 to settle to 0.1% of V

in 270 ns. The selection of C2

IN

and R3 is made by considering droop rate, settling time, and
kickback. R3 prevents overshoot from occurring at Node 3. The
time constants of R1, C1 and R3, C2 are roughly equal to achieve
the best performance. Slower time constants can be selected by
increasing C2 to minimize droop rate and kickback at the cost
of increased settling time. R1 and C1 should also be increased
to match, reducing the incoming pulse’s effect on kickback.

INPUT

OUTPUT

1.00V/DIV 100nS/DIV

Figure 6. Peak Detector Response 4 V 300 ns Pulse

Figure 6 shows the peak detector in Figure 5 capturing a 300 ns
4 V pulse with 10 mV of kickback and a droop rate of 5 V/s. For
larger peak-peak pulses, the time constants of R1, C1 and R3, C3
should be increased to reduce overshoot. The best droop rate will
occur by isolating parasitic resistances from Node 3. This can be
accomplished using a guard band connected to the output of the
second amplifier that surrounds its summing junction (Node 3).

Increasing both time constants by a factor of 3 permits a

larger

peak pulse to be captured and increases the output accuracy.

C3

10pF

R2

1k⍀

LS4148

+V

S

R1

V

IN

49.9⍀

1k⍀

R5

39pF/

C1

120pF

1/2

AD8034

–V

S

D1

D3

LS4148

C4

4.7pF

R4
6k⍀

D2

LS4148

C2

200⍀

R3

AD8034

180pF/560pF

1/2

+V

S

V

OUT

–V

S

Figure 5. High Speed Unity Gain Peak Detector Using AD8034

REV. B–16–

INPUT

10k 1M 10M

FREQUENCY – Hz

–100

REF LEVEL – dB

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

100k

OUTPUT

1.00V/DIV 200nS/DIV

Figure 7. Peak Detector Response 5 V 1 µs Pulse

Figure 7 shows a 5 V peak pulse being captured in 1 s with less
than 1 mV of kickback. With this selection of time constants, up
to a 20 V peak pulse can be captured with no overshoot.

Active Filters

The response of an active filter varies greatly depending on the
performance of the active device. Open-loop bandwidth and gain,
along with the order of the filter, will determine stop-band
attenuation as well as the maximum cutoff frequency, while input
capacitance can set a limit on which passive components are used.
Topologies for active filters are varied, and some are more
dependent on the performance of the active device than others.

The Sallen-Key topology is the least dependent on the active
device, requiring that the bandwidth be flat to beyond the stop­band frequency since it is used simply as a gain block. In the
case of high Q filter stages, the peaking must not exceed the
open-loop bandwidth and linear input range of the amplifier.

Using an AD8033/AD8034, a four-pole cascaded Sallen-Key
filter can be constructed with f

C

stop-band attenuation, as shown in Figure 8.

C3

33pF

V

IN

C4

82pF

R4

4.99k⍀

Figure 8. Four-Pole Cascade Sallen-Key Filter

Component values are selected using a normalized cascaded
two-stage Butterworth filter table and Sallen-Key two-pole
active filter equations. The overall frequency response is shown
in Figure 9.

REV. B

R1

4.22k⍀

R5

49.9⍀

4.99k⍀

R2

6.49k⍀

C1

27pF

R3

C2

10pF

= 1 MHz and over 80 dB of

+V

S

1/2

AD8034

–V

S

+V

S

1/2

AD8034

–V

S

V

OUT

AD8033/AD8034

Figure 9. Four-Pole Cascade Sallen-Key Filter Response

The common-mode input capacitance should be considered
in the component selection.

Filter cutoff frequencies can be increased beyond 1 MHz using
the AD8033/AD8034, but limited open-loop gain and input
impedance begin to interfere with the higher Q stages. This can
cause early roll-off of the overall response.

Additionally, the stop-band attenuation will decrease with
decreasing open-loop gain.

Keeping these limitations in mind, a two-pole Sallen-Key
Butterworth filter with f
has a relatively low Q of 0.707 while still maintaining 15 dB
of attenuation an octave above f
attenuation. The filter and response are shown in Figures 10
and 11, respectively.

R5

49.9⍀

2.49k⍀

V

IN

Figure 10. Two-Pole Butterworth Active Filter

5

0

–5

–10

–15

–20

GAIN – dB

–25

–30

–35

–40

–45

100k 100M1M 10M

Figure 11. Two-Pole Butterworth Active Filter Response

–17–

= 4 MHz can be constructed that

C

and 35 dB of stop-band

C

22pF

R1

C3

R2

2.49k⍀

C1

10pF

FREQUENCY – Hz

AD8033

+V

S

–V

S

V

OUT

AD8033/AD8034

Wideband Photodiode Preamp

Figure 12 shows an I/V converter with an electrical model of a
photodiode.

The basic transfer function is

where I

V

IR

=

OUT

is the output current of the photodiode, and the

PHOTO

×

PHOTO F

sC R

+1

FF

parallel combination of RF and CF sets the signal bandwidth.

The stable bandwidth attainable with this preamp is a function
of R

, the gain bandwidth product of the amplifier, and the total

F

capacitance at the amplifier’s summing junction, including C

S

and the amplifier input capacitance. RF and the total capaci­tance produce a pole in the amplifier’s loop transmission that can
result in peaking and instability. Adding C

creates a zero in the

F

loop transmission that compensates for the pole’s effect and
reduces the signal bandwidth. It can be shown that the signal
bandwidth resulting in a 45° phase margin (f

) is defined by the

(45)

expression

f

f

()45

2=××π

CR

RC

FS

fCR is the amplifier crossover frequency.

R

is the feedback resistor.

F

C

is the total capacitance at the amplifier summing junction

S

(amplifier + photodiode + board parasitics).

The value of C

that produces f

F

C

=

F

can be shown to be

(45)

C

S

Rf

××2π

FCR

The frequency response in this case will show about 2 dB of
peaking and 15% overshoot. Doubling C

and cutting the

F

bandwidth in half will result in a flat frequency response, with
about 5% transient overshoot.

The preamp’s output noise over frequency is shown in Figure 13.

The pole in the loop transmission translates to a zero in the
amplifier’s noise gain, leading to an amplification of the input
voltage noise over frequency. The loop transmission zero
introduced by C

limits the amplification. The noise gain’s

F

bandwidth extends past the preamp signal bandwidth and

is eventually rolled off by the decreasing loop gain of the
amplifier. Keeping the input terminal impedances matched is
recommended to eliminate common-mode noise peaking
effects that will add to the output noise.

Integrating the square of the output voltage noise spectral density
over frequency and then taking the square root results in the
total rms output noise of the preamp.

C

F

R

F

C

M

C

D

C

M

V

O

I

PHOTO

R

= 1011⍀

SH

C

S

CF + C

V

B

S

R

F

Figure 12. Wideband Photodiode Preamp

f

=

1

2␲RF (CF + CS + CM + 2CD)

f

=

2

2␲RFC

f

=

3

(CS + CM + 2CD + CF) /C

RF NOISE

VOLTAGE NOISE – nV/ Hz

f

1

VEN

f

2

NOISE DUE TO AMPLIFIER

1

1

F

f

CR

VEN (CF + CS + CM + 2CD) /C

FREQUENCY – Hz

F

f

3

F

Figure 13. Photodiode Voltage Noise Contributions

REV. B–18–

OUTLINE DIMENSIONS

1 3

5 6

2

8

4

7

2.90 BSC

PIN 1

1.60 BSC

1.95

BSC

0.65 BSC

0.38

0.22

0.15 MAX

1.30

1.15

0.90

SEATING
PLANE

1.45 MAX

0.22

0.08

0.60

0.45

0.30

10ⴗ

0ⴗ

2.80 BSC

COMPLIANT TO JEDEC STANDARDS MO-178BA

AD8033/AD8034

8-Lead Standard Small Outline Package [SOIC]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

85

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

BSC

6.20 (0.2440)

5.80 (0.2284)

41

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.33 (0.0130)

0.25 (0.0098)

0.19 (0.0075)

0.50 (0.0196)

0.25 (0.0099)

8ⴗ
0ⴗ

1.27 (0.0500)

0.41 (0.0160)

8-Lead Small Outline Transistor Package [SOT-23]

(RT-8)

Dimensions shown in millimeters

ⴛ 45ⴗ

REV. B

5-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-5)

Dimensions shown in millimeters

2.00 BSC

0.30

0.15

4

3

0.65 BSC

2.10 BSC

1.10 MAX

SEATING
PLANE

0.22

0.08

2

–19–

1.25 BSC

1.00

0.90

0.70

0.10 MAX

5

1

PIN 1

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-203AA

0.46

0.36

0.26

AD8033/AD8034

Revision History

Location Page

2/03—Data Sheet changed from REV. A to REV. B.

Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to CONNECTION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Replaced TPC 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Changes to TPC 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Changes to Test Circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8/02—Data Sheet changed from REV. 0 to REV. A.

Added AD8033 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

V

= 2 V p-p deleted from Default Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

OUT

Added SOIC-8 (R) and SC70 (KS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to GENERAL DESCRIPTION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

New Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to MAXIMUM POWER DISSIPATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Change to TPC 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Change to TPC 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Change to TPC 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

New TPC 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

New TPC 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

New TPC 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

New TPC 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

New Test Circuit 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

SC70 (KS) package added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

C02924–0–2/03(B)

–20–

PRINTED IN U.S.A.

REV. B