Datasheet AD8027 Datasheet (Analog Devices)

Low Distortion, High Speed

FEATURES

High speed

190 MHz, –3 dB bandwidth (G = +1)
100 V/µs slew rate

Low distortion

120 dBc @ 1 MHz SFDR

80 dBc @ 5 MHz SFDR
Selectable input crossover threshold
Low noise

4.3 nV/√Hz

1.6 pA/√Hz
Low offset voltage: 900 µV max
Low power: 6.5 mA/amplifier supply current
Power-down mode
No phase reversal: V
Wide supply range: 2.7 V to 12 V
Small packaging: SOIC-8, SOT-23-6, MSOP-10

APPLICATIONS

Filters
ADC drivers
Level shifting
Buffering
Professional video
Low voltage instrumentation

GENERAL DESCRIPTION

The AD8027/AD80281 are high speed amplifiers with rail-to­rail input and output that operate on low supply voltages and
are optimized for high performance and wide dynamic signal
range. The AD8027/AD8028 have low noise (4.3 nV/√Hz,

1.6 pA/√Hz) and low distortion (120 dBc at 1 MHz). In appli­cations that use a fraction of, or the entire input dynamic range
and require low distortion, the AD8027/AD8028 are ideal
choices.

Many rail-to-rail input amplifiers have an input stage that
switches from one differential pair to another as the input signal
crosses a threshold voltage, which causes distortion. The
AD8027/AD8028 have a unique feature that allows the user to
select the input crossover threshold voltage through the
SELECT pin. This feature controls the voltage at which the
complementary transistor input pairs switch. The AD8027/
AD8028 also have intrinsically low crossover distortion.

> |VS| + 200 mV

IN

Rail-to-Rail Input/Output Amplifiers

AD8027/AD8028

CONNECTION DIAGRAMS

V

–IN A
+IN A

V

OUT

–V

OUTA

–V

+IN

AD8027

SOT-23-6

(RT)

6

+–

(RM)

03327-B-001

= +5V

+V

S

5

DISABLE/SELECT

4

–IN

10

+V
V

9

OUTB

–IN B

8

–

+

7

+IN B

6

DISABLE/SELECT B

VS = ±5V

S

03327-A-063

0

1

2

S

3

AD8028

MSOP-10

1
2

–
+

3
4

S

5

V

S

AD8027

SOIC-8

(R)

NC

V

+IN

–V

OUTA

–IN A
+IN A

–V

–IN

S

S

1
2
3
4

NC = NO CONNECT

AD8028

SOIC-8

1

–

2
3

+

4

8

DISABLE/SELECT
+V

7

S

V

6

OUT

NC

5

(R)

8

+V

S

V

7

OUTB

–IN B

6

–
+

5

+IN B

DISABLE/SELECT A

Figure 1. Connection Diagrams (Top View)

With their wide supply voltage range (2.7 V to 12 V) and wide
bandwidth (190 MHz), the AD8027/AD8028 amplifiers are
designed to work in a variety of applications where speed and
performance are needed on low supply voltages. The high per­formance of the AD8027/AD8028 is achieved with a quiescent
current of only 6.5 mA/amplifier typical. The AD8027/AD8028
have a shutdown mode that is controlled via the SELECT pin.

The AD8027/AD8028 are available in SOIC-8, MSOP-10, and
SOT-23-6 packages. They are rated to work over the industrial
temperature range of –40°C to +125°C.

–20

G = +1
FREQUENCY = 100kHz
R

= 1kΩ

L

–40

–60

= +3V

V

S

–80

SFDR (dB)

–100

–120

–140

01234567891

1

Protected by U.S. patent numbers 6,486,737B1; 6,518,842B1

OUTPUT VOLTAGE (V p-p)

Figure 2. SFDR vs. Output Amplitude

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

www.analog.com

AD8027/AD8028

TABLE OF CONTENTS

Specifications..................................................................................... 3

Wideband Operation ..................................................................... 19

Absolute Maximum Ratings............................................................ 6

Maximum Power Dissipation .....................................................6

ESD Caution.................................................................................. 6

Typical Performance Characteristics............................................. 8

Theory of Operation ......................................................................17

Input Stage................................................................................... 17

Crossover Selection.................................................................... 17

Output Stage................................................................................ 18

DC Errors.................................................................................... 18

REVISION HISTORY

3/05—Rev. B to Rev. C

Updated Format..................................................................Universal

Change to Figure 1 ........................................................................... 1

10/03—Rev. A to Rev. B

Changes to Figure 1...........................................................................1

Circuit Considerations .............................................................. 19

Applications..................................................................................... 21

Using the SELECT Pin............................................................... 21

Driving a 16-Bit ADC................................................................ 21

Band-Pass Filter.......................................................................... 22

Design Tools and Technical Support....................................... 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 24

8/03—Rev. 0 to Rev. A

Addition of AD8028........................................................... Universal

Changes to GENERAL DESCRIPTION.........................................1

Changes to Figures 1, 3, 4, 8, 13, 15, 17............................1, 6, 7, 8, 9

Changes to Figures 58, 60.........................................................18, 20

Changes to SPECIFICATIONS........................................................3

Updated OUTLINE DIMENSIONS .............................................22

Updated ORDERING GUIDE.......................................................23

3/03—Revision 0: Initial Version

Rev. C | Page 2 of 24

AD8027/AD8028

SPECIFICATIONS

VS = ±5 V at TA = 25°C, RL = 1 kΩ to midsupply, G = 1, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

G = 1, VO = 2 V p-p 20 32 MHz

NOISE/DISTORTION PERFORMANCE

f

DC PERFORMANCE

T

T

INPUT CHARACTERISTICS

SELECT PIN

OUTPUT CHARACTERISTICS

POWER SUPPLY

1

No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin.

–3 dB Bandwidth G = 1, VO = 0.2 V p-p 138 190 MHz

Bandwidth for 0.1 dB Flatness G = 2, VO = 0.2 V p-p 16 MHz
Slew Rate G = +1, VO = 2 V step/G = −1, VO = 2 V step 90/100 V/µs
Settling Time to 0.1% G = 2, VO = 2 V step 35 ns

Spurious-Free Dynamic Range (SFDR) fC = 1 MHz, VO = 2 V p-p, RF = 24.9 Ω 120 dBc

= 5 MHz, VO = 2 V p-p, RF = 24.9 Ω 80 dBc

C

Input Voltage Noise f = 100 kHz 4.3 nV/√Hz
Input Current Noise f = 100 kHz 1.6 pA/√Hz
Differential Gain Error NTSC, G = 2, R
Differential Phase Error NTSC, G = 2, R

= 150 Ω

L

= 150 Ω

L

Crosstalk, Output to Output G = 1, RL = 100 Ω, V

V

= ±5 V @ 1 MHz

S

= 2 V p-p,

OUT

0.1 %

0.2 Degrees

−93 dB

Input Offset Voltage SELECT = three-state or open, PNP active 200 800 µV
SELECT = high NPN active 240 900 µV
Input Offset Voltage Drift T

Input Bias Current

1

V

MIN

to T

MAX

1.50 µV/°C

VCM = 0 V, NPN active 4 6 µA

to T

MIN

MAX

= 0 V, PNP active −8 −11 µA

CM

to T

MIN

MAX

4 µA

−8 µA
Input Offset Current ±0.1 ±0.9 µA
Open-Loop Gain VO = ±2.5 V 100 110 dB

Input Impedance 6 MΩ
Input Capacitance 2 pF
Input Common-Mode Voltage Range −5.2 to +5.2 V
Common-Mode Rejection Ratio VCM = ±2.5 V 90 110 dB

Crossover Low, Selection Input Voltage Three-state < ±20 µA −3.3 to +5 V
Crossover High, Selection Input Voltage −3.9 to −3.3 V
Disable Input Voltage −5 to −3.9 V
Disable Switching Speed 50% of input to <10% of final V

O

980 ns

Enable Switching Speed 45 ns

Output Overdrive Recovery Time

VI = +6 V to −6 V, G = −1 40/45 ns

(Rising/Falling Edge)

Output Voltage Swing −VS + 0.10 +VS − 0.06,

−V

+ 0.06

S

+V

− 0.10 V

S

Short-Circuit Output Sinking and Sourcing 120 mA
Off Isolation VIN = 0.2 V p-p, f = 1 MHz, SELECT = low −49 dB

Capacitive Load Drive 30% overshoot 20 pF

Operating Range 2.7 12 V
Quiescent Current/Amplifier 6.5 8.5 mA

Quiescent Current (Disabled) SELECT = low 370 500 µA
Power Supply Rejection Ratio VS ± 1 V 90 110 dB

Rev. C | Page 3 of 24

AD8027/AD8028

VS = 5 V at TA = 25°C, RL = 1 kΩ to midsupply, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = 1, VO = 0.2 V p-p 131 185 MHz

G = 1, VO = 2 V p-p 18 28 MHz

Bandwidth for 0.1 dB Flatness G = 2, V
Slew Rate G = +1, VO = 2 V step/G = −1, VO = 2 V step 85/100 V/µs
Settling Time to 0.1% G = 2, VO = 2 V step 40 ns

NOISE/DISTORTION PERFORMANCE

Spurious-Free Dynamic Range (SFDR) fC = 1 MHz, VO = 2 V p-p, RF = 24.9 Ω 90 dBc

f

C

Input Voltage Noise f = 100 kHz 4.3 nV/√Hz
Input Current Noise f = 100 kHz 1.6 pA/√Hz
Differential Gain Error NTSC, G = 2, R
Differential Phase Error NTSC, G = 2, R
Crosstalk, Output to Output G = 1, RL = 100 Ω, V

V

DC PERFORMANCE

Input Offset Voltage SELECT = three-state or open, PNP active 200 800 µV
SELECT = high NPN active 240 900 µV
Input Offset Voltage Drift T

Input Bias Current

1

VCM = 2.5 V, NPN active 4 6 µA

T

V
T
Input Offset Current ±0.1 ±0.9 µA
Open-Loop Gain VO = 1 V to 4 V 96 105 dB

INPUT CHARACTERISTICS

Input Impedance 6 MΩ
Input Capacitance 2 pF
Input Common-Mode Voltage Range −0.2 to +5.2 V
Common-Mode Rejection Ratio VCM = 0 V to 2.5 V 90 105 dB

SELECT PIN

Crossover Low, Selection Input Voltage Three-state < ±20 µA 1.7 to 5 V
Crossover High, Selection Input Voltage 1.1 to 1.7 V
Disable Input Voltage 0 to 1.1 V
Disable Switching Speed 50% of input to <10% of final V

Enable Switching Speed 50 ns

OUTPUT CHARACTERISTICS

Overdrive Recovery Time

VI = −1 V to +6 V, G = −1 50/50 ns

(Rising/Falling Edge)

Output Voltage Swing RL = 1 kΩ −VS + 0.08 +VS − 0.04,

Off Isolation VIN = 0.2 V p-p, f = 1 MHz, SELECT = low −49 dB
Short-Circuit Current Sinking and sourcing 105 mA
Capacitive Load Drive 30% overshoot 20 pF

POWER SUPPLY

Operating Range 2.7 12 V
Quiescent Current/Amplifier 6 8.5 mA

Quiescent Current (Disabled) SELECT = low 320 450 µA
Power Supply Rejection Ratio VS ± 1 V 90 105 dB

1

No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin.

= 0.2 V p-p 12 MHz

O

= 5 MHz, VO = 2 V p-p, RF = 24.9 Ω 64 dBc

= 150 Ω

L

= 150 Ω 0.2 Degrees

L

= 2 V p-p,

= ±5 V @ 1 MHz

S

to T

MIN

MAX

to T

MIN

MAX

= 2.5 V, PNP active −8 −11 µA

CM

to T

MIN

MAX

OUT

O

0.1 %

−92 dB

2 µV/°C

4 µA

−8 µA

1100 ns

+V

− 0.08 V

−V

+ 0.04

S

S

Rev. C | Page 4 of 24

AD8027/AD8028

VS = 3 V at TA = 25°C, RL = 1 kΩ to midsupply, unless otherwise noted.

Table 3.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth G = 1, VO = 0.2 V p-p 125 180 MHz

G = 1, VO = 2 V p-p 19 29 MHz

Bandwidth for 0.1 dB Flatness G = 2, VO = 0.2 V p-p 10 MHz
Slew Rate G = +1, VO = 2 V step/G = –1, VO = 2 V step 73/100 V/µs
Settling Time to 0.1% G = 2, VO = 2 V step 48 ns

NOISE/DISTORTION PERFORMANCE

Spurious-Free Dynamic Range (SFDR) fC = 1 MHz, VO = 2 V p-p, RF = 24.9 Ω 85 dBc

f

Input Voltage Noise f = 100 kHz 4.3 nV/√Hz
Input Current Noise f = 100 kHz 1.6 pA/√Hz
Differential Gain Error NTSC, G = 2, R
Differential Phase Error NTSC, G = 2, R
Crosstalk, Output to Output G = 1, RL = 100 Ω, V

DC PERFORMANCE

Input Offset Voltage SELECT = three-state or open, PNP active 200 800 µV
SELECT = high NPN active 240 900 µV
Input Offset Voltage Drift T
Input Bias Current

1

T
V
T

Input Offset Current ±0.1 ±0.9 µA
Open-Loop Gain VO = 1 V to 2 V 90 100 dB

INPUT CHARACTERISTICS

Input Impedance 6 MΩ
Input Capacitance 2 pF
Input Common-Mode Voltage Range RL = 1 kΩ –0.2 to +3.2 V

Common-Mode Rejection Ratio VCM = 0 V to 1.5 V 88 100 dB

SELECT PIN

Crossover Low, Selection Input Voltage Three-state < ±20 µA 1.7 to 3 V
Crossover High, Selection Input Voltage 1.1 to 1.7 V
Disable Input Voltage 0 to 1.1 V
Disable Switching Speed 50% of input to <10% of final V

Enable Switching Speed 50 ns

OUTPUT CHARACTERISTICS

Output Overdrive Recovery Time

(Rising/Falling Edge)

Output Voltage Swing RL = 1 kΩ –VS + 0.07 +VS – 0.03,

Short-Circuit Current Sinking and sourcing 72 mA
Off Isolation VIN = 0.2 V p-p, f = 1 MHz, SELECT = low –49 dB
Capacitive Load Drive 30% Overshoot 20 pF

POWER SUPPLY

Operating Range 2.7 12 V
Quiescent Current/Amplifier 6.0 8.0 mA
Quiescent Current (Disabled) SELECT = low 300 420 µA
Power Supply Rejection Ratio VS ± 1 V 88 100 dB

1

No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin.

= 5 MHz, VO = 2 V p-p, RF = 24.9 Ω 64 dBc

C

V

= 3 V @ 1 MHz

S

to T

MIN

MAX

= 150 Ω

L

= 150 Ω 0.20 Degrees

L

= 2 V p-p,

OUT

0.15 %

–89 dB

2 µV/°C

VCM = 1.5 V, NPN active 4 6 µA

to T

MIN

MAX

= 1.5 V, PNP active –8 –11 µA

CM

to T

MIN

MAX

O

= –1 V to +4 V, G = –1 55/55 ns

V

I

4 µA

–8 µA

1150 ns

+VS – 0.07 V

–V

+ 0.03

S

Rev. C | Page 5 of 24

AD8027/AD8028

(

)

(

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage 12.6 V
Power Dissipation See Figure 3
Common-Mode Input Voltage ±VS ± 0.5 V
Differential Input Voltage ±1.8 V
Storage Temperature –65°C to +125°C
Operating Temperature Range –40°C to +125°C
Lead Temperature Range

(Soldering 10 sec)

Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

MAXIMUM POWER DISSIPATION

The maximum safe power dissipation in the AD8027/AD8028
package is limited by the associated rise in junction temperature

) on the die. The plastic encapsulating the die locally reaches

(T

J

the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8027/AD8028.
Exceeding a junction temperature of 175°C for an extended
period of time can result in changes in the silicon devices,
potentially causing failure.

The still-air thermal properties of the package and PCB (θ
ambient temperature (T
package (P

) determine the junction temperature of the die.

D

The junction temperature can be calculated as

), and the total power dissipated in the

A

300°C

),

JA

The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent

/2 × I

S

) times the

S

, some of

OUT

OUT

power is the voltage between the supply pins (V
quiescent current (I

). Assuming the load (RL) is referenced to

S

midsupply, then the total drive power is V
which is dissipated in the package and some in the load (V

). The difference between the total drive power and the load

I

OUT

power is the drive power dissipated in the package.

= Quiescent Power + (Total D ri v e Po wer − Load Power)

P

D

⎛

V

()

D

⎜

IVP

SS

⎜

2

⎝

×+×=

⎞

V

OUTS

⎟
⎟

R

L

⎠

RMS output voltages should be considered. If R

2

V

OUT

–

R

L

is referenced

L

to VS−, as in single-supply operation, then the total drive power

× I

is V

.

S

OUT

If the rms signal levels are indeterminate, then consider the
worst case, when V

()

D

In single-supply operation with R

= VS/2.

is V

OUT

Airflow increases heat dissipation, effectively reducing θ

= VS/4 for RL to midsupply.

OUT

2

)

4/

V

S

+×=

IVP

SS

R

L

referenced to VS–, worst case

L

. Also,

JA

more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes reduces

. Care must be taken to minimize parasitic capacitances at

the θ

JA

the input leads of high speed op amps, as discussed in the PCB
Layout section.

×

θPTT ×+=

J

D

A

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada­tion or loss of functionality.

Rev. C | Page 6 of 24

AD8027/AD8028

Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the SOIC-8 (125°C/W),
SOT-23-6 (170°C/W), and MSOP-10 (130°C/W) packages on a
JEDEC standard 4-layer board.

Output Short Circuit

Shorting the output to ground or drawing excessive current
from the AD8027/AD8028 can likely cause catastrophic failure.

2.0

1.5

1.0

MSOP-10

0.5

MAXIMUM POWER DISSIPATION (W)

0

–55 –35 –15 5 25 45 65 85 105 125

SOT-23-6

SOIC-8

AMBIENT TEMPERATURE (°C)

03327-A-002

Figure 3. Maximum Power Dissipation vs. Ambient Temperature

Rev. C | Page 7 of 24

AD8027/AD8028

TYPICAL PERFORMANCE CHARACTERISTICS

Default conditions: VS = 5 V at TA = 25°C, RL = 1 kΩ, unless otherwise noted.

2

V

= 200mV p-p

OUT

1

0
–1
–2
–3
–4
–5
–6
–7
–8

NORMALIZED CLOSED-LOOP GAIN (dB)

–9

–10

0.1 1 10 100 1000

G = +10

G = –1

FREQUENCY (MHz)

Figure 4. Small Signal Frequency Response for Various Gains

2

G = +1

1

V

= 200mV p-p

OUT

0
–1
–2
–3
–4
–5
–6
–7

CLOSED- LOOP GAIN (dB)

–8
–9

–10

0.1 1 10 100 1000

VS = +3V RF = 24.9Ω

VS = +5V

FREQUENCY (MHz)

Figure 5. AD8027 Small Signal Frequency Response for Various Supplies

2

G = +1

1

V

= 2V p-p

OUT

0
–1
–2
–3
–4
–5
–6
–7

CLOSED-LOOP GAIN (dB)

–8
–9

–10

0.1 1 10 1000

VS = +3V

FREQUENCY (MHz)

VS = ±5V

VS = +5V

Figure 6. Large Signal Frequency Response for Various Supplies

100

AD8027
G = +1

G = +2

AD8028
G = +1

03327-A-003

VS = +3V

VS = ±5V

03327-A-004

03327-A-005

8

G = +2

7

V

= 200mV p-p

OUT

6
5
4
3
2
1
0

–1

CLOSED-LOOP GAIN (dB)

–2
–3
–4

0.1 1 10 100 1000

VS = +3V

VS = +5V

FREQUENCY (MHz)

VS = ±5V

03327-A-006

Figure 7. Small Signal Frequency Response for Various Supplies

2

G = +1

1

V

= 200mV p-p

OUT

0
–1
–2
–3
–4
–5
–6
–7

CLOSED-LOOP GAIN (dB)

–8
–9

–10

0.1 1 10 100 1000
FREQUENCY (MHz)

V

S

= +5V

VS = ±5V

= +3V

V

S

03327-A-007

Figure 8. AD8028 Small Signal Frequency Response for Various Supplies

8

G = +2

7

= 2V p-p

V

OUT

6
5
4
3
2
1
0

–1

CLOSED-LOOP GAIN (dB)

–2
–3
–4

0.1 1 10 100 1000

VS = +5V

VS = +3V

FREQUENCY (MHz)

VS = ±5V

03327-A-008

Figure 9. Large Signal Frequency Response for Various Supplies

Rev. C | Page 8 of 24

AD8027/AD8028

4

G = +1

3

V

= 200mV p-p

OUT

2
1

0
–1
–2
–3
–4
–5

CLOSED-LOOP GAIN (dB)

–6
–7
–8

0.1 1 10 100 1000
FREQUENCY (MHz)

C

L

Figure 10. AD8027 Small Signal Frequency Response for Various C

CL = 20pF

CL = 5pF

= 0pF

03327-A-009

LOAD

8

G = +2

7
6
5
4
3
2
1
0

–1

CLOSED-LOOP GAIN (dB)

–2
–3
–4

0.1 1 10 100 1000

V

= 2V p-p

OUT

V

OUT

FREQUENCY (MHz)

= 4V p-p

V

= 200mV p-p

OUT

03327-A-010

Figure 11. Frequency Response for Various Output Amplitudes

2

1

0

–1

–2

–3

–4

–5

CLOSED-LOOP GAIN (dB)

–6

G = +1

–7

V

= 200mV p-p

OUT

–8

0.1 1 10 100 1000
FREQUENCY (MHz)

–40°C

+125°C

+25°C

03327-A-011

Figure 12. AD8027 Small Signal Frequency Response vs. Temperature

3

G = +1

2

V

= 200mV p-p

OUT

1

0
–1
–2
–3
–4
–5
–6

CLOSED-LOOP GAIN (dB)

–7
–8
–9

–10

0.1 1 10 100 1000
FREQUENCY (MHz)

Figure 13. AD8028 Small Signal Frequency Response for Various C

CL = 20pF

CL = 0pF

C

= 5pF

L

03327-A-012

LOAD

8

G = +2

7
6
5
4
3
2
1
0

–1

CLOSED-LOOP GAIN (dB)

–2
–3
–4

0.1 1 10 100 1000

Figure 14. Small Signal Frequency Response for Various R

V

= 0.2V p-p

OUT

RL = 150

Ω

V

= 2.0V p-p

OUT

R

= 150

Ω

L

V

= 2.0V p-p

OUT

R

= 1k

Ω

L

FREQUENCY (MHz)

V

OUT

R

L

= 0.2V p-p

= 1k

Ω

LOAD

03327-A-013

Valu es

2

1

0

–1

–2

–3

–4

–5

CLOSED-LOOP GAIN (dB)

–6

–7

G = +1
V

= 200mV p-p

OUT

–8

0.1 1 10 100 1000
FREQUENCY (MHz)

–40°C

+125°C

+25°C

03327-A-014

Figure 15. AD8028 Small Signal Frequency Response vs. Temperature

Rev. C | Page 9 of 24

AD8027/AD8028

4

G = +1

3

V

= 200mV p-p

OUT

2
1

0
–1
–2
–3
–4
–5

CLOSED-LOOP GAI (dB)

–6
–7
–8

0.1 1 10 100 1000

Figure 16. Small Signal Frequency Response vs.

Input Common-Mode Voltages

R1

50Ω

V1

R2

VI

50Ω

–10
–20
–30
–40
–50
–60
–70
–80
–90

CROSSTALK (dB)

–100
–110
–120
–130
–140

0.001 0.01 0.1 1 10 100 1000

Figure 17. AD8028 Crosstalk Output to Output

110
100

GAIN

90
80
70
60
50
40
30

OPEN-LOOP GAIN (dB)

20
10

0

–10

10 100 1k 10k 100k 1M 10M 100M 1G

Figure 18. Open-Loop Gain and Phase vs. Frequency

V

= VS–+ 0.3V

ICM

SELECT = TRI

V

= VS+– 0.2V

ICM

SELECT = HIGH

V

= VS–+ 0.2V

ICM

SELECT = TRI

V

= 0V

ICM

SELECT = HIGH OR TRI

FREQUENCY (MHz)

U1

+

1/2

AD8028

–

CROSSTALK = 20log (V

B TO A

FREQUENCY (MHz)

FREQUENCY (Hz)

R3
1kΩ

PHASE

V

= VS+– 0.3V

ICM

SELECT = HIGH

U2

+

1/2

AD8028

–

OUT/VIN

A TO B

03327-A-017

03327-A-015

G = +1

= 5V

V

S

= 1kΩ

R

L

03327-A-016

100

10

VOLTAGE

VOLTAGE NOISE (nV/ Hz)

1

10 100 1k 10k 100k

CURRENT

1M 10M 100M 1G

FREQUENCY (Hz)

03327-A-018

100

10

CURRENT NOISE (pA/ Hz)

1

Figure 19. Voltage and Current Noise vs. Frequency

V

OUT

)

6.9
G = +2

= 150

Ω

R

6.8

L

6.7

6.6

6.5

6.4

6.3

6.2

CLOSED-LOOP GAIN (dB)

6.1

6.0

5.9

0.1 1 10 1000

V

= 200mV p-p

OUT

FREQUENCY (MHz)

100

V

OUT

= 2V p-p

03327-A-019

Figure 20. 0.1 dB Flatness Frequency Response

–20

G = +1
V

= 2V p-p

135

115

95

75

55

35

15

–5

–25

PHASE (Degrees)

Figure 21. Harmonic Distortion vs. Frequency and Supply Voltage

OUT

= 1k

Ω

R

L

–40

SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE

–60

VS = +3V

–80

= +5V

V

DISTORTION (dB)

–100

–120

–140

S

V

S

0.1 1 2010
FREQUENCY (MHz)

=±5V

03327-A-020

Rev. C | Page 10 of 24

AD8027/AD8028

–20

G = +1 (RF = 24.9Ω)
FREQUENCY = 100kHz
R

= 1kΩ

L

–40

–60

V

= +3V

S

–80

V

= +5V

S

VS = ±5V

–45

G = +1 (RF = 24.9Ω)
V

–55

–65

–75

–85

= 1.0V p-p @ 2MHz

OUT

SELECT = TRI

SELECT = HIGH

–100

DISTORTION (dB)

–120

–140

01234567891

SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE

OUTPUT VOLTAGE (V p-p)

03327-A-021

Figure 22. Harmonic Distortion vs. Output Amplitude

–50

G = +1 (RF = 24.9Ω)
V

= 1.0V p-p @ 100kHz

OUT

–60

= 1kΩ

R

L

–70

–80

–90

–100

–110

DISTORTION (dB)

–120

–130

SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE

–140

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
INPUT COMMON-MODE VOLTAGE (V)

VS = +3V

V

= +5V

S

03327-A-022

Figure 23. Harmonic Distortion vs. Input Common-Mode Voltage,

SELECT = High

–20

G = +1 (RF = 24.9Ω)
V

= 2.0V p-p

OUT

SECOND HARMONIC: SOLID LINE

–40

THIRD HARMONIC: DASHED LINE

RL = 1kΩ

0

–95

DISTORTION (dB)

–105

–115

–125

SELECT = TRI

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
INPUT COMMON-MODE VOLTAGE (V)

SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE

SELECT = HIGH

03327-A-024

Figure 25. Harmonic Distortion vs. Input Common-Mode Voltage, V

–50

G = +1 (RF = 24.9Ω)

= 1.0V p-p @ 100kHz

V

OUT

–60

–70

–80

–90

–100

–110

DISTORTION (dB)

–120

–130

–140

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
INPUT COMMON-MODE VOLTAGE (V)

VS = +3V

= +5V

V

S

SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE

03327-A-025

Figure 26. Harmonic Distortion vs. Input Common-Mode Voltage,

SELECT = Three-State or Open

–20

VS = +5

= 2.0V p-p

V

OUT

SECOND HARMONIC: SOLID LINE

–40

THIRD HARMONIC: DASHED LINE

G = +2

= 5 V

S

–60

–80

RL = 150Ω

–100

DISTORTION (dB)

–120

–140

0.1 1 10 20
FREQUENCY (MHz)

Figure 24. Harmonic Distortion vs. Frequency and Load

03327-A-023

Rev. C | Page 11 of 24

–60

–80

–100

DISTORTION (dB)

–120

–140

0.1 1 10 20

G = +10

FREQUENCY (MHz)

Figure 27. Harmonic Distortion vs. Frequency and Gain

G = +1

03327-A-026

AD8027/AD8028

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

0.20
G = +1

= ± 2.5V

V

S

0.15

0.10

0.20

0.15

0.10

G = +1
V

= ±2.5V

S

C

L

= 20pF

= 5pF

C

L

0.05

0

0.05

0.10

0.15

0.20

Figure 28. Small Signal Transient Response

2.0

1.0

1.0

2.0

G = +1

= ±2.5V

V

S

0

V

V

OUT

OUT

= 4V p-p

= 2V p-p

Figure 29. Large Signal Transient Response, G = +1

2.5

2.0

1.5

1.0

0.5

0.5

1.0

1.5

2.0

2.5

0

G = +2
V

= ±2.5V

S

V

V

OUT

OUT

= 4V p-p

= 2V p-p

Figure 30. Large Signal Transient Response, G = +2

100ns/DIV500mV/DIV

20ns/DIV50mV/DIV

03327-A-027

03327-A-028

20ns/DIV50mV/DIV

03327-A-029

0.05

0

0.05

0.10

0.15

0.20

20ns/DIV50mV/DIV

03327-A-030

Figure 31. Small Signal Transient Response with Capacitive Load

4.0
G = –1

3.5
R

= 1kΩ

L

3.0

= ±2.5V

V

S

2.5

2.0

1.5

1.0

0.5

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

50ns/DIV500mV/DIV

03327-A-031

Figure 32. Output Overdrive Recovery

4.0
G = +1

3.5

= 1k

Ω

R

L

3.0

VS =±2.5V

2.5

2.0

1.5

1.0

0.5

0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0

50ns/DIV500mV/DIV

03327-A-032

Figure 33. Input Overdrive Recovery

Rev. C | Page 12 of 24

AD8027/AD8028

–10

G = +2

VIN (200mV/DIV)

V

– 2VIN (2mV/DIV)

OUT

Figure 34. Long-Term Settling Time

VIN (200mV/DIV)

5µs/DIV

03327-A-033

+0.1%

–0.1%

–8

= +5V

SELECT = TRI

= ±5V

V

S

03327-A-036

–6

–4

–2

0

2

4

INPUT BIAS CURRENT (µA)

6

SELECT = HIGH

8

10

01234567891

V

S

VS= +3V

INPUT COMMON-MODE VOLTAGE (V)

Figure 37. Input Bias Current vs. Input Common-Mode Voltage

250

COUNT = 1780

200

SELECT
MEAN
STD. DEV

HIGH
49µV
193µV

TRI
55µV
150µV

SELECT = TRI

0

V

(400mV/DIV)

OUT

V

– 2VIN (0.1%/DIV)

OUT

20ns/DIV

03327-A-034

Figure 35. 0.1% Short-Term Settling Time

4.5

4.0

3.5

= ±5V

V

S

3.0

INPUT BIAS CURRENT (SELECT = HIGH) (µA)

2.5
–40 –25 –10 5 20 35 50 65 80 11095 125

SELECT = HIGH

V

= +3V

S

SELECT = TRI

TEMPERATURE (°C)

V

= +5V

S

Figure 36. Input Bias Current vs. Temperature

03327-A-035

+0.1%

–0.1%

–6.5

–7.0

–7.5

–8.0

–8.5

150

100

FREQUENCY

50

0

–800 –600 –400 –200 0 200 400 600 800

INPUT OFFSET VOLTAGE (µV)

SELECT = HIGH

03327-A-037

Figure 38. Input Offset Voltage Distribution

360
340
320
300

V)

280

µ

260
240
220
200
180
160
140
120

INPUT OFFSET VOLTAGE (

100

INPUT BIAS CURRENT (SELECT = TRI) (µA)

80
60

–40 –25 –10 5 20 35 50 65 80 11095 125

SELECT = TRI

VS =±5V

SELECT = HIGH

V

= +5V

S

TEMPERATURE (°C)

V

= +3V

S

03327-A-038

Figure 39. Input Offset Voltage vs. Temperature

Rev. C | Page 13 of 24

AD8027/AD8028

290

270

250

230

210

190

INPUT OFFSET VOLTAGE (µV)

170

SELECT = HIGH

SELECT = TRI

VS= ±5V

120

100

80

60

CMRR (dB)

40

20

150

–5–4–3–2–1012345

INPUT COMMON-MODE VOLTAGE (V)

03327-A-039

Figure 40. Input Offset Voltage vs. Input Common-Mode Voltage, V

290

VS= +5V

270

V)

µ

250

230

210

190

INPUT OFFSET VOLTAGE (

170

150

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

INPUT COMMON-MODE VOLTAGE (V)

SELECT = HIGH

SELECT = TRI

03327-A-040

Figure 41. Input Offset Voltage vs. Input Common-Mode Voltage, V

270

VS= +3V

250

SELECT = HIGH

230

= ±5

S

= 5

S

0

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 43. CMRR vs. Fre quency

0
–10
–20
–30
–40
–50
–60

PSSR (dB)

–70
–80
–90

–100
–110

100 1k 10k 100k 1M 10M 100M 1G

–PSRR

+PSRR

FREQUENCY (Hz)

Figure 44. PSRR v s. Frequency

–20

VIN = 0.2V p-p
G = +1

–30

SELECT = LOW

–40

–50

03327-A-042

03327-A-043

210

190

INPUT OFFSET VOLTAGE (µV)

170

150

0 0.50 1.00 1.50 2.00 2.50 3.00

INPUT COMMON-MODE VOLTAGE (V)

SELECT = TRI

03327-A-041

Figure 42. Input Offset Voltage vs. Input Common-Mode Voltage, V

= 3

S

Rev. C | Page 14 of 24

–60

–70

OFF ISOLATION (dB)

–80

–90

–100

10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

Figure 45. Off Isolation vs. Frequency

03327-A-044

AD8027/AD8028

200

150

100

50

VS = +3V VS = +5V VS = ±5V

0

–50

–100

–150

OUTPUT SATURATION VOLTAGE (mV)

–200

100 1000 10000

LOAD RESISTANCE (Ω)

LOAD RESISTANCE TIED
TO MIDSUPPLY

VOL– V

S–

VOH– V

S+

Figure 46. Output Saturation Voltage vs. Output Load

100

03327-A-045

130

120

110

100

90

80

OPEN-LOOP GAIN (dB)

70

60

0 10203040506

+3V

I

LOAD

±5V

+5V

(mA)

03327-A-048

Figure 49. Open-Loop Gain vs. Load Current

1M

SELECT = LOW

0

10

1

0.1

OUTPUT IMPEDANCE (Ω)

0.01

0.001

G = +2

1k 10k 100k 1M 10M 100M 1G

G = +5

G = +1

FREQUENCY (Hz)

Figure 47. Output Enabled— Impedance vs. Frequency

45

VS = +5V

= 1kΩ TIED TO MIDSUPPLY

R

L

40

– V

V

OL

35

30

S–

VS+– V

03327-A-046

OH

100k

10k

1k

OUTPUT IMPEDANCE (Ω)

100

10

100k 1M 10M 100M 1G

FREQUENCY (Hz)

03327-A-049

Figure 50. Output Disabled—Impedance vs. Frequency

80

VS = +5V

60

40

A)

µ

20

0

–20

SELECT CURRENT (

–40

= +10V

V

S

@ +25°C

+125°C

+25°C

–40°C

OUTPUT SATURATION VOLTAGE (mV)

25

–40 –25 –10 5 20 35 50 65 80 11095 125

TEMPERATURE (°C)

Figure 48. Output Saturation Voltage vs. Temperature

03327-A-047

Rev. C | Page 15 of 24

–60

–80

0 0.5 1.0 1.5 2.0 2.5 3.0

SELECT VOLTAGE (V)

Figure 51. SELECT Pin Current vs.

SELECT Pin Voltage and Temperature

03327-A-050

AD8027/AD8028

1.5

1.0

0.5

= 100Ω

R

0

–0.5

OUTPUT VOLTAGE (V)

–1.0

–1.5

1.5

1.0

L

RL = 1kΩ

= 10kΩ

R

L

0 50 100 150 200 250

Figure 52. Enable Turn-On Timing

SELECT PIN (–2.0V TO –0.5V)

OUTPUT

SELECT PIN (–2.0V TO –0.5V)

OUTPUT

G = –1
V
V

TIME (ns)

= ±2.5V

S

= –1.0V

IN

03327-A-051

9.0

8.5

8.0

7.5

7.0

6.5

6.0

5.5

SUPPLY CURRENT (mA)

5.0

4.5

4.0

–40 –25 –10 5 20 35 50 65 80 11095 125

= ±5V

V

S

VS = +3V

TEMPERATURE (°C)

V

= +5V

S

03327-A-053

Figure 54. Quiescent Supply Current vs. Supply Voltage and Temperature

0.5

–0.5

OUTPUT VOLTAGE (V)

–1.0

–1.5

RL = 100

RL = 1k

RL = 10k

Ω

Ω

Ω

0

03327-A-052

0

G = –1
V

=±2.5V

S

V

= –1.0V

IN

0.51234567891
TIME (µs)

Figure 53. Disable Turn-Off Timing

Rev. C | Page 16 of 24

AD8027/AD8028

V

THEORY OF OPERATION

The AD8027/AD8028 are rail-to-rail input/output amplifiers
designed in the Analog Devices XFCB process. The XFCB
process enables the AD8027/AD8028 to run on 2.7 V to 12 V
supplies with 190 MHz of bandwidth and over 100 V/µs of slew
rate. The AD8027/AD8028 have 4.3 nV/√Hz of wideband noise
with 17 nV/√Hz noise at 10 Hz. This noise performance, with
an offset and drift performance of less than 900 µV maximum
and 1.5 µV/°C typical, respectively, makes the AD8027/AD8028
ideal for high speed, precision applications. Additionally, the
input stage operates 200 mV beyond the supply rails and shows
no phase reversal. The amplifiers feature overvoltage protection
on the input stage. Once the inputs exceed the supply rails by

0.7 V, ESD protection diodes are turned on, drawing excessive
current through the differential input pins. A series input
resistor should be included to limit the input current to less
than 10 mA.

INPUT STAGE

The rail-to-rail input performance is achieved by operating
complementary input pairs. Which pair is on is determined by
the common-mode level of the differential input signal. As
shown in Figure 55, a tail current (I
sources the PNP differential input structure consisting of Q1
and Q2. A reference voltage is generated internally that is
connected to the base of Q5. This voltage is continually com­pared against the common-mode input voltage. When the
common-mode level exceeds the internal reference voltage,
Q5 diverts the tail current (I

TAI L

current mirror that sources the NPN input pair consisting of
Q3 and Q4.

) is generated that

TAI L

) from the PNP input pair to a

VCC

+

1.2V

–

The NPN input pair can now operate at 200 mV above the
positive rail. Both input pairs are protected from differential
input signals above 1.4 V by four diodes across the input (see
Figure 55). In the event of differential input signals that exceed

1.4 V, the diodes conduct and excessive current flows through
them. A series input resistor should be included to limit the
input current to 10 mA.

CROSSOVER SELECTION

The AD8027/AD8028 have a feature called crossover selection,
which allows the user to choose the crossover point between the
PNP/NPN differential pairs. Although the crossover region is
small, operating in this region should be avoided, because it can
introduce offset and distortion to the output signal. To help
avoid operating in the crossover region, the AD8027/AD8028
allow the user to select from two preset crossover locations
(voltage levels) using the SELECT pin. As shown in Figure 55,
the crossover region is about 200 mV and is defined by the
voltage level at the base of Q5. Internally, two separate voltage
sources are created approximately 1.2 V from either rail. One or
the other is connected to Q5, based on the voltage applied to the
SELECT pin. This allows either dominant PNP pair operation,
when the SELECT pin is left open, or dominant NPN pair
operation, when the SELECT pin is pulled high.

The SELECT pin also provides the traditional power-down
function when it is pulled low. This allows the designer to
achieve the best precision and ac performance for high-side and
low-side signal applications. See Figure 50 through Figure 53 for
SELECT pin characteristics.

I

TAIL

03327-A-054

VOUTP

VOUTN

SEL

LOGIC

VEE

Q5 Q3 Q1

VP

+

1.2V

–

Q2 Q4

Figure 55. Simplified Input Stage

VN

I

CMFB

I

CMFB

VEE

VCC

Rev. C | Page 17 of 24

AD8027/AD8028

(

In the event that the crossover region cannot be avoided,
specific attention has been given to the input stage to ensure
constant transconductance and minimal offset in all regions of
operation. The regions are PNP input pair running, NPN input
pair running, and both running at the same time (in the
200 mV crossover region). Maintaining constant transconduc­tance in all regions ensures the best wideband distortion
performance when going between these regions. With this
technique, the AD8027/AD8028 can achieve greater than 80 dB
SFDR for a 2 V p-p, 1 MHz, and G = 1 signal on ±1.5 V supplies.
Another requirement needed to achieve this level of distortion
is that the offset of each pair must be laser trimmed to achieve
greater than 80 dB SFDR, even for low frequency signals.

OUTPUT STAGE

The AD8027/AD8028 use a common-emitter output structure
to achieve rail-to-rail output capability. The output stage is
designed to drive 50 mA of linear output current, 40 mA within
200 mV of the rail, and 2.5 mA within 35 mV of the rail.
Loading of the output stage, including any possible feedback
network, lowers the open-loop gain of the amplifier. Refer to
Figure 49 for the loading behavior. Capacitive load can degrade
the phase margin of the amplifier. The AD8027/AD8028 can
drive up to 20 pF, G = 1, as shown in Figure 10. A small (25 Ω to
50 Ω) series resistor, R
load is to exceed 20 pF for a gain of 1. Increasing the closed­loop gain increases the amount of capacitive load that can be
driven before a series resistor needs to be included.

DC ERRORS

The AD8027/AD8028 use two complementary input stages to
achieve rail-to-rail input performance, as mentioned in the
Input Stage section. To use the dc performance over the entire
common-mode range, the input bias current and input offset
voltage of each pair must be considered.

Referring to Figure 56, the output offset voltage of each pair is
calculated by

,,

OUTPNPOS

OUTNPNOS

,,

where the difference of the two is the discontinuity experienced
when going through the crossover region.

, should be included, if the capacitive

SNUB

⎛

=

VV

=

VV

⎜

,

PNPOS

⎜
⎝

⎛
⎜

NPNOS

,

⎜
⎝

⎞

+

RR

F

G

⎟

,

⎟

R

G

⎠

⎞

+

RR

F

G

⎟
⎟

R

G

⎠

The size of the discontinuity is defined as

⎛
⎜

VVV

)

×−=

NPNOS,PNPOS,DIS

⎜
⎝

⎞

RR

+

F

G

⎟
⎟

R

G

⎠

Using the crossover select feature of the AD8027/AD8028 helps
to avoid this region. In the event that the region cannot be
avoided, the quantity (V

OS, PNP

– V

) is trimmed to minimize

OS, NPN

this effect.

Because the input pairs are complementary, the input bias cur­rent reverses polarity when going through the crossover region
shown in Figure 37. The offset between pairs is described by

⎡

⎛

()

NPNOS,PNPOS,

is the input bias current of either input when the PNP

I

B, PNP

input pair is active, and I

B, NPN

NPNB,PNPB,

is the input bias current of either
input pair when the NPN pair is active. If R
when multiplied by the gain factor it equals R

⎜

×−=−

RIIVV

⎢

S

⎜

⎢

⎝

⎣

is sized so that

S

, this effect is

F

+

RR

G

R

G

⎤

⎞

F

⎟

R

−

⎥

F

⎟

⎥

⎠

⎦

eliminated. It is strongly recommended to balance the imped­ances in this manner when traveling through the crossover
region to minimize the dc error and distortion. As an example,
assuming that the PNP input pair has an input bias current of
6 µA and the NPN input pair has an input bias current of

−2 µA, a 200 µV shift in offset occurs when traveling through
the crossover region with R

equal to 0 Ω and RS equal to 25 Ω.

F

In addition to the input bias current shift between pairs, each
input pair has an input bias current offset that contributes to the
total offset in the following manner:

OS

⎛

=∆

⎜

RIV

B

S

⎜
⎝

V

R

OS

+–

G

V

I

R

+–

S

Figure 56. Op Amp DC Error Sources

⎞

+

RR

F

G

⎟

−

⎟

R

G

⎠

R

F

IB–

IB+

RI

FB

−+

+V

–

AD8027/
AD8028

+

–V

V

OUT

+–

SELECT

03327-A-055

Rev. C | Page 18 of 24

AD8027/AD8028

WIDEBAND OPERATION

C

R

+V

–V

R

F

F

C1

0.1µF

C2

10µF

C3

10µF

C4

0.1µF

= 49.9Ω

F

SELECT

V

OUT

03327-A-057

F

03327-A-058

Voltage feedback amplifiers can use a wide range of resistor
values to set their gain. Proper design of the application’s
feedback network requires consideration of the following issues:

• Poles formed by the amplifier’s input capacitances with the

resistances seen at the amplifier’s input terminals

• Effects of mismatched source impedances

• Resistor value impact on the application’s voltage noise

• Amplifier loading effects

The AD8027/AD8028 have an input capacitance of 2 pF. This
input capacitance forms a pole with the amplifier’s feedback
network, destabilizing the loop. For this reason, it is generally
desirable to keep the source resistances below 500 Ω, unless
some capacitance is included in the feedback network. Likewise,
keeping the source resistances low also takes advantage of the
AD8027/AD8028’s low input referred voltage noise of

4.3 nV/√Hz.

With a wide bandwidth of over 190 MHz, the AD8027/AD8028
have numerous applications and configurations. The AD8027/
AD8028 part shown in Figure 57 is configured as a noninvert­ing amplifier. An easy selection table of gain, resistor values,
bandwidth, slew rate, and noise performance is presented in
Table 5, and the inverting configuration is shown in Figure 58.

R

F

C1

+V

0.1µF

C2

10µF

V

OUT

SELECT

C3

10µF

C4

0.1µF

–V

03327-A-056

V

IN

R

G

R1

R1 = RF||R

–

AD8027/

AD8028

+

G

Figure 57. Wideband Noninverting Gain Configuration

Table 5. Component Values, Bandwidth, and Noise
Performance (V

= ±2.5 V)

S

Output
Noise with
Resistors

Hz

)

(nV/√

Noise Gain
(Noninverting)

R

SOURCE

(Ω)

R

F

(Ω)

R

G

(Ω)

–3 dB
SS BW
(MHz)

1 50 0 N/A 190 4.4
2 50 499 499 95 10
10 50 499 54.9 13 45

R

G

V

IN

R1 = RF||R

C5

G

–

AD8027/

AD8028

+

R1

Figure 58. Wideband Inverting Gain Configuration

CIRCUIT CONSIDERATIONS

Balanced Input Impedances

Balanced input impedances can help to improve distortion
performance. When the amplifier transitions from PNP pair to
NPN pair operation, a change in both the magnitude and
direction of the input bias current occurs. When multiplied
times imbalanced input impedances, a change in offset can
result. The key to minimizing this distortion is to keep the input
impedances balanced on both inputs. Figure 59 shows the effect
of the imbalance and degradation in distortion performance for
a 50 Ω source impedance, with and without a 50 Ω balanced
feedback path.

–20

G = +1
V

= 2V p-p

OUT

–30

R

= 1kΩ

L

V

= +3V

S

–40

–50

–60

R

= 0Ω

F

–70

DISTORTION (dB)

–80

–90

–100

0.1 1 10 20

RF = 24.9Ω

FREQUENCY (MHz)

Figure 59. SFDR v s. Frequency and Vari ous R

Rev. C | Page 19 of 24

AD8027/AD8028

PCB Layout

As with all high speed op amps, achieving optimum perform­ance from the AD8027/AD8028 requires careful attention to
PCB layout. Particular care must be exercised to minimize lead
lengths of the bypass capacitors. Excess lead inductance can
influence the frequency response and even cause high
frequency oscillations. The use of a multilayer board with an
internal ground plane can reduce ground noise and enable a
tighter layout.

To achieve the shortest possible lead length at the inverting
input, the feedback resistor, R
board and span the distance from the output, Pin 6, to the input,
Pin 2. The return node of the resistor, R
closely as possible to the return node of the negative supply
bypass capacitor connected to Pin 4.

On multilayer boards, all layers underneath the op amp should
be cleared of metal to avoid creating parasitic capacitive
elements. This is especially true at the summing junction
(the −input). Extra capacitance at the summing junction can
cause increased peaking in the frequency response and lower
phase margin.

Grounding

To minimize parasitic inductances and ground loops in high
speed, densely populated boards, a ground plane layer is critical.
Understanding where the current flows in a circuit is critical in
the implementation of high speed circuit design. The length of
the current path is directly proportional to the magnitude of the
parasitic inductances and, therefore, the high frequency
impedance of the path. Fast current changes in an inductive
ground return can create unwanted noise and ringing.

should be located beneath the

F,

, should be situated as

G

The length of the high frequency bypass capacitor pads and
traces is critical. A parasitic inductance in the bypass grounding
works against the low impedance created by the bypass
capacitor. Because load currents flow from supplies as well as
ground, the load should be placed at the same physical location
as the bypass capacitor ground. For large values of capacitors,
which are intended to be effective at lower frequencies, the
current return path length is less critical.

Power-Supply Bypassing

Power-supply pins are actually inputs, and care must be taken to
provide a clean, low noise, dc voltage source to these inputs. The
bypass capacitors have two functions:

• Provide a low impedance path for unwanted frequencies

from the supply inputs to ground, thereby reducing the
effect of noise on the supply lines.

• Provide sufficient localized charge storage, for fast switching

conditions and minimizing the voltage drop at the supply
pins and the output of the amplifier. This is usually accom­plished with larger electrolytic capacitors.

Decoupling methods are designed to minimize the bypassing
impedance at all frequencies. This can be accomplished with a
combination of capacitors in parallel to ground.

Good-quality ceramic chip capacitors should be used and
always kept as close as possible to the amplifier package . A
parallel combination of a 0.01 µF ceramic and a 10 µF electro­lytic covers a wide range of rejection for unwanted noise. The
10 µF capacitor is less critical for high frequency bypassing, and,
in most cases, one per supply line is sufficient.

Rev. C | Page 20 of 24

AD8027/AD8028

APPLICATIONS

USING THE SELECT PIN

The AD8027/AD8028’s unique SELECT pin has two functions:

• The power-down function places the AD8027/AD8028 into

low power consumption mode. In power-down mode, the
amplifiers draw 450 µA (typical) of supply current.

• The second function, as mentioned in the Theory of

Operation section, shifts the crossover point (where the
NPN/PNP input differential pairs transition from one to the
other) closer to either the positive supply rail or the negative
supply rail. This selectable crossover point allows the user to
minimize distortion based on the input signal and environ­ment. The default state is 1.2 V from the positive power
supply, with the SELECT pin left floating or in three-state.

Table 6 lists the SELECT pin’s required voltages and modes.

Table 6. SELECT Pin Mode Control

SELECT Pin Voltage (V)

Mode

V

= ±5 V VS = +5 V VS = +3 V

S

Disable −5 to −4.2 0 to 0.8 0 to 0.8
Crossover Referenced

–1.2 V to Positive

−4.2 to

−3.3

0.8 to 1.7 0.8 to 1.7

Supply
Crossover Referenced

−3.3 to +5 1.7 to 5.0 1.7 to 3.0
+1.2 V to Negative
Supply

When the input stage transitions from one input differential
pair to the other, there is virtually no noticeable change in the
output waveform.

The disable time of the AD8027/AD8028 amplifiers is load­dependent. Typical data is presented in Table 7. See Figure 52
and Figure 53 for the actual switching measurements.

Table 7.

DISABLE

Switching Speeds

Supply Voltages (RL = 1 kΩ)

Time

t

ON

t

OFF

±5 V +5 V +3 V

45 ns 50 ns 50 ns
980 ns 1100 ns 1150 ns

DRIVING A 16-BIT ADC

With the adjustable crossover distortion selection point and low
noise, the AD8028 is an ideal amplifier for driving or buffering
input signals into high resolution ADCs such as the AD7767, a
16-bit, 1 LSB INL, 1 MSPS differential ADC. Figure 60 shows
the typical schematic for driving the ADC. The AD8028 driving
the AD7677 offers performance close to non-rail-to-rail
amplifiers and avoids the need for an additional supply other
than the single 5 V supply already used by the ADC.

In this application, the SELECT pins are biased to avoid the
crossover region of the AD8028 for low distortion operation.

Summary test data for the schematic shown in Figure 60 is
listed in Table 8.

+5V

0.1µF

ANALOG INPUT +

INPUT RANGE

(0.15V TO 2.65V)

ANALOG INPUT –

–

AD8028

+

SELECT

(OPEN)

+5V

–

AD8028

+

SELECT

(OPEN)

Figure 60. Unity Gain Differential Drive

0.1µF

15Ω

2.7nF

15Ω

4MHz LPF

2.7nF

+5V

AD7677

4MHz LPF

16 BITS

03327-A-059

Table 8. ADC Driver Performance, fC = 100 kHz,

= 4.7 V p-p

V

OUT

Parameter Measurement

Second Harmonic Distortion –105 dB
Third Harmonic Distortion –102 dB
THD –102 dB
SFDR +105 dBc

As shown in Figure 61, the AD8028 and AD7677 combination
offers excellent integral nonlinearity (INL).

1.0

0.5

0

INL (LSB)

–0.5

–1.0

0 16384 32768 49152 65536

Figure 61. Integral Nonlinearity

CODE

03327-A-060

Rev. C | Page 21 of 24

AD8027/AD8028

V

BAND-PASS FILTER

In communication systems, active filters are used extensively in
signal processing. The AD8027/AD8028 are excellent choices
for active filter applications. In realizing this filter, it is impor­tant that the amplifier have a large signal bandwidth of at least
10× the center frequency, f
in the amplifier, causing instability and oscillations.

In Figure 62, the AD8027/AD8028 part is configured as a
1 MHz band-pass filter. The target specifications are f
and a −3 dB pass band of 500 kHz. To start the design, select f
Q, C1, and R4. Then use the following equations to calculate the
remaining variables:

Q

k = 2πf

O

PassBand

C1

(MHz)

f

O

=

C2 = 0.5C1

R1 = 2/k, R2 = 2/(3k), R3 = 4/k

H = 1/3(6.5 – 1/Q)

R5 = R4/(H – 1)

R2

105

Ω

R1

316

IN

1000pF

Ω

500pF

. Otherwise, a phase shift can occur

O

(MHz)

+5

C3

0.1

µ

C1

+

C2

634

AD8027/

R3

AD8028

Ω

–

F

SELECT

= 1 MHz

O

V

OUT

O

The test data shown in Figure 63 indicates that this design
yields a filter response with a center frequency of f

= 1 MHz,

O

and a bandwidth of 450 kHz.

CH1 S21 LOG 5dB/REF 6.342dB 1:6.3348dB 1.00 000MHz

1

,

0.1

Figure 63. Band-Pass Filter Response

1

FREQUENCY – MHz

03327-A-062

10

DESIGN TOOLS AND TECHNICAL SUPPORT

Analog Devices, Inc. (ADI) is committed to simplifying the
design process by providing technical support and online
design tools. ADI offers technical support via free evaluation
boards, sample ICs, interactive evaluation tools, data sheets,
spice models, application notes, and phone and email support
available at

www. analog.com.

C4

–5

0.1

µ

F

523

R5

Ω

523

R4

Ω

03327-A-061

Figure 62. Band-Pass Filter Schematic

Rev. C | Page 22 of 24

AD8027/AD8028

Y

N

0

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

85

6.20 (0.2440)

5.80 (0.2284)

41

1.27 (0.0500)
BSC

0.25 (0.0098)

0.10 (0.0040)

COPLANARIT

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIG

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

Figure 64. 8-Lead Standard Small Outline Package [SOIC]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

2.90 BSC

1.90
BSC

0.50

0.30

4 5

2.80 BSC

2

0.95 BSC

1.45 MAX

SEATING
PLANE

0.22

0.08
10°

0.60

4°

0.45

0°

0.30

1.60 BSC

1.30

1.15

0.90

.15 MAX

6

13

PIN 1

× 45°

COMPLIANT TO JEDEC STANDARDS MO-178AB

Figure 65. 6-Lead Small Outline Transistor Package [SOT-23]

(RT-6)

Dimensions shown in millimeters

3.00 BSC

6

10

5

4.90 BSC

1.10 MAX

SEATING
PLANE

0.23

0.08

8°
0°

-

3.00 BSC

PIN 1

0.95

0.85

0.75

0.15

0.00

1

0.50 BSC

0.27

0.17

COPLANARITY

0.10

Figure 66. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

Rev. C | Page 23 of 24

0.80

0.60

0.40

AD8027/AD8028

ORDERING GUIDE

Minimum

Model

AD8027AR 1 –40°C to +125°C 8-Lead SOIC R-8
AD8027AR-REEL 2,500 –40°C to +125°C 8-Lead SOIC R-8
AD8027AR-REEL7 1,000 –40°C to +125°C 8-Lead SOIC R-8
AD8027ARZ

1

AD8027ARZ-REEL1 2,500 –40°C to +125°C 8-Lead SOIC R-8
AD8027ARZ-REEL71 1,000 –40°C to +125°C 8-Lead SOIC R-8
AD8027ART-R2 250 –40°C to +125°C 6-Lead SOT-23 RT-6 H4B
AD8027ART-REEL 10,000 –40°C to +125°C 6-Lead SOT-23 RT-6 H4B
AD8027ART-REEL7 3,000 –40°C to +125°C 6-Lead SOT-23 RT-6 H4B
AD8027ARTZ-R21 250 –40°C to +125°C 6-Lead SOT-23 RT-6 H4B#
AD8027ARTZ-REEL1 10,000 –40°C to +125°C 6-Lead SOT-23 RT-6 H4B#
AD8027ARTZ-REEL71 3,000 –40°C to +125°C 6-Lead SOT-23 RT-6 H4B#
AD8028AR 1 –40°C to +125°C 8-Lead SOIC R-8
AD8028AR-REEL 2,500 –40°C to +125°C 8-Lead SOIC R-8
AD8028AR-REEL7 1,000 –40°C to +125°C 8-Lead SOIC R-8
AD8028ARZ1 1 –40°C to +125°C 8-Lead SOIC R-8
AD8028ARZ-REEL1 2,500 –40°C to +125°C 8-Lead SOIC R-8
AD8028ARZ-REEL71 1,000 –40°C to +125°C 8-Lead SOIC R-8
AD8028ARM 1 –40°C to +125°C 10-Lead MSOP RM-10 H5B
AD8028ARM-REEL 3,000 –40°C to +125°C 10-Lead MSOP RM-10 H5B
AD8028ARM-REEL7 1,000 –40°C to +125°C 10-Lead MSOP RM-10 H5B
AD8028ARMZ1 1 –40°C to +125°C 10-Lead MSOP RM-10 H5B#
AD8028ARMZ-REEL1 3,000 –40°C to +125°C 10-Lead MSOP RM-10 H5B#
AD8028ARMZ-REEL71 1,000 –40°C to +125°C 10-Lead MSOP RM-10 H5B#

1

Z = Pb-free part, # denotes lead-free, may be top or bottom marked.

Ordering Quantity Temperature Range Package Description Package Option Branding

1 –40°C to +125°C 8-Lead SOIC R-8

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C03327–0–3/05(C)

Rev. C | Page 24 of 24