Datasheet AD8023AR-REEL7, AD8023AR-REEL, AD8023AR, AD8023ACHIPS Datasheet (Analog Devices)

REV. A

a

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

High Current Output,

Triple Video Amplifier

FEATURES
Drives 13 V Output
Drives Unlimited Capacitive Load
High Current Output Drive: 70 mA
Excellent Video Specifications (R

L

= 150 )

Gain Flatness 0.1 dB to 10 MHz

0.06% Differential Gain Error

0.02 Differential Phase Error

Power

Operates on 2.5 V to 7.5 V Supply

10.0 mA/Amplifier Max Power Supply Current

High Speed

250 MHz Unity Gain Bandwidth (3 dB)
1200 V/s Slew Rate
Fast Settling Time of 35 ns (0.1%)

High Speed Disable Function

Turn-Off Time 30 ns

Easy to Use

200 mA Short Circuit Current
Output Swing to 1 V of Rails

APPLICATIONS
LCD Displays
Video Line Driver
Broadcast and Professional Video
Computer Video Plug-In Boards
Consumer Video
RGB Amplifier in Component Systems

AD8023

PRODUCT DESCRIPTION

The AD8023 is a high current output drive, high voltage output
drive, triple video amplifier. Each amplifier has 70 mA of output
current and is optimized for driving large capacitive loads. The
amplifiers are current feedback amplifiers and feature gain
flatness of 0.1 dB to 10 MHz while offering differential gain and
phase error of 0.06% and 0.02°.

The AD8023 uses maximum supply current of 10.0 mA per
amplifier and runs on ±2.5 V to ±7.5 V power supply. The
outputs of each amplifier swing to within one volt of either
supply rail to easily accommodate video signals. The AD8023
is unique among current feedback op amps by virtue of its large
capacitive load drive with a small series resistor, while still
achieving rapid settling time. For instance, it can settle to 0.1% in
35 ns while driving 300 pF capacitance.

The bandwidth of 250 MHz along with a 1200 V/µs slew rate
make the AD8023 useful in high speed applications requiring
a single +5 V or dual power supplies up to ±7.5 V. Further­more, the AD8023 contains a high speed disable function for
each amplifier in order to power down the amplifier or high
impedance the output. This can then be used in video multi­plexing applications. The AD8023 is available in the indus­trial temperature range of –40°C to +85°C.

PIN CONFIGURATION

14-Lead SOIC

14

13

12

11

10

9

8

1

2

3

4

7

6

5

DISABLE 1

–V

S

+IN 2

–IN 2

OUT 2

DISABLE 2

DISABLE 3

+V

S

AD8023

OUT 3

–IN 3

+IN 3

+IN 1

–IN 1

OUT 1

V

IN

Figure 1. Pulse Response Driving a Large Load Capacitor,
C

L

= 300 pF, G = +3, RF = 750 Ω, RS = 16.9 Ω, RL = 10 k

Ω

Figure 2. Output Swing Voltage,

R

L

= 150Ω; VS = ±7.5 V, G = +10

V

IN

V

O

V

O

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD8023–SPECIFICATIONS

Model AD8023A

Conditions V

S

Min Typ Max Units

DYNAMIC PERFORMANCE

Bandwidth (3 dB) R

FB

= 750 Ω No Peaking, G = +3 125 MHz

Bandwidth (0.1 dB) No Peaking, G = +3 7 MHz
Slew Rate 5 V Step 1200 V/µs
Settling Time to 0.1% 0 V to ±6 V (6 V Step)

C

LOAD

= 300 pF

R

LOAD

> 1 kΩ, RFB = 750 Ω

TA = +25°C to +70°C, RS = 16.9 Ω 30 ns

NOISE/HARMONIC PERFORMANCE

Total Harmonic Distortion

fC = 5 MHz, RL = 150 Ω, VO = 2 p-p –72 dBc

Input Voltage Noise f = 10 kHz 2.0 nV/√Hz
Input Current Noise f = 10 kHz (–I

IN

) 14 pA/√Hz

Differential Gain (R

L

= 150 Ω) f = 3.58 MHz, G = +2, RFB = 750 Ω 0.06 %

Differential Phase (RL = 150 Ω) f = 3.58 MHz, G = +2, RFB = 750 Ω 0.02 Degrees

DC PERFORMANCE

Input Offset Voltage T

MIN

to T

MAX

–5 2 5 mV

Offset Drift 2 µV/°C
Input Bias Current (–) T

MIN

to T

MAX

–45 15 45 µA

Input Bias Current (+) T

MIN

to T

MAX

–25 5 25 µA

Open-Loop Transresistance 67 111 kΩ

T

MIN

to T

MAX

50 111 kΩ

INPUT CHARACTERISTICS

Input Resistance

+Input T

MIN

to T

MAX

100 kΩ

–Input T

MIN

to T

MAX

75 Ω

Input Capacitance 2pF
Input Common-Mode Voltage Range ±6.0 V
Common-Mode Rejection Ratio

Input Offset Voltage 50 56 dB
–Input Current 0.2 µA/V
+Input Current 5 µA/V

OUTPUT CHARACTERISTICS

Output Voltage Swing

RL = 1 kΩ VOL–V

EE

0.8 1.0 V

V

CC–VOH

0.8 1.0 V

R

L

= 150 Ω VOL–V

EE

1.0 1.3 V

V

CC–VOH

1.0 1.3 V
Output Current 50 70 mA
Short-Circuit Current 300 mA
Capacitive Load Drive 1000 pF

MATCHING CHARACTERISTICS

Dynamic

Crosstalk G = +2, f = 5 MHz 70 dB

DC

Input Offset Voltage –5 0.3 5 mV
–Input Bias Current –10 3 10 µA

POWER SUPPLY

Operating Range Single Supply +4.2 +15 V

Dual Supply ±2.1 ±7.5 V

Quiescent Current/Amplifier 6.2 mA

7.0 10.0 mA

T

MIN to TMAX

Power-Down 1.3 4.0 mA

(@ TA = +25C, VS = 7.5, C

LOAD

= 10 pF, R

LOAD

= 150 , unless otherwise noted)

–2–

REV. A

AD8023

Model AD8023A

Conditions V

S

Min Typ Max Units

POWER SUPPLY (Continued)

Power Supply Rejection Ratio V

S

= ±2.5 V to ±7.5 V dB

Input Offset Voltage 54 76 dB
–Input Current 0.03 µA/V
+Input Current 0.07 µA/V

DISABLE CHARACTERISTICS

Off Isolation f = 6 MHz –70 dB
Off Output Capacitance G = +1 12 pF
Turn-On Time 50 ns
Turn-Off Time R

L

= 150 Ω 30 ns

Switching Threshold V

TH

– V

EE

1.6 V

Specifications subject to change without notice.

–3–

REV. A

ABSOLUTE MAXIMUM RATINGS

*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5 V Total

Internal Power Dissipation

Small Outline (R) . . . . 1.0 Watts (Observe Derating Curves)

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V

S

Differential Input Voltage . . . . . . . . . . . . . . . .±3 V (Clamped)

Output Voltage Limit

Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+V

S

Minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V

S

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves

Storage Temperature Range

R Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C

Operating Temperature Range

AD8023A . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD8023AR –40°C to +85°C 14-Lead Plastic SOIC R-14
AD8023AR- –40°C to +85°C 13" Tape and Reel R-14

REEL

AD8023AR- –40°C to +85°C 7" Tape and Reel R-14

REEL7

AD8023ACHIPS –40°C to +85°CDie

Maximum Power Dissipation

The maximum power that can be safely dissipated by the AD8023
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for the plastic encapsulated
parts is determined by the glass transition temperature of the
plastic, about 150°C. Temporarily exceeding this limit may
cause a shift in parametric performance due to a change in the
stresses exerted on the die by the package. Exceeding a junction
temperature of 175°C for an extended period can result in
device failure.

While the AD8023 is internally short circuit protected, this may
not be enough to guarantee that the maximum junction temper­ature is not exceeded under all conditions. To ensure proper
operation, it is important to observe the derating curves.

It must also be noted that in (noninverting) gain configurations
(with low values of gain resistor), a high level of input overdrive
can result in a large input error current, which may result in a
significant power dissipation in the input stage. This power
must be included when computing the junction temperature rise
due to total internal power.

MAXIMUM POWER DISSIPATION – Watts

AMBIENT TEMPERATURE – C

2.5

2.0

0.5
–50 90–40 –30 –20 0 1020 30 4050 6070 80

1.5

1.0

–10

TJ = +150C

14-LEAD SOIC

Figure 3. Maximum Power Dissipation vs. Ambient
Temperature

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8023 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recom­mended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

AD8023

REV. A

–4–

Figure 4. Input Common-Mode Voltage Range vs.
Supply Voltage

Typical Performance Characteristics

METALIZATION PHOTO

Contact factory for latest dimensions.

Dimensions shown in inches and (mm).

–IN1

6

+IN

5

–IN3

9

+IN 3

10

–V

S

11

+V

S

4

DISABLE 3

3

DISABLE 2

2

DISABLE 1

1

+IN 2

12

0.0634
(1.61)

0.0713
(1.81)

7

OUT 1

8

OUT 3

–IN 2

13

14

OUT 2

Figure 5. Output Voltage Swing vs. Load Resistance

COMMON-MODE VOLTAGE RANGE – Volts

SUPPLY VOLTAGE – Volts

8

0

7

4

3

2

1

6

5

2834567

LOAD RESISTANCE – 

14

13

6

10 10k100 1k

10

9

8

7

12

11

OUTPUT VOLTAGE SWING – V p-p

VS = 7.5V

–5–

REV. A

AD8023

SUPPLY VOLTAGE – Volts

25

20

0

192

3

4

5

6

7

8

15

10

5

TA = +25C

TOTAL SUPPLY CURRENT – mA

Figure 6. Total Supply Current vs. Supply Voltage

SUPPLY VOLTAGE – Volts

OUTPUT VOLTAGE SWING – Vp-p

16

2

2834567

14

12

10

6

4

8

TA = +25C

SWING

NO LOAD

SWING

R

L

= 150

Figure 7. Output Voltage Swing vs. Supply Voltage

TEMPERATURE – C

24

16

10

–50

–40 –30–20

–10010

20

22

20

14

12

18

30

40 50 60 70 8090100

VS = 7.5V

VS = 2.5V

TOTAL SUPPLY CURRENT – mA

Figure 8. Total Supply Current vs. Temperature

TEMPERATURE – C

35

15

0

–50 –40 –30–20 –10 0 10 20

30

25

10

5

20

30 40 50 60 70 80 90

100

–I

B

+I

B

INPUT BIAS CURRENT – A

Figure 9. Input Bias Current vs. Temperature

TEMPERATURE – C

1

–2

–40 90–30

–20

–10 0 1020304050607080

0

–1

VS = 2.5V

VS = 7.5V

INPUT OFFSET VOLTAGE – mV

Figure 10. Input Offset Voltage vs. Temperature

FREQUENCY – MHz

100

1 300

10

100

31

10

0.1

3.1

1

0.31

G = +2

VS = 2.5V

VS = 7.5V

CLOSED-LOOP OUTPUT RESISTANCE – V

Figure 11. Closed-Loop Output Resistance vs. Frequency

AD8023

REV. A

–6–

FREQUENCY – kHz

200

10

1

0.1 100110

100

200

10

0

100

– I NOISE

+I NOISE

V NOISE

VOLTAGE NOISE – nVHz

CURRENT NOISE – pAHz

Figure 12. Input Current and Voltage Noise vs. Frequency

TEMPERATURE – C

450

400

250

–50 80–40

SHORT CIRCUIT CURRENT – mA

–30 –20 –10 0 10203040506070

350

300

90 100

VS = 7.5V

SOURCE

SINK

Figure 13. Short Circuit Current vs. Temperature

FREQUENCY – Hz

10k

1 100

10

100

10

G = +1
VS = 7.5V

200

1k

OUTPUT RESISTANCE – 

Figure 14. Output Resistance vs. Frequency,
Disabled State

FREQUENCY – MHz

90

80

0

1 200

10

70

60

20

50

40

30

10

VS = 7.5V

VS = 2.5V

100

COMMON-MODE REJECTION – dB

R

R

R

R

V

CM

Figure 15. Common-Mode Rejection vs. Frequency

VS = 2.5V (+PSRR)

VS = 2.5V (–PSRR)

VS = 7.5V (–PSRR)

FREQUENCY – MHz

1

10 100

0

70

60

50

40

30

20

10

VS = 7.5V (+PSRR)

POWER SUPPLY REJECTION – dB

Figure 16. Power Supply Rejection Ratio vs. Frequency

2ND

3RD

FREQUENCY – MHz

0

–10

–90

1 10010

HARMONIC DISTORTION – dBc

–20

–30

–70

–40

–50

–60

–80

G = +1
V

S

= 7.5V

V

O

= 2V p-p

Figure 17. Harmonic Distortion vs. Frequency, RL = 150

Ω

–7–

REV. A

AD8023

FREQUENCY – Hz

100k

10

1k 1G10k

TRANSIMPEDANCE – 

10M

10k

100

1k

100k 1M 100M

Figure 18. Open-Loop Transimpedance vs. Frequency

OUTPUT VOLTAGE STEP – V p-

p

1600

0

1400

800

600

400

200

1200

1000

0

61

2

345

G = +10

G = +1

G = +2

G = –1

SLEW RATE V/s

Figure 19. Slew Rate vs. Output Step Size

Figure 20. Large Signal Pulse Response,
Gain = +1, (R

F

= 2 kΩ, RL = 150 Ω, VS = ±7.5 V)

Figure 21. Small Signal Pulse Response, Gain = +1,
(R

F

= 2 kΩ, RL = 150 Ω, VS = ±7.5 V)

SUPPLY VOLTAGE – V

1600

0

1400

800

600

400

200

1200

1000

2834 5 67

G = –1

G = +2

G = +1

G = +10

SLEW RATE – V/s

Figure 22. Maximum Slew Rate vs. Supply Voltage

Figure 23. Large Signal Pulse Response,
Gain = +10, (R

F

= 274 Ω, RL = 150 Ω, VS = ±7.5 V)

V

IN

V

O

V

IN

V

O

V

IN

V

O

AD8023

REV. A

–8–

FREQUENCY – MHz

+1

–8

1

500

10 100

–4

–5

–6

–7

–2

–3

0

–1

0

–90

–180

GAIN

PHASE

VS = 7.5V

VS = 2.5V

VS = 7.5V

VS = 2.5V

+2

G = +10
R

L

= 150

CLOSED-LOOP GAIN (NORMALIZED) – dB

PHASE SHIFT – Degrees

Figure 24. Closed-Loop Gain and Phase vs. Frequency,
G = +10, R

L

= 150

Ω

FREQUENCY – MHz

+1

–8

1

400

10

CLOSED-LOOP GAIN (NORMALIZED) – dB

100

–4

–5

–6

–7

–2

–3

0

–1

0

–90

–180

–9

GAIN

PHASE

VS = 2.5V

VS = 7.5V

PHASE SHIFT – Degrees

Figure 25. Closed-Loop Gain and Phase vs. Frequency,
G = +1, R

L

= 150

Ω

Figure 26. Large Signal Pulse Response,
Gain = –1, (R

F

= 750 Ω, RL = 150 Ω, VS = ±7.5 V)

V

IN

V

O

FREQUENCY – MHz

+1

–8

1 50010

CLOSED-LOOP GAIN (NORMALIZED) – dB

100

–4

–5

–6

–7

–2

–3

0

–1

PHASE SHIFT – Degrees

0

–90

–180

GAIN

PHASE

G = +1
R

L

= 150

VS = 7.5V

VS = 2.5V

VS = 7.5V

VS = 2.5V

–9

Figure 27. Closed-Loop Gain and Phase vs. Frequency,
G = –1, R

L

= 150

Ω

Figure 28. Small Signal Pulse Response,
Gain = +10, (R

F

= 274 Ω, RL = 150 Ω, VS = ±7.5 V)

Figure 29. Small Signal Pulse Response,
Gain = –1, (R

F

= 750 Ω, RL = 150 Ω, VS = ±7.5 V)

V

IN

V

O

V

IN

V

O

–9–

REV. A

AD8023

ACL 

G

1+ SC

T(RF

+ Gn rin )

where: CT = transcapacitance  1 pF

R

F

= feedback resistor

G = ideal closed loop gain

Gn =

1 +

R

F

R

G











= noise gain

rin = inverting input resistance  150 Ω
ACL = closed loop gain

The –3 dB bandwidth is determined from this model as:

f

3



1

2 π C

T(RF

+ Gn rin)

This model will predict –3 dB bandwidth to within about
10% to 15% of the correct value when the load is 150 Ω and
V

S

= ±7.5 V. For lower supply voltages there will be a slight

decrease in bandwidth. The model is not accurate enough to
predict either the phase behavior or the frequency response
peaking of the AD8023.

It should be noted that the bandwidth is affected by attenuation
due to the finite input resistance. Also, the open-loop output
resistance of about 6 Ω reduces the bandwidth somewhat when
driving load resistors less than about 150 Ω. (Bandwidths will
be about 10% greater for load resistances above a couple
hundred ohms.)

Table I. –3 dB Bandwidth vs. Closed-Loop Gain and Feedback
Resistor, R

L

= 150  (SOIC)

VS – Volts Gain RF – Ohms BW – MHz

±7.5 [phone]

+2 750 240
+10 300 50

–1 750 150
–10 250 60

±2.5 [phone]

+2 1000 90
+10 300 30

–1 750 95
–10 250 50

Driving Capacitive Loads

When used in combination with the appropriate feedback
resistor, the AD8023 will drive any load capacitance without
oscillation. The general rule for current feedback amplifiers is
that the higher the load capacitance, the higher the feedback
resistor required for stable operation. Due to the high open-loop
transresistance and low inverting input current of the AD8023,
the use of a large feedback resistor does not result in large closed­loop gain errors. Additionally, its high output short circuit current
makes possible rapid voltage slewing on large load capacitors.

For the best combination of wide bandwidth and clean pulse
response, a small output series resistor is also recommended.
Table II contains values of feedback and series resistors which
result in the best pulse responses. Figure 28 shows the AD8023
driving a 300 pF capacitor through a large voltage step with
virtually no overshoot. (In this case, the large and small signal
pulse responses are quite similar in appearance.)

FREQUENCY – MHz

+1

–8

1 50010

CLOSED-LOOP GAIN (NORMALIZED) – dB

100

–4

–5

–6

–7

–2

–3

0

–1

GAIN

PHASE

G = –10
R

L

= 150

VS = 7.5V

VS = 2.5V

VS = 2.5V

–9

PHASE SHIFT – Degrees

0

–90

–180

Figure 30. Closed-Loop Gain and Phase vs. Frequency,
G = –10, R

L

= 150

Ω

General

The AD8023 is a wide bandwidth, triple video amplifier that
offers a high level of performance on less than 9.0 mA per
amplifier of quiescent supply current. The AD8023 achieves
bandwidth in excess of 200 MHz, with low differential gain and
phase errors and high output current making it an efficient video
amplifier.

The AD8023’s wide phase margin coupled with a high output
short circuit current make it an excellent choice when driving
any capacitive load up to 300 pF.

It is designed to offer outstanding functionality and performance
at closed-loop inverting or noninverting gains of one or greater.

Choice of Feedback and Gain Resistors

Because it is a current feedback amplifier, the closed-loop band­width of the AD8023 may be customized using different values
of the feedback resistor. Table I shows typical bandwidths at
different supply voltages for some useful closed-loop gains when
driving a load of 150 Ω.

The choice of feedback resistor is not critical unless it is desired
to maintain the widest, flattest frequency response. The resistors
recommended in the table (chip resistors) are those that will
result in the widest 0.1 dB bandwidth without peaking. In
applications requiring the best control of bandwidth, 1%
resistors are adequate. Resistor values and widest bandwidth
figures are shown. Wider bandwidths than those in the table can
be attained by reducing the magnitude of the feedback resistor
(at the expense of increased peaking), while peaking can be
reduced by increasing the magnitude of the feedback resistor.

Increasing the feedback resistor is especially useful when driving
large capacitive loads as it will increase the phase margin of the
closed-loop circuit. (Refer to the Driving Capacitive Loads
section for more information.)

To estimate the –3 dB bandwidth for closed-loop gains of 2 or
greater, for feedback resistors not listed in the following table,
the following single pole model for the AD8023 may be used:

AD8023

REV. A

–10–

Figure 33. 50% Overload Recovery, Gain = +10,
(R

F

= 300 Ω, RL = 1 kΩ, VS = ±7.5 V)

As noted in the warning under Maximum Power Dissipation, a
high level of input overdrive in a high noninverting gain circuit
can result in a large current flow in the input stage. Though this
current is internally limited to about 30 mA, its effect on the
total power dissipation may be significant.

Disable Mode Operation

Pulling the voltage on any one of the Disable pins about 1.6 V up
from the negative supply will put the corresponding amplifier
into a disabled, powered down, state. In this condition, the
amplifier’s quiescent current drops to about 1.3 mA, its output
becomes a high impedance, and there is a high level of isolation
from input to output. In the case of a gain of two line driver for
example, the impedance at the output node will be about the
same as for a 1.5 kΩ resistor (the feedback plus gain resistors)
in parallel with a 12 pF capacitor.

Leaving the Disable pin disconnected (floating) will leave the
corresponding amplifier operational, in the enabled state. The
input impedance of the disable pin is about 25 kΩ in parallel
with a few picofarads. When driven to 0 V, with the negative
supply at –7.5 V, about 100 µA flows into the disable pin.

When the disable pins are driven by complementary output
CMOS logic, on a single 5 V supply, the disable and enable
times are about 50 ns. When operated on dual supplies, level
shifting will be required from standard logic outputs to the
Disable pins. Figure 33 shows one possible method, which
results in a negligible increase in switching time.

+7.5V

10k

TO DISABLE PIN

V

I

VI HIGH => AMPLIFIER ENABLED
V

I

LOW => AMPLIFIER DISABLED

–7.5V

4k

15k

+5

Figure 34. Level Shifting to Drive Disable Pins on Dual
Supplies

The AD8023’s input stages include protection from the large
differential input voltages that may be applied when disabled.
Internal clamps limit this voltage to about ±3 V. The high input to
output isolation will be maintained for voltages below this limit.

Figure 31. Circuit for Driving a Capacitive Load

Table II. Recommended Feedback and Series Resistors vs.
Capacitive Load and Gain

RS – Ohms

CL – pF RF – Ohms G = 2 G ≥ 3

20 2k 0 0
50 2k 10 10
100 2k 15 15
200 3k 10 10
300 3k 10 10
≥500 3k 10 10

Figure 32. Pulse Response Driving a Large Load Capacitor.

C

L

= 300 pF, G = +3, RF = 750 Ω, RS = 16.9 Ω, RL = 10 k

Ω

Overload Recovery

The three important overload conditions are: input common­mode voltage overdrive, output voltage overdrive, and input
current overdrive. When configured for a low closed-loop gain,
this amplifier will quickly recover from an input common-mode
voltage overdrive; typically in under 25 ns. When configured for
a higher gain, and overloaded at the output, the recovery time
will also be short. For example, in a gain of +10, with 50%
overdrive, the recovery time of the AD8023 is about 20 ns (see
Figure 31). For higher overdrive, the response is somewhat
slower. For 100% overdrive, (in a gain of +10), the recovery
time is about 80 ns.

V

IN

V

O

V

IN

V

O

4

+V

S

AD8023

1.0F

0.1F

11

1.0F

0.1F

–V

S

R

G

R

T

V

IN

15

C

L

V

O

R

F

R

S

–11–

REV. A

AD8023

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

14-Lead Plastic SOIC

(R-14)

14 8

71

0.3444 (8.75)

0.3367 (8.55)

0.2440 (6.20)

0.2284 (5.80)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

SEATING

PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0688 (1.75)

0.0532 (1.35)

0.0500
(1.27)

BSC

0.0099 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

8°
0°

0.0196 (0.50)

0.0099 (0.25)

x 45°

PRINTED IN U.S.A.

C3137–0–3/00 (rev. A)