Dual High-Speed
FREQUENCY – Hz
3.0
10k
pA AND nV/ Hz
2.5
2.0
1.5
1.0
0.5
0
100k 1M
VOLTAGE NOISE, nV
CURRENT NOISE, pA
a
FEATURES
Low-Noise Amplifiers Provide Low Noise and Low
Distortion, Ideal for xDSL Modem Receiver
+5 V to ⴞ12 V Voltage Supply
Low-Power Consumption
4.0 mA/Amp (Typ) Supply Current
Voltage Feedback Amplifiers
Low Noise and Distortion
2.5 nV/√Hz Voltage Noise @ 100 kHz
SFDR –95 dBc @ 1 MHz
MTPR < –66 dBc
High Speed
120 MHz Bandwidth (–3 dB), G = 1
50 V/s Slew Rate
Low-Offset Voltage, 1.5 mV Typical
APPLICATIONS
ADSL, VDSL, HDSL, and Proprietary xDSL Systems
Low-Noise Instrumentation Front End
Ultrasound Preamp
Low-Noise Op Amps
AD8022
FUNCTIONAL BLOCK DIAGRAM
OUT1
–IN1
+IN1
–V
S
1
2
3
4
AD8022
–
+
8
+V
S
7
OUT2
6
–IN2
–
+
5
+IN2
PRODUCT DESCRIPTION
The AD8022 consists of two low-noise, high-speed, voltage feed-
back amplifiers. Both inputs add only 2.5 nV/√Hz of voltage
noise. These dual amplifiers provide wideband, low-distortion
performance, with high-output current optimized for stability
when driving capacitive loads. Operating from +5 V to ±12 V
supplies, the AD8022 typically consumes only 4.0 mA/Amp
quiescent current. The AD8022 is available in both an 8-lead
microSOIC and an 8-lead SOIC package. Fast overvoltage
recovery and wide bandwidth make the AD8022 ideal as the
receive channel front end to an ADSL, VDSL or proprietary
xDSL transceiver design.
Low-noise receive amplifiers in the AD8022 are independent
voltage feedback amplifiers and can be configured as the differential receiver from the line transformer or as independent active
filters in an xDSL line interface circuit.
Figure 1. Current and Voltage Noise vs. Frequency
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD8022–SPECIFICATIONS
(@ 25ⴗC, VS = ⴞ12 V, RL = 500 ⍀, G = 1, T
otherwise noted)
= –40ⴗC, T
MIN
= +85ⴗC, unless
MAX
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth V
Bandwidth for 0.1 dB Flatness V
Large Signal Bandwidth V
Slew Rate V
Rise and Fall Time V
Settling Time 0.1% V
Overdrive Recovery Time V
= 0.2 V p-p 120 MHz
OUT
= 0.2 V p-p 25 MHz
OUT
= 4 V p-p 15 MHz
OUT
= 2 V p-p, G = 2 50 V/µs
OUT
= 2 V p-p, G = 2 30 ns
OUT
= 2 V p-p 62 ns
OUT
= 150% of Max Output
OUT
Voltage, G = 2 200 ns
NOISE/DISTORTION PERFORMANCE
Distortion V
Second Harmonic f
Third Harmonic f
Multitone Input Power Ratio
1
= 2 V p-p
OUT
= 1 MHz –95 dBc
C
= 1 MHz –100 dBc
C
G = 7 Differential
26 kHz to 132 kHz –67.2 dBc
144 kHz to 1.1 MHz –66 dBc
Voltage Noise (RTI) f = 100 kHz 2.5 nV/√Hz
Input Current Noise f = 100 kHz 1.2 pA/√Hz
INPUT CHARACTERISTICS
RTI Offset Voltage –6 –1.5 +6 mV
T
MIN
to T
MAX
–7.25 +7.25 mV
Input Bias Current –5 +2.5 +5 µA
to T
T
MIN
MAX
–7.5 +7.5 µA
Input Resistance (Differential) 20 kΩ
Input Capacitance 0.7 pF
Input Common-Mode Voltage Range –11.25 to +11.75 V
OUTPUT CHARACTERISTICS
Output Voltage Swing Single-Ended –10.1 +10.1 V
Short Circuit Output Current 100 mA
Capacitive Load Drive R
= 0 Ω, <3 dB of Peaking 75 pF
S
POWER SUPPLY
Operating Range +4.5 ±13.0 V
Quiescent Current 4.0 5.5 mA/Amp
T
Power Supply Rejection Ratio V
to T
MIN
S
MAX
= ±5 V to ±12 V 80 dB
6.1 mA
OPERATING TEMPERATURE RANGE –40 +85 °C
NOTES
1
Multitone testing performed with 800 mV rms across a 500 Ω load at Points A and B on Figure 17.
Specifications subject to change without notice.
–2–
REV. 0
SPECIFICATIONS
(@ 25ⴗC, VS = ⴞ2.5 V, RL = 500 ⍀, G = 1, T
otherwise noted)
= –40ⴗC, T
MIN
= +85ⴗC, unless
MAX
AD8022
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth V
Bandwidth for 0.1 dB Flatness V
Large Signal Bandwidth V
Slew Rate V
Rise and Fall Time V
Settling Time 0.1% V
Overdrive Recovery Time V
= 0.2 V p-p 94 MHz
OUT
= 0.2 V p-p 22 MHz
OUT
= 3 V p-p 10 MHz
OUT
= 2 V p-p, G = 2 42 V/µs
OUT
= 2 V p-p, G = 2 40 ns
OUT
= 2 V p-p 75 ns
OUT
= 150% of Max Output
OUT
Voltage, G = 2 225 ns
NOISE/DISTORTION PERFORMANCE
Distortion V
Second Harmonic f
Third Harmonic f
Multitone Input Power Ratio
1
= 2 V p-p
OUT
= 1 MHz –77.5 dBc
C
= 1 MHz –94 dBc
C
G = 7 Differential, V
= ±6 V
S
26 kHz to 132 kHz –69 dBc
144 kHz to 1.1 MHz –66.7 dBc
Voltage Noise (RTI) f = 100 kHz 2.3 nV/√Hz
Input Current Noise f = 100 kHz 1 pA/√Hz
INPUT CHARACTERISTICS
RTI Offset Voltage –5.0 –0.8 +5.0 mV
T
MIN
to T
MAX
–6.25 +6.25 mV
Input Bias Current –5.0 +2.0 +5.0 µA
to T
T
MIN
MAX
7.5 µA
Input Resistance (Differential) 20 kΩ
Input Capacitance 0.7 pF
Input Common-Mode Voltage Range –1.83 to +2.5 V
OUTPUT CHARACTERISTICS
Output Voltage Swing Single-Ended –1.38 +1.48 V
Short Circuit Output Current 80 mA
Capacitive Load Drive R
= 0 Ω, <3 dB of Peaking 75 pF
S
POWER SUPPLY
Operating Range +4.5 ±13.0 V
Quiescent Current 3.5 4.25 mA/Amp
T
MIN
to T
MAX
4.4 mA
Power Supply Rejection Ratio ∆VS = ±1 V 86 dB
OPERATING TEMPERATURE RANGE –40 +85 °C
NOTES
1
Multitone testing performed with 800 mV rms across a 500 Ω load at Points A and B on Figure 17.
Specifications subject to change without notice.
REV. 0
–3–
AD8022
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 V
Internal Power Dissipation
2
1
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . 1.6 W
microSOIC Package (RM) . . . . . . . . . . . . . . . . . . . . . 1.2 W
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±0.8 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range RM, R . . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for the device in free air:
8-Lead SOIC Package: θJA = 160°C/W.
8-Lead microSOIC Package: θJA = 200°C/W.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD8022AR –40°C to +85°C 8-Lead Plastic SOIC SO-8
AD8022ARM –40°C to +85°C 8-Lead microSOIC RM-8
AD8022AR-EVAL Evaluation Board SO-8
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8022
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change
in the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can result
in device failure.
While the AD8022 is internally short circuit protected, this may not
be sufficient to guarantee that the maximum junction temperature
(150°C) is not exceeded under all conditions. To ensure proper
operation, it is necessary to observe the maximum power derating curves.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8022 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
2.0
1.5
8-LEAD SOIC PACKAGE
1.0
0.5
MAXIMUM POWER DISSIPATION – Watts
0
–50
8-LEAD MICROSOIC
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – 8C
TJ = 150 8C
Figure 2. Plot of Maximum Power Dissipation vs.
Temperature
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD8022
FREQUENCY – MHz
dB
0.1 10 100 5001
5
4
3
2
1
0
–1
–2
–3
–4
–5
50V
50V
50V
R
F
+
RF = 402V
RF = 0V
RF = 715V
V
IN
V
OUT
FREQUENCY – Hz
0.4
100k
dB
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
1M 10M 100M
G = 2
RL = 509V
612V
65.0V
62.5V
SUPPLY VOLTAGE – Volts
70
2.5
SLEW RATE – V/ms
60
50
40
30
20
10
0
4.5 6.5 8.5 10.5 12.5
NEGATIVE EDGE
POSITIVE EDGE
dB
5
4
3
2
1
0
–1
–2
–3
–4
–5
0.1
V
50V
402V
V
453V
IN
+
VIN = 2V p-p
VIN = 0.8V p-p
1 10 100 500
OUT
56.2V
VIN = 0.4V p-p
FREQUENCY – MHz
VIN = 0.05V p-p
VIN = 0.2V p-p
Figure 3. Frequency Response vs. Signal Level,
V
= ±12 V, G = 1
S
0.4
G = 1
0.3
RL = 509V
0.2
0.1
0
–0.1
dB
–0.2
–0.3
–0.4
–0.5
–0.6
100k
1M 10M 100M
FREQUENCY – Hz
612V
65.0V
62.5V
Figure 4. Fine-Scale Gain Flatness vs. Frequency, G = 1
Figure 6. Frequency Response vs. RF, G = 1, VS = ±12 V,
V
= 22 dBm
IN
Figure 7. Fine-Scale Gain Flatness vs. Frequency, G = 2
140
120
100
80
60
FREQUENCY – MHz
40
Figure 5. Bandwidth vs. Supply, RL = 500 Ω, VIN = –10 dBm
20
0
0142
REV. 0
G = +1, RF = 402V
G = +2, RF = 715V
4681012
SUPPLY VOLTAGE – 6Volts
Figure 8. Slew Rate vs. Supply Voltage, VS = ±12 V, G = 2
–5–
AD8022
100mV
100
90
10
0%
100ns
100mV
INPUT
OUTPUT
1.00V
100
90
10
0%
100ns
1.00V
INPUT
OUTPUT
TIME – ns
0.4
SETTLING TIME – %
0
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
40 60 80 100 12020
+0.1%
–0.1%
100mV
100
90
100ns
INPUT
10
0%
100mV
OUTPUT
Figure 9. Noninverting Small Signal Pulse Response,
R
= 500 Ω, VS = ±12 V, G = 1, RF = 0
L
2.00V
100
90
100ns
INPUT
10
0%
2.00V
OUTPUT
Figure 12. Noninverting Small Signal Pulse Response,
R
= 500 Ω, VS = ±2.5 V, G = 1, RF = 0
L
Figure 10. Noninverting Large Signal Pulse Response,
R
= 500 Ω, VS = ±12 V, G = 1, RF = 0
L
0.4
0.3
0.2
0.1
0
–0.1
SETTLING TIME – %
–0.2
–0.3
–0.4
0
40 60 80 100 12020
TIME – ns
+0.1%
–0.1%
Figure 11. Settling Time to 0.1%, VS = ±12 V,
Step Size = 2 V p-p, G = 2, R
= 500
L
Figure 13. Noninverting Large Signal Pulse Response,
R
= 500 Ω, VS = ±2.5 V, G = 1, RF = 0
L
Figure 14. Settling Time to 0.1%, VS = ±2.5 V,
Ω
Step Size = 2 V p-p, G = 2, R
= 500
L
Ω
–6–
REV. 0
AD8022
p
p
FREQUENCY – Hz
HARMONIC DISTORTION – dB
–60
–70
–80
–90
–100
10k 100k 1M1k
–110
–120
–130
–50
2ND
3RD
4
3
2
1
0
–1
–2
–3
–4
–12.5 –10.0 –7.5 –5.0 –2.5 0 2.5 5.0 7.5 10.0 12.5
V
CM
– Volts
V
OS
– mV
VS = 612V
VS = 62.5V
1kV
500V
V
OUT
V
IN
1kV
1kV
1kV
–20
–30
–40
–50
–60
–70
–80
–90
HARMONIC DISTORTION – dBc
–100
–120
0
3RD
2ND
5101520
OUTPUT VOLTAGE – Volts p-
Figure 15. Distortion vs. Output Voltage, VS = ±12 V,
G = 2, f = 1 MHz, R
–50
–60
–70
–80
= 500 Ω, RF = 715
L
3RD
Ω
0
–20
–40
–60
–80
HARMONIC DISTORTION – dBc
–100
–120
0
2ND
3RD
1.0 1.5 2.0 3.00.5 2.5
OUTPUT VOLTAGE – Volts p-
Figure 18. Distortion vs. Output Voltage, VS = ±2.5 V,
G = 2, f = 1 MHz, R
= 500 Ω, RF = 715
L
Ω
–90
–100
250V
2ND
10k 100k 1M1k
FREQUENCY – Hz
+V
AD8022
1/2
715V
715V
AD8022
1/2
–V
= 2 V p-p, Gain = 1
OUT
500V
Figure 19. Distortion vs. Frequency, VS = ±2.5 V,
R
= 500 Ω, RF = 715 Ω, V
L
= 2 V p-p, Gain = 1
OUT
Figure 20. Input Common-Mode Voltage Range
-
–110
HARMONIC DISTORTION – dB
–120
–130
Figure 16. Distortion vs. Frequency, VS = ±12 V,
R
= 500 Ω, RF = 715 Ω, V
L
Figure 17. Multitone Power Ratio Test Circuit
REV. 0
–7–
AD8022
FREQUENCY – kHz
102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 110.4 111.4 112.4
10dB/DIV
–69.0dBc
FREQUENCY – kHz
102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 110.4 111.4 112.4
10dB/DIV
–67.2dBc
10dB/DIV
–66.7dBc
549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3
FREQUENCY – kHz
Figure 21. Multitone Power Ratio: VS = ±6 V, RL = 500 Ω,
Full Rate ADSL (DMT), Downstream
–66.0dBc
10dB/DIV
549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3
FREQUENCY – kHz
Figure 22. Multitone Power Ratio: VS = ±12 V, RL = 500 Ω,
Full Rate ADSL (DMT), Downstream
4.5
4.0
3.5
3.0
2.5
2.0
1.5
BIAS CURRENT – mA
1.0
0.5
0
–60
–40 –20 0 20 40 60 80 100 120 140
Figure 23. Bias Current vs. Temperature
VS = 612V
VS = 62.5V
TEMPERATURE – 8C
Figure 24. Multitone Power Ratio: VS = ±6 V, RL = 500 Ω,
Full Rate ADSL (DMT), Upstream
Figure 25. Multitone Power Ratio: VS = ±12 V, RL = 500 Ω,
Full Rate ADSL (DMT), Upstream
8.5
8.0
7.5
7.0
6.5
6.0
SUPPLY CURRENT – Total mA
5.5
5.0
–50 1500
VS = 612V
VS = 62.5V
50 100
TEMPERATURE – 8C
Figure 26. Total Supply Current Over Temperature
–8–
REV. 0
100
FREQUENCY – Hz
0
CROSSTALK – dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1M 10M 100M100k
SIDE A OUT
SIDE B OUT
TEMPERATURE – Degrees
0
–60
VOLTAGE OFFSET – mV
–0.5
–1.0
–1.5
–2.0
–2.5
20–40 –20 0 40 60 80 100 120 140
SIDE B
VS = +12V
SIDE A
SIDE A
SIDE B
VS = 62.5V
31.6
10
3.16
1
0.316
0.1
OUTPUT IMPEDANCE – V
0.0316
100k30k
1M 10M 100M 500M
FREQUENCY – Hz
Figure 27. Output Impedance vs. Frequency, VS = ±12 V
0
–10
–20
–30
–40
–50
–60
CROSSTALK – dB
–70
–80
–90
–100
100k
1M 10M 100M
SIDE A OUT
SIDE B OUT
FREQUENCY – Hz
Figure 28. Output-to-Output Crosstalk vs. Frequency,
V
= ±12 V
S
AD8022
5
4
V
IN
50V
3
2
715V
1
0
–1
–2
FREQUENCY RESPONSE – dB
–3
–4
–5
0.1 10 100 5001
Figure 30. Frequency Response vs. Capacitive Load,
C
= 0 pF, 30 pF and 50 pF, RS = 0
L
Figure 31. Output -to-Output Crosstalk vs. Frequency,
V
= ± 2.5 V
S
R
+
715V
FREQUENCY – kHz
453V
S
C
L
56.2V
30pF
0pF
V
OUT
50pF
Ω
REV. 0
–10
–30
–50
–70
CMRR – dB
–90
–110
1k
154V
604V604V
154V56.7V
10k 100k 1M
FREQUENCY – Hz
Figure 29. CMRR vs. Frequency
50V
Figure 32. Voltage Offset vs. Temperature
–9–
AD8022
0
–10
–20
–30
–40
–50
–60
–70
–80
POWER SUPPLY REJECTION – dB
–90
–100
10k
100k 1M 10M 100M
–PSRR
+PSRR
FREQUENCY – Hz
Figure 33. Power Supply Rejection vs. Frequency,
V
= ±12 V
S
THEORY OF OPERATION
The AD8022 is a voltage-feedback op amp designed especially
for ADSL or other applications requiring very low voltage and
current noise along with low-supply current, low distortion, and
ease of use.
The AD8022 is fabricated on Analog Devices’ proprietary eXtraFast Complementary Bipolar (XFCB) process, which enables
the construction of PNP and NPN transistors with similar fTs in
the 4 GHz region. The process is dielectrically isolated to eliminate
the parasitic and latch-up problems caused by junction isolation.
These features enable the construction of high-frequency, lowdistortion amplifiers with low-supply currents.
+V
S
15V
+IN
7.5pF
–IN
600mA
OFFSET NULL
15V
OUTPUT
–V
S
Figure 35. Simplified Schematic
As shown in Figure 35, the AD8022 input stage consists of an
NPN differential pair in which each transistor operates a 300 µA
collector current. This gives the input devices a high transconduc-
tance and hence gives the AD8022 low-input noise of 2.5 nV/√Hz
@ 100 kHz. The input stage drives a folded cascode that consists
of a pair of PNP transistors. These PNP’s then drive a current
mirror that provides a differential-input to single-ended-output conversion. The output stage provides a high-current gain
of 10,000, so that the AD8022 can maintain a high-dc openloop gain, even into low-load impedances.
0
–10
–20
–30
–40
–50
–60
–70
–80
POWER SUPPLY REJECTION – dB
–90
–100
10k
100k 1M 10M 100M
–PSRR
+PSRR
FREQUENCY – Hz
Figure 34. Power Supply Rejection vs. Frequency,
V
= ±2.5 V
S
APPLICATIONS
The low-noise AD8022 dual xDSL receiver amplifier is specifically designed for the dual differential receiver amplifier function
within xDSL transceiver hybrids as well as other low-noise
amplifier applications. The AD8022 may be used in receiving
modulated signals including Discrete Multitone (DMT) on either
end of the subscriber loop. Communication systems designers
can be challenged when designing an xDSL modem transceiver
hybrid capable of receiving the smallest signals embedded in noise
that inherently exists on twisted pair phone lines. Noise sources
include Near End Cross Talk (NEXT), Far End Cross Talk
(FEXT), background and impulse noise, all of which are fed, to
some degree, into the receiver front end. Based on a Bellcore
noise survey, the background noise level for typical twisted pair
telephone loop is said to be –140 dBm/√Hz or 31 nV/√Hz. It
is therefore important to minimize the noise added by the receiver
amplifiers in order to preserve as much Signal-to-Noise Ratio
(SNR) as is possible. With careful transceiver hybrid design
using the AD8022 dual low-noise receiver amplifier, maintaining
power density levels lower than –140 dBm/Hz in ADSL modems is
easily achieved.
DMT Modulation and Multitone Power Ratio (MTPR)
ADSL systems rely on Discrete Multitone (or DMT) modulation
to carry digital data over phone lines. DMT modulation appears
in the frequency domain as power contained in several individual
frequency subbands, sometimes referred to as tones or bins,
each of which is uniformly separated in frequency. (See Figures
21, 22, 24, and 25 for MTPR results while the AD8022 receives
DMT driving 800 mV rms across 500 Ω differential load). A
uniquely encoded, Quadrature Amplitude Modulation (QAM)
signal occurs at the center frequency of each subband or tone.
Difficulties will exist when decoding these subbands if a QAM
signal from one subband is corrupted by the QAM signal(s) from
other subbands, regardless of whether the corruption comes from
an adjacent subband or harmonics of other subbands. Conventional methods of expressing the output signal integrity of line
receivers such as spurious free dynamic range (SFDR), single
tone harmonic distortion or THD, two-tone Intermodulation
Distortion (IMD) and third-order intercept (IP3) become
significantly less meaningful when amplifiers are required to
–10–
REV. 0
AD8022
process DMT and other heavily modulated waveforms. A typical
xDSL downstream DMT signal may contain as many as 256
carriers (subbands or tones) of QAM signals. MTPR is the relative difference between the measured power in a typical subband
(at one tone or carrier) versus the power at another subband
specifically selected to contain no QAM data. In other words, a
selected subband (or tone) remains open or void of intentional
power (without a QAM signal) yielding an empty frequency
bin. MTPR, sometimes referred to as the “empty bin test,” is
typically expressed in dBc, similar to expressing the relative difference between single tone fundamentals and second or third
harmonic distortion components. Measurements of MTPR are
typically made at the output of the receiver directly across the
differential load. Other components aside, the receiver function
of an ADSL transceiver hybrid will be affected by the turns ratio
of the selected transformers within the hybrid design. Since a
transformer reflects the secondary voltage back to the primary
side by the inverse of the turns ratio 1/N, increasing the turns
ratio on the secondary side reduces the voltage across the primary side inputs of the differential receiver. Increasing the turns
ratio of the transformers may inadvertently cause a reduction
of the SNR by reducing the received signal strength.
Channel Capacity and SNR
The efficiency of an ADSL system in delivering the digital data
embedded in the DMT signals can be compromised when the
noise power of the transmission system increases. The graph
below shows the relationship between SNR and the relative maximum number of bits per tone or subband while maintaining a bit
error rate at 1E-7 errors per second.
60.00
50.00
40.00
30.00
SNR – dB
20.00
10.00
0.00
0
51015
BITS/TONE
Figure 36. ADSL DMT SNR vs. Bits/Tone
Generating DMT
At this time, DMT modulated waveforms are not typically menu
selectable items contained within arbitrary waveform generators.
AWGs that are available today may not deliver DMT signals
sufficient in performance with regard to MTPR due to limitations in the D/A converters and output amplifiers used by AWG
manufacturers. Similar to evaluating single tone distortion performance of an amplifier, MTPR evaluation requires a DMT signal
generator capable of delivering MTPR performance better than
that of the driver under evaluation. Generating DMT signals can
be accomplished using a Tektronics AWG 2021 equipped with
Opt 4, (12-bit/24-bit, TTL Digital Data Out), digitally coupled
to Analog Devices’ AD9754, a 14-bit TxDAC, buffered by an
AD8002 amplifier configured as a differential driver. See Figure
37 for schematics of a circuit used to generate DMT signals
that can achieve down to –80 dBc of MTPR performance,
sufficient for use in evaluating xDSL receivers. WFM files are
needed to produce the necessary digital data required to drive
the TxDAC from the optional TTL Digital Data output of
the TEK AWG2021. Copies of .WFM files for upstream and
downstream DMT waveforms with a peak-to-average ratio (crest
factor) of ~5.3 can be obtained through the Analog Devices
web site. http://products.analog.com/products/info.asp?
product=AD8022
Upstream data is contained in the ...24.wfm files and downstream
data in the ...128.wfm files. These DMT modulated signals are
used to evaluate xDSL products for Multitone Power Ratio or
MTPR performance. The data files are used in pairs (adslu24.wfm
and adsll24.wfm go together, etc.) and are loaded into Tektronics
AWG2021 arbitrary waveform generator. The adslu24.wfm is
loaded via the TEK AWG2021 floppy drive into Channel 1
while the adsll24.wfm is simultaneously loaded into Channel
2. The number in the file name, prefixed with ‘u,’ goes into
CH1 or upper channel and the ‘l’ goes into CH2 or the lower
channel. Twelve bits from channel CH1 are combined with two
bits from CH2 to achieve 14-bit digital data at the digital outputs of the TEK 2021. The resulting waveforms produced at the
AD9754-EB outputs are then buffered and amplified by the
AD8002 differential driver to achieve 14-bit performance from
this DMT signal source.
Power Supply and Decoupling
The AD8022 should be powered with a good quality (i.e., low
noise) dual supply of ±12 V for the best overall performance.
The AD8022 circuit will also function at voltages lower than
±12 V. Careful attention must be paid to decoupling the power
supply pins. A pair of 10 µF capacitors located in near proximity
to the AD8022 is required to provide good decoupling for lower
frequency signals. In addition, 0.1 µF decoupling capacitors should
be located as close to each of the power supply pins as is physically possible.
REV. 0
–11–
AD8022
TP13
AVCC
AVDD
23222120191817
NC
AVDD
DCOM
DB11
DB10
DB9
OUT 2
OUT 1
IOUTA
COMP2
DB8
DB7
IOUTB
ACOM
COMP1
DB6
DB5
DB4
1011121314
16
REFIO
FS ADJ
DB3
DB2
TP10 TP9
TP11
15
SLEEP
REFLO
DB1
DB0
C10
0.1mF
AVDD
TP14
R
20kV
R16
2kV
AVDD
A
A
CT1
C11
JP4
0.1mF
1
2
3
A A A
JP2
J2
PDIN
R17
49.9V
TP12
1
DVDD
R8
1
DIFFERENTIAL
DMT OUTPUTS
A
A
TP8
C9
0.1mF
A
AVDD
C8
0.1mF
C7
1mF
3
2
CLK
JP1
1
AB
R15
49.9V
TP1
J1
EXTCLK
A
DVDD
C6
10mF
TP7
B6
U1
R7
1
2827262524
DVDD
CLOCK
AD9754
DB13
DB12
123456789
10
98765432
10
98765432
AVEE
AGND
AVDD
DGND
DVDD
A
C5
TP6
B5
TP5
TP19
TP18
B4
B3
B2
B1
A
C4
TP4
TP2
C3
TP3
R3
DVDD
R5
R1
1
RES PK
16 PINDIP
1
1
P1
16151413121110
1234567
C19C1C2
10
98765432
10
98765432
13579
246
9
8
C25
C26
C27
C28
C29
11131517192123
2021
AWG
TO TEK
8
101214161820222426283032343638
RES PK
16 PINDIP
25
2729313335
1615141312
12345
C30
C31
C32
C33
37
C34
11
10
6
7
C35
C36
39
40
10mF
10mF
10mF
1098765432
1098765432
98765432
10 1098765432
R4
AVCC
1
DVDD
R6
1
R2
249V
A
0.1mF
750V
AD8002
10kV
A
1mF
49.9V
A
C12
22pF
OUT1
J3
A
249V
A
750V
226V
AD8002
1mF
OUT2
J4
0.1mF
AVEE
10kV
A
49.9V
A
C13
22pF
A
Figure 37. DMT Signal Generator Schematic
–12–
REV. 0
AD8022
FREQUENCY – Hz
10k
–47.5
100k 1M 10M
–42.5
–37.5
–32.5
–27.5
–22.5
–17.5
–12.5
–7.5
–2.5
2.5
7.5
dB
EVALUATION BOARDS
The evaluation board layout of Figures 40, 41, and 42 is our
standard dual SOIC noninverting evaluation circuit offering
the ability to evaluate the AD8022 in typical op amp circuits,
is available from Analog Devices Inc. In addition, the AD8022
receiver function may be added to on our ADSL EVAL boards.
The AD8016ARB-EVAL, the AD8016ARP-EVAL, the
AD8017AR-EVAL and AD8018ARU-EVAL boards are available through Analog Devices. These platforms provide the
capability to fully evaluate the Analog Devices ADSL transceiver hybrid. All of the ADSL evaluation boards mentioned
above can accommodate the evaluation of the AD8022 as a
receiver amplifier when installed in the U2 location. The receiver
circuit on these boards is typically unpopulated. Requesting
samples of the AD8022 along with the EVAL board of your
choice will provide the capability to evaluate the AD8022 along
with many other Analog Devices ADSL line driver products in a
typical transceiver circuit. The evaluation circuits have been
designed to replicate the CPE or CO side analog transceiver
hybrid circuits.
The ADSL EVAL circuits mentioned above are designed using a
two transformer transceiver topology, including a line receiver, line
driver, line matching network, an RJ11 jack for interfacing to
line simulators, and transformer-coupled inputs for single-todifferential input conversion.
Layout Considerations
As is the case with all “hi speed” amplifiers, careful attention to
printed circuit board layout details will prevent associated board
parasitics from becoming problematic. Proper RF design technique
is mandatory. The PCB should have a ground plane covering all
unused portions of the component side of the board to provide a
low-impedance return path. Removing the ground plane from
the area near the input signal lines will reduce stray capacitance.
Chip capacitors should be used for the supply bypassing. One
end of the capacitor connected to the ground plane and the other
no more than 1/8 inch away from each supply pin. An additional
large (0.47 µF to 10 µF) tantalum capacitor should be connected
in parallel, although not necessarily as close, in order to supply
current for fast, large signal changes at the AD8022 output.
Signal lines connecting the feedback and gain resistors should
be as short as possible, minimizing the inductance and stray
capacitance associated with these traces. Locate termination
resistors and loads as close as possible to the input(s) and output respectively. Adhere to stripline design techniques for long
signal traces (greater than about 1 inch). Following these
generic guidelines will improve the performance of the AD8022
in all applications.
680pF
5% NPO
5%
1%
12V
8
AD8022
3
1
U27
2
1kV 1%
1kV 1%
6
7
U27
5
AD8022
4
1.91kV
1%
0.1mF
1.91kV
1%
16V
10%
X7R
2.43kV
6V
2.43kV
1%
820pF
10%
820pF
10%
1%
1.69kV
0.1mF
50V
NPO
680pF
5% NPO
Figure 38. Differential Input Sallen-Key Filter Using
AD8022 on Single Supply, 12 V
REV. 0
Figure 39. Frequency Response of Sallen-Key Filter
–13–
AD8022
J1
Figure 40.
R
G
715V
R
T
49.9V
R
0V
Figure 41.
R
R
F
715V
+V
S
–V
S
AMP #1
AD8022
C
R
O
0V
499V
+V
–V
G = 2
S
S
0.01mF
0.01mF
C3
C4
J3
J2
BYPASSING
R
715V
49.9V
C1
10mF
C2
10mF
G
R
C
0V
715V
AMP #2
F
AD8022
Figure 42.
G = 2
R
O
0V
499V
J4
Figure 43. Evaluation Board Schematic
–14–
REV. 0
OUTLINE DIMENSIONS
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
338
278
0.120 (3.05)
0.112 (2.84)
85
41
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.120 (3.05)
0.112 (2.84)
Dimensions shown in inches and (mm).
AD8022
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0098 (0.25)
0.0040 (0.10)
SEATING
0.1 968 (5.00)
0.1 890 (4.80)
85
0.0500 (1.27)
PLANE
8-Lead Plastic SOIC
(SO-8)
0.2440 (6.20)
0.2284 (5.80)
41
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0075 (0.19)
0.0196 (0.50)
0.0099 (0.25)
88
0.0500 (1.27)
08
0.0160 (0.41)
8-Lead microSOIC
(RM-8)
C3714–8–10/99
3 458
REV. 0
PRINTED IN U.S.A.
–15–
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