Datasheet AD8019ARU-REEL, AD8019ARU-EVAL, AD8019ARU, AD8019AR-REEL, AD8019AR-EVAL Datasheet (Analog Devices)

DSL Line Driver

FREQUENCY – kHz

132.5

10dB/DIV

137.5 142.5

–80dBc

a

FEATURES
Low Distortion, High Output Current Amplifiers

Operate from 12 V to ⴞ12 V Power Supplies,
Ideal for High-Performance ADSL CPE, and xDSL

Modems

Low Power Operation

9 mA/Amp (Typ) Supply Current

Digital (1-Bit) Power-Down
Voltage Feedback Amplifiers
Low Distortion

Out-of-Band SFDR –80 dBc @ 100 kHz into 100 ⍀ Line
High Speed

175 MHz Bandwidth (–3 dB), G = +1

400 V/␮s Slew Rate
High Dynamic Range

to within 1.2 V of Power Supply

V

OUT

APPLICATIONS
ADSL, VDSL, HDSL, and Proprietary xDSL USB, PCI,

PCMCIA Modems, and Customer Premise Equipment

(CPE)

8-Lead SOIC

AD8019AR

1

OUT1

2

–IN1

+IN1

3

–V

4

S

with Power-Down

PIN CONFIGURATIONS

14-Lead TSSOP

(R-8)

8

7

6

5

+V

OUT2

–IN2

+IN2

NC

S

OUT1

–IN1

+IN1

–V

S

PWDN

NC

AD8019

(RU-14)

1

AD8019ARU

2

3

4

5

6

7

NC = NO CONNECT

14

13

12

11

10

9

8

NC

+V

S

OUT2

–IN2

+IN2

NC

DGND

PRODUCT DESCRIPTION

The AD8019 is a low cost xDSL line driver optimized to drive a
minimum of 13 dBm into a 100 Ω load while delivering outstand­ing distortion performance. The AD8019 is designed on a 24 V
high-speed bipolar process enabling the use of ±12 V power
supplies or 12 V only. When operating from a single 12 V sup­ply the highly efficient amplifier architecture can typically deliver
170 mA output current into low impedance loads through a
1:2 turns ratio transformer. Hybrid designs using ±12 V supplies
enable the use of a 1:1 turns ratio transformer, minimizing attenu­ation of the receive signal. The AD8019 typically draws 9 mA/
amplifier quiescent current. A 1-bit digital power down feature
reduces the quiescent current to approximately 1.6 mA/amplifier.

Figure 1 shows typical Out of Band SFDR performance under
ADSL CPE (upstream) conditions. SFDR is measured while
driving a 13 dBm ADSL DMT signal into a 100 Ω line with
50 Ω back termination.

The AD8019 comes in thermally enhanced 8-lead SOIC and
14-lead TSSOP packages. The 8-lead SOIC is pin-compatible
with the AD8017 12 V line driver.

Figure 1. Out-of-Band SFDR; VS = ±12 V; 13 dBm Output

Ω

Power into 200

, Upstream

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD8019–SPECIFICATIONS

(@ 25ⴗC, VS = 12 V, RL = 25 ⍀, RF = 500 ⍀, T
otherwise noted.)

= –40ⴗC, T

MIN

= +85ⴗC, unless

MAX

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth G = +5 35 MHz

G = +1, V
G = +2, V

0.1 dB Bandwidth V

< 0.4 V p-p, RL = 100 Ω 6 MHz

OUT

G = +5, V

Large Signal Bandwidth V

= 4 V p-p 50 MHz

OUT

Slew Rate Noninverting, V
Rise and Fall Time Noninverting, V
Settling Time 0.1%, V

< 0.4 V p-p, RL = 100 Ω 175 180 MHz

OUT

< 0.4 V p-p, RL = 100 Ω 70 75 MHz

OUT

< 0.4 V p-p, RL = 100 Ω 35 MHz

OUT

= 4 V p-p 450 V/µs

OUT

= 2 V p-p 5.5 ns

OUT

= 2 V p-p 40 ns

OUT

NOISE/DISTORTION PERFORMANCE

Distortion V

Second Harmonic 100 kHz, R

Third Harmonic 100 kHz, R

Out-of-Band SFDR 144 kHz–1.1 MHz, Differential R
MTPR 25 kHz–138 kHz, Differential R

= 3 V p-p (Differential)

OUT

500 kHz, R

500 kHz, R

= 50 Ω –78 dBc

L(DM)

= 50 Ω –74 dBc

L(DM)

= 50 Ω –85 dBc

L(DM)

= 50 Ω –80 dBc

L(DM)

= 70 Ω –80 dBc

L

= 70 Ω –72 dBc

L

Input Voltage Noise f = 100 kHz 8 nV/√Hz
Input Current Noise f = 100 kHz 0.9 pA√Hz
Crosstalk f = 1 MHz, G = +2 –80 dB

DC PERFORMANCE

Input Offset Voltage 820mV

T

MIN–TMAX

10 23 mV

Input Offset Voltage Match 112mV

Open-Loop Gain V

T

MIN–TMAX

= 6 V p-p, RL = 25 Ω 72 80 dB

OUT

T

MIN–TMAX

72 80 dB

217mV

INPUT CHARACTERISTICS

Input Resistance 10 MΩ
Input Capacitance 0.5 pF
+Input Bias Current –3 +1 +3 µA

T

MIN–TMAX

–4 +4 µA

–Input Bias Current –1.5 –0.5 +1.5 µA

T

MIN–TMAX

–1.8 +1.8 µA

+Input Bias Current Match –1.0 –0.2 +1.0 µA

T

MIN–TMAX

–1.5 +1.5 µA

–Input Bias Current Match –0.5 +0.1 +0.5 µA

T

CMRR ∆V

MIN–TMAX

= –4 V to +4 V 71 74 dB

CM

–0.8 +0.8 µA

Input CM Voltage Range 2 10 V

OUTPUT CHARACTERISTICS

Output Resistance 0.2 Ω
Output Voltage Swing R
Output Current SFDR –80 dBc into 25 Ω at 100 kHz 175 200 mA
Short Circuit Current

1

= 25 Ω –4.8 +4.8 V

L

400 mA

POWER SUPPLY

Supply Current/Amp PWDN = 5 V 9 10.5 mA

T

MIN–TMAX

14.5 mA

PWDN = 0 V 0.8 2.0 mA

Operating Range Dual Supply ±4.0 ±6.0 V
Power Supply Rejection Ratio ∆±VS = +1.0 V to –1.0 V 65 68 dB

LOGIC LEVELS V

t

ON

t

OFF

PWDN = “1” Voltage 1.8 +V

= 0 V to 3 V; VIN = 10 MHz, G = +5

PWDN

120 ns
80 ns

S

V

PWDN = “0” Voltage 0.5 V
PWDN = “1” Bias Current 220 µA
PWDN = “0” Bias Current –100 µA

NOTES

1

This device is protected from overheating during a short-circuit by a thermal shutdown circuit.

Specifications subject to change without notice.

–2–

REV. 0

AD8019

(@ 25ⴗC, VS = ⴞ12 V, RL = 100 ⍀, RF = 500 ⍀, T

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Bandwidth G = +5 35 MHz

0.1 dB Bandwidth V
Large Signal Bandwidth V
Slew Rate Noninverting, V
Rise and Fall Time Noninverting, V
Settling Time 0.1%, V

NOISE/DISTORTION PERFORMANCE

Distortion V

Second Harmonic 100 kHz, R

Third Harmonic 100 kHz, R

Out-of-Band SFDR 144 kHz–500 kHz, Differential R
MTPR 25 kHz–138 kHz, Differential R
Input Voltage Noise f = 100 kHz 8 nV/√Hz
Input Current Noise f = 100 kHz 0.9 pA√Hz
Crosstalk f = 1 MHz, G = +2 –85 dB

DC PERFORMANCE

Input Offset Voltage 520mV

Input Offset Voltage Match 112mV

Open-Loop Gain V

INPUT CHARACTERISTICS

Input Resistance 10 MΩ
Input Capacitance 0.5 pF
+Input Bias Current –3 –0.5 +3 µA

–Input Bias Current –1.5 –0.2 +1.5 µA

+Input Bias Current Match –1.0 +0.2 +1.0 µA

–Input Bias Current Match –1.0 +0.1 +1.0 µA

CMRR ∆V
Input CM Voltage Range –10 +10 V

OUTPUT CHARACTERISTICS

Output Resistance 0.2 Ω
Output Voltage Swing RL = 100 Ω –10.8 +10.8 V
Output Current SFDR –80 dBc into 100 Ω at 100 kHz 125 170 mA
Short Circuit Current

1

POWER SUPPLY

Supply Current/Amp PWDN = High 9 10 mA

Operating Range Dual Supply ±4.0 ± 12 V
Power Supply Rejection Ratio ∆±VS = +1.0 V to –1.0 V 61 64 dB

LOGIC LEVELS V

t

ON

t

OFF

PWDN = “1” Voltage 1.8 +V
PWDN = “0” Voltage 0.5 V
PWDN = “1” Bias Current 220 µA
PWDN = “0” Bias Current –100 µA

NOTES

1

This device is protected from overheating during a short-circuit by a thermal shutdown circuit.

Specifications subject to change without notice.

REV. 0

= –40ⴗC, T

MIN

G = +1, V
G = +2, V

< 0.4 V p-p 5.5 MHz

OUT

= 4 V p-p 50 MHz

OUT

OUT

= 16 V p-p (Differential)

OUT

500 kHz, R

500 kHz, R

T

MIN–TMAX

T

MIN–TMAX

= 18 V p-p, RL = 100 Ω 86 92 dB

OUT

T

MIN–TMAX

T

MIN–TMAX

T

MIN–TMAX

T

MIN–TMAX

T

MIN–TMAX

= –10 V to +10 V 71 76 dB

CM

= +85ⴗC, unless otherwise noted.)

MAX

< 0.4 V p-p 175 180 MHz

OUT

< 0.4 V p-p 70 75 MHz

OUT

= 4 V p-p 400 V/µs

OUT

= 2 V p-p 5.5 ns

OUT

= 2 V p-p 40 ns

= 200 Ω –80 dBc

L(DM)

= 200 Ω –72 dBc

L(DM)

= 200 Ω –85 dBc

L(DM)

= 200 Ω –80 dBc

L(DM)

= 200 Ω –80 dBc

L

= 200 Ω –73 dBc

L

10 mV

218mV

90 dB

–3.8 +3.8 µA

–1.7 +1.7 µA

–2.4 +2.4 µA

–2.5 +2.5 µA

800 mA

T

MIN–TMAX

11.5 mA

PWDN = Low 0.8 1.75 mA

= 0 V to 3 V; VIN = 10 MHz, G = +5

PWDN

120 ns
80 ns

S

V

–3–

AD8019

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V

Internal Power Dissipation

TSSOP-14 Package
SOIC-8 Package

Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . . ± V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . ± V

2

. . . . . . . . . . . . . . . . . . . . . . . . . 2.2 W

3

. . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 W

S

S

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves

Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for device on a four-layer board with 10 inches2 of 1 oz. copper at

85°C 14-lead TSSOP package: θJA = 90°C/W.

3

Specification is for device on a four-layer board with 10 inches2 of 1 oz. copper at

85°C 8-lead SOIC package: θJA = 100°C/W.

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the AD8019
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for a plastic encapsulated
device is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package.

The output stage of the AD8019 is designed for maximum load
current capability. As a result, shorting the output to common
can cause the AD8019 to source or sink 500 mA. To ensure
proper operation, it is necessary to observe the maximum power
derating curves. Direct connection of the output to either power
supply rail can destroy the device.

2.5

2.0

1.5

1.0

0.5

MAXIMUM POWER DISSIPATION – W

TSSOP

SOIC

0

–40 –30 –20

–10

0102030

AMBIENT TEMPERATURE – ⴗC

Figure 2. Plot of Maximum Power Dissipation vs.
Temperature for AD8019 for T

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD8019ARU –40°C to +85°C 14-Lead TSSOP RU-14
AD8019ARU-Reel –40°C to +85°C 14-Lead TSSOP RU-14 Reel
AD8019ARU-EVAL –40°C to +85°C Evaluation Board ARU-EVAL
AD8019AR –40°C to +85°C 8-Lead SOIC R-8
AD8019AR-Reel –40°C to +85°C 8-Lead SOIC R-8 Reel
AD8019AR-EVAL –40°C to +85°C Evaluation Board AR EVAL

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8019 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

40 50 60 70 80

= 150°C

J

–4–

REV. 0

124⍀ 499⍀

R

L

V

IN

49.9⍀

0.1␮F

0.1␮F

+

+

10␮F

10␮F

TPC 1. Single-Ended Test Circuit; G = +5

Typical Performance Characteristics–AD8019

+V

55⍀

55⍀

S

+V

O

500⍀

R

500⍀

–V

S

L

–V

O

V

OUT

+V

IN

0.1␮F

+V

S

–V

S

+

47␮F

0.1␮F

–V

50⍀

0.1␮F

50⍀

IN

TPC 4. Differential Test Circuit; G = +10

100

80

60

40

20

– mV

0

OUT

V

–20

–40

–60

–80

–100

0 100 200 300 400 500 600 700

–100

TIME – ns

TPC 2. 100 mV Step Response; G = +5, VS = ±6 V,

= 25 Ω, Single-Ended

R

L

4

3

2

1

100

80

60

40

20

0

–20

VOLTS – mV

–40

–60

–80

–100

0 100 200 300 400 500 600 700

–100

TIME – 100ns/DIV

TPC 5. 100 mV Step Response; G = +5, VS = ±12 V,

= 100 Ω, Single-Ended

R

L

4

3

2

1

0

– Volts

OUT

V

–1

–2

–3

–4

0 100 200 300 400 500 600 700

–100

TIME – ns

TPC 3. 4 V Step Response; G = +5, VS = ±6 V,

= 25 Ω, Single-Ended

R

L

REV. 0

–5–

0

– Volts

OUT

V

–1

–2

–3

–4

0 100 200 300 400 500 600 700

–100

TIME – ns

TPC 6. 4 V Step Response; G = +5, VS = ±12 V,

= 100 Ω, Single-Ended

R

L

AD8019

–20

–30

–40

–50

–60

–70

DISTORTION – dBc

–80

–90

–100

0.01

2ND

0.1

FREQUENCY – MHz

3RD

1

5

TPC 7. Distortion vs. Frequency; VS = ±12 V, RL = 200 Ω,
Differential, V

–30

–40

–50

–60

–70

DISTORTION – dBc

–80

–90

= 16 V p-p

O

2ND HARMONIC

3RD HARMONIC

–20

–30

–40

–50

–60

–70

DISTORTION – dBc

–80

–90

–100

0.01

3RD

2ND

0.1

FREQUENCY – MHz

1

5

TPC 10. Distortion vs. Frequency; VS = ±6 V, RL = 50 Ω,
Differential, V

–20

–30

–40

–50

–60

–70

DISTORTION – dBc

–80

–90

= 3 V p-p

O

2ND

3RD

–100

50

75

100 125 150 175 200

PEAK OUTPUT CURRENT – mA

TPC 8. Distortion vs. Peak Output Current; VS = ±6 V;

= 10 Ω; f = 100 kHz; Single-Ended; Second Harmonic

R

L

–20

–30

–40

–50

–60

–70

DISTORTION – dBc

–80

–90

–100

50

2ND HARMONIC

3RD HARMONIC

100

75

125 150 175

PEAK OUTPUT CURRENT – mA

200

225

250

TPC 9. Distortion vs. Peak Output Current; VS = ±12 V;

= 25 Ω; f = 100 kHz; Single-Ended; Second Harmonic

R

L

–100

0

246 810

DIFFERENTIAL OUTPUT VOLTAGE – V p-p

12 14 16 18 20

TPC 11. Distortion vs. Output Voltage; f = 100 kHz,

= ±6 V, G = +10, RL = 50Ω, Differential

V

S

–10

–20

–30

–40

–50

–60

–70

DISTORTION – dBc

–80

–90

–100

–110

0246810

DIFFERENTIAL OUTPUT VOLTAGE – V p-p

2ND

3RD

12 14 16 18 20

TPC 12. Distortion vs. Output Voltage; f = 500 kHz,

= ±6 V, G = +10, RL = 50 Ω, Differential

V

S

–6–

REV. 0

–20

1000

FREQUENCY – MHz

–19

1

OUTPUT VOLTAGE – dBV

10010

–16

–13

–10

–7

–4

–1

2

5

8

11

1000

FREQUENCY – MHz

–19

1

OUTPUT VOLTAGE – dBV

10010

–16

–13

–10

–7

–4

–1

2

5

8

11

–30

–40

–50

–60

AD8019

–70

DISTORTION – dBc

–80

–90

–100

0

5 10152025

2ND

DIFFERENTIAL OUTPUT VOLTAGE – V p-p

3RD

30 35 40 45 50

TPC 13. Distortion vs. Output Voltage; f = 100 kHz,

= ±12 V, G = +10, RL = 200Ω, Differential

V

S

–10

–20

–30

–40

–50

–60

–70

DISTORTION – dBc

–80

–90

–100

–110

0 5 10 15 20 25

2ND

DIFFERENTIAL OUTPUT VOLTAGE – V p-p

3RD

30 35 40 45 50

TPC 14. Distortion vs. Output Voltage; f = 500 kHz,
V

= ±12 V, G = +10, RL = 200 Ω, Differential

S

TPC 16. Output Voltage vs. Frequency; VS = ±12 V,

= 100 Ω; G = +5

R

L

0

–10

–20

–30

–40

–50

CMRR – dB

–60

–70

–80

–90

0.10.01

V

IN

50⍀

1

FREQUENCY – MHz

909⍀

909⍀

909⍀

909⍀

50⍀

10010

50⍀

V

OUT

1000

TPC 17. CMRR vs. Frequency; VS = ±12 V, RL = 100

Ω

1.2

1.1

1.0

0.9

V

0.8

0.7

0.6

OUTPUT SATURATION VOLTAGE – Volts

0.5

TPC 15. Output Saturation Voltage vs. Load; VS = ±12 V,

= ±6 V

V

S

+25ⴗC

V

OH

V

OL

V

OH

LOAD CURRENT – mA

REV. 0

–40ⴗC

V

OH

OL

+85ⴗC

V

OL

10

10010.1

1000

TPC 18. Output Voltage vs. Frequency; VS = ±6 V,

= 100 Ω; G = +5

R

L

–7–

AD8019

–10

–20

–30

–PSRR

0.10.01

+PSRR

1

FREQUENCY – MHz

PSRR – dB

–40

–50

–60

–70

–80

–90

TPC 19. PSRR vs. Frequency; RL = 100

100

V

NOISE

10

+I

– nV Hz

NOISE

V

1

0.1

–I

0.10.01

NOISE

NOISE

1 10010

FREQUENCY – kHz

TPC 20. Noise vs. Frequency

–20

–30

–40

–50

–60

–70

CROSSTALK – dB

–80

–90

10010

1000

Ω

100

10

– pA Hz

NOISE

I

1

0.1

1000

–100

TPC 22. Crosstalk vs. Frequency, VS = ±12 V, VS = ±6 V;
G = +2; V

GAIN – dB

120

110

100

–10

–20

IN

90

80

70

60

50

40

30

20

10

0

0.001

0.10.01

= 10 dBm

A

OL

PHASE

0.01

1

FREQUENCY – MHz

500

⍀

50

⍀

10

⍀

10

⍀

FREQUENCY – MHz

10010

2k

⍀

50

⍀

50

⍀

1000

270

50

⍀

225

180

50

⍀

135

90

PHASE – Degrees

45

0

–45

10000.1 1 10 100

TPC 23. Open-Loop Gain and Phase vs. Frequency

V

IN

V

OUT

1.1k⍀

V

IN

20ns/DIV

6.8pF

1.1k⍀

50⍀

50⍀

50⍀

V

OUT

2mV/DIV ⴞ0.1%

TPC 21. Settling Time 0.1%; VS = ±12 V, RL = 100 Ω,

= 2 V p-p

V

OUT

–8–

V

IN

V

OUT

0.1%

ⴞ

2mV/DIV

1.1k⍀

V

IN

20ns/DIV

6.8pF

1.1k⍀

50⍀

50⍀

50⍀

V

OUT

TPC 24. Settling Time 0.1%; VS = ±6 V, RL = 100 Ω,

= 2 V p-p

V

OUT

REV. 0

AD8019

1000

100

10

1

0.1

OUTPUT IMPEDANCE – ⍀

0.01

0.001

0.01

0.1

1

FREQUENCY – MHz

10010

TPC 25. Output Impedance vs. Frequency; VS = ±12 V;
V

= ±6 V

S

V

V

OUT

0V

IN

V

OUT

= 2V/DIV

= 5V/DIV

0V

–2000V0

V

OUT

V

IN

400

800 1200 1600

TIME – ns

V
V

IN

OUT

= 1V/DIV

= 2V/DIV

TPC 28. Overload Recovery; VS = ±6 V, G = +5, RL = 100

V

= 1V/DIV

V

OUT

V

IN

OUT

= 2V/DIV

Ω

V

IN

0V

–100

0 100

300 400 500 600 700 800 900

200

TIME – ns

TPC 26. Overload Recovery; VS = ±12 V, G = +5, RL =100

V

= 2V/DIV

IN

V

OUT

= 5V/DIV

0V

0V

–100

0 100

V

OUT

V

IN

300 400 500 600 700 800 900

200

TIME – ns

TPC 27. Overload Recovery; VS = ±12 V, G = +5, RL = 100

V

IN

0V

–2000V0

TPC 29. Overload Recovery; VS = ±6 V, G = +5, RL = 100

Ω

400

800 1200 1600

TIME – ns

Ω

Ω

REV. 0

–9–

AD8019

0

–10

–20

–30

–40

MTPR – dBc

–50

–60

–70

–80

1.0

10dBm

1.1

12dBm

11dBm

1.2

TURNS RATIO – N

13dBm

1.3 1.4 1.5 1.6 1.7

TPC 30. MTPR vs. Turns Ratio; VS = ±6 V, RL = 100 Ω Line

–30

–40

–50

–60

MTPR – dBc

–70

–80

1.0

17dBm

16dBm

1.1

18dBm

13dBm

1.2

1.3 1.4 1.5 1.6 1.7

TURNS RATIO – N

TPC 31. MTPR vs. Turns Ratio; VS = ±12 V, RL = 100 Ω Line

–30

–40

–50

–60

SFDR – dBc

–70

–80

–90

1.0

10dBm

1.1

11dBm

1.2

13dBm

12dBm

1.3 1.4 1.5 1.6 1.7

TURNS RATIO – N

TPC 32. SFDR vs. Turns Ratio; VS = ±6 V, RL = 100 Ω Line

–50

17dBm

16dBm

1.1

18dBm

13dBm

1.2

1.3 1.4 1.5 1.6 1.7

TURNS RATIO – N

–55

–60

–65

–70

SFDR – dBc

–75

–80

–85

–90

1.0

TPC 33. SFDR vs. Turns Ratio; VS = ±12 V, RL = 100 Ω Line

–10–

REV. 0

AD8019

GENERAL INFORMATION

The AD8019 is a voltage feedback amplifier with high output
current capability. As a voltage feedback amplifier, the AD8019
features lower current noise and more applications flexibility than
current feedback designs. It is fabricated on Analog Devices’
proprietary High Voltage eXtra Fast Complementary Bipolar
Process (XFCB-HV), which enables the construction of PNP
and NPN transistors with similar f

s in the 4 GHz region. The

T

process is dielectrically isolated to eliminate the parasitic and
latch-up problems caused by junction isolation. These features
enable the construction of high-frequency, low-distortion amplifiers.

POWER-DOWN FEATURE

A digitally programmable logic pin (PWDN) is available on the
TSSOP-14 package. It allows the user to select between two
operating conditions, full on and shutdown. The DGND pin is
the logic reference. The threshold for the PWDN pin is typically

1.8 V above DGND. If the power-down feature is not being
used, it is better to tie the DGND pin to the lowest potential
that the AD8019 is tied to and place the PWDN pin at a poten­tial at least 3 V higher than that of the DGND pin, but lower
than the positive supply voltage.

POWER SUPPLY AND DECOUPLING

The AD8019 can be powered with a good quality (i.e., low-noise)
supply anywhere in the range from +12 V to ±12 V. In order to
optimize the ADSL upstream drive capability of 13 dBm and
maintain the best Spurious Free Dynamic Range (SFDR), the
AD8019 circuit should be powered with a well-regulated supply.

Careful attention must be paid to decoupling the power supply.
High quality capacitors with low equivalent series resistance
(ESR) such as multilayer ceramic capacitors (MLCCs) should
be used to minimize supply voltage ripple and power dissipa­tion. In addition, 0.1 µF MLCC decoupling capacitors should
be located no more than 1/8 inch away from each of the power
supply pins. A large, usually tantalum, 10 µF to 47 µF capacitor
is required to provide good decoupling for lower frequency
signals and to supply current for fast, large signal changes at
the AD8019 outputs.

POWER DISSIPATION

It is important to consider the total power dissipation of the
AD8019 in order to properly size the heat sink area of an appli­cation. Figure 3 is a simple representation of a differential driver.
With some simplifying assumptions we can estimate the total
power dissipated in this circuit. If the output current is large
compared to the quiescent current, computing the dissipation
in the output devices and adding it to the quiescent power dissipa­tion will give a close approximation of the total power dissipation in
the package. A factor α (~0.6-1) corrects for the slight error
due to the Class A/B operation of the output stage. It can be
estimated by subtracting the quiescent current in the output
stage from the total quiescent current and ratioing that to the
total quiescent current. For the AD8019, α = 0.833.

+V

S

+V

O

R

L

–V

S

+V

S

–V

O

–V

S

Figure 3. Simplified Differential Driver

Remembering that each output device only dissipates for half
the time gives a simple integral that computes the power for
each device:



1

( – )

VV

∫×

SO



2





()

V

2

O



R

L



The total supply power can then be computed as:

1

PVVV IVP

=∫−∫×+ +4

TOT S O O Q S OUT

(|| ) α

2

2

2

In this differential driver, VO is the voltage at the output of one
amplifier, so 2 V

is the voltage across RL. RL is the total

O

impedance seen by the differential driver, including back
termination. Now, with two observations the integrals are easily
evaluated. First, the integral of V
rms value of V
average rectified value of V

. Second, the integral of | VO | is equal to the

O

O

2

is simply the square of the

O

, sometimes called the mean average
deviation, or MAD. It can be shown that for a DMT signal, the
MAD value is equal to 0.8 times the rms value.

1

PVrmsVVrmsRIV P

=×++408

TOT O S O

(. – ) α

2

2

L

Q S OUT

For the AD8019 operating on a single 12 V supply and delivering a
total of 16 dBm (13 dBm to the line and 3 dBm to the matching
network) into 17.3 Ω (100 Ω reflected back through a 1:1.7
transformer plus back termination), the dissipated power is:

= 332 mW + 40 mW

= 372 mW
Using these calculations and a θ

of 90°C/W for the TSSOP

JA

package and 100°C/W for the SOIC, Tables I–IV show junc­tion temperature versus power delivered to the line for several
supply voltages while operating with an ambient temperature
of 85°C. The shaded areas indicate operation at a junction
temperature over the absolute maximum rating of 150°C, and
should be avoided.

Table I. Junction Temperature vs. Line Power and Operating
Voltage for TSSOP

V

P

, dBm ⴞ12 ⴞ12.5 ⴞ13

LINE

SUPPLY

13 132 134 137
14 134 137 139
15 136 139 141
16 139 141 144
17 141 144 147
18 143 147 150

REV. 0

–11–

AD8019

Table II. Junction Temperature vs. Line Power and Operating
Voltage for SOIC

V

P

, dBm ⴞ12 ⴞ12.5 ⴞ13

LINE

SUPPLY

13 137 140 143
14 140 142 145
15 142 145 148
16 145 148 151
17 147 150 154
18 150 153 157

Table III. Junction Temperature vs. Line Power and
Operating Voltage for TSSOP

V

SUPPLY

P

, dBm +12 +13

LINE

13 115 118
14 116 119
15 118 121
16 120 123

Table IV. Junction Temperature vs. Line Power and
Operating Voltage for SOIC

V

SUPPLY

P

, dBm +12 +13

LINE

13 118 121
14 120 123
15 122 125
16 124 128

Thermal stitching, which connects the outer layers to the inter­nal ground plane(s), can help to utilize the thermal mass of the
PCB to draw heat away from the line driver and other active
components.

LAYOUT CONSIDERATIONS

As is the case with all high-speed applications, careful attention
to printed circuit board layout details will prevent associated
board parasitics from becoming problematic. Proper RF design
technique is mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the board
to provide a low-impedance return path. Removing the ground
plane on all layers from the areas near the input and output pins
will reduce stray capacitance, particularly in the area of the
inverting inputs. The signal routing should be short and direct
in order to minimize parasitic inductance and capacitance asso­ciated with these traces. Termination resistors and loads should
be located as close as possible to their respective inputs and
outputs. Input and output traces should be kept as far apart as
possible to minimize coupling (crosstalk) though the board.

Wherever there are complementary signals, a symmetrical
layout should be provided to the extent possible to maximize
balanced performance. When running differential signals over a
long distance, the traces on the PCB should be close together or
any differential wiring should be twisted together to minimize
the area of the loop that is formed. This will reduce the radiated

energy and make the circuit less susceptible to RF interference.
Adherence to stripline design techniques for long signal traces
(greater than about 1 inch) is recommended.

Evaluation Board

The AD8019 is available installed on an evaluation board for
both package styles. Figures 8 and 9 show the schematics for the
TSSOP evaluation board.

The receiver circuit on these boards is typically unpopulated.
Requesting samples of the AD8022AR, along with either of the
AD8019 evaluation boards, will provide the capability to evaluate
the AD8019 along with other Analog Devices products in a typical
transceiver circuit. The evaluation circuits have been designed
to replicate the CPE side analog transceiver hybrid circuits.

The circuit mentioned above is designed using a 1-transformer
transceiver topology including a line receiver, line driver, line
matching network, an RJ11 jack for interfacing to line simula­tors, and differential inputs.

AC-coupling capacitors of 0.1 µF, C8, and C10, in combination
with 10 kΩ, resistors R24 and R25, will form a 1st order high­pass pole at 160 Hz.

Transformer Selection

Customer premise ADSL requires the transmission of a 13 dBm
(20 mW) DMT signal. The DMT signal has a crest factor of 5.3,
requiring the line driver to provide peak line power of 560 mW.
560 mW peak line power translates into a 7.5 V peak voltage on
a 100 Ω telephone line. Assuming that the maximum low distor­tion output swing available from the AD8019 line driver on a
±12 V supply is 20 V and taking into account the power lost due
to the termination resistance, a step-up transformer with turns
ratio of 1:1 is adequate for most applications. If the modem
designer desires to transmit more than 13 dBm down the twisted
pair, a higher turns ratio can be used for the transformer. This
trade-off comes at the expense of higher power dissipation by
the line driver as well as increased attenuation of the downstream
signal that is received by the transceiver.

In the simplified differential drive circuit shown in Figure 7,
the AD8019 is coupled to the phone line through a step-up
transformer with a 1:1 turns ratio. R1 and R2 are back termi­nation or line matching resistors, each 50 Ω (100 Ω/(2 × 1

2

))

where 100 Ω is the approximate phone line impedance. A
transformer reflects impedance from the line side to the IC
side as a value inversely proportional to the square of the turns
ratio. The total differential load for the AD8019, including the
termination resistors, is 200 Ω. Even under these conditions
the AD8019 provides low distortion signals to within 2 V of
the power supply rails.

One must take care to minimize any capacitance present at the
outputs of a line driver. The sources of such capacitance can
include, but are not limited to EMI suppression capacitors,
overvoltage protection devices and the transformers used in the
hybrid. Transformers have two kinds of parasitic capacitances,
distributed, or bulk capacitance, and interwinding capacitance.
Distributed capacitance is a result of the capacitance created
between each adjacent winding on a transformer. Interwinding
capacitance is the capacitance that exists between the windings
on the primary and secondary sides of the transformer. The
existence of these capacitances is unavoidable, but in specifying

–12–

REV. 0

AD8019

a transformer, one should do so in a way to minimize them in
order to avoid operating the line driver in a potentially unstable
environment. Limiting both distributed and interwinding capaci­tance to less than 20 pF each should be sufficient for most
applications.

Stability Enhancements

Voltage feedback amplifiers may exhibit sensitivity to capaci­tance present at the inverting input. Parasitic capacitance, as small
as several picofarads, in combination with the high-impedance of
the input can create a pole that can dramatically decrease the phase
margin of the amplifier. In the case of the AD8019, a compen­sation capacitor of 10 pF–20 pF in parallel with the feedback
resistor will form a zero that can serve to cancel out the effects
of the parasitic capacitance. Placing 100 Ω in series with each of
the noninverting inputs serves to isolate the inputs from each
other and from any high frequency signals that may be coupled
into the amplifier via the midsupply bias.

It may also be necessary to configure the line driver as two sepa­rate, noninverting amplifiers rather than a single differential
driver. When doing this, the two gain resistors can share an ac
coupling capacitor of 0.1 µF to minimize any dc errors.

Adhering to previously mentioned layout techniques will also be
of assistance in keeping the amplifier stable.

Receive Channel Considerations

A transformer used at the output of the differential line driver to
step up the differential output voltage to the line has the inverse
effect on signals received from the line. A voltage reduction or
attenuation equal to the inverse of the turns ratio is realized in
the receive channel of a typical bridge hybrid. The turns ratio of
the transformer may also be dictated by the ability of the receive
circuitry to resolve low-level signals in the noisy twisted pair tele­phone plant. While higher turns ratio transformers boost transmit
signals to the appropriate level, they also effectively reduce the
received signal to noise ratio due to the reduction in the received
signal strength.

Using a transformer with as low a turns ratio as possible will limit
degradation of the received signal.

The AD8022, a dual amplifier with typical RTI voltage noise of
only 2.5 nV/√Hz and a low supply current of 4 mA/amplifier is
recommended for the receive channel.

DMT Modulation, Multi-Tone Power Ratio (MTPR) and
Out-of-Band SFDR

ADSL systems rely on Discrete Multi-Tone (or DMT) modula­tion to carry digital data over phone lines. DMT modulation
appears in the frequency domain as power contained in several
individual frequency subbands, sometimes referred to as tones
or bins, each of which are uniformly separated in frequency. A
uniquely encoded, Quadrature Amplitude Modulation (QAM)­like signal occurs at the center frequency of each subband or
tone. See Figure 4 for an example of a DMT waveform in the
frequency domain, and Figure 5 for a time domain waveform.
Difficulties will exist when decoding these subbands if a QAM
signal from one subband is corrupted by the QAM signal(s)

from other subbands, regardless of whether the corruption
comes from an adjacent subband or harmonics of other subbands.

Conventional methods of expressing the output signal integrity
of line drivers such as single tone harmonic distortion or THD,
two-tone Intermodulation Distortion (IMD) and third order
intercept (IP3) become significantly less meaningful when
amplifiers are required to process DMT and other heavily
modulated waveforms. A typical ADSL upstream DMT signal
can contain as many as 27 carriers (subbands or tones) of QAM
signals. Multi-Tone Power Ratio (MTPR) is the relative differ­ence between the measured power in a typical subband (at one
tone or carrier) versus the power at another subband specifi­cally selected to contain no QAM data. In other words, a
selected subband (or tone) remains open or void of intentional
power (without a QAM signal) yielding an empty frequency bin.
MTPR, sometimes referred to as the ‘empty bin test,’ is typically
expressed in dBc, similar to expressing the relative difference
between single tone fundamentals and second or third harmonic
distortion components. Measurements of MTPR are typically
made on the line side or secondary side of the transformer.

20

0

–20

–40

POWER – dBm

–60

–80

0 100 150

Figure 4. DMT Waveform in the Frequency Domain

50

FREQUENCY – kHz

MTPR versus transformer turns ratio is depicted in TPCs 30 and
31 and covers a variety of line power ranging from 10 dBm to
18 dBm. As the turns ratio increases, the driver hybrid can
deliver more undistorted power to the load due to the high
output current capability of the AD8019. Significant degrada­tion of MTPR will occur if the output of the driver swings to
the rails, causing clipping at the DMT voltage peaks. Driving
DMT signals to such extremes not only compromises “in band”
MTPR, but will also produce spurs that exist outside of the
frequency spectrum containing the transmitted signal. “Out­of-band” spurious free dynamic range (SFDR) can be defined
as the relative difference in amplitude between these spurs and a
tone in one of the upstream bins. Compromising out-of-band
SFDR is the equivalent of increasing near-end cross talk (NEXT).
Regardless of terminology, maintaining out-of-band SFDR
while reducing NEXT will improve the overall performance of
the modems connected at either end of the twisted pair.

REV. 0

–13–

AD8019

Generating DMT Signals

At this time, DMT-modulated waveforms are not typically
menu-selectable items contained within arbitrary waveform
generators. Even using (AWG) software to generate DMT sig­nals, AWGs that are available today may not deliver DMT
signals sufficient in performance with regard to MTPR due to
limitations in the D/A converters and output drivers used by
AWG manufacturers. Similar to evaluating single-tone distor­tion performance of an amplifier, MTPR evaluation requires a
DMT signal generator capable of delivering MTPR performance
better than that of the driver under evaluation. Generating
DMT signals can be accomplished using a Tektronics AWG
2021 equipped with Option 4, (12-/24-bit, TTL Digital Data
Out), digitally coupled to Analog Devices’ AD9754, a 14-bit
TxDAC

®

, buffered by an AD8002 amplifier configured as a
differential driver. Note that the DMT waveforms, available on
the Analog Devices website, www.analog.com, or similar. WFM
files are needed to produce the necessary digital data required to
drive the TxDAC from the optional TTL Digital Data output of
the TEK AWG2021.

+12V

301⍀

301⍀

0.1␮F

P

OUT

16dBm

V

IN

0.1␮F

0.1␮F

10k⍀

10k⍀

6V

0.1␮F

100⍀

0.1␮F

100⍀

50⍀

50⍀

Figure 6. Recommended Application Circuit for Single +12 V Supply

4

3

2

1

VOLTS

0

–1

–2

–3

–0.25 –0.15 –0.05 0

Figure 5. DMT Signal in the Time Domain

10␮F

R1

17.3⍀

RL = 100⍀

R2

17.3⍀

1:1.7

TRANSFORMER

LINE

POWER

13dBm

TIME – ms

0.10 0.15 0.20

0.05–0.10–0.20

0.1␮F

V

IN

0.1␮F

100⍀

10k⍀

0.1␮F

10k⍀

100⍀

Figure 7. Recommended Application Circuit for ±12 V Supply

TxDAC is a registered trademark of Analog Devices, Inc.

50⍀

50⍀

–12V

+12V

301⍀

301⍀

0.1␮F

0.1␮F

–14–

P

OUT

16dBm

10␮F

R1

12.4⍀

R2

12.4⍀

1:1

TRANSFORMER

10␮F

RL = 100⍀

LINE

POWER

13dBm

REV. 0

AD8019

R38

DNI

R28

VCC

DNI

C9

DNI

DNI

P1

123

R32

100⍀

10

789

NC = 5,6

TP1

C6

DNI

T1

78

6

5

4

TP2

TP19

VCC

C23

DNI

U2 DECOUPLING

C15

0.01␮F

C26

0.1␮F

+

1

2

3

4

L5

BEAD

C27

DNI

R4

R19

DNI

DNI

301⍀

TP23 TP24 TP25 TP26

VEE

PR2

C12

R21

AD8019

5

DNI

DNI

–V

11

B

TP9

DNI

R37

DNI

R39

TP8

12

VCC

13

U1

+V

10

C7

DNI

DNI

301⍀

R2

DNI

50⍀

DNI

R1

100⍀

1WATT

2

1

C13

0.1␮F

R42

DNI

C29

DNI

R35

PR1

TP7

DNI

C11

DNI

R20

A

TP6

2

AD8019

13

U1

5

–V

+V

3

4

R36

C22

R3

R18

VEE

TB1 1

C2

DNI

C1

DNI

C14

10␮F

VCCIN

TP4

25V

3

R9

DNI

VEE

TP12

U1 DECOUPLING

L1

BEAD

JP5

B

DNI

TB1 3

JP6

1

A

2

VCC-2

R10

DNI

TB1 2

R23

C4

C17

C20

C21

C18

10␮F

DNI

0.1␮F

0.1␮F

+

25V

DNI

U2 DECOUPLING

U1 DECOUPLING

TP5

C3

DNI

DNI

R22

R13

DNI

C16

*DNI : DO NOT INSTALL

DNI

REV. 0

TP10

R30

R29

2
A

JP3

10k⍀

1

P4 3

R41

R15

DNI

50⍀

VCC

A

R14

100⍀

DNI

R12

C10

0.1␮F

TP11

0⍀

R31

S6

3

C5

0.1␮F

B

2
A

JP4

1

JP7

A

1

VCC-2

2

DNI

C28

B

3

P4 1

P4 2

DNI

R40

R8

100⍀

R24

10k⍀

C8

0.1␮F

50⍀

R11

B

0⍀

S5

3

VCC

3

VCC;8

VEE;4

1

R33

U2

DNI

2

AD8022

TP17

S3

VCC

Figure 8. TSSOP Noninverting DSL Evaluation Board Schematic

–15–

R6

R5

DNI

P3 3

DNI

P3 2

5k⍀

R16

R7

P3 1

DNI

TP3

6

AD8022

TP18

VCC-2

R34

U2

S4

R17

DNI

5

7

C19

5k⍀

VCC;8

VEE;4

0.1␮F

AD8019

VCC

R25
VAL

R26
VAL

R27
VAL

JP1

9

NC4

1

A

2

B

3

C24
VAL

6

PWDN

DGND

AD8019

U1

NC1 NC2 NC3

8

1714

Figure 9. DSL Driver Input Control Circuit

Figure 10. TSSOP Evaluation Board Silkscreen Top

Figure 11. TSSOP Evaluation Board Silkscreen Bottom

AGND

2

AGND

Figure 12. TSSOP Evaluation Board Power Plane

–16–

REV. 0

AD8019

Figure 13. Solder Mask Top

Figure 14. Solder Mask Bottom

Figure 15. Ground Plane Bottom

Figure 16. Assembly Top

REV. 0

–17–

AD8019

Figure 17. Ground Plane Top

Figure 18. Assembly Bottom

–18–

REV. 0

AD8019

REV. 0

Figure 19. Board Fabrication

–19–

AD8019

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

14-Lead TSSOP

(RU-14)

0.201 (5.10)

0.193 (4.90)

PIN 1

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0098 (0.25)

0.0040 (0.10)

SEATING

14 8

0.0433 (1.10)

0.0118 (0.30)

0.0256
(0.65)

0.0075 (0.19)

BSC

0.1968 (5.00)

0.1890 (4.80)

85

0.0500 (1.27)
BSC

0.0192 (0.49)

0.0138 (0.35)

PLANE

0.177 (4.50)

0.169 (4.30)

0.256 (6.50)

71

0.246 (6.25)

MAX

0.0079 (0.20)

0.0035 (0.090)

8-Lead SOIC

(R-8)

0.2440 (6.20)

0.2284 (5.80)

41

0.102 (2.59)

0.094 (2.39)

8ⴗ
0ⴗ

0.0098 (0.25)

0.0075 (0.19)

0.0196 (0.50)

0.0099 (0.25)

8ⴗ
0ⴗ

0.0500 (1.27)

0.0160 (0.41)

C02551–1.5–4/01(0)

0.028 (0.70)

0.020 (0.50)

ⴛ 45ⴗ

–20–

PRINTED IN U.S.A.

REV. 0