Dual High Output Current,
a
FEATURES
High Output Drive Capability
20 V p-p Differential Output Voltage, R
10 V p-p Single-Ended Output Voltage While
Delivering 200 mA to a 25 ⍀ Load
Low Power Operation
+5 V to +12 V Voltage Supply @ 7 mA/Amplifier
Low Distortion
–78 dBc @ 500 kHz SFDR, R
= 100 ⍀, VO = 2 V p-p
L
–58 dBc Highest Harmonic @ 1 MHz, I
= 10 ⍀)
(R
L
High Speed
160 MHz, –3 dB Bandwidth (G = +2)
1600 V/s Slew Rate
APPLICATIONS
xDSL PCI Cards
Consumer DSL Modems
Line Driver
Video Distribution
PRODUCT DESCRIPTION
The AD8017 is a low cost, dual high speed amplifier capable of
driving low distortion signals to within 1.0 V of the supply rail.
It is intended for use in single supply xDSL systems where low
distortion and low cost are essential. The amplifiers will be able
to drive a minimum of 200 mA of output current per amplifier.
The AD8017 will deliver –78 dBc of SFDR at 500 kHz, required
for many xDSL applications.
Fabricated in ADI’s high speed XFCB process, the high bandwidth and fast slew rate of the AD8017 keep distortion to a
minimum, while dissipating a minimum amount of power. The
quiescent current of the AD8017 is 7 mA/amplifier.
Low distortion, high output voltage drive, and high output
current drive make the AD8017 ideal for use in low cost Customer Premise End (CPE) equipment for ADSL, SDSL, VDSL
and proprietary xDSL systems.
= 50 ⍀
L
= 270 mA
O
High Speed Amplifier
AD8017
PIN CONFIGURATION
8-Lead Thermal Coastline SOIC (SO-8)
AD8017
1
OUT1
2
12
10
8
6
4
OUTPUT VOLTAGE SWING – V p-p
2
0
–IN1
+IN1
1
–
+
3
–V
4
S
VS = ⴞ6V
VS = ⴞ2.5V
LOAD RESISTANCE – ⍀
Figure 1. Output Swing vs. Load Resistance
The AD8017 drive capability comes in a very compact form.
Utilizing ADI’s proprietary Thermal Coastline SOIC package,
the AD8017’s total (static and dynamic) power on +12 V supplies is easily dissipated without external heatsink, other than to
place the AD8017 on a 4-layer PCB.
The AD8017 will operate over the commercial temperature
range –40°C to +85°C.
+V
S
+
R1
8
+V
S
7
OUT2
6
–IN2
–
+
5
+IN2
10010
1000
+
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
= 100⍀
R
V
IN
–
–V
V
REF
R2
N
:N
S
P
S
TRANSFORMER
L
OR
135⍀
LINE
V
OUT
POWER
IN dB
–
Figure 2. Differential Drive Circuit for xDSL Applications
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
AD8017–SPECIFICATIONS
(@ +25ⴗC, VS = ⴞ6 V, RL = 100 ⍀, RF = RG = 619 ⍀, unless otherwise noted)
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth G = +2, V
0.1 dB Bandwidth V
Large Signal Bandwidth V
< 0.4 V p-p 70 MHz
OUT
= 4 V p-p 105 MHz
OUT
Slew Rate Noninverting, V
Rise and Fall Time Noninverting, V
Settling Time 0.1%, V
< 0.4 V p-p 100 160 MHz
OUT
= 2 V p-p, G = +2 1600 V/µs
OUT
= 2 V p-p 2.6 ns
OUT
= 4 V Step 35 ns
OUT
Overload Recovery VIN = 5 V p-p 74 ns
NOISE/HARMONIC PERFORMANCE
Distortion V
2nd Harmonic 500 kHz, R
3rd Harmonic 500 kHz, R
IP3 500 kHz, R
IMD 500 kHz, R
= 2 V p-p
OUT
1 MHz, R
1 MHz, R
= 100 Ω/25 Ω –78/–71 dBc
L
= 100 Ω/25 Ω –76/–69 dBc
L
= 100 Ω/25 Ω –105/–91 dBc
L
= 100 Ω/25 Ω –81/–72 dBc
L
= 100 Ω/25 Ω 40/35 dBm
L
= 100 Ω/25 Ω –76/–66 dBc
L
MTPR 26 kHz to 1.1 MHz –66 dBc
Input Noise Voltage f = 10 kHz 1.9 nV/√Hz
Input Noise Current f = 10 kHz (+ Inputs) 23 pA√Hz
f = 10 kHz (– Inputs) 21 pA√Hz
Crosstalk f = 5 MHz, G = +2 –66 dB
DC PERFORMANCE
Input Offset Voltage 1.8 3.0 mV
4.0 mV
Open Loop Transimpedance V
T
MIN–TMAX
= 2 V p-p 185 700 kΩ
OUT
T
MIN–TMAX
143 kΩ
INPUT CHARACTERISTICS
Input Resistance +Input 50 kΩ
Input Capacitance +Input 2.4 pF
Input Bias Current (+) 16 ±45 µA
T
MIN–TMAX
±67 µA
Input Bias Current (–) 1.0 ±25 µA
CMRR V
T
MIN–TMAX
= ±2.5 V 59 63 dB
CM
±32 µA
Input CM Voltage Range ±5.1 V
OUTPUT CHARACTERISTICS
Output Resistance 0.2 Ω
Output Voltage Swing R
Output Current
1
= 25 Ω±4.6 ±5.0 V
L
Highest Harmonic < –58 dBc, 200 270 mA
f = 1 MHz, R
T
MIN–TMAX
= 10 Ω
L
, Highest Harmonic < –52 dBc 100 mA
Short-Circuit Current 1500 mA
POWER SUPPLY
Supply Current/Amp 7.0 7.7 mA
T
MIN–TMAX
7.8 mA
Operating Range Dual Supply ±2.2 ± 6.0 V
Power Supply Rejection Ratio 58 61 dB
Operating Temperature Range –40 +85 °C
NOTES
1
Output current is defined here as the highest current load delivered by the output of each amplifier into a specified resistive load ( RL = 10 Ω), while maintaining an
acceptable distortion level (i.e., less than –60 dBc highest harmonic) at a given frequency (f = 1 MHz).
Specifications subject to change without notice.
–2–
REV. A
AD8017
SPECIFICATIONS
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth G = +2, V
0.1 dB Bandwidth V
Large Signal Bandwidth V
Slew Rate Noninverting, V
Rise and Fall Time Noninverting, V
Settling Time 0.1%, V
Overload Recovery VIN = 2.5 V p-p 74 ns
NOISE/HARMONIC PERFORMANCE
Distortion V
2nd Harmonic 500 kHz, R
3rd Harmonic 500 kHz, R
IP3 500 kHz, R
IMD 500 kHz, R
MTPR 26 kHz to 1.1 MHz –66 dBc
Input Noise Voltage f = 10 kHz 1.8 nV/√Hz
Input Noise Current f = 10 kHz (+ Inputs) 23 pA√Hz
Crosstalk f = 5 MHz, G = +2 –66 dB
DC PERFORMANCE
Input Offset Voltage 0.8 2.0 mV
Open Loop Transimpedance V
INPUT CHARACTERISTICS
Input Resistance +Input 50 kΩ
Input Capacitance +Input 2.4 pF
Input Bias Current (+) 16 ±40 µA
Input Bias Current (–) 2 ±25 µA
CMRR V
Input CM Voltage Range ±1.6 V
OUTPUT CHARACTERISTICS
Output Resistance 0.2 Ω
Output Voltage Swing R
Output Current
Short-Circuit Current 1300 mA
POWER SUPPLY
Supply Current/Amp 6.2 7 mA
Operating Range Dual Supply ±2.2 ± 6.0 V
Power Supply Rejection Ratio 59 62 dB
Operating Temperature Range –40 +85 °C
NOTES
1
Output current is defined here as the highest current load delivered by the output of each amplifier into a specified resistive load ( RL = 10 Ω), while maintaining an
acceptable distortion level (i.e., less than –60 dBc highest harmonic) at a given frequency (f = 1 MHz).
Specifications subject to change without notice.
1
(@ +25ⴗC, VS = ⴞ2.5 V, RL = 100 ⍀, RF = RG = 619 ⍀, unless otherwise noted)
< 0.4 V p-p 75 120 MHz
OUT
< 0.4 V p-p 40 MHz
OUT
= 4 V p-p 100 MHz
OUT
OUT
= 2 V p-p
OUT
1 MHz, R
1 MHz, R
= 2 V Step 35 ns
L
= 100 Ω/25 Ω –73/–66 dBc
L
L
= 100 Ω/25 Ω –79/–74 dBc
L
L
L
= 2 V p-p, G = +2 800 V/µs
OUT
= 2 V p-p 2.0 ns
OUT
= 100 Ω/25 Ω –75/–68 dBc
= 100 Ω/25 Ω –91/–88 dBc
= 100 Ω/25 Ω 40/36 dBm
= 100 Ω/25 Ω –78/–64 dBc
f = 10 kHz (– Inputs) 21 pA√Hz
T
MIN–TMAX
= 2 V p-p 40 166 kΩ
OUT
T
MIN–TMAX
T
MIN–TMAX
T
MIN–TMAX
= ±1.0 (±1.0) 57 60 dB
CM
= 25 Ω±1.55 ±1.65 V
L
45 kΩ
Highest Harmonic < –55 dBc, 100 120 mA
f = 1 MHz, R
T
MIN–TMAX
T
MIN–TMAX
= 10 Ω
L
Highest Harmonic < 50 dBc 60 mA
2.6 mV
±62 µA
±32 µA
7.3 mA
–3–REV. A
AD8017
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 V
Internal Power Dissipation
2
1
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ± 2.5 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device on a two-layer board with 2500 mm2 of 2 oz. copper at
+25°C 8-lead SOIC package: θJA = 95.0°C/W.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8017
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
device is determined by the glass transition temperature of the
plastic, approximately +150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a junction temperature of +175°C for an extended period can result in
device failure.
The output stage of the AD8017 is designed for maximum load
current capability. As a result, shorting the output to common
can cause the AD8017 to source or sink 500 mA. To ensure
proper operation, it is necessary to observe the maximum power
derating curves. Direct connection of the output to either power
supply rail can destroy the device.
2.0
1.5
TJ = +150ⴗC
1.0
0.5
MAXIMUM POWER DISSIPATION – Watts
0
09010
TJ = +125ⴗC
20 30 40 50 60 70 80
AMBIENT TEMPERATURE – ⴗC
Figure 3. Plot of Maximum Power Dissipation vs.
Temperature for AD8017
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD8017AR –40°C to +85°C 8-Lead SOIC SO-8
AD8017AR-REEL –40°C to +85°C Tape and Reel 13" SO-8
AD8017AR-REEL7 –40°C to +85°C Tape and Reel 7" SO-8
AD8017AR-EVAL Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8017 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. A
Typical Performance Characteristics–
619⍀ 619⍀
R
L
V
OUT
+V
S
–V
S
10F
10F
+
+
0.1F
0.1F
54.4⍀
V
IN
AD8017
619⍀ 619⍀
V
IN
49.9⍀
0.1F
0.1F
+
10F
+
10F
V
OUT
R
L
+V
S
–V
S
Figure 4. Test Circuit: Gain = +2
OUTPUT = 100mV
25mV/DIV
INPUT = 50mV
200ns/DIV
Figure 5. 100 mV Step Response; G = +2, VS = ±2.5 V or
±
6 V, RL = 100
Ω
Figure 7. Test Circuit: Gain = –1
OUTPUT = 100mV
INPUT = 100mV
50mV/DIV 25 mV/DIV
200ns/DIV
Figure 8. 100 mV Step Response; G = –1, VS = ±2.5 V or
±
6 V, RL = 100
Ω
OUTPUT = 4V
1V/DIV
INPUT = 2V
200ns/DIV
Figure 6. 4 V Step Response; G = +2, VS = ±6 V,
= 100
R
L
Ω
OUTPUT = 4V
2V/DIV 1V/DIV
INPUT = 4V
200ns/DIV
Figure 9. 4 V Step Response; G = –1, VS = ±6 V,
= 100
R
L
Ω
–5–REV. A
AD8017
0
V
= 2V p-p
OUT
G = +2
–20
–40
DISTORTION – dBc
–100
–120
–60
–80
0.1
2ND
3RD
FREQUENCY – MHz
101
100
Figure 10. Distortion vs. Frequency; VS = ±6 V, RL = 100
0
V
= 2V p-p
OUT
G = +2
–20
–40
–60
DISTORTION – dBc
–80
–100
0.1 100
2ND
3RD
FREQUENCY – MHz
101
Figure 11. Distortion vs. Frequency; VS = ±6 V, RL = 25
0
V
= 2V p-p
OUT
G = +2
–20
–40
–60
DISTORTION – dBc
–80
–100
–120
0.1 100
Ω
Figure 13. Distortion vs. Frequency; VS = ±2.5 V, RL = 100
0
–10
–20
–30
–40
–50
–60
DISTORTION – dBc
–70
–80
–90
0.1 100
Ω
Figure 14. Distortion vs. Frequency; VS = ±2.5 V, RL = 25
V
OUT
G = +2
2ND
3RD
101
FREQUENCY – MHz
Ω
= 2V p-p
2ND
3RD
101
FREQUENCY – MHz
Ω
–20
–30
–40
–50
–60
HIGHEST HARMONIC DISTORTION – dBc
–70
0 500
VS = ⴞ6V
R
= 25⍀
L
100 200 300 400
OUTPUT CURRENT – mA
VS = ⴞ6V
R
= 10⍀
L
VS = ⴞ6V
R
= 5⍀
L
600
Figure 12. Distortion vs. Output Current; VS = ±6 V,
f = 1 MHz, G = +2
–20
–30
–40
–50
–60
HIGHEST HARMONIC DISTORTION – dBc
–70
0 300
VS = ⴞ2.5V
R
= 25⍀
L
VS = ⴞ2.5V
R
= 10⍀
L
OUTPUT CURRENT – mA
VS = ⴞ2.5V
R
Figure 15. Distortion vs. Output Current; VS = ±2.5 V,
f = 1 MHz, G = +2
–6–
= 5⍀
L
400100 200
REV. A
AD8017
–20
–40
–60
–80
–100
DISTORTION – dBc
–120
–140
0 1000
LOAD RESISTANCE – ⍀
2ND
3RD
10010
Figure 16. Distortion vs. RL, VS = ±6 V, G = +2, V
f = 1 MHz
0
VS = ⴞ6V
f = 1MHz
–10
G = +2
–20
–30
= 2 V p-p,
OUT
0
–20
–40
–60
–80
DISTORTION – dBc
–100
–120
–140
0 1000
LOAD RESISTANCE – ⍀
2ND
3RD
10010
Figure 19. Distortion vs. RL, VS = ±2.5 V, G = +2,
V
= 2 V p-p, f = 1 MHz
OUT
0
VS = ⴞ2.5V
f = 1MHz
–10
G = +2
–20
–30
–40
HIGHEST HARMONIC DISTORTION – dBc
–50
–60
–70
–80
0
RL = 25⍀
RL = 100⍀
OUTPUT VOLTAGE – Volts
6
54321
Figure 17. Distortion vs. Output Voltage, VS = ±6 V, G = +2,
f = 1 MHz
0
VS = ⴞ6V
f = 10MHz
–10
G = +2
–20
–30
HIGHEST HARMONIC DISTORTION – dBc
–40
–50
–60
–70
0
RL = 25⍀
RL = 100⍀
OUTPUT VOLTAGE – Volts
6
54321
Figure 18. Distortion vs. Output Voltage, VS = ±6 V, G = +2,
f = 10 MHz
–40
–50
–60
–70
HIGHEST HARMONIC DISTORTION – dBc
–80
0 0.5
RL = 25⍀
RL = 100⍀
1.0 1.5 2.0 2.5
OUTPUT VOLTAGE – Volts
Figure 20. Distortion vs. Output Voltage, VS = ±2.5 V,
G = +2, f = 1 MHz
0
VS = ⴞ2.5V
–10
f = 10MHz
G = +2
–20
–30
–40
–50
–60
–70
HIGHEST HARMONIC DISTORTION – dBc
–80
0
RL = 25⍀
RL = 100⍀
1 1.5
OUTPUT VOLTAGE – Volts
2
2.50.5
Figure 21. Distortion vs. Output Voltage, VS = ±2.5 V,
G = +2, f = 10 MHz
–7–REV. A
AD8017
3
RL = 100⍀
0
GAIN = +10
–3
NORMALIZED GAIN – dB
GAIN = +5
–6
101
FREQUENCY – MHz
GAIN = +2
100
Figure 22. Frequency Response; VS = ±6 V
0.3
0.2
0.1
0.0
G = +2
R
= 100⍀
L
1000
2
1
RL = 100⍀
0
–1
–2
–3
NORMALIZED GAIN – dB
–4
–5
–6
0.1 10001
GAIN = +5
GAIN = +10
10 100
FREQUENCY – MHz
GAIN = +2
Figure 25. Frequency Response; VS = ±2.5 V
0.3
G = +2
R
= 100⍀
L
0.2
0.1
0.0
–0.1
0.1dB FLATNESS – dB
–0.2
–0.3
0.1
10 100
FREQUENCY – MHz
10001
Figure 23. Gain Flatness; VS = ±6 V
OUTPUT VOLTAGE – dBV
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
V
OUT
G = +2
R
= 100⍀
L
0.1 10001
= 2V p-p
10 100
FREQUENCY – MHz
Figure 24. Output Voltage vs. Frequency; VS = ±6 V
–0.1
0.1dB FLATNESS – dB
–0.2
–0.3
0.1
10 100
FREQUENCY – MHz
10001
Figure 26. Gain Flatness; VS = ±2.5 V
3
0
–3
–6
–9
–12
–15
–18
–21
OUTPUT VOLTAGE – dBV
–24
–27
–30
0.1 10001
G = +2
R
= 100⍀
L
V
= 1V
OUT
FREQUENCY – MHz
RMS
10 100
Figure 27. Output Voltage vs. Frequency; VS = ±2.5 V
–8–
REV. A
AD8017
+20
0
–20
–40
POWER – dBm
–60
–80
0
50 100 150
FREQUENCY – kHz
Figure 28. Multitone Power Ratio: VS = ±6 V, 13 dBm
Output Power into 25
0
–10
–20
–30
–40
–50
CMRR – dB
–60
–70
–80
–90
–100
0.1 10001
Ω
10 100
FREQUENCY – MHz
Figure 29. CMRR vs. Frequency; VS = ±6 V or VS = ±2.5 V
120
100
80
60
CAP LOAD – pF
40
20
0
0
24 8
SERIES RESISTANCE – ⍀
6
Figure 31. RS and CL vs. 30% Overshoot
0
–10
–20
–30
–40
PSRR – dB
–50
–60
–70
–80
0.1 10001
10 100
FREQUENCY – MHz
–PSRR
+PSRR
Figure 32. PSRR vs. Frequency; VS = ±6 V or VS = ±2.5 V
0.4
0.3
0.2
i
N
0.1
INPUT CURRENT NOISE – nA/ Hz
0
0.01 1000.1
e
N
110
FREQUENCY – kHz
Figure 30. Noise vs. Frequency
12
10
8
6
4
INPUT VOLTAGE NOISE – nA/ Hz
2
0
1000
PHASE
100
TRANSIMPEDANCE
10
TRANSIMPEDANCE – k⍀
1
0.001 10
0.01
0.1 1
FREQUENCY – MHz
180
120
PHASE – Degrees
60
0
1000100
Figure 33. Open-Loop Transimpedance and Phase vs.
Frequency
–9–REV. A
AD8017
–20
–30
–40
–50
–60
G = +2
V
= 2V
OUT
STEP
RL - 100⍀
+2mV
(+0.1%)
–2mV
(+0.1%)
OUTPUT VOLTAGE ERROR – mV/DIV (% /DIV)
0
0 102030405060708090
VS = ⴞ6V
TIME – ns
Figure 34. Settling Time; VS = ±6.0 V
V
= 2V p-p
OUT
G = +2
R
= 100⍀
L
6
5
4
3
2
VOLTS
1
0
–1
–2
–10 10 30 50 70 90 110 130 150
2
1
0
–3
–3
VOLTS
–3
–4
–5
–6
–10 10 30 50 70 90 110 130 150
V
OUT
V
IN
V
IN
V
OUT
TIME – ns
Figure 37. Overload Recovery; VS = ±6 V, G = +2,
R
= 100 Ω, VIN = 5 V p-p, T = 1 µs
L
–70
CROSSTALK – dB
–80
–90
–100
0.1 10001
10 100
FREQUENCY – MHz
Figure 35. Output Crosstalk vs. Frequency
1000000
Z
IN
⍀
100000
10000
INPUT IMPEDANCE –
1000
0.1 100
110
FREQUENCY – MHz
100
10
Z
OUT
1
0.1
1000
Figure 36. Input and Output Impedance vs. Frequency
⍀
OUTPUT IMPEDANCE –
–10–
REV. A
AD8017
THEORY OF OPERATION
The AD8017 is a dual high speed CF amplifier that attains new
levels of bandwidth (BW), power, distortion and signal swing,
under heavy current loads. Its wide dynamic performance (including noise) is the result of both a new complementary high
speed bipolar process and a new and unique architectural
design. The AD8017 basically uses a two gain stage complementary design approach versus the traditional “single stage”
complementary mirror structure sometimes referred to as the
Nelson amplifier. Though twin stages have been tried before,
they typically consumed high power since they were of a folded
cascode design much like the AD9617.
This design allows for the standing or quiescent current to add
to the high signal or slew current-induced stages. In the time
domain, the large signal output rise/fall time and slew rate is
typically controlled by the small signal BW of the amplifier and
the input signal step amplitude respectively, not the dc quiescent current of the gain stages (with the exception of input level
shift diodes Q1/Q2). Using two stages as opposed to one, also
allows for a higher overall gain bandwidth product (GBWP) for
the same power, thus providing lower signal distortion and the
ability to drive heavier external loads. In addition, the second
gain stage also isolates (divides down) A3’s input reflected load
drive and the nonlinearities created resulting in relatively lower
distortion and higher open-loop gain. See Figure 38.
Overall, when “high” external load drive and low ac distortion is
a requirement, a twin gain stage integrating amplifier like the
AD8017 will provide excellent results for low power over the
traditional single stage complementary devices. In addition,
being a CF amplifier, closed-loop BW variations versus external
gain variations (varying R
) will be much lower compared to a
G
VF op amp, where the BW varies inversely with gain. Another
key attribute of this amplifier is its ability to run on a single 5 V
supply due in part to its wide common-mode input and output
voltage range capability. For 5 V supply operation, the device
obviously consumes less than half the quiescent power (vs. 12 V
supply) with little degradation in its ac and dc performance
characteristics. See specification pages for comparisons.
DC GAIN CHARACTER
Gain stages A1/A1 and A2/A2 combined provide negative
feedforward transresistance gain. See Figure 38. Stage A3 is a
unity gain buffer which provides external load isolation to A2.
Each stage uses a symmetrical complementary design. (A3 is
also complementary, though not explicitly shown). This is done
to reduce both second order signal distortion and overall quiescent power as discussed above. In the quasi dc-to-low frequency
region, the closed loop gain relationship can be approximated as:
G = 1+R
G = –R
for Noninverting Operation
F/RG
for Inverting Operation
F/RG
These basic relationships above are common to all traditional
operational amplifiers.
IPP
+
INP
C
–A2
P
–A2
C
D
2
ICQ + IO
V
9
O
–A3
R
Z2
ICQ – IO
R
F
R
N
L
V
O
C
L
AD8017
C
D
A1
IPN
IQ1
Q3
Q1
V
P
V
N
–
Q2
Z1
IE
Q4
IQ1
IPN
A1
Z1 = R1 || C1
–V
I
IR + IFC
IR – IFC
–V
I
Z1
CP1
Z1
CP1
Figure 38. Simplified Block Diagram
–11–REV. A
AD8017
APPLICATIONS
Output Power Characteristics as Applied to ADSL Signals
The AD8017 was designed to provide both relatively high current and voltage output capability. Figures 17 and 20 quantify
the ac load current versus distortion of the device at loads of
100 Ω and 25 Ω at 1 MHz. Using approximately –50 dBc as the
worst case distortion limit, the AD8017 exhibits acceptable
linearity to within approximately 1.4 V of either supply rail (12 V
or ±6 V) while simultaneously providing 200 mA of load current. These levels are achieved at only 7 mA of quiescent current for each amplifier.
ADSL applications require signal line powers of 13 dBm that
can randomly peak to an instantaneous power (or V × I product)
of 28.5 dBm. This equates to peak-to-rms voltage ratio of 5.3to-1. Using a 1:2 transformer in the ADSL circuit illustrated
below and 100 Ω as the line resistance, a peak voltage of 4.2 V
at a peak current of 168 mA will be required from the line driver
output (see Table I). See detailed application below. A higher
turns ratio transformer can be used to reduce the primary output voltage swing of the amplifier (for devices that do not have
the voltage swing, but do have the current drive capability).
However, this requires more than an equivalent increase in
current due to the added I × R losses from the transformer for
the same receiver power. Generally this will result in added
distortion. Table I below shows the ADSL ac current and voltages required for both a 1:1 and 1:2 transformer turns ratio.
+12V
0.1F
169⍀
4.7V
1k⍀
V
IN
4.7V
169⍀
1k⍀
0.1F
0.1F
1k⍀
2
3
AD8017
5
6
1k⍀
0.1F
8
4
1F
1
EFFECTIVE
LOAD
7
1F
50⍀
10F
12.5⍀
12.5⍀
1:2
V
OUT
100⍀
Figure 39. Single +12 V Supply ADSL Remote Terminal
Transmitter
Single +12 V Supply ADSL Remote Terminal (RT) Transmitter
For consumer use, it is desirable to create an ADSL modem
that can be a plug-in accessory for a PC. In such an application,
the circuit should dissipate a minimum of power, yet still meet
the ADSL specification.
The circuit in Figure 39 shows a single +12 V supply circuit
that uses the AD8017 as a remote terminal transmitter. This
supply voltage is readily available on the PCI connector of PCs.
The circuit configures each half of the AD8017 as an inverter
with a gain of about six. Both of the amplifier circuits are ac
coupled at both the inputs and the outputs. This makes the dc
levels of the circuit independent of the other dc levels of the
signal chain.
The inputs will generally be driven by the output of an active
filter, which has a low output impedance. Thus there will be a
minimum of loading of the source caused by the 169 Ω input
impedance in the pass band. The output will require a 1:2 stepup transformer to drive a 100 Ω line. The reflected impedance
back to the primary will be 25 Ω. With 25 Ω of series termination added (12.5 Ω in each output), the effective load that the
differential amplifier outputs will drive is 50 Ω.
The input and output ac coupling provides two high pass circuits. The inputs are formed by the 0.1 µF capacitor and the
169 Ω resistor, which provides a break frequency of about
9.4 kHz. The two 1 µF capacitors in the output along with the
50 Ω effective load provides a 6.4 kHz break frequency in the
output side. Both of these circuits want to reject the Plain Old
Telephone System (POTS) band (dc to 4 kHz) while passing
the ADSL upstream band, which starts at about 20 kHz.
The positive inputs must be biased at mid supply, which is
nominally +6 V. This will maintain the maximum dynamic
range of the output in each direction, regardless of the tolerance
of the supply. The inverting configuration was chosen as this
requires a steady dc current from this supply, as opposed to the
signal-dependent current that would be required in a noninverting configuration. Several options were studied for creating this
supply.
A voltage regulator could be used, but there are several disadvantages. The first is that this will not track the middle of the
supplies as it will always have an output that is a fixed voltage
from ground. This also requires an additional active component
that will impact the cost of the total solution.
A two-resistor divider could also be used. There is a tradeoff
required here in the selection of the value of the resistors. As the
resistors become smaller, the amount of power that they will
dissipate will increase. For two 1 kΩ resistors, the power dissipation in this circuit would be 72 mW. Thus, in order to keep
this power to a minimum, it is desirable to make the resistors as
large as possible.
Table I. DSL Drive Amplifier Requirements for Various Combinations of Line Power, Line Impedance and Turn Ratios
Line Insertion Line Turns Crest Reflected Per Amp Peak Per Amplifier Peak Current
Power Loss Load Ratio Factor Impedance R1 = R2 Voltage Voltage Output Output
13 dBm 1 dB 100 Ω 1:1 5.3 100 Ω 50 Ω 1.585 V rms 8.4 V peak 84 mA
13 dBm 1 dB 100 Ω 1:2 5.3 25 Ω 12.5 Ω 0.792 V rms 4.2 V peak 168 mA
–12–
REV. A
The practical maximum value that these resistors can have is
A1
A1
R
L
V
O1
V
O2
VCC
VEE
determined by the offset voltage that is created by the input bias
current that flows through them. The maximum input bias
current into the + inputs is 45 µA. This will create an offset
voltage of 45 mV per 1 kΩ of bias resistor. Fortunately, the ac
coupling of the stages provides only unity gain for this dc offset
voltage, which is another advantage of this configuration. Any
dc offset in the output will limit the amount of dynamic signal
swing that will be available between the rails.
The circuit shown uses two 4.7 V Zener diodes that provide a
voltage drop which serves to limit the power dissipation in the
bias circuit. This allows the use of smaller value resistors in the
bias circuit. Thus, for this circuit the current will be (12 V –
(2 × 4.7 V))/2 kΩ = 1.3 mA. Thus, this circuit will dissipate
only 15.6 mW, yet only induce a maximum of 40 mV of offset
at the output. This circuit will also track the midpoint of the
supplies over their specified tolerance range.
The distortion of the circuit was measured with a 50 Ω load.
The frequency used was 500 kHz, which is beyond the maximum required for the upstream signal. For ADSL over POTS, a
maximum frequency of 135 kHz is required. For ADSL over
ISDN, the maximum frequency is 276 kHz. The amplitude was
20 V p-p (10 V p-p for each amplifier), which is the maximum
crest signal that will be required. The second harmonic was
better than –80 dBc, while the third harmonic was –64 dBc.
This represents a worst case of the absolute maximum signal
that will be required for only a very small statistical basis and at
a frequency that is higher than the maximum required. For a
statistical majority of the time, the signal will be at a lower amplitude and frequency, where the distortion performance will be
better.
When the circuit was run while providing the upstream drive
signal in an ADSL system, the supply current to the part was
measured at 25 mA. Thus, the total power to the drive circuit
was 300 mW. This power winds up in three places: the drive
amplifier, down the line and in the termination and interface
circuitry.
The ADSL specification calls for 13 dBm or 20 mW into the
line. The line termination will consume an equal amount of
power, as it is the same resistance value. About a 1 dB loss can
be expected in the losses in the interface circuitry, which translates into about 10 mW of power. Thus, the total power dissipated in the AD8017 when used as a driver in this application is
about 250 mW.
AD8017
Figure 40. Differential Driver Simplified Circuit Schematic
It is important to consider the total power dissipation of the
AD8017 in order to properly size the heatsinking area for your
application. The dc power dissipation for V
I
. (VCC + VEE), or 2 × IQ × VS. For the AD8017, this number is
Q
0.17 W. In this purely differential circuit we can use symmetry
to simplify the computation for a dc input signal,
PIVVV
=× × +×
DQS SO
()
This formula is slightly pessimistic due to the fact that some of
the quiescent supply current commutates during sourcing or
sinking current into the load. For a sine wave source, integration over a half cycle yields:
PIV
=× × +× −
22
DQS
4
VVRV
OSLO
π
2
R
L
The situation is more complicated with a complex modulated
signal. In the case of a DMT signal, taking the equivalent sine
wave power overestimates the power dissipation by > 15%. For
example:
P
= 16 dBm = 40 mW
OUT
V
@ 50 Ω = 1.41 V rms or VO = 1.0 V
OUT
at each amplifier output, which yields a P
actual measurement, P
for a DMT signal of 16 dBm requires
D
0.38 W of power to be dissipated by the AD8017.
= 0 is simply,
IN
V
O
×24–
R
L
(Refer to Figure 41)
of 0.436 W. By
D
–13–REV. A
AD8017
0.8
0.7
0.6
) – W
D
0.5
0.4
0.3
0.2
POWER DISSIPATION (P
0.1
0
OUTPUT VOLTAGE (VO) – V
41203
56
PK
Figure 41. Power Dissipation (PD) vs. Output Voltage (VO),
R
= 50
Ω
L
Thermal Considerations
The AD8017 in a “Thermal Coastline” SO-8 package relies on
the device pins to assist in removing heat from the die at a faster
rate than that of conventional packages. The effect is to provide
a lower θ
for the device. To make the most effective use of
JC
this, special details should be worked into the copper traces of
the printed circuit board.
There will be a tradeoff, however, between designing a board
that will maximally remove heat, and one that will provide the
desired ac performance. This is the result of the additional parasitic capacitance on some of the pins that would be caused by
the addition of extra heatsinking copper traces.
The first technique for maximum heatsinking is to use a heavy
layer of copper. 2 oz. copper will provide better heatsinking than
1 oz. copper. Additional internal circuit layers can also be used
to more effectively remove heat, and to provide better power
and ground distribution.
There are no “ground” pins per se on the AD8017 (when run
on a dual supply), but the power supplies (Pins 4 and 8) are at
ac ground. Thus, these pins can be safely tied to a maximum
area of copper foil without affecting the ac performance of the
part. On the surface side of the board, the copper area that
connects to Pins 4 and 8 should be enlarged and spread out to
the maximum extent possible. As a practical matter, there will
be diminishing returns from adding copper more than a few
centimeters from the pins.
When the power supplies are run on the board on internal
power planes, then these should also be made as large as practical, and multiple vias (~0.012 in. or 0.3 mm) should be provided from the component layer near the power supply pins of
the AD8017 to the inner layers. These vias should not have any
of the traditional “thermal relief” spokes to the planes, because
the function of these is to impede heat flow for ease of soldering.
This is counter to the effect desired for heatsinking.
On the side of the board opposite the component, additional
heatsinking can be provided by adding copper area near the vias
to further lower the thermal resistance. Additional vias can be
provided throughout to better conduct heat from the inner
layers to the outer layers.
The remainder of the device pins are active signal pins and must
be treated a bit more carefully. Pins 2 and 6 are the summing
junctions of the op amps and will be the most adversely affected by
stray capacitance. For this reason, the copper area of these pins
should be minimized. In addition, the copper nearby on the
component layer should be kept more than 3 mm–5 mm away
from these pins, where possible. The inner and opposite side
circuit layers directly below the summing junctions should also
be void of copper.
The positive inputs and outputs can withstand somewhat more
capacitance than the summing junctions without adversely affecting ac performance. However, these pins should be treated
carefully, and the amount of heatsinking and excess capacitance
should be analyzed and adjusted depending on the application.
If maximum ac performance is desired and the power dissipation is not extreme, then the copper area connected to these
pins should be minimized. If the ac performance is not very
critical and maximum power must be dissipated, then the copper area connected to these pins can be increased. As in many
other areas of analog design, the designer must use some judgment based on the consideration of the above, in order to produce a satisfactory design.
–14–
REV. A
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8017 requires
careful attention to board layout and component selection.
Table II shows recommended component values for the AD8017
and Figures 42–44 show recommended layouts for the 8-lead
SOIC package for a positive gain. Proper RF design techniques
and low parasitic component selections are mandatory.
Table II. Typical Bandwidth vs. Gain Setting Resistors
= 6 V, RL = 100 ⍀)
(V
S
Small Signal
Gain RF (⍀)RG (⍀)RT (⍀) –3 dB BW (MHz)
–1 619 619 54.5 110
+1 619 49.9 320
+2 619 619 49.9 160
+10 619 68.8 49.9 40
chosen for 50 Ω characteristic input impedance.
R
T
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see Figures 4 and 7). One end should be connected to the ground
plane and the other within 1/8 in. of each power pin. An additional (4.7 µF–10 µF) tantalum electrolytic capacitor should be
connected in parallel.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to
a minimum. Capacitance greater than 1.5 pF at the inverting
input will significantly affect high speed performance when
operating at low noninverting gain.
AD8017
Figure 43. Universal SOIC Noninverter Top
Figure 44. Universal SOIC Noninverter Bottom
Figure 42. Universal SOIC Noninverter Top Silkscreen
–15–REV. A
AD8017
0.1574 (4.00)
0.1497 (3.80)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
5
0.2440 (6.20)
41
0.2284 (5.80)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
PIN 1
0.0500
(1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
0.0196 (0.50)
0.0099 (0.25)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
x 45°
C3428–0–5/00 (rev. A) 01042
–16–
PRINTED IN U.S.A.
REV. A
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