Datasheet AD8011 Datasheet (Analog Devices)

300 MHz, 1 mA

a

FEATURES
Easy to Use
Low Power

1 mA Power Supply Current (5 mW on +5 V

High Speed and Fast Settling on +5 V

300 MHz, –3 dB Bandwidth (G = +1)
180 MHz, –3 dB Bandwidth (G = +2)
2000 V/␮s Slew Rate
29 ns Settling Time to 0.1%

Good Video Specifications (R

= 1 k⍀, G = +2)

L

Gain Flatness 0.1 dB to 25 MHz

0.02% Differential Gain Error

0.06ⴗ Differential Phase Error

Low Distortion

–70 dBc Worst Harmonic @ 5 MHz
–62 dBc Worst Harmonic @ 20 MHz

Single Supply Operation

Fully Specified for +5 V Supply

APPLICATIONS
Power Sensitive, High Speed Systems
Video Switchers
Distribution Amplifiers
A-to-D Driver
Professional Cameras
CCD Imaging Systems
Ultrasound Equipment (Multichannel)

PRODUCT DESCRIPTION

The AD8011 is a very low power, high-speed amplifier designed
to operate on +5 V or ±5 V supplies. With wide bandwidth, low
distortion and low power, this device is ideal as a general-purpose

)

S

Current Feedback Amplifier

AD8011*

FUNCTIONAL BLOCK DIAGRAM

8-Lead Plastic DIP and SOIC

NC

1

2

–IN

3

+IN

4

V–

AD8011

NC = NO CONNECT

amplifier. It also can be used to replace high-speed amplifiers
consuming more power. The AD8011 is a current feedback
amplifier and features gain flatness of 0.1 dB to 25 MHz while
offering differential gain and phase error of 0.02% and 0.06° on
a single +5 V supply. This makes the AD8011 ideal for profes­sional video electronics such as cameras, video switchers or any
high speed portable equipment. Additionally, the AD8011’s
low distortion and fast settling make it ideal for buffering high
speed 8-, 10-, 12-bit A-to-D converters.

The AD8011 offers very low power of 1 mA max and can run
on single +5 V to +12 V supplies. All this is offered in a small
8-lead plastic DIP or 8-lead SOIC package. These features fit
well with portable and battery-powered applications where size
and power are critical.

The AD8011 is available in the industrial temperature range of –
40°C to +85°C.

8

NC

V+

7

OUT

6

NC

5

+5

G = +2

+4

= 1k⍀

R

F

= +5V OR ⴞ5V

V

S

NORMALIZED GAIN – dB

+3

+2

+1

–1

–2

–3

–4

–5

0

1

V

OUT

= 200mV p-p

10
FREQUENCY – MHz

100 500

Figure 1. Frequency Response; G = +2, VS = +5 V or ±5 V

*Protected under Patent Number 5,537,079.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

–40

–60

DISTORTION – dBc

–80

–100

G = +2

2nd
R

3rd

= 150⍀

R

L

3rd

=1k⍀

R

L

= 1k⍀

L

FREQUENCY – MHz

2nd

= 150⍀

R

L

10 20

Figure 2. Distortion vs. Frequency; VS = ±5 V

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD8011–SPECIFICATIONS

DUAL SUPPLY

(@ TA = +25ⴗC, VS = ⴞ5 V, G = +2, RF = 1 k⍀, RL = 1 k⍀, unless otherwise noted)

Model AD8011A

Conditions Min Typ Max Units

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth, VO < 1 V p-p G = +1 340 400 MHz
–3 dB Small Signal Bandwidth, V
–3 dB Large Signal Bandwidth, V

< 1 V p-p G = +2 180 210 MHz

O

= 5 V p-p G = +10, RF = 500 Ω 57 MHz

O

Bandwidth for 0.1 dB Flatness G = +2 20 25 MHz
Slew Rate G = +2, V

G = –1, V
Settling Time to 0.1% G = +2, V
Rise and Fall Time G = +2, V

= 4 V Step 3500 V/µs

O

= 4 V Step 1100 V/µs

O

= 2 V Step 25 ns

O

= 2 V Step 0.4 ns

O

G = –1, VO = 2 V Step 3.7 ns

NOISE/HARMONIC PERFORMANCE

2nd Harmonic fC = 5 MHz, VO = 2 V p-p, G = +2

= 1 kΩ –75 dB

R

L

= 150 Ω –67 dB

R
3rd Harmonic R

L

= 1 kΩ –70 dB

L

= 150 Ω –54 dB

R

L

Input Voltage Noise f = 10 kHz 2 nV/√Hz
Input Current Noise f = 10 kHz, +In 5 pA/√Hz

–In 5 pA/√Hz
Differential Gain Error NTSC, G = +2, R

R
Differential Phase Error NTSC, G = +2, R

= 1 kΩ 0.02 %

L

= 150 Ω 0.02 %

L

= 1 kΩ 0.06 Degrees

L

RL = 150 Ω 0.3 Degrees

DC PERFORMANCE

Input Offset Voltage 25±mV

T

MIN–TMAX

26±mV
Offset Drift 10 µV/°C
–Input Bias Current 515±µA

T

MIN–TMAX

20 ±µA

+Input Bias Current 515±µA

T

MIN–TMAX

20 ±µA

Open-Loop Transresistance 800 1300 kΩ

T

MIN–TMAX

550 kΩ

INPUT CHARACTERISTICS

Input Resistance +Input 450 kΩ
Input Capacitance +Input 2.3 pF
Input Common-Mode Voltage Range 3.8 4.1 ± V
Common-Mode Rejection Ratio

Offset Voltage VCM = ±2.5 V –52 –57 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing 3.9 4.1 ± V
Output Resistance 0.1 0.3 Ω
Output Current T

MIN–TMAX

15 30 mA

Short Circuit Current 60 mA

POWER SUPPLY

Operating Range ±1.5 ±6.0 V
Quiescent Current T

MIN–TMAX

1.0 1.3 mA

Power Supply Rejection Ratio Vs = ±5 V ± 1 V 55 58 dB

Specifications subject to change without notice.

–2–

REV. B

AD8011

SINGLE SUPPLY

(@ TA = +25ⴗC, VS = +5 V, G = +2, RF = 1 k⍀, VCM = 2.5 V, RL = 1 k⍀, unless otherwise noted)

Model AD8011A

Conditions Min Typ Max Units

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth, V
–3 dB Small Signal Bandwidth, V
–3 dB Large Signal Bandwidth, V

< 0.5 V p-p G = +1 270 328 MHz

O

< 0.5 V p-p G = +2 150 180 MHz

O

= 2.5 V p-p G = +10, RF = 500 Ω 57 MHz

O

Bandwidth for 0.1 dB Flatness G = +2 15 20 MHz
Slew Rate G = +2, V

G = –1, V
Settling Time to 0.1% G = +2, V
Rise and Fall Time G = +2, V

= 2 V Step 2000 V/µs

O

= 2 V Step 500 V/µs

O

= 2 V Step 29 ns

O

= 2 V Step 0.6 ns

O

G = –1, VO = 2 V Step 4 ns

NOISE/HARMONIC PERFORMANCE

2nd Harmonic fC = 5 MHz, VO = 2 V p-p, G = +2

= 1 kΩ –84 dB

R

L

R

= 150 Ω –67 dB

3rd Harmonic R

L

= 1 kΩ –76 dB

L

= 150 Ω –54 dB

R

L

Input Voltage Noise f = 10 kHz 2 nV/√Hz
Input Current Noise f = 10 kHz, +In 5 pA/√Hz

–In 5 pA/√Hz
Differential Gain Error NTSC, G = +2, R

R
Differential Phase Error NTSC, G = +2, R

= 1 kΩ 0.02 %

L

= 150 Ω 0.6 %

L

= 1 kΩ 0.06 Degrees

L

RL = 150 Ω 0.8 Degrees

DC PERFORMANCE

Input Offset Voltage 25mV

T

MIN–TMAX

26mV

Offset Drift 10 µV/°C
–Input Bias Current 515±µA

T

MIN–TMAX

20 ±µA

+Input Bias Current 515±µA

T

MIN–TMAX

20 ±µA

Open-Loop Transresistance 800 1300 kΩ

T

MIN–TMAX

550 kΩ

INPUT CHARACTERISTICS

Input Resistance +Input 450 kΩ
Input Capacitance +Input 2.3 pF
Input Common-Mode Voltage Range 1.5 to 3.5 1.2 to 3.8 V
Common-Mode Rejection Ratio

Offset Voltage VCM = 1.5 V to 3.5 V –52 –57 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing 1.2 to 3.8 0.9 to 4.1 +V
Output Resistance 0.1 0.3 Ω
Output Current T

MIN–TMAX

15 30 mA

Short Circuit Current 50 mA

POWER SUPPLY

Operating Range +3 +12 V
Quiescent Current T

MIN–TMAX

0.8 1.15 mA

Power Supply Rejection Ratio ∆Vs = ±1 V 55 58 dB

Specifications subject to change without notice.

REV. B

–3–

AD8011

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V

Internal Power Dissipation

2

1

Plastic DIP Package (N) . . . . . . . . Observe Derating Curves

Small Outline Package (R) . . . . . . . Observe Derating Curves

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 2.5 V

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves

Storage Temperature Range (N, R) . . . . . . . . –65°C to +125°C

Operating Temperature Range (A Grade) . . . –40°C to +85°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for device in free air:

8-Lead Plastic DIP Package: θJA = 90°C/W
8-Lead SOIC Package: θJA = 155°C/W

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8011 is limited by the associated rise in junction tempera­ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition tem­perature of the plastic, approximately +150°C. Exceeding this
limit temporarily may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of +175°C for an extended
period can result in device failure.

While the AD8011 is internally short circuit protected, this
may not be sufficient to guarantee that the maximum junction
temperature is not exceeded under all conditions. To ensure
proper operation, it is necessary to observe the maximum power
derating curves (shown below in Figure 3).

2.0
TJ = +150ⴗC

8-LEAD PLASTIC DIP PACKAGE

1.5

1.0

8-LEAD SOIC PACKAGE

0.5

MAXIMUM POWER DISSIPATION – Watts

0
–50 –40 –30 –20 –10 0 10203040 5060708090

AMBIENT TEMPERATURE – ⴗC

Figure 3. Maximum Power Dissipation vs. Temperature

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD8011AN –40°C to +85°C 8-Lead Plastic DIP N-8
AD8011AR –40°C to +85°C 8-Lead SOIC SO-8
AD8011AR-REEL –40°C to +85°C 13" Tape and Reel SO-8
AD8011AR-REEL7 –40°C to +85°C 7" Tape and Reel SO-8
AD8011-EB Evaluation Bo

ard

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8011 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

AD8011

1k⍀1k⍀

V

IN

50⍀

0.01␮F

0.01␮F

10␮F

10␮F

R

L

1k⍀

V

OUT

+V

S

–V

S

V

IN

Figure 4. Test Circuit; Gain = +2

1k⍀

52.3⍀

1k⍀

0.01␮F

0.01␮F

10␮F

10␮F

Figure 7. Test Circuit; Gain = –1

R
1k⍀

V

OUT

L

+V

S

–V

S

Figure 5.* 100 mV Step Response; G = +2, VS = ±2.5 V or ±5 V

Figure 6.* Step Response; G = +2, VS = ±2.5 V (2 V

±

Step) and

*NOTE: VS = ±2.5 V operation is identical to VS = +5 V single supply operation.

5 V (4 V Step)

Figure 8.* 100 mV Step Response; G = –1, VS = ±2.5 V or ±5 V

Figure 9.* Step Response; G = –1, VS = ±2.5 V (2 V

±

Step) and

5 V (4 V Step)

REV. B

–5–

AD8011

6.5

G = +2

6.4

V

= 100mV p-p

IN

R

= 1k⍀

L

R

= 1k⍀

6.3

F

6.2

6.1

6.0

GAIN – dB

5.9

5.8

5.7

5.6

5.5
1 10 100 500

VS = +5V

VS = ⴞ5V

FREQUENCY – MHz

Figure 10. Gain Flatness; G = +2

–40

G = +2

–60

3rd
R

= 150⍀

L

2nd
R

= 150⍀

L

9

8

7

6

5

4

SWING – V p-p

3

2

1

0

10 100 1000 10000

LOAD RESISTANCE – Ohms

ⴞ5V

+5V

Figure 13. Output Voltage Swing vs. Load

–40

G = +2

–60

3rd
R

= 150⍀

L

2nd
R

L

= 150⍀

DISTORTION – dBc

–80

–100

1

3rd
R

=1k⍀

= 1k⍀

L

L

2nd
R

FREQUENCY – MHz

10 20

Figure 11. Distortion vs. Frequency; VS = ±5 V

0.04
VS = ⴞ5V

0.03
G = +2

0.02

0.01

0.00

–0.01
–0.02

DIFF GAIN – %

–0.03
–0.04

0.04

0.03

0.02

0.01

0.00

–0.01
–0.02

–0.03
–0.04

1k⍀ DIFF PHASE – Degrees

VS = ⴞ5V
G = +2

RL = 150⍀

RL = 1k⍀

1000 IRE

RL = 150⍀

RL = 1k⍀

Figure 12. Diff Phase and Diff Gain; VS = ±5 V

DISTORTION – dBc

–80

–100

2nd
R

=1k⍀

L

1

FREQUENCY – MHz

3rd
R

=1k⍀

L

10 20

Figure 14. Distortion vs. Frequency; VS = +5 V

0.08
VS = +5V

0.06
G = +2

0.04

0.02

0.00

–0.02
–0.04
–0.06

1k⍀ DIFF GAIN – %

–0.08

0.4

0.3

0.2

0.1

0.00

–0.1
–0.2
–0.3

–0.4

1000 IRE

150⍀ DIFF PHASE – Degrees

0.08

0.06

0.04

0.02

0.00

–0.02
–0.04
–0.06
–0.08

1k⍀ DIFF PHASE – Degrees

VS = +5V
G = +2

RL=150⍀

RL=1k⍀

RL=150⍀

RL=1k⍀

IRE

0.8

0.6

0.4

0.2

0.0

–0.2
–0.4
–0.6

150⍀ DIFF GAIN – %

–0.8

1000 IRE

0.8

0.6

0.4

0.2

0.0

–0.2
–0.4
–0.6

–0.8

1000

150⍀ DIFF PHASE – Degrees

Figure 15. Diff Phase and Diff Gain; VS = +5 V

–6–

REV. B

AD8011

+9

+6

+3

1V rms

0

–3

–6

–9

–12

OUTPUT VOLTAGE – dBV

–15

–18

–21

1 10 40 100 500

FREQUENCY – MHz

Figure 16. Large Signal Frequency Response;
V

= ±5 V, G = +2

S

+5

+4

VS = +5V OR ⴞ5V

NORMALIZED GAIN – dB

+3

+2

+1

0

–1

–2

–3

–4

–5

= 200mV p-p

V

OUT

1 10 100 500

FREQUENCY – MHz

G = +1
RF = 1k⍀

G = +10
RF = 500⍀

G = +2
RF = 1k⍀

Figure 17. Frequency Response; G = +1, +2, +10;

= +5 V or ±5 V

V

S

+3

1V rms

0

–3

–6

–9

–12

–15

–18

OUTPUT VOLTAGE – dBV

–21

–24

–27

1 10 40 100 500

FREQUENCY – MHz

Figure 19. Large Signal Frequency Response;
V

= +5 V, G = +2

S

OUTPUT VOLTAGE – 0.1%/DIV

t

= 0

Figure 20. Short-Term Settling Time; VS = +5 V or ±5 V

REV. B

+2

VS = +5V OR ⴞ5V

NORMALIZED GAIN – dB

+1

0

–1

–2

–3

–4

–5

–6

–7

–8

= 200mV p-p

V

OUT

G = –1

= 1k⍀

R

F

= 1k⍀

R

L

1 10 100 500

FREQUENCY – MHz

G = –10

= 500⍀

R

F

= 1k⍀

R

L

Figure 18. Frequency Response; G = –1, –10;

= +5 V or ±5 V

V

S

OUTPUT VOLTAGE – 0.1%/DIV

t

= 0

Figure 21. Long-Term Settling Time; VS = +5 V or ±5 V

–7–

AD8011

–10

–15

VS = +5V OR ⴞ5V
G = +2

–20

–25

–30

–35

CMRR – dB

–40

–45

–50

–55

–60

0.1 1 10 100
FREQUENCY – MHz

Figure 22. CMRR vs. Frequency; VS = +5 V or ±5 V

VS = +5V OR ⴞ5V

100

G = +2
R

= 1k⍀

F

10

1

0.1

OUTPUT RESISTANCE – ⍀

0.01

10k 0.1M 1M 10M 100M 500M

FREQUENCY – Hz

Figure 23. Output Resistance vs. Frequency; VS = +5 V
or

±

5 V

+10

0

VS = +5V OR ⴞ5V
G = +2

–10

R

= 1k⍀

F

100k 1M 10M 100M 500M

FREQUENCY – Hz

PSRR – dB

–20

–30

–40

–50

–60

–70

–80

–90

–PSRR

+PSRR

Figure 25. PSRR vs. Frequency; VS = +5 V or ±5 V

12.5

10

7.5

5

2.5

INPUT VOLTAGE NOISE – nV/ Hz

0

500 1k 10k 100k

FREQUENCY – Hz

50

40

30

20

10

0

Figure 26. Noise vs. Frequency; VS = +5 V or ±5 V

INPUT CURRENT NOISE – pA/ Hz

140

120

100

80

60

GAIN – dB Ohms

40

20

0

1k 10k 100k 1M 10M 100M 1G

FREQUENCY – Hz

GAIN

PHASE

0

–40

–80

–120

–160

PHASE – Degrees

–200

–240

–280

Figure 24. Transimpedance Gain and Phase vs. Frequency

–8–

9

8

f = 5MHz
G = +2

7

R

= 1k⍀

F

6

5

4

3

2

1

0

PEAK-TO-PEAK OUTPUT AT 5MHz ( 0.5% THD) – V

3 4 5 6 7 8 9 10 11

TOTAL SUPPLY VOLTAGE – V

RL = 1k⍀

RL = 150⍀

Figure 27. Output Swing vs. Supply

REV. B

AD8011

THEORY OF OPERATION

The AD8011 is a revolutionary generic high-speed CF amplifier
that attains new levels of BW, power, distortion, and signal
swing capability. If these key parameters were combined as a
figure of ac merit performance or [(frequency × V

)/(distortion

SIG

× power)], no IC amplifier today would come close to the merit
value of the AD8011 for frequencies above a few MHz. Its wide
dynamic performance (including noise) is the result of both a
new complementary high speed bipolar process and a new and
unique architectural design. The AD8011 uses basically a two
gain stage complementary design approach versus the traditional
“single stage” complementary mirror structure sometimes re­ferred to as the Nelson amplifier. Though twin stages have been
tried before, they typically consumed high power since they
were of a folded cascade design much like the AD9617. This
design allows for the standing or quiescent current to add to the
high signal or slew current induced stages much like the Nelson
or single stage design. Thus, in the time domain, the large signal
output rise/fall time and slew rate is controlled typically by the
small signal BW of the amplifier and the input signal step ampli­tude respectively, not the dc quiescent current of the gain stages
(with the exception of input level shift diodes Q1/Q2). Using
two stages vs. one also allows for a higher overall gain band­width product (GBWP) for the same power, thus lower signal
distortion and the ability to drive heavier external loads. In
addition, the second gain stage also isolates (divides down) A3’s
input reflected load drive and the nonlinearities created result­ing in relatively lower distortion and higher open-loop gain.

Overall, when “high” external load drive and low ac distortion is
a requirement, a twin gain stage integrating amplifier like the
AD8011 will provide superior results for lower power over the
traditional single stage complementary devices. In addition,
being a CF amplifier, closed-loop BW variations versus external
gain variations (varying RN) will be much lower compared to a
VF op amp, where the BW varies inversely with gain. Another
key attribute of this amplifier is its ability to run on a single 5 V
supply due in part to its wide common-mode input and output
voltage range capability. For 5 V supply operation, the device
obviously consumes half the quiescent power (vs. 10 V supply)
with little degradation in its ac and dc performance characteris­tics. See data sheet comparisons.

DC GAIN CHARACTERISTICS

Gain stages A1/A1B and A2/A2B combined provide negative
feedforward transresistance gain. See Figure 28. Stage A3 is a
unity gain buffer which provides external load isolation to A2.
Each stage uses a symmetrical complementary design. (A3 is
also complementary though not explicitly shown). This is done
to both reduce second order signal distortion and overall quies­cent power as discussed above. In the quasi dc to low frequency
region, the closed loop gain relationship can be approximated as:

G = 1+R
G = –R

F/RN

F/RN

noninverting operation
inverting operation

These basic relationships above are common to all traditional
operational amplifiers. Due to the inverting input error current
(I

) required to servo the output and the inverting IE × RI drop

E

IPP

INP

A2

CP2

A2

C

D

ICQ + IO

V

O

ICQ – IO

A3

R

L

R

R

L

F

Z2

V

O

C

L

AD8011

C

D

A1

IPN

IQ1

Q3

Q1

Q2

V

N

Z

I

IE

Q4

IQ1

IPN

A1

V

P

–V

I

IR + IFC

IR – IFC

–V

I

Z1 = R1 || C1

Z1

CP1

Z1

C

1

P

Figure 28. Simplified Block Diagram

REV. B

–9–

AD8011

(error current times the open loop inverting input resistance)
that results (see Figure 29), a more exact low frequency closed
loop transfer functions can be described as:

This analysis assumes perfect current sources and infinite tran­sistor V
These assumptions result in actual vs. model open loop voltage
gain and associated input referred error terms being less accurate

1+

G

G × R

T

O

I

+

AV=

for noninverting (G is positive)

AV=

1+

1 – G

for inverting (G is negative)

=

R

F

T

O

G

A

O

1+

G

R

G

F

+

T

A

O

O

for low gain (G) noninverting operation at the frequencies below
the open loop pole of the AD8011. This is primarily a result of
the input signal (V
Q3/Q4 resulting in R
ing operation, the actual vs. model dc error terms are relatively
much less.

R

F

+

T

O

AC TRANSFER CHARACTERISTICS

The ac small signal transfer derivations below are based on a
simplified single-pole model. Though inaccurate at frequencies
approaching the closed-loop BW (CLBW) of the AD8011 at low
noninverting external gains, they still provide a fair approximation
and a intuitive understanding of its primary ac small signal

+V

S

L

F

TO (s)
A

O

S

V

(s)

L

S

–V

S

R

L

O

C

L

L

L

R

N

S

V

P

C

P

IE

Z

L

I

I

R

R

N

ZI = OPEN LOOP INPUT IMPEDANCE = CI || R

characteristics.

For inverting operation and high noninverting gains these trans­fer equations provide a good approximation to the actual ac
performance of the device.

To accurately quantify the V
and T
nonexpanded noninverting gain relationship:

Figure 29. ZI = Open-Loop Input Impedance

where G is the ideal gain as previously described. With

= TO/AO (open-loop inverting input resistance), the second

R

I

with

expression (positive G) clearly relates to the classical voltage
feedback “op amp” equation with T
much higher value and thus insignificant effect. A

omitted do to its relatively

O

and TO are

O

the open-loop dc voltage and transresistance gains of the ampli­fier respectively. These key transfer variables can be described as:

RgmfA

××

12

A

=

OOI

Where g

g

1

( – )

mc

is the positive feedback transconductance (not

mc

shown) and 1/g
D1/D2 and Q3/Q4. The g

|

|

×

R

1

is the thermal emitter resistance of devices

mf

RA

12

T

=

× R1 product has a design value that

mc

|

×

|

;and therefore

2

g

−×

11

R

=

R

mc

g

×

2

mf

results in a negative dc open loop gain of typically –2500 V/V (see
Figure 30).

Though atypical of conventional CF or VF amps, this negative
open-loop voltage gain results in an input referred error term
(V

/G = G/AO + RF/TO) that will typically be negative for G

P–VO

greater than +3/–4. As an example, for G = 10, A

= 1.2 MΩ, results in a error of –3 mV using the AV deriva-

T

O

= –2500 and

O

tion above.

s (Q3, Q4 output conductances are assumed zero).

A

) modulating the output conductances of

P

less negative than derived here. For invert-

I

vs. VP relationship, both AO(s)

(s) need to be derived. This can be seen by the following

O

VO(s )/VP(s ) =

AO(s ) =

80

70

60

50

40

30

20

10

GAIN – dB Ohms

0

–10

–20

–30

1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09

O

G

[s]

A

O

R1× g

mf

1 – g

mc

Sτ1

1 – gmc× R1

GAIN

AO(s)

FREQUENCY – Hz

G

R

+

TO[s]

×|A2|
× R1

PHASE

F

+1

–90

–100

–110

–120

–130

–140

–150

–160

PHASE – Degrees

–170

–180

–190

–200

Figure 30. Open-Loop Voltage Gain and Phase

–10–

REV. B

1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09

400

370

340

310

280

220

190

FREQUENCY – Hz

250

RESISTANCE – Ohms

20

PHASE – Degrees

0

–20

–40

–120

160

130

100

–140

–160

–180

–60

–80

–100

SERIES 1

IMPEDANCE

ZI(s)

SERIES 2

PHASE

where R1 is the input resistance to A2/A2B, and τ1 (equal to

g

CD × R1 × A2) is the open loop dominate time constant.

AD8011

and TO(s ) =

140

120

100

80

60

GAIN – dB Ohms

40

20

0

1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09

TO(s)

FREQUENCY – Hz

|A2| ×R1

2

sτ1+1

GAIN

PHASE

0

–40

–80

–120

–160

–200

–240

–280

rees

PHASE – De

Figure 31. Open-Loop Transimpedance Gain

Note that the ac open-loop plots in Figures 31, 32 and 33 are
based on the full Spice AD8011 simulations and do not include
external parasitics (see below). Nevertheless, these ac loop equa­tions still provide a good approximation to simulated and actual
performance up to the CLBW of the amplifier. Typically g
R1 is –4, resulting in A
time domain (inverse Laplace of A
causing V

to exponentially rail out of its linear region. When

O

(s) having a right half plane pole. In the

O

) it appears as unstable,

O

mc

×

the loop is closed however, the BW is greatly extended and the
transimpedance gain, T
the amplifiers stability behavior due to Z

(s) “overrides” and directly controls

O

approaching 1/2 g

I

mf

for s>>1/τ1. See Figure 32. This can be seen by the ZI (s) and

(s) noninverting transfer equations below.

A

V

ZI(s ) =

(1 – gmc× R1)

2 × gmf(Sτ1+1)



Sτ1



1 – gmc× R1



+1






AV(s ) =






1+

R

G

+

T

A

O

O

G




2 g





mfTO

G







F

Sτ1





R





F

+

+1



T





O



Figure 32. Open-Loop Inverting Input Impedance

ZI (s) goes positive real and approaches 1/2 gmf as ω approaches
(g

× R1 – 1)/τ1. This results in the input resistance for the

mc

A

(s) complex term being 1/2 gmf; the parallel thermal emitter

V

resistances of Q3/Q4. Using the computed CLBW from A

(s)

V

above and the nominal design values for the other parameters,
results in a closed loop 3 dB BW equal to the open loop corner
frequency (1/2 πτ1) times 1/[G/(2 g
fixed R
gains and G/(2 g

, the 3 dB BW is controlled by the RF/TO term for low

F

× TO) for high gains. For example, using

mf

nominal design parameters and R
nominal T
(inverting I-V mode with R

of 1.2 MΩ, the computed BW is 80 MHz for G = 0

O

removed) and 40 MHz for

N

× TO) + RF/TO]. For a

mf

= 1 kΩ (which results in a

1

G = +10/–9.

DRIVING CAPACITIVE LOADS

The AD8011 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, best
settling response is obtained by the addition of a small series
resistance as shown in Figure 33. The accompanying graph
shows the optimum value for R

vs. capacitive load. It is

SERIES

worth noting that the frequency response of the circuit when
driving large capacitive loads will be dominated by the passive
roll-off of R

SERIES

1k⍀

and CL.

1k⍀

AD8011

R

SERIES

1k⍀

R

L

C

L

REV. B

Figure 33. Driving Capacitive Load

–11–

AD8011

40

30

– ⍀

SERIES

R

20

10

010152025

Figure 34. Recommended R

≤

30 ns Settling to 0.1%

5

C

– pF

L

vs. Capacitive Load for

SERIES

OPTIMIZING FLATNESS

As mentioned, the ac transfer equations above are based on
a simplified single pole model. Due to the devices internal para­sitics (primarily CP1/CP1B and CP2 in Figure 28) and
external package/board parasites (partially represented in Figure

34) the computed BW, using the V

(s) equation above, typi-

O

cally will be lower than the AD8011’s measured small signal
BW. See data sheet Bode plots.

With internal parasitics included only, the BW is extended do to
the complex pole pairs created primarily by CP1/CP2B and CP2
versus the single-pole assumption shown above. This results in a
“design controlled” closed-loop damping factor (ζ) of nominally

0.6 resulting in the CLBW increasing by approximately 1.3×
higher than the computed single pole value above for optimized
external gains of +2/–1! As external noninverting gain (G) is
increased, the actual closed-loop bandwidth vs. the computed
single pole ac response is in closer agreement.

Inverting pin and external component capacitance (designated
C

) will further extend the CLBW do the closed loop zero cre-

P

ated by C
Using proper R

and RN储RF when operating in the noninverting mode.

P

component and layout techniques (see layout

F

section) this capacitance should be about 1.5 pF. This results in a
further incremental BW increase of almost 2× (versus the com­puted value) for G = +1 decreasing and approaching its complex
pole pair BW for gains approaching +6 or higher. As previously
discussed, the single-pole response begins to correlate well. Note
that a pole is also created by 1/2 g

and CP which prevents the

mf

AD8011 from becoming unstable. This parasitic has the greatest
effect on BW and peaking for low positive gains as the data
sheet Bode plots clearly show. For inverting operation, C

has

P

relatively much less effect on CLBW variation.

11

10

VS = ⴞ5V
G = +2

9

V

= 200mV

IN

8

7

6

GAIN – dB

5

4

3

2

1

1 10 100 500

FREQUENCY – MHz

RF = 750⍀

RF = 1k⍀

Figure 35. Flatness vs. Feedback

Output pin and external component capacitance (designated

) will further extend the devices BW and can also cause peak-

C

L

ing below and above the CLBW if too high. In the time domain,
poor step settling characteristics (ringing up to about 2 GHz
and excessive overshoot) can result. For high C

values greater

L

than about 5 pF an external series “damping” resistor is recom­mended. See section on Settling Time vs. C

. For light loads,

L

any output capacitance will reflect back on A2’s output (Z2 of
buffer A3) as both added capacitance near the CLBW (CLBW

/B) and eventually negative resistance at much higher fre-

> f

T

quencies. These added effects are proportional to the load C.
This reflected capacitance and negative resistance has the effect
of both reducing A2/s phase margin and causing high frequency
“L × C” peaking respectively. Using an external series resistor
(as specified above) reduces these unwanted effects by creating a
reflected zero to A2’s output which will reduce the peaking and
eliminate ringing. For heavy resistive loads, relatively more Load
C would be required to cause these same effects.

High inductive parasitics, especially on the supplies and inverting/
noninverting inputs, can cause modulated low level RF ringing
on the output in the transient domain. Again, proper R

compo-

F

nent and board layout practices need to be observed. Relatively
high parasitic lead inductance (roughly L >15 nh) can result in
L × C underdamped ringing. Here L/C means all associated
input pin, external component and leadframe strays including
collector to substrate device capacitance. In the ac domain, this
L × C resonance effect would typically not appear in the pass­band of the amplifier but would appear in the open loop re­sponse at frequencies well above the CLBW of the amplifier.

–12–

REV. B

AD8011

INCREASING BW AT HIGH GAINS

As presented above, for a fixed RF (feedback gain setting resis­tor) the AD8011 CLBW will decrease as R
creased G). This effect can be minimized by simply reducing R

is reduced (in-

N

F

and thus partially restoring the devices optimized BW for gains
greater than +2/–1. Note that the AD8011 is ac optimized (high
BW and low peaking) for A
Using this optimized G as a reference and the V

=+2/–1 and RF equal to 1 kΩ.

V

(s) equations

O

above, the following relationships results:

R

= 1k + 2 – G/2 gm for G = 1+ RF/R

F

N

(noninverting) or:

R

= 1k + G + 1/2 gm for G = –RF/R

F

N

(inverting)
Using 1/2 gm equal to 120 Ω results in a R

G = 5/–4 and a corresponding R

of 125 Ω. This will extend the

N

of 500 Ω for

F

AD8011’s BW to near its optimum design value of typically 180
MHz at R

= 1 kΩ. In general, for gains greater than +7/–6, R

L

F

should not be reduced to values much below 400 Ω else ac
peaking can result. Using this R

value as the a lower limit, will

F

result in BW restoration near its optimized value to the upper G
values specified. Gains greater than about +7/–6 will result
in CLBW reduction. Again, the derivations above are just
approximations.

DRIVING A SINGLE-SUPPLY A/D CONVERTER

New CMOS A/D converters are placing greater demands on the
amplifiers that drive them. Higher resolutions, faster conversion
rates and input switching irregularities require superior settling
characteristics. In addition, these devices run off a single +5 V
supply and consume little power, so good single-supply operation
with low power consumption are very important. The AD8011
is well positioned for driving this new class of A/D converters.

Figure 36 shows a circuit that uses an AD8011 to drive an
AD876, a single supply, 10-bit, 20 MSPS A/D converter that
requires only 140 mW. Using the AD8011 for level shifting and
driving, the A/D exhibits no degradation in performance com­pared to when it is driven from a signal generator.

The analog input of the AD876 spans 2 V centered at about

2.6 V. The resistor network and bias voltages provide the level
shifting and gain required to convert the 0 V to 1 V input signal
to a 3.6 V to 1.6 V range that the AD876 wants to see.

Biasing the noninverting input of the AD8011 at 1.6 V dc forces
the inverting input to be at 1.6 V dc for linear operation of the
amplifier. When the input is at 0 V, there is 3.2 mA flowing out
of the summing junction via R1 (1.6 V/499 Ω). R3 has a current
of 1.2 mA flowing into the summing junction (3.6 V–1.6 V)/

1.65 kΩ. The difference of these two currents (2 mA) must flow
through R2. This current flows toward the summing junction
and requires that the output be 2 V higher than the summing
junction or at 3.6 V.

When the input is at 1 V, there is 1.2 mA flowing into the sum­ming junction through R3 and 1.2 mA flowing out through R1.
These currents balance and leave no current to flow through
R2. Thus the output is at the same potential as the inverting
input or 1.6 V.

The input of the AD876 has a series MOSFET switch that turns
on and off at the sampling rate. This MOSFET is connected to
a hold capacitor internal to the device. The on impedance of the
MOSFET is about 50 Ω, while the hold capacitor is about 5 pF.

In a worst case condition, the input voltage to the AD876 will
change by a full-scale value (2 V) in one sampling cycle. When
the input MOSFET turns on, the output of the op amp will be
connected to the charged hold capacitor through the series
resistance of the MOSFET. Without any other series resistance,
the instantaneous current that flows would be 40 mA. This
would cause settling problems for the op amp.

The series 100 Ω resistor limits the current that flows instanta­neously after the MOSFET turns on to about 13 mA. This
resistor cannot be made too large or the high frequency perfor­mance will be affected.

The sampling MOSFET of the AD876 is closed for only half of
each cycle or for 25 ns. Approximately 7 time constants are
required for settling to 10 bits. The series 100 Ω resistor along
with the 50 Ω on resistance and the hold capacitor, create a
750 ps time constant. These values leave a comfortable margin
for settling. Obtaining the same results with the op amp A/D
combination as compared to driving with a signal generator
indicates that the op amp is settling fast enough.

Overall the AD8011 provides adequate buffering for the AD876
A/D converter without introducing distortion greater than that
of the A/D converter by itself.

+5V

0.1␮F

R3

50⍀

1.65k⍀

R1

499k⍀

0.1␮F

1.6V

3.6V

0.1␮F

V

1V

0V

IN

R2

1k⍀

AD8011

3.6V

1.6V

10␮F

100⍀

+3.6V

REFT

AD876

REFB

+1.6V

Figure 36. AD8011 Driving the AD876

REV. B

–13–

AD8011

LAYOUT CONSIDERATIONS

The specified high speed performance of the AD8011 requires
careful attention to board layout and component selection.
Table I shows the recommended component values for the
AD8011 and Figures 38–40 show the layout for the AD8011
evaluation board (8-lead SOIC, Gain = +2). Proper R

design

F

techniques and low parasitic component selection are mandatory.

The PCB should have a ground plane covering all unused por­tions of the component side of the board to provide a low im­pedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.

Chip capacitors should be used for supply bypassing (see Fig­ure 37). One end should be connected to the ground plane
and the other within 1/8 in. of each power pin. An additional
(4.7 µF–10 µF) tantalum electrolytic capacitor should be con-
nected in parallel.

The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance greater than 1.5 pF at the inverting
input will significantly affect high speed performance when
operating at low noninverting gains.

Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with the
proper system characteristic impedance and be properly termi­nated at each end.

R

V

IN

V

IN

G

R

T

R

G

R

T

R

F

INVERTING CONFIGURATION

R

F

NONINVERTING CONFIGURATION

C1

0.01␮F

C2

0.01␮F

C1

0.01␮F

C2

0.01␮F

R

O

C3
10␮F

C4
10␮F

R

O

C3
10␮F

C4
10␮F

V

OUT

+V

S

–V

S

V

OUT

+V

S

–V

S

Figure 37. Inverting and Noninverting Configurations

Table I. Typical Bandwidth vs. Gain Setting Resistors

Small Signal –3 dB BW

Gain RF (⍀)R

(⍀)R

G

(⍀) (MHz), VS = ⴞ5 V

T

–1 1000 1000 52.3 150
–2 1000 499 54.9 130
–10 499 49.9 140

+1 1000 49.9 400
[phone] 49.9 250
+10 422 47.5 49.9 100
[phone] 49.9 70
+6 500 100 49.9 170

RT chosen for 50 Ω characteristic input impedance.
RO chosen for characteristic output impedance.

–14–

REV. B

Figure 38. Evaluation Board Silkscreen (Top)

AD8011

REV. B

Figure 39. Evaluation Board Layout (Solder Side)

Figure 40. Evaluation Board Layout (Component Side)

–15–

AD8011

PIN 1

0.210

(5.33)

MAX

0.160 (4.06)

0.115 (2.93)

0.022 (0.558)

0.014 (0.356)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead Plastic DIP

(N-8)

0.430 (10.92)

0.348 (8.84)

8

0.100 (2.54)

5

0.280 (7.11)

14

BSC

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.070 (1.77)

0.045 (1.15)

0.130
(3.30)
MIN

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

8-Lead Plastic SOIC

(SO-8)

0.195 (4.95)

0.115 (2.93)

C01048a–0–7/00 (rev. B)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0098 (0.25)

0.0040 (0.10)

SEATING

0.1968 (5.00)

0.1890 (4.80)

85

0.0500 (1.27)
BSC

PLANE

0.2440 (6.20)

0.2284 (5.80)

41

0.0192 (0.49)

0.0138 (0.35)

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0075 (0.19)

0.0196 (0.50)

0.0099 (0.25)

8ⴗ

0.0500 (1.27)

0ⴗ

0.0160 (0.41)

ⴛ 45ⴗ

–16–

PRINTED IN U.S.A.

REV. B