Datasheet AD8009JRT-REEL7, AD8009JRT-REEL, AD8009AR-REEL7, AD8009AR-REEL, AD8009AR Datasheet (Analog Devices)

1 GHz, 5,500 V/␮s

a

FEATURES
Ultrahigh Speed

5,500 V/␮s Slew Rate, 4 V Step, G = +2
545 ps Rise Time, 2 V Step, G = +2
Large Signal Bandwidth

440 MHz, G = +2
320 MHz, G = +10

Small Signal Bandwidth (–3 dB)

1 GHz, G = +1
700 MHz, G = +2

Settling Time 10 ns to 0.1%, 2 V Step, G = +2

Low Distortion Over Wide Bandwidth

SFDR

–44 dBc @ 150 MHz, G = +2, V
–41 dBc @ 150 MHz, G = +10, V

3rd Order Intercept (3IP)

26 dBm @ 70 MHz, G = +10
18 dBm @ 150 MHz, G = +10

Good Video Specifications

Gain Flatness 0.1 dB to 75 MHz

0.01% Differential Gain Error, R

0.01ⴗ Differential Phase Error, R

High Output Drive

175 mA Output Load Drive
10 dBm with –38 dBc SFDR @ 70 MHz, G = +10

Supply Operation

ⴞ5 V Voltage Supply
14 mA (Typ) Supply Current

APPLICATIONS
Pulse Amplifier
IF/RF Gain Stage/Amplifiers
High Resolution Video Graphics
High Speed Instrumentations
CCD Imaging Amplifier

2

1

0

–1

VO = 2Vp–p

–2

–3

–4

–5

NORMALIZED GAIN – dB

–6

–7

–8

1

FREQUENCY RESPONSE – MHz

Figure 1. Large Signal Frequency Response; G = +2 & +10

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

= 2 V p-p

O

= 2 V p-p

O

= 150 ⍀

L

= 150 ⍀

L

G = +10

= 200⍀

R

F

RL = 100⍀

100

G = +2

= 301⍀

R

F

RL = 150⍀

100010

Low Distortion Amplifier

AD8009

FUNCTIONAL BLOCK DIAGRAMS

8-Lead Plastic SOIC (SO-8) 5-Lead SOT-23 (RT-5)

AD8009

1

NC

2

–IN

3

+IN

4

–V

S

NC = NO CONNECT

8

NC

7

+V

6

OUT

NC

5

V

S

PRODUCT DESCRIPTION

The AD8009 is an ultrahigh speed current feedback amplifier
with a phenomenal 5,500 V/µs slew rate that results in a rise
time of 545 ps, making it ideal as a pulse amplifier.

The high slew rate reduces the effect of slew rate limiting and
results in the large signal bandwidth of 440 MHz required for
high resolution video graphic systems. Signal quality is main­tained over a wide bandwidth with worst case distortion of
–40 dBc @ 250 MHz (G = +10, 1 V p-p). For applications
with multitone signals such as IF signal chains, the third order
Intercept (3IP) of 12 dBm is achieved at the same frequency.
This distortion performance coupled with the current feedback
architecture make the AD8009 a flexible component for a gain
stage amplifier in IF/RF signal chains.

The AD8009 is capable of delivering over 175 mA of load
current and will drive four back terminated video loads while
maintaining low differential gain and phase error of 0.02% and

0.04° respectively. The high drive capability is also reflected in
the ability to deliver 10 dBm of output power @ 70 MHz with
–38 dBc SFDR.

The AD8009 is available in a small SOIC package and will
operate over the industrial temperature range –40°C to +85°C.
The AD8009 is also available in an SOT-23-5 and will operate
over the commercial temperature range 0°C to +70°C.

–30

G = 2

–40

R

= 301⍀

F

= 2V p-p

V

O

–50

–60

–70

DISTORTION – dBc

–80

–90

–100

1 20010 100

2ND,

150⍀ LOAD

FREQUENCY RESPONSE – MHz

2ND,

100⍀ LOAD

3RD,
150⍀ LOAD

Figure 2. Distortion vs. Frequency; G = +2

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD8009

1

OUT

2

–V

S

+IN

34

3RD,
100⍀ LOAD

5

+V

–IN

S

AD8009–SPECIFICATIONS

(@ TA = 25ⴗC, VS = ⴞ5 V, RL = 100 ⍀, for R Package: RF = 301 ⍀ for G = +1, +2,

RF = 200 ⍀ for G = +10, for RT Package: RF = 332 ⍀ for G = +1, RF = 226 ⍀ for G = +2 and RF = 191 for G = +10, unless otherwise noted.)

AD8009AR/JRT

Model Conditions Min Typ Max Units

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth, V

R Package G = +1, R
RT Package G = +1, R

= 0.2 V p-p

O

= 301 Ω 1000 MHz

F

= 332 Ω 845 MHz

F

G = +2 480 700 MHz
G = [phone] MHz

Large Signal Bandwidth, V

= 2 V p-p G = +2 390 440 MHz

O

G = [phone] MHz
Gain Flatness 0.1 dB, V
Slew Rate G = +2, R
Settling Time to 0.1% G = +2, R

= 0.2 V p-p G = +2, RL = 150 Ω 45 75 MHz

O

= 150 Ω, 4 V Step 4500 5500 V/µs

L

= 150 Ω, 2 V Step 10 ns

L

G = +10, 2 V Step 25 ns
Rise and Fall Time G = +2, RL = 150 Ω, 4 V Step 0.725 ns

HARMONIC/NOISE PERFORMANCE

SFDR G = +2, V

= 2 V p-p 5 MHz –74 dBc

O

70 MHz –53 dBc

150 MHz –44 dBc

SFDR G = +10, V

= 2 V p-p 5 MHz –58 dBc

O

70 MHz –41 dBc

150 MHz –41 dBc
Third Order Intercept (3IP) 70 MHz 26 dBm

W.R.T. Output, G = +10 150 MHz 18 dBm

250 MHz 12 dBm
Input Voltage Noise f = 10 MHz 1.9 nV/√Hz
Input Current Noise f = 10 MHz, +In 46 pA/√Hz

f = 10 MHz, –In 41 pA/√Hz

Differential Gain Error NTSC, G = +2, R

NTSC, G = +2, R

Differential Phase Error NTSC, G = +2, R

= 150 Ω 0.01 0.03 %

L

= 37.5 Ω 0.02 0.05 %

L

= 150 Ω 0.01 0.03 Degrees

L

NTSC, G = +2, RL = 37.5 Ω 0.04 0.08 Degrees

DC PERFORMANCE

Input Offset Voltage 25 mV

T

MIN–TMAX

7mV

Offset Voltage Drift 4 µV/°C
–Input Bias Current 50 150 ±µA

T

MIN–TMAX

75 ±µA

+Input Bias Voltage 50 150 ±µ A

T

MIN–TMAX

75 ±µA

Open Loop Transresistance 90 250 kΩ

T

MIN–TMAX

170 kΩ

INPUT CHARACTERISTICS

Input Resistance +Input 110 kΩ

–Input 8 Ω
Input Capacitance +Input 2.6 pF
Input Common-Mode Voltage Range 3.8 ±V
Common-Mode Rejection Ratio VCM = ±2.5 50 52 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing ±3.7 ±3.8 V
Output Current R

= 10 Ω, PD Package = 0.7 W 150 175 mA

L

Short Circuit Current 330 mA

POWER SUPPLY

Operating Range ±4 ±6V
Quiescent Current 14 16 mA

T

MIN–TMAX

18 mA

Power Supply Rejection Ratio VS = ±4 V to ±6 V 64 70 dB

Specifications subject to change without notice.

–2–

REV. C

AD8009

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V

Internal Power Dissipation

2

1

Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . 0.75 Watts

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 3.5 V

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves

Storage Temperature Range R Package . . . . –65°C to +125°C

Operating Temperature Range (A Grade) . . . –40°C to +85°C

Operating Temperature Range (J Grade) . . . . . . 0°C to +70°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for device in free air:

8-Lead SOIC Package: θJA = 155°C/W.

5-Lead SOT-23 Package: θJA = 240°C/W.

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8009 is limited by the associated rise in junction tempera­ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 150°C. Exceeding
this limit temporarily may cause a shift in parametric perfor­mance due to a change in the stresses exerted on the die by the
package. Exceeding a junction temperature of 175°C for an
extended period can result in device failure.

While the AD8009 is internally short circuit protected, this
may not be sufficient to guarantee that the maximum junction
temperature (150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maxi­mum power derating curves.

2.0

TJ = +150°C

1.5

8-LEAD SOIC PACKAGE

1.0

0.5

MAXIMUM POWER DISSIPATION – Watts

0
–50

5-LEAD SOT-23 PACKAGE

AMBIENT TEMPERATURE – °C

9080

706050403020100–40 –30 –20 –10

Figure 3. Plot of Maximum Power Dissipation vs.
Temperature

ORDERING GUIDE

Temperature Package Package Branding

Model Range Description Option Information

AD8009ACHIPS –40°C to +85°C Die
AD8009AR –40°C to +85°C 8-Lead SOIC SO-8
AD8009AR-REEL –40°C to +85°C 8-Lead SOIC 13" Tape and Reel
AD8009AR-REEL7 –40°C to +85°C 8-Lead SOIC 7" Tape and Reel
AD8009JRT-REEL 0°C to +70°C 5-Lead SOT-23 13" Tape and Reel HKJ
AD8009JRT-REEL7 0°C to +70°C 5-Lead SOT-23 7" Tape and Reel HKJ
AD8009-EB Evaluation Board SO-8

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8009 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. C

–3–

AD8009

–Typical Performance Characteristics

3

NORMALIZED GAIN – dB

2

1

0

–1

–2

–3

–4

–5

–6

–7

1

R PACKAGE
R

L

V

O

G = +1, +2: R

G = +10: R
RT PACKAGE

G = +1: RF = 332⍀
G = +2: RF = 226⍀
G = +10: R

:

= 100⍀

= 200mV p–p

F

= 200⍀

F

= 191⍀

F

= 301⍀

:

10 100

FREQUENCY – MHz

G = +1, RT

G = +2, R & RT

G = +10, R & RT

G = +1, R

1000

Figure 4. Frequency Response; G = +1, +2, +10, R and RT
Packages

8

7

6

5

G = +2

4

R

= 301⍀

GAIN – dB

3

2

1

0

–1

–2

F

RL = 150⍀
VO AS SHOWN

FREQUENCY – MHz

4V p–p

2V p–p

1001 100010

Figure 5. Large Signal Frequency Response; G = +2

6.2

6.1

6.0

5.9
G = +2

R

= 301⍀

5.8

F

= 150⍀

R

L

5.7

VO = 200mV p–p

5.6

5.5

GAIN FLATNESS – dB

5.4

5.3

5.2

10 1001

FREQUENCY – MHz

1000

Figure 7. Gain Flatness; G = +2

22

21

20

19

GAIN – dB

G = +10

18

17

16

15

14

13

12

= 200⍀

R

F

RL = 100⍀

AS SHOWN

V

O

4V p–p

1001 100010

FREQUENCY – MHz

2V p–p

Figure 8. Large Signal Frequency Response; G = +10

8

GAIN – dB

7

6

5

4

3

2

1

0

–1

–2

G = +2
RF = 301⍀

= 150⍀

R

L

VO = 2V p–p

–40ⴗC

1001 100010

FREQUENCY – MHz

+85ⴗC

–40ⴗC

+85ⴗC

Figure 6. Large Signal Frequency Response vs.

Temperature; G = +2

–4–

22

21

20

GAIN – dB

19

G = +10

18

= 200⍀

R

F

RL = 100⍀

17

= 2V p–p

V

O

16

15

14

13

12

FREQUENCY – MHz

1001 100010

–40ⴗC

+85ⴗC

Figure 9. Large Signal Frequency Response vs.
Temperature; G = +10

REV. C

–30

–30

–35

–80

–40

–45

–50

–55

–60

–65

–70

–75

DISTORTION – dBc

100105 200

FREQUENCY – MHz

G = +10
R

F

= 200⍀
RL = 100⍀
VO = 2V p–p

2ND

3RD

–40

–50

G = 2

= 301⍀

R

F

V

= 2V p-p

O

2ND,

100⍀ LOAD

AD8009

–60

–70

DISTORTION – dBc

–80

–90

–100

1 20010 100

2ND,

150⍀ LOAD

3RD,
150⍀ LOAD

FREQUENCY RESPONSE – MHz

3RD,
100⍀ LOAD

Figure 10. Distortion vs. Frequency; G = +2

–35

250MHz

–40

–45

–50

–55

–60

–65

–70

DISTORTION – dBc

–75

–80

–85

–10 12–6 –4 –2 0 2 4 6 8 10 14–8

70MHz

P

OUT

– dBm

22.1⍀

50⍀

5MHz

200⍀

Figure 11. 2nd Harmonic Distortion vs. P

50⍀

P

OUT

50⍀

; (G = +10)

OUT

Figure 13. Distortion vs. Frequency; G = +10

–35

–40

–45

–50

–55

–60

–65

–70

–75

DISTORTION – dBc

–80

–85

–90

–95

–10 –812–6 –4 –20 24 6810

250MHz

70MHz

5MHz

200⍀

22.1⍀

50⍀

P

– dBm

OUT

Figure 14. 3rd Harmonic Distortion vs. P

50⍀

P

OUT

50⍀

; (G = +10)

OUT

14

REV. C

0.02
G = +2

= 301⍀

R

0.01

0.00

–0.01

DIFF GAIN – %

–0.02

0.10

0.05

–0.00

–0.05

–0.10

DIFF PHASE – Degrees

F

RL = 37.5⍀

0

G = +2

= 301⍀

R

F

RL = 150⍀

0

Figure 12. Differential Gain and Phase

IRE

RL = 37.5⍀

IRE

RL = 150⍀

100

100

–5–

50

45

40

35

30

25

INTERCEPT POINT – dBm

20

15

10

10 250100

FREQUENCY – MHz

22.1⍀

50⍀

200⍀

50⍀

50⍀

P

OUT

Figure 15. Two Tone, 3rd Order IMD Intercept vs.
Frequency; G = +10

AD8009

1M

100k

RL = 100⍀

10k

TRANSRESISTANCE– ⍀

1k

100

0.01 0.1 1001

GAIN

PHASE

FREQUENCY – MHz

0

–40

–80

–120

–160

100010

Figure 16. Transresistance and Phase vs. Frequency

10

G = +2

PSRR – dB

–10

–20

–30

–40

–50

–60

–70

0

0.03

= 301⍀

R

F

RL = 100⍀
100mV p–p ON TOP OF V

0.1 10010

1 500

S

–PSRR

FREQUENCY – MHz

+PSRR

Figure 17. PSRR vs. Frequency

PHASE – Degrees

CMRR– dB

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

–60

VIN =

200mVp–p

301⍀

301⍀

154⍀

154⍀

FREQUENCY – MHz

100⍀

V

O

1001 100010

Figure 19. CMRR vs. Frequency

100

G = +2
R

= 301⍀

F

10

1

0.1

OUTPUT RESISTANCE – ⍀

0.01

0.1 100101 500

0.03

FREQUENCY – MHz

Figure 20. Output Resistance vs. Frequency

300

250

Hz

200

150

100

INPUT CURRENT – pA

50

0

10 100 250M1k 10k 100k 1M 10M 100M

NONINVERTING CURRENT

INVERTING CURRENT

FREQUENCY – Hz

Figure 18. Current Noise vs. Frequency

–6–

10

Hz

8

6

4

2

INPUT VOLTAGE NOISE – nV

0

10 100 250M1k 10k 100k 1M 10M 100M

FREQUENCY – Hz

Figure 21. Voltage Noise vs. Frequency

REV. C

AD8009

NOISE FIGURE – dB

2.0

1.8

1.6

1.4

VSWR

1.2

– dB

S

–20

–30

G = +10
R

= 200⍀

F

–40

–50

–60

12

–70

–80

25

20

15

G = +10

= 301⍀

R

F

RL = 100⍀

10

5

–90

0

SOURCE RESISTANCE – ⍀

Figure 22. Noise Figure

1

100101 500

FREQUENCY – MHz

1001 100010

Figure 25. Reverse Isolation (S

2.2

C

200⍀

COMP

49.9⍀

C

COMP

C

COMP

2.0

1.8

1.6

VSWR

1.4

1.2

49.9⍀

22.1⍀

1

); G = +10

12

= 0pF

= 3pF

0

0.1 1 10010
FREQUENCY – MHz

500

Figure 23. Input VSWR; G = +10

20

18

16

14

12

10

MAX – dBm

OUT

P

8

6

4

2

0

R

G

50⍀

5 10010

R

F

50⍀

50⍀

FREQUENCY – MHz

G = +10
R

P

OUT

= 200⍀

F

G = +2

= 301⍀

R

F

250

Figure 24. Maximum Output Power vs. Frequency

0

0.1 1 10010
FREQUENCY – MHz

Figure 26. Output VSWR; G = +10

G = +10

= 200⍀

100

90

10

0%

V

OUT

V

= 2V

IN

STEP

2V

2V

R
R

250ns

F

= 100⍀

L

Figure 27. Overdrive Recovery; G = +10

500

REV. C

–7–

AD8009

G = +2

= 301⍀

R

F

= 150⍀

R

L

V

= 200mV p–p

O

50mV

1ns

Figure 28. Small Signal Transient Response; G = +2

G = +2

= 301⍀

R

F

= 150⍀

R

L

V

= 2V p–p

O

G = +10

= 200⍀

R

F

R

= 100⍀

L

VO = 200mV p–p

50mV

2ns

Figure 31. Small Signal Transient Response; G = +10

G = +10

= 200⍀

R

F

RL = 100⍀

= 2V p–p

V

O

500mV

1ns

Figure 29. 2 V Transient Response; G = +2

G = +2

= 301⍀

R

F

RL = 150⍀

= 4V p–p

V

O

1.5ns1V

Figure 30. 4 V Transient Response; G = +2

500mV

2ns

Figure 32. 2 V Transient Response; G = +10

G = +10
R

= 200⍀

F

RL = 100⍀
VO = 4V p–p

1V

3ns

Figure 33. 4 V Transient Response; G = +10

–8–

REV. C

AD8009

CENTER 50.000 MHz SPAN 80.000 MHz

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

REJECTION – dB

AD8009
G = 2
R

F

= RG= 301⍀

DRIVING
WAVETEK 5201
TUNABLE BPF
f

C

= 50MHz

GAIN – dB

8

7

6

C

5

4

3

2

V

IN

1

0

–1

50⍀

499⍀

C

499⍀

A

1

A

1 dB/div

V

= 200mV p–p

OUT

V

100⍀

10

FREQUENCY – MHz

= 1pF

C

A

1 dB/div

OUT

= 0pF

100

CA = 2pF

3 dB/div

1000

12

9

6

3

0

–3

–6

–9

–12

–15

GAIN – dB

Figure 34. Small Signal Frequency Response vs. Parasitic
Capacitance

CA = 1pF

CA = 2pF

CA = 0pF

V

50⍀

C

IN

A

V

= 200mV p–p

OUT

= ⴞ5V

V

S

499⍀

499⍀

V

OUT

100⍀

HP8753D

0.1␮F

49.9⍀

0.1␮F

ZIN = 50⍀

+

10␮F

10␮F

+

WAVETEK 5201

BPF

49.9⍀

2

3

301⍀

+5V

7

–5V

AD8009

6

4

301⍀

Z

= 50⍀

OUT

0.001␮F

0.001␮F

Figure 36. AD8009 Driving a Bandpass RF Filter

40mV

Figure 35. Small Signal Pulse Response vs. Parasitic

1.5ns

Figure 37. Frequency Response of Bandpass Filter Circuit

Capacitance

APPLICATIONS

All current feedback op amps are affected by stray capacitance
on their –INPUT. Figures 34 and 35 illustrate the AD8009’s
response to such capacitance.

Figure 34 shows the bandwidth can be extended by placing a
capacitor in parallel with the gain resistor. The small signal pulse
response corresponding to such an increase in capacitance/
bandwidth is shown in Figure 35.

As a practical consideration, the higher the capacitance on the
–INPUT to GND, the higher R

needs to be to minimize

F

peaking/ringing.

RF Filter Driver

The output drive capability, wide bandwidth and low distortion
of the AD8009 are well suited for creating gain blocks that can
drive RF filters. Many of these filters require that the input be
driven by a 50 Ω source, while the output must be terminated in
50 Ω for the filters to exhibit their specified frequency response.

REV. C

Figure 36 shows a circuit for driving and measuring the
frequency response of a filter, a Wavetek 5201 Tunable Band
Pass Filter that is tuned to a 50 MHz center frequency. The
HP8753D network provides a stimulus signal for the measure­ment. The analyzer has a 50 Ω source impedance that drives a
cable that is terminated in 50 Ω at the high impedance nonin­verting input of the AD8009.

The AD8009 is set at a gain of two. The series 50 Ω resistor at
the output, along with the 50 Ω termination provided by the
filter and its termination, yield an overall unity gain for the
measured path. The frequency response plot of Figure 37
shows the circuit to have an insertion loss of 1.3 dB in the pass
band and about 75 dB rejection in the stop band.

–9–

AD8009

75⍀ COAX PRIMARY MONITOR

R

I

OUT

75⍀

RED

75⍀

ADV7160
ADV7162

I

G

OUT

75⍀

I

B

OUT

75⍀

5V

0.1␮F

7

3

AD8009

2

301⍀

3

AD8009

2

301⍀

3

AD8009

2

6

4

301⍀

–5V

6

301⍀

6

75⍀

75⍀

75⍀

+

10␮F

75⍀ COAX

+

GREEN

BLUE

RED

10␮F0.1␮F

GREEN

BLUE

75⍀

75⍀

ADDITIONAL MONITOR

75⍀

75⍀

75⍀

301⍀

301⍀

Figure 38. Driving an Additional High Resolution Monitor Using Three AD8009s

RGB Monitor Driver

High resolution computer monitors require very high full power
bandwidth signals to maximize their display resolution. The
RGB signals that drive these monitors are generally provided by
a current-out RAMDAC that can directly drive a 75 Ω doubly
terminated line.

There are times when the same output wants to be delivered to
additional monitors. The termination provided internally by
each monitor prohibits the ability to simply connect a second
monitor in parallel with the first. Additional buffering must be
provided.

Figure 38 shows a connection diagram for two high resolution
monitors being driven by an ADV7160 or ADV7162, a 220 MHz
(Mega-pixel per second) triple RAMDAC. This pixel rate
requires a driver whose full power bandwidth is at least half the
pixel rate or 110 MHz. This is to provide good resolution for a
worst case signal that swings between zero scale and full scale
on adjacent pixels.

The primary monitor is connected in the conventional fashion
with a 75 Ω termination to ground at each end of the 75 Ω
cable. Sometimes this configuration is called “doubly termi­nated” and is used when the driver is a high output impedance
current source.

For the additional monitor, each of the RGB signals close to the
RAMDAC output is applied to a high input impedance, noninvert­ing input of an AD8009 that is configured for a gain of +2. The
outputs each drive a series 75 Ω resistor, cable and termination
resistor in the monitor that divides the output signal by two, thus
providing an overall unity gain. This scheme is referred to as
“back termination” and is used when the driver is a low output
impedance voltage source. Back termination requires that the
voltage of the signal be double the value that the monitor sees.
Double termination requires that the output current be double the
value that flows in the monitor termination.

–10–

REV. C

AD8009

Driving a Capacitive Load

A capacitive load, like that presented by some A/D converters,
can sometimes be a challenge for an op amp to drive depending
on the architecture of the op amp. Most of the problem is
caused by the pole created by the output impedance of the op
amp and the capacitor that is driven. This creates extra phase
shift that can eventually cause the op amp to become unstable.

One way to prevent instability and improve settling time when
driving a capacitor is to insert a resistor in series between the op
amp output and the capacitor. The feedback resistor is still
connected directly to the output of the op amp, while the series
resistor provides some isolation of the capacitive load from the
op amp output.

G = + 2: RF = 301⍀ = R

G = + 10: RF = 200⍀, RG = 22.1⍀

R

49.9⍀

T

+5V

G

0.001␮F

3

7

2V

STEP

AD8009

2

R

R

G

6

4

F

–5V

0.1␮F

R

S

0.1␮F0.001␮F

+

10␮F

C

50pF

L

10␮F

+

Figure 39. Capacitive Load Drive Circuit

Figure 39 shows such a circuit with an AD8009 driving a 50 pF
load. With R
gain of +2 and +10, it was found experimentally that setting R

= 0, the AD8009 circuit will be unstable. For a

S

S

to 42.2 Ω will minimize the 0.1% settling time with a 2 V step at
the output. The 0.1% settling time was measured to be 40 ns with
this circuit.

For smaller capacitive loads, a smaller R
settling time, while a larger R

will be required for larger

S

will yield optimal

S

capacitive loads. Of course, a larger capacitance will always
require more time for settling to a given accuracy than a smaller
one, and this will be lengthened by the increase in R

required.

S

At best, a given RC combination will require about 7 time
constants by itself to settle to 0.1%, so a limit will be reached
where too large a capacitance cannot be driven by a given
op amp and still meet the system’s required settling time
specification.

REV. C

–11–

AD8009

0.1574 (4.00)

0.1497 (3.80)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead SOIC

(SO-8)

0.1968 (5.00)

0.1890 (4.80)

8

5

0.2440 (6.20)

41

0.2284 (5.80)

0.0098 (0.25)

0.0040 (0.10)

0.0669 (1.70)

0.0590 (1.50)

0.0512 (1.30)

0.0354 (0.90)

0.0059 (0.15)

0.0019 (0.05)

SEATING

PLANE

PIN 1

0.0500
(1.27)

BSC

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

0.0098 (0.25)

0.0075 (0.19)

0.0196 (0.50)

0.0099 (0.25)

8°
0°

0.0500 (1.27)

0.0160 (0.41)

5-Lead Plastic Surface Mount (SOT-23)

(RT-5)

0.1181 (3.00)

0.1102 (2.80)

4 5

0.1181 (3.00)

0.1024 (2.60)

0.0374 (0.95) BSC

0.0571 (1.45)

0.0374 (0.95)

SEATING
PLANE

10ⴗ

0ⴗ

PIN 1

1 3

2

0.0748 (1.90)

BSC

0.0197 (0.50)

0.0138 (0.35)

x 45°

C01011–0–9/00 (rev. C)

0.0079 (0.20)

0.0031 (0.08)

0.0217 (0.55)

0.0138 (0.35)

–12–

PRINTED IN U.S.A.

REV. C