Datasheet AD80066 Datasheet (ANALOG DEVICES)

Complete 16-Bit

A

A

FEATURES

16-bit, 24 MSPS analog-to-digital converter (ADC)
4-channel operation up to 24 MHz (6 MHz/channel)
3-channel operation up to 24 MHz (8 MHz/channel)
Selectable input range: 3 V or 1.5 V peak-to-peak
Input clamp circuitry
Correlated double sampling
1×~6× programmable gain
±300 mV programmable offset
Internal voltage reference
Multiplexed byte-wide output
Optional single-byte output mode
3-wire serial digital interface
3 V/5 V digital I/O compatibility
Power dissipation: 490 mW at 24 MHz operation
Reduced power mode and sleep mode available
28-lead SSOP package

APPLICATIONS

Flatbed document scanners
Film scanners
Digital color copiers
Multifunction peripherals

FUNCTIONAL BLOCK DIAGRAM

AVDD AVSS CML

CCD/CIS Signal Processor

GENERAL DESCRIPTION

The AD80066 is a complete analog signal processor for imaging
applications. It features a 4-channel architecture designed to sample
and condition the outputs of linear charged coupled device (CCD)
or contact image sensor (CIS) arrays. Each channel consists of
an input clamp, correlated double sampler (CDS), offset digital­to-analog converter (DAC), and programmable gain amplifier
(PGA), multiplexed to a high performance 16-bit ADC. For
maximum flexibility, the AD80066 can be configured as a
4-channel, 3-channel, 2-channel, or 1-channel device.

The CDS amplifiers can be disabled for use with sensors that
do not require CDS, such as CIS and CMOS sensors.

The 16-bit digital output is multiplexed into an 8-bit output word,
which is accessed using two read cycles. There is an optional
single-byte output mode. The internal registers are programmed
through a 3-wire serial interface and enable adjustment of the
gain, offset, and operating mode. The AD80066 operates from a
5 V power supply, typically consumes 490 mW of power, and is
packaged in a 28-lead SSOP.

VDD CAPT CAPB

VSS

AD80066

DRVDD DRVSS

VINA

VINB

VINC

VIND

OFFSET

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

CDS

CDS

CDS

CDS

INPUT

CLAMP

BIAS

CDSCLK2CDSCLK1

9-BIT

DAC

9-BIT

DAC

9-BIT

DAC

9-BIT

DAC

PGA

PGA

PGA

PGA

9

6

CH. A
CH. B
CH. C
CH. D

4:1

MUX

CONFIGURAT ION

CH. A
CH. B
CH. C
CH. D

OFFSET
REGISTERS

BAND GAP

REFERENCE

16-BIT

ADC

REGISTER

MUX

REGISTER

GAIN
REGISTERS

ADCCLK

AD80066

16

DIGITAL

CONTROL

INTERFACE

16:8
MUX

8

DOUT
(D[0:7])

SCLK

SLOAD

SDATA

8552-001

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

AD80066

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Analog Specifications ................................................................... 3

Digital Specifications ................................................................... 4

Timing Specifications .................................................................. 5

Absolute Maximum Ratings ............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 12

Theory of Operation ...................................................................... 13

4-Channel CDS Mode ................................................................ 13

4-Channel SHA Mode ................................................................ 13

1-Channel CDS Mode ............................................................... 13

1-Channel SHA Mode ............................................................... 13

Internal Register Map .................................................................... 14

Internal Register Details ................................................................ 15

Configuration Register .............................................................. 15

Mux Register ............................................................................... 15

PGA Gain Registers ................................................................... 15

Offset Registers ........................................................................... 15

Circuit Operation ........................................................................... 17

Analog Inputs—CDS Mode ...................................................... 17

External Input Coupling Capacitors ........................................ 17

Analog Inputs—SHA Mode ...................................................... 18

Programmable Gain Amplifiers (PGA) .................................. 18

Applications Information .............................................................. 19

Circuit and Layout Recommendations ................................... 19

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

4/10—Revision A: Initial Version

Rev. A | Page 2 of 20

AD80066

SPECIFICATIONS

ANALOG SPECIFICATIONS

T

to T

MIN

, AVDD = 5 V, DRVDD = 5 V, CDS mode, f

MAX

Table 1.

Parameter Min Typ Max Unit

MAXIMUM CONVERSION RATE

4-Channel Mode with CDS 24 MSPS
3-Channel Mode with CDS 24 MSPS
2-Channel Mode with CDS 24 MSPS
1-Channel Mode with CDS 12 MSPS

ACCURACY (ENTIRE SIGNAL PATH)

ADC Resolution 16 Bits
Integral Nonlinearity (INL) +20/−5 LSB
Differential Nonlinearity (DNL) ±0.5 LSB
No Missing Codes Guaranteed

ANALOG INPUTS

Input Signal Range

1

1.5/3.0 V p-p

Allowable Reset Transient1 2.0 V
Input Limits

2

AVSS − 0.3 AVDD + 0.3 V

Input Capacitance 10 pF
Input Bias Current 10 nA

AMPLIFIERS

PGA Gain Range 1 5.9 V/V
PGA Gain Resolution2 64 Steps
PGA Gain Monotonicity Guaranteed
Programmable Offset Range −305 +295 mV
Programmable Offset Resolution 512 Steps
Programmable Offset Monotonicity Guaranteed

NOISE AND CROSSTALK

Total Output Noise at PGA Minimum 9.5 LSB rms
Total Output Noise at PGA Maximum 35 LSB rms
Channel-to-Channel Crosstalk

@ 24 MSPS 70 dB
@ 12 MSPS 90 dB

POWER SUPPLY REJECTION

AVDD = 5 V ± 0.25 V 0.1 % FSR

VOLTAGE REFERENCE (TA = 25°C)

CAPT − CAPB 0.75 V

TEMPERATURE RANGE

Operating 0 70 °C
Storage −65 +150 °C

POWER SUPPLIES

AVDD 4.5 5.0 5.25 V
DRVDD 3.0 3.3 5.25 V

OPERATING CURRENT

AVDD 95 mA
DRVDD 4 mA
Power-Down Mode Current 300 μA

ADCCLK

= 24 MHz, f

CDSCLK1

= f

= 6 MHz, PGA gain = 1, unless otherwise noted.

CDSCLK2

Rev. A | Page 3 of 20

AD80066

A

Parameter Min Typ Max Unit

POWER DISSIPATION

4-Channel Mode at 24 MHz 490 mW
1-Channel Mode at 12 MHz 300 mW
4-Channel Mode at 8 MHz, Slow Power Mode

1

The linear input signal range is up to 3 V p-p when the CCD reference level is clamped to 3 V by the AD80066 input clamp (see ). Figure 2

2

The PGA gain is approximately linear-in-dB but varies nonlinearly with register code (see the section for more information). Programmable Gain Amplifiers (PGA)

3

Measured with Bit D1 of the configuration register set high for 8 MHz, low power operation.

2V TYP

RESET TRANSIENT

DIGITAL SPECIFICATIONS

T

to T

MIN

Table 2.

Parameter Symbol Min Typ Max Unit

LOGIC INPUTS

High Level Input Voltage VIH 2.0 V
Low Level Input Voltage VIL 0.8 V
High Level Input Current IIH 10 μA
Low Level Input Current IIL 10 μA
Input Capacitance CIN 10 pF

LOGIC OUTPUTS (DRVDD = 5 V)

High Level Output Voltage (IOH = 2 mA) VOH 4.5 V
Low Level Output Voltage (IOL = 2 mA) VOL 0.5 V

LOGIC OUTPUTS (DRVDD = 3 V)

High Level Output Voltage (IOH = 2 mA) VOH 2.5 V
Low Level Output Voltage (IOL = 2 mA) VOL 0.5 V

, AVDD = 5 V, DRVDD = 5 V, CDS mode, f

MAX

3

165 mW

VDD = 5V

3V BIAS SET BY INPUT CLAMP

1.5V OR 3V p-p MAX INPUT SIGNAL RANGE
GND

08552-002

Figure 2. Input Signal with the CCD Reference Level Clamped to 3 V

ADCCLK

= 24 MHz, f

CDSCLK1

= f

= 6 MHz, CL = 10 pF, unless otherwise noted.

CDSCLK2

Rev. A | Page 4 of 20

AD80066

TIMING SPECIFICATIONS

T

to T

MIN

Table 3.

Parameter Symbol Min Typ Max Unit

CLOCK PARAMETERS

4-Channel Pixel Rate t
1-Channel Pixel Rate t
ADCCLK Pulse Width t
CDSCLK1 Pulse Width tC1 15 ns
CDSCLK2 Pulse Width tC2 15 ns
CDSCLK1 Falling1 to CDSCLK2 Rising t
ADCCLK Falling to CDSCLK2 Rising t
CDSCLK2 Rising to ADCCLK Rising t
CDSCLK2 Falling1 to ADCCLK Falling t
CDSCLK2 Falling1 to CDSCLK1 Rising t
Aperture Delay for CDS Clocks tAD 2 ns

SERIAL INTERFACE

Maximum SCLK Frequency, Write Operation f
Maximum SCLK Frequency, Read Operation f
SLOAD to SCLK Setup Time tLS 5 ns
SCLK to SLOAD Hold Time tLH 5 ns
SDATA to SCLK Rising Setup Time tDS 2 ns
SCLK Rising to SDATA Hold Time tDH 2 ns
SCLK Falling to SDATA Valid t

DATA OUTPUT

Output Delay tOD 8 ns
Latency (Pipeline Delay) 3 (fixed) Cycles

1

CDSCLKx falling edges should not occur within the first 10 ns following an ADCCLK edge.

Timing Diagrams

, AVDD = 5 V, DRVDD = 5 V.

MAX

t

PRA

166 ns

PRA

83 ns

PRB

20 ns

ADCCLK

0 ns

C1C2

0 ns

ADC2

5 ns

C2ADR

20 ns

C2ADF

5 ns

C2C1

50 MHz

SCLK

25 MHz

SCLK

10 ns

RDV

ANALOG

INPUTS

CDSCLK1

CDSCLK2

ADCCLK

OUTPUT

DATA

(D[7:0])

t

ADCCLK

t

AD

t

C1

t

ADCCLK

C(n – 2)B(n – 2) C(n – 2) D(n – 2) D(n – 2) A(n – 1) A(n – 1) B(n – 1) B(n – 1) C( n – 1) C(n – 1) D(n – 1) D(n – 1) A(n) A(n) B(n )

HIGH

LOW

BYTE

HIGH
BYTE

BYTE

PIXEL n (A,B,C,D) PIXEL (n + 1)

t

AD

t

C2C1

t

C1C2

LOW

BYTE

t

ADC2

HIGH
BYTE

LOW

BYTE

t

C2

t

C2ADR

HIGH
BYTE

t

C2ADF

t

OD

LOW

HIGH

LOW

HIGH

BYTE

BYTE

BYTE

BYTE

LOW

BYTE

HIGH
BYTE

LOW

BYTE

HIGH
BYTE

Figure 3. 4-Channel CDS Mode Timing

Rev. A | Page 5 of 20

8552-003

AD80066

ANALOG

INPUTS

CDSCLK1

CDSCLK2

ADCCLK

OUTPUT

DATA

(D[7:0])

t

ADCCLK

t

AD

t

C1

B(n – 2)A(n – 2) B(n – 2) C(n – 2) C(n – 2) A(n – 1) A(n – 1) B( n – 1) B(n – 1) C(n – 1) C(n – 1) A(n) A(n) B(n) B(n)

HIGH
BYTE

PIXEL n (A, B, C) PIXEL (n + 1) PIXEL (n + 2)

t

AD

LOW

BYTE

t

C1C2

t

t

ADC2

ADCCLK

HIGH

BYTE

LOW

BYTE

t

C2

t

C2ADF

t

C2ADR

HIGH

BYTE

t

C2C1

LOW

BYTE

HIGH
BYTE

t

OD

LOW
BYTE

HIGH
BYTE

t

PRA

LOW

HIGH

LOW

BYTE

BYTE

BYTE

HIGH
BYTE

LOW

BYTE

08552-004

Figure 4. 3-Channel CDS Mode Timing

ANALOG

INPUTS

PIXEL n

t

AD

t

AD

t

C1

t

C2C1

PIXEL (n + 1) PIXEL (n + 2)

t

PRA

CDSCLK1

CDSCLK2

ADCCLK

OUTPUT

DATA

(D[7:0])

t

C1C2

t

ADC2

t

CH 1 (n – 2) CH 2 (n – 2) CH 1 (n – 1) CH 2 (n – 1) CH 1 (n)

HIGH

BYTE

ADCCLK

LOW

BYTE

t

C2ADR

t

C2

t

ADCCLK

HIGH
BYTE

t

C2ADF

LOW

BYTE

HIGH

BYTE

LOW
BYTE

HIGH
BYTE

LOW

BYTE

HIGH
BYTE

LOW

BYTE

08552-005

Figure 5. 2-Channel CDS Mode Timing

Rev. A | Page 6 of 20

AD80066

PIXEL n

ANALOG

INPUTS

CDSCLK1

CDSCLK2

ADCCLK

OUTPUT

DATA

(D[7:0])

NOTES

1. IN 1-CHANNEL CDS MODE. THE CDSCLK1 FALL ING EDGE AND THE CDSCLK2 RIS ING EDGE M UST OCCUR WHI LE ADCCLK IS LOW.

PIXEL (n – 4)

HIGH
BYTE

t

AD

t

t

ADCCLK

AD

t

C2C1

t

C2ADF

HIGH
BYTE

t

C1

t

C1C2

t

ADCCLK

PIXEL (n – 4) PIXEL (n – 3) PIXEL (n – 3) PIXEL (n – 2) PIXEL (n – 2)

LOW

BYTE

t

C2ADR

t

C2

PIXEL (n + 1) PIXEL (n + 2)

t

PRB

t

OD

LOW

BYTE

Figure 6. 1-Channel CDS Mode Timing

PIXEL n (A, B, C, D)

ANALOG

INPUTS

t

AD

HIGH

BYTE

PIXEL (n + 1)

LOW

BYTE

08552-006

t

PRA

t

C2

t

CDSCLK2

ADCCLK

OUTPUT

DATA

(D[7:0])

t

ADCCLK

t

ADCCLK

B(n – 2)

C(n – 2) C(n – 2) D(n – 2) D(n – 2) D(n) D(n) A(n) A(n)

HIGH

BYTE

LOW

BYTE

t

ADC2

HIGH
BYTE

C2ADF

t

C2ADR

t

OD

A(n – 1) A(n – 1) B(n – 1) B(n – 1) C(n – 1) C(n – 1)

HIGH

LOW

BYTE

HIGH

BYTE

LOW
BYTE

BYTE

LOW

BYTE

HIGH
BYTE

LOW

BYTE

HIGH

BYTE

LOW

BYTE

HIGH
BYTE

LOW

BYTE

08552-007

Figure 7. 4-Channel SHA Mode Timing

Rev. A | Page 7 of 20

AD80066

S

ANALOG

INPUTS

CDSCLK2

PIXEL n

t

AD

t

C2

t

PRB

PIXEL (n + 1)

ADCCLK

OUTPUT

DATA

(D[7:0])

ADCCLK

OUTPUT DATA

(D[7:0])

ADCCLK

OUTPUT DATA

(D[7:0])

SDATA

t

C2ADR

t

ADCCLK

PIXEL ( n – 4) PIXEL ( n – 4) PIXEL (n – 3) PIXEL (n – 3) PIXEL (n – 2) PIXEL (n – 2)

HIGH BYTE LOW BYTE LOW BYTEHIGH BYTE HIGH BYTE LOW BYTE

t

t

ADCCLK

C2ADF

t

OD

Figure 8. 1-Channel SHA Mode Timing

t

OD

HIGH BYTE

(DB[15:8])

PIXEL n PIXEL n

LOW BYTE

(DB[7:0])

t

OD

HIGH BYTE

(DB[15:8])

PIXEL (n + 1) PIXEL (n + 1) PIXEL (n + 2) PIXEL (n + 3)

LOW BYTE

(DB[7:0])

LOW BYTE

(DB[7:0])

HIGH BYTE

(DB[15:8])

Figure 9. Digital Output Data Timing

t

OD

HIGH BYTE

(DB[15:8])

PIXEL n PIXEL (n + 1)

HIGH BYTE

(DB[15:8])

HIGH BYTE

(DB[15:8])

PIXEL (n + 2)

Figure 10. Single-Byte Mode Digital Output Data Timing

R/W

A0A2

A3

t

DH

A1

t

DS

D8

D7

D5

D6

D3 D2

D4

D0

D1

8552-008

8552-009

08552-010

SCLK

SLOAD

t

LS

t

LH

8552-011

Figure 11. Serial Write Operation Timing

A1A3 A2

SDATA

SCLK

LOAD

R/W

t

LS

A0

Figure 12. Serial Read Operation Timing

D8 D7 D6 D5 D4 D3 D2 D1 D0

t

RDV

t

LH

08552-012

Rev. A | Page 8 of 20

AD80066

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter With Respect To Rating

VINx, CAPT, CAPB AVSS −0.3 V to AVDD + 0.3 V
Digital Inputs AVSS −0.3 V to AVDD + 0.3 V
SDATA DRVSS −0.3 V to DRVDD
AVDD AVSS −0.5 V to +6.5 V
DRVDD DRVSS −0.5 V to +6.5 V
AVSS DRVSS −0.3 V to +0.3 V
Digital Outputs

(D[7:0])

Tem p erature

Junction 150°C
Storage −65°C to +150°C
Lead (10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

DRVSS −0.3 V to DRVDD + 0.3 V

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 5. Thermal Resistance

Package Type θJA θ

28-Lead, 5.3 mm SSOP 109 39 °C/W

Unit

JC

ESD CAUTION

Rev. A | Page 9 of 20

AD80066

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

AVDD AVSS

DRVDD

DRVSS

D6

D5

D4

D3

D2

D1

2

3

4

5

6

7

8

9

10

11

12

13

14

AD80066

TOP VIEW

(Not to Scale)

CDSCLK1

CDSCLK2

ADCCLK

(MSB) D7

(LSB) D0

Figure 13. Pin Configuration

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VINA

OFFSET

VINB

CML

VINC

CAPT

CAPB

VIND

AVSS

AVDD

SLOAD

SCLK

SDATA

08552-013

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type

1

Description

1 AVDD P 5 V Analog Supply.
2 CDSCLK1 DI CDS Reference Level Sampling Clock.
3 CDSCLK2 DI CDS Data Level Sampling Clock.
4 ADCCLK DI ADC Sampling Clock.
5 DRVDD P Digital Output Driver Supply (3 V or 5 V).
6 DRVSS P Digital Output Driver Ground.
7 D7 (MSB) DO Data Output MSB. ADC DB15 high byte; ADC DB7 low byte.
8 D6 DO Data Output. ADC DB14 high byte; ADC DB6 low byte.
9 D5 DO Data Output. ADC DB13 high byte; ADC DB5 low byte.
10 D4 DO Data Output. ADC DB12 high byte; ADC DB4 low byte.
11 D3 DO Data Output. ADC DB11 high byte; ADC DB3 low byte.
12 D2 DO Data Output. ADC DB10 high byte; ADC DB2 low byte.
13 D1 DO Data Output. ADC DB9 high byte; ADC DB1 low byte.
14 D0 (LSB) DO Data Output LSB. ADC DB8 high byte; ADC DB0 low byte.
15 SDATA DI/DO Serial Interface Data Input/Output.
16 SCLK DI Serial Interface Clock Input.
17 SLOAD DI Serial Interface Load Pulse.
18 AVDD P 5 V Analog Supply.
19 AVSS P Analog Ground.
20 VIND AI Analog Input, D Channel.
21 CAPB AO ADC Bottom Reference Voltage Decoupling.
22 CAPT AO ADC Top Reference Voltage Decoupling.
23 VINC AI Analog Input, C Channel.
24 CML AO Internal Bias Level Decoupling.
25 VINB AI Analog Input, B Channel.
26 OFFSET AO Clamp Bias Level Decoupling.
27 VINA AI Analog Input, A Channel.
28 AVSS P Analog Ground.

1

AI = analog input, AO = analog output, DI = digital input, DO = digital output, and P = power.

Rev. A | Page 10 of 20

AD80066

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

15

0.5

0

DNL (LS B)

–0.5

–1.0

0 64,00025,60012,800 38, 400 51,200

ADC OUTPUT CODE

Figure 14. Typical DNL Performance

50

45

40

35

30

25

20

15

OUTPUT NOISE (LSB)

10

5

0

015

PGA REGISTER VALUE (Decimal)

30 45 63

08552-014

08552-015

10

5

INL (LSB)

0

–5

0 64,00025,60012,800 38,400 51,200

ADC OUTPUT CODE

Figure 16. Typical INL Performance

08552-016

Figure 15. Output Noise vs. PGA Gain

Rev. A | Page 11 of 20

AD80066

TERMINOLOGY

Integral Nonlinearity (INL)

Integral nonlinearity error refers to the deviation of each
individual code from a line drawn from zero scale through
positive full scale. The point used as zero scale occurs ½ LSB
before the first code transition. Positive full scale is defined as a
level 1½ LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.

Differential Nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value; therefore, every
code must have a finite width. No missing codes guaranteed to
16-bit resolution indicates that all 65,536 codes must be present
over all operating ranges.

Offset Error

The first ADC code transition should occur at a level ½ LSB above
the nominal zero-scale voltage. The offset error is the deviation
of the actual first code transition level from the ideal level.

Gain Error

The last code transition should occur for an analog value
1½ LSB below the nominal full-scale voltage. Gain error is the
deviation of the actual difference between the first and last code
transitions and the ideal difference between the first and last
code transitions.

Input-Referred Noise

The rms output noise is measured using histogram techniques. The
standard deviation of the ADC output codes is calculated in LSB
and converted to an equivalent voltage, using the relationship
1 LSB = 1.5 V/65,536 = 23 μV. The noise is then referred to the
input of the AD80066 by dividing by the PGA gain.

Channel-to-Channel Crosstalk

In an ideal 3-channel system, the signal in one channel does not
influence the signal level of another channel. The channel-to­channel crosstalk specification is a measure of the change that
occurs in one channel as the other two channels are varied. In
the AD80066, one channel is grounded and the other two channels
are exercised with full-scale input signals. The change in the output
codes from the first channel is measured and compared with the
result when all three channels are grounded. The difference is
the channel-to-channel crosstalk, stated in LSB.

Aperture Delay

The aperture delay is the delay that occurs from when a sampling
edge is applied to the AD80066 until the actual sample of the
input signal is held. Both CDSCLK1 and CDSCLK2 sample the
input signal during the transition from high to low; therefore,
the aperture delay is measured from each falling edge of the
clock to when the internal sample is taken.

Power Supply Rejection

The power supply rejection specifies the maximum full-scale
change that occurs from the initial value when the supplies are
varied over the specified limits.

Rev. A | Page 12 of 20

AD80066

THEORY OF OPERATION

The AD80066 can be operated in several different modes,
including 4-channel CDS mode, 4-channel SHA mode, 1-channel
CDS mode, and 1-channel SHA mode. Each mode is selected
by programming the configuration register through the serial
interface. For more information on CDS or SHA mode operation,
see the Circuit Operation section.

4-CHANNEL CDS MODE

In 4-channel CDS mode, the AD80066 simultaneously samples
the A, B, C, and D input voltages from the CCD outputs. The
sampling points for each CDS are controlled by CDSCLK1 and
CDSCLK2 (see Figure 17 and Figure 18). The CDSCLK1 falling
edge samples the reference level of the CCD waveform, and the
CDSCLK2 falling edge samples the data level of the CCD wave­form. Each CDS amplifier outputs the difference between the
CCD reference level and the data level. The output voltage of
each CDS amplifier is then level-shifted by an offset DAC. The
voltages are scaled by the four PGAs before being multiplexed
through the 16-bit ADC. The ADC sequentially samples the
PGA outputs on the falling edges of ADCCLK.

The offset and gain values for the A, B, C, and D channels are
programmed using the serial interface. The order in which the
channels are switched through the multiplexer is selected by
programming the mux register.

Timing for this mode is shown in Figure 3. The falling edge of
CDSCLK2 should occur coincident with or before the rising
edge of ADCCLK. However, this is not required to satisfy the
minimum timing constraints. The rising edge of CDSCLK2
should not occur before the previous falling edge of ADCCLK,
as shown by t

. The output data latency is 3 ADCCLK cycles.

ADC2

4-CHANNEL SHA MODE

In 4-channel SHA mode, the AD80066 simultaneously samples
the A, B, C, and D input voltages. The sampling point is controlled
by CDSCLK2. The falling edge of CDSCLK2 samples the input
waveforms on each channel. The output voltages from the three

SHAs are modified by the offset DACs and then scaled by the
four PGAs. The outputs of the PGAs are then multiplexed
through the 16-bit ADC. The ADC sequentially samples the
PGA outputs on the falling edges of ADCCLK.

The input signal is sampled with respect to the voltage applied to
the OFFSET pin (see Figure 19). With the OFFSET pin grounded,
a 0 V input corresponds to the zero-scale output of the ADC.
The OFFSET pin can also be used as a coarse offset adjustment
pin. A voltage applied to this pin is subtracted from the voltages
applied to the A, B, C, and D inputs in the first amplifier stage
of the AD80066. The input clamp is disabled in this mode. For
more information, see the Analog Inputs—SHA Mode section.

The offset and gain values for the A, B, C, and D channels are
programmed using the serial interface. The order in which the
channels are switched through the multiplexer is selected by
programming the mux register.

Timing for this mode is shown in Figure 7. The CDSCLK1 pin
should be grounded in this mode. Although not required, the
falling edge of CDSCLK2 should occur coincident with or before
the rising edge of ADCCLK. The rising edge of CDSCLK2 should
not occur before the previous falling edge of ADCCLK, as shown
by t

. The output data latency is 3 ADCCLK cycles.

ADC2

1-CHANNEL CDS MODE

The 1-channel CDS mode operates in the same way as the
4-channel CDS mode, except the multiplexer remains fixed.
Only the channel specified in the mux register is processed.

Timing for this mode is shown in Figure 6.

1-CHANNEL SHA MODE

The 1-channel SHA mode operates in the same way as the
4-channel SHA mode, except the multiplexer remains fixed.
Only the channel specified in the mux register is processed.

Timing for this mode is shown in Figure 8. The CDSCLK1 pin
should be grounded in this mode of operation.

Rev. A | Page 13 of 20

AD80066

INTERNAL REGISTER MAP

Table 7. Internal Register Map

Address Data Bits
Register Name A3 A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0

Configuration 0 0 0 0 0 0 0 VREF 2/1 byte CDS on Input range Fast/slow Power on
Mux 0 0 0 1 0 0 0 0 Ch. order Ch. A Ch. B Ch. C Ch. D
Gain A 0 0 1 0 0 0 0 MSB LSB
Gain B 0 0 1 1 0 0 0 MSB LSB
Gain C 0 1 0 0 0 0 0 MSB LSB
Gain D 0 1 0 1 0 0 0 MSB LSB
Offset A 0 1 1 0 MSB LSB
Offset B 0 1 1 1 MSB LSB
Offset C 1 0 0 0 MSB LSB
Offset D 1 0 0 1 MSB LSB

Rev. A | Page 14 of 20

AD80066

INTERNAL REGISTER DETAILS

CONFIGURATION REGISTER

The configuration register controls the AD80066 operating mode
and bias levels. The D8, D7, and D6 bits should always be set low.
Bit D2 sets the full-scale input voltage range of the AD80066 ADC
to either 3 V (high) or 1.5 V (low). Bit D5 controls the internal
voltage reference. If the AD80066 internal voltage reference is
used, this bit is set low. Setting Bit D5 high disables the internal
voltage reference, allowing an external voltage reference to be
used. Setting Bit D3 low enables the CDS mode of operation and
setting this bit high enables the SHA mode of operation. If Bit D4
is set high, the 16-bit ADC output is multiplexed into two bytes.
The most significant byte is output on the ADCCLK rising edge,
and the least significant byte is output on the ADCCLK falling
edge (see Figure 10). If Bit D1 is set high, the AD80066 is con­figured for slow operation (8 MHz) to reduce power consumption.
Bit D0 controls the power-down mode. Setting Bit D0 low places the
AD80066 into a very low power sleep mode. All register contents
are retained while the AD80066 is in the power-down state.

MUX REGISTER

The mux register controls the sampling channel order in the
AD80066. The D8, D7, D6, and D5 bits should always be set
low. Bit D4 is used when operating in 4-channel mode. Setting
Bit D4 low sequences the multiplexer to sample the A channel
first, and then the B, C, and D channels. When in this mode,

the CDSCLK2 pulse always resets the multiplexer to sample the
A channel first. When Bit D4 is set high, the channel order is
reversed to D, C, B, and A. The CDSCLK2 pulse always resets the
multiplexer to sample the D channel first. Bits D[3:0] are used
when operating in 1-channel mode. Bit D3 is set high to sample
the A channel. Bit D2 is set high to sample the B channel. Bit D1
is set high to sample the C channel. Bit D0 is set high to sample the
D channel. The multiplexer remains stationary in 1-channel mode.

PGA GAIN REGISTERS

There are four PGA registers for individually programming the
gain for the A, B, C, and D channels. The D8, D7, and D6 bits in
each register must be set low, and the D5 through D0 bits control
the gain range in 64 increments. See Figure 22 for the PGA gain vs.
the PGA register value. The coding for the PGA registers is straight
binary, with a word of all 0s corresponding to the minimum gain
setting (1×) and a word of all 1s corresponding to the maximum
gain setting (5.9×).

OFFSET REGISTERS

There are four offset registers for individually programming the
offset in the A, B, C, and D channels. The D8 through D0 bits
control the offset range from −300 mV to +300 mV in 512 incre­ments. The coding for the offset registers is sign magnitude, with
D8 as the sign bit. Tabl e 11 shows the offset range as a function
of the D8 through D0 bits.

Table 8. Configuration Register Settings

D8 D7 D6 D5 D4 D3 D2 D1 D0

Set to 0 Set to 0 Set to 0

Internal voltage

2/1 byte output CDS operation Input range Fast/slow Power mode

reference

1 = disabled 1 = one byte 1 = SHA mode 1 = 3 V 1 = 8 MHz 1 = on (normal)

0 = enabled

1

Power-on default.

1

0 = two bytes

1

0 = CDS mode10 = 1.5 V1 0 = 24 MHz1 0 = off

1

Table 9. Mux Register Settings

D8 D7 D6 D5 D4 D3 D2 D1 D0

Set to 0 Set to 0 Set to 0 Set to 0 Mux order Channel A Channel B Channel C Channel D

1 = D, C, B, A 1 = channel used 1 = channel used 1 = channel used 1 = channel used

0 = A, B, C, DD

1

Power-on default.

1

0 = not used

1

0 = not used

1

0 = not used

1

0 = not used

1

Table 10. PGA Gain Register Settings

(MSB) (LSB)

1

D8

D7

0 0 0 0 0 0 0 0 0

1

D6

1

D5 D4 D3 D2 D1 D0 Gain (V/V) Gain (dB)

2

1.0 0.0
0 0 0 0 0 0 0 0 1 1.013 0.12
… … … … … … … … … … …
0 0 0 1 1 1 1 1 0 5.56 14.9
0 0 0 1 1 1 1 1 1 5.9 15.56

1

Must be set to 0.

2

Power-on default.

Rev. A | Page 15 of 20

AD80066

Table 11. Offset Register Settings

(MSB) (LSB)
D8 D7 D6 D5 D4 D3 D2 D1 D0 Offset (mV)

0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 +1.2
… … … … … … … … … …
0 1 1 1 1 1 1 1 1 +300
1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1 −1.2
… … … … … … … … … …
1 1 1 1 1 1 1 1 1 −300

1

Power-on default value.

1

0

Rev. A | Page 16 of 20

AD80066

CIRCUIT OPERATION

ANALOG INPUTS—CDS MODE

Figure 17 shows the analog input configuration for the CDS
mode of operation. Figure 18 shows the internal timing for the
sampling switches. The CCD reference level is sampled when
CDSCLK1 transitions from high to low, opening S1. The CCD
data level is sampled when CDSCLK2 transitions from high to
low, opening S2. S3 is then closed, generating a differential
output voltage that represents the difference between the two
sampled levels.

The input clamp is controlled by CDSCLK1. When CDSCLK1
is high, S4 closes and the internal bias voltage is connected to
the analog input. The bias voltage charges the external 0.1 μF
input capacitor, level-shifting the CCD signal into the input
common-mode range of the AD80066. The time constant of the
input clamp is determined by the internal 5 kΩ resistance and
the external 0.1 μF input capacitance.

AD80066

3V

AVDD

S1

S2

1.7kΩ

2.2kΩ

6.9kΩ

0.1µF

+

VINA

C

IN

OFFSET

0.1µF1µF

S1, S4 OPEN

5kΩ

S4

CCD SIGNAL

Figure 17. CDS Mode Input Configuration (All Four Channels Are Identical)

S1, S4 CLOSED S1, S4 CLOSED

CDSCLK1

2pF

CML

S3

CML

2pF

8552-017

EXTERNAL INPUT COUPLING CAPACITORS

The recommended value for the input coupling capacitors is

0.1 μF. Although it is possible to use a smaller capacitor, this
larger value is preferable for several reasons:

• Signal attenuation: The input coupling capacitor creates

a capacitive divider using the input capacitance from an
integrated CMOS circuit, which, in turn, attenuates the
CCD signal level. CIN should be large relative to the 10 pF
input capacitance of the IC in order to minimize this effect.

• Linearity: Some of the input capacitance of a CMOS IC is

junction capacitance, which varies nonlinearly with applied
voltage. If the input coupling capacitor is too small, the
attenuation of the CCD signal varies nonlinearly with signal
level. This degrades the system linearity performance.

• Sampling errors: The internal 2 pF sampling capacitors retain

a memory of the previously sampled pixel. There is a charge
redistribution error between CIN and the internal sample
capacitors for larger pixel-to-pixel voltage swings. As the
value of CIN is reduced, the resulting error in the sampled
voltage increases. With a CIN value of 0.1 μF, the charge
redistribution error is less than 1 LSB for a full-scale, pixel­to-pixel voltage swing.

CDSCLK2

(INTERNAL)

S2 CLOSED S2 CLOSED

S2 OPEN

S3 CLOSED S3 CLOSED

Q3

S3 OPEN

Figure 18. CDS Mode Internal Switch Timing

08552-018

Rev. A | Page 17 of 20

AD80066

ANALOG INPUTS—SHA MODE

Figure 19 shows the analog input configuration for the SHA
mode of operation. Figure 20 shows the internal timing for the
sampling switches. The input signal is sampled when CDSCLK2
transitions from high to low, opening S1. The voltage on the
OFFSET pin is also sampled on the falling edge of CDSCLK2,
when S2 opens. S3 is then closed, generating a differential
output voltage that represents the difference between the
sampled input voltage and the OFFSET voltage. The input
clamp is disabled during SHA mode operation.

AD80066

INPUT SIGNAL

OPTIO NAL DC OFFSE T

(OR CONNECT TO GND)

VINA

OFFSET

VINB

VINC

VIND

Figure 19. SHA Mode Input Configuration (All Four Channels Are Identical)

CDSCLK2

(INTERNAL)

Q3

S1, S2 CLOSED S1, S2 CLOSED

S1, S2 OPEN

S3 CLOSED S3 CLOSED

S3 OPEN

Figure 20. SHA Mode Internal Switch Timing

Figure 21 shows how the OFFSET pin can be used in a CIS
application for coarse offset adjustment. Many CIS signals have
dc offsets ranging from several hundred millivolts to more than
1 V. By connecting the appropriate dc voltage to the OFFSET pin,
the large dc offset is removed from the CIS signal. Then, the
signal can be scaled using the PGA to maximize the dynamic
range of the ADC.

S1

S2

2pF

CML

2pF

A

CML

CML

B

CML

CML

C

CML

CML

D

CML

S3

VINA

VINB

VOLTAGE

REFERENCE

FROM CIS

MODULE

DC OFFSET

AVDD

R1

R2

VINC

OFFSET

0.1µF

Figure 21. SHA Mode Used with External DC Offset

PROGRAMMABLE GAIN AMPLIFIERS (PGA)

The AD80066 uses one PGA for each channel. Each PGA has a
gain range from 1× (0 dB) to 5.8× (15.5 dB), adjustable in
64 steps. Figure 22 shows the PGA gain as a function of the
PGA register value. Although the gain curve is approximately
linear-in-dB, the gain in V/V varies nonlinearly with register
code, following the equation

=

Gain

08552-019

G is the decimal value of the gain register contents and

where
varies from 0 to 63.

1

5

12

08552-020

9

6

GAIN (dB)

3

0

4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 63

0

5.9

−

63

⎡

+

4.91

⎢

63

⎣

PGA REGISTER VALUE (Decimal)

Figure 22. PGA Gain Transfer Function

AD80066

SHA

SHA

SHA

G

⎤
⎥

⎦

A OFFSET

B OFFSET

C OFFSET

5.9

5.0

4.0

3.0

2.0

1.0

GAIN (V/V)

08552-022

08552-021

Rev. A | Page 18 of 20

AD80066

V

C

V

APPLICATIONS INFORMATION

CIRCUIT AND LAYOUT RECOMMENDATIONS

Figure 23 shows the recommended circuit configuration for
4-channel CDS mode operation. The recommended input
coupling capacitor value is 0.1 μF (see the Analog Inputs—CDS
Mode section). A single ground plane is recommended for the
AD80066. A separate power supply can be used for DRVDD,
the digital driver supply, but this supply pin should still be
decoupled to the same ground plane as the rest of the AD80066.
The loading of the digital outputs should be minimized, either
by using short traces to the digital ASIC or by using external
digital buffers. To minimize the effect of digital transients
during major output code transitions, the falling edge of

5

0.1µF

CLOCK
INPUTS

3.3V

0.1µF

DATA

INPUTS

AVDD AVSS

CDSCLK1

CDSCLK2

ADCCLK

DRVDD

DRVSS

(MSB) D7

(LSB) D0

D6

D5

D4

D3

D2

D1

1

2

3

4

5

6

AD80066

7

TOP VIEW

(Not to Scale)

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

Figure 23. Recommended Circuit Configuration, 4-Channel CDS Mode

5

0.1µF

VINA

OFFSET

VINB

CML

VINC

CAPT

CAPB

VIND

AVSS

AVDD

SLOAD

SCLK

SDATA

CDSCLK2 should occur coincident with or before the rising
edge of ADCCLK (see Figure 3 through Figure 8 for timing).
All 0.1 μF decoupling capacitors should be located as close as
possible to the AD80066 pins. When operating in 1-channel
mode, the unused analog inputs should be grounded.

Figure 24 shows the recommended circuit configuration for
4-channel SHA mode. All of the previously explained consid­erations also apply to this configuration, except that the analog
input signals are directly connected to the AD80066 without the
use of coupling capacitors. Before connecting the signals, the
analog input signals must be dc-biased between 0 V and 1.5 V
or 3 V (see the Analog Inputs—SHA Mode section).

0.1µF

A INPUT

0.1µF
B INPUT

0.1µF

0.1µF

1.0µF

0.1µF

0.1µF

A INPUT

C INPUT

D INPUT

8552-023

0.1µF

0.1µF

0.1µF

5V

0.1µF

10µF

SERIAL
INTERFACE

0.1µF

0.1µF

B INPUT

C INPUT

D INPUT

08552-024

LOCK

INPUTS

0.1µF

DATA

INPUTS

3.3V

AVDD

DRVDD

DRVSS

D6

D5

D4

D3

D2

D1

1

2

3

4

5

6

AD80066

7

TOP VIEW

8

(Not to Scale)

9

10

11

12

13

14

2

CDSCLK1

CDSCLK2

ADCCLK

(MSB) D7

(LSB) D0

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AVSS

VINA

OFFSET

VINB

CML

VINC

CAPT

CAPB

VIND

AVSS

AVDD

SLOAD

SCLK

SDATA

0.1µF

0.1µF

0.1µF

5V

10µF

SERIAL
INTERFACE

Figure 24. Recommended Circuit Configuration, 4-Channel SHA Mode (Analog Inputs Sampled with Respect to Ground)

Rev. A | Page 19 of 20

AD80066

OUTLINE DIMENSIONS

10.50

10.20

9.90

0.38

0.22

15

5.60

5.30

8.20

5.00

7.80

1.85

1.75

1.65

SEATING
PLANE

7.40

0.25

0.09

8°
4°
0°

0.95

0.75

0.55

14

2.00 MAX

0.05 MIN

COPLANARITY

0.10

28

1

0.65 BSC

COMPLIANT TO JEDEC STANDARDS MO-150-AH

Figure 25. 28-Lead Shrink Small Outline Package [SSOP]

(RS-28)

Dimensions shown in millimeters

ORDERING GUIDE

1

Model

Temperature Range Package Description Package Option

AD80066KRSZ 0°C to 70°C 28-Lead SSOP RS-28
AD80066KRSZRL 0°C to 70°C 28-Lead SSOP RS-28

1

Z = RoHS Compliant Part.

060106-A

©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08552-0-4/10(A)

Rev. A | Page 20 of 20