Datasheet AD8004AR-14-REEL7, AD8004AR-14-REEL, AD8004AR-14, AD8004AN Datasheet (Analog Devices)

Quad 3000 V/␮s, 35 mW

0.04

0.03

0.02

0.01

0.00
–0.01
–0.02
–0.03
–0.04

1

ST

DIFF GAIN – %

0.12

0.10

0.08

0.06

0.04

0.02

0.00
–0.02
–0.04

DIFF PHASE – Degrees

2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH

1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH

80 IRE
R

L

= 150V

V

S

= 65V

R

F

= 1.21kV

80 IRE
R

L

= 150V

V

S

= 65V

R

F

= 1.21kV

a

FEATURES
High Speed

250 MHz –3 dB Bandwidth (G = +1)
3000 V/␮s Slew Rate
21 ns Settling Time to 0.1%

1.8 ns Rise Time for 2 V Step

Low Power

3.5 mA/Amp Power Supply Current (35 mW/Amp)

Single Supply Operation

Fully Specified for +5 V Supply

Good Video Specifications (R

Gain Flatness 0.1 dB to 30 MHz

0.04% Differential Gain Error

0.10ⴗ Differential Phase Error

Low Distortion

–78 dBc THD at 5 MHz

–61 dBc THD at 20 MHz
High Output Current of 50 mA
Available in a 14-Lead Plastic DIP and SOIC

APPLICATIONS
Image Scanners
Active Filters
Video Switchers
Special Effects

PRODUCT DESCRIPTION

The AD8004 is a quad, low power, high speed amplifier designed
to operate on single or dual supplies. It utilizes a current feed­back architecture and features high slew rate of 3000 V/µs
making the AD8004 ideal for handling large amplitude pulses.
Additionally, the AD8004 provides gain flatness of 0.1 dB to

= 150 ⍀, G = +2)

L

Current Feedback Amplifier

AD8004

CONNECTION DIAGRAM

Plastic DIP (N) and

SOIC (R) Packages

1

OUTPUT

1

2

–IN

3

+IN

+V

+IN
–IN

OUTPUT

4

S

5
6
7

AD8004

(

TOP VIEW)

23

30 MHz while offering differential gain and phase error of

0.04% and 0.10°. This makes the AD8004 suitable for video

electronics such as cameras and video switchers.

The AD8004 offers low power of 3.5 mA/amplifier and can run
on a single +4 V to +12 V power supply, while being capable of
delivering up to 50 mA of load current. All this is offered in a
small 14-lead plastic DIP or 14-lead SOIC package. These
features make this amplifier ideal for portable and battery pow­ered applications where size and power are critical.

The outstanding bandwidth of 250 MHz along with 3000 V/µs

of slew rate make the AD8004 useful in many general purpose,
high speed applications where dual power supplies of up to

±6 V and single supplies from 4 V to 12 V are needed. The
AD8004 is available in the industrial temperature range of –40°C
to +85°C.

14

OUTPUT

4

13

–IN

12

+IN

11

–V

S

+IN

10

–IN

9

OUTPUT

8

G = +2

= 50mV rms

V

IN

= 100V

R

L

= 1.10kV

R

F

R PACKAGE

+0.1

0

–0.1

–0.2

–0.3

–0.4

NORMALIZED FLATNESS – dB

–0.5

1 50010 40

Figure 1. Frequency Response and Flatness, G = +2

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

+5V

S

FREQUENCY – MHz

+5V

S

65V

+1

0

–1

65V

S

S

100

–2

–3

–4

–5

–6

–7

–8

NORMALIZED FREQUENCY RESPONSE – dB

–9

Figure 2. Differential Gain/Differential Phase

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD8004–SPECIFICATIONS

(@ TA = + 25ⴗC, VS = ⴞ5 V, RL = 100 ⍀, unless otherwise noted)

AD8004A

Parameter Conditions Min Typ Max Units

DYNAMIC PERFORMANCE

–3 dB Bandwidth, N Package G = +2, R

G = +1

Bandwidth for 0.1 dB Flatness

G = +2 30 MHz

Slew Rate G = +2, V

G = –2, V

Settling Time to 0.1% G = +2, V

= 698 Ω 185 MHz

F

, R

= 806 Ω

F

= 4 V Step 3000 V/µs

O

= 4 V Step 2000 V/µs

O

= 2 V Step 21 ns

O

250 MHz

Rise & Fall Time (10% to 90%) G = +2, VO = 2 V Step 1.8 ns

NOISE/HARMONIC PERFORMANCE

Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, R
Crosstalk, R Package, Worst Case f = 5 MHz, G = +2, R
Crosstalk, N Package, Worst Case f = 5 MHz, G = +2, R

L

L

= 1 kΩ –78 dBc

L

= 1 kΩ –69 dB

= 1 kΩ –64 dB
Input Voltage Noise f = 10 kHz 1.5 nV/√Hz
Input Current Noise f = 10 kHz, +In 38 pA/√Hz

–In 38 pA/√Hz

Differential Gain Error NTSC, G = +2, R
Differential Phase Error NTSC, G = +2, R
Differential Gain Error NTSC, G = +2, R
Differential Phase Error NTSC, G = +2, R

= 150 Ω, RF = 1.21 kΩ 0.04 %

L

= 150 Ω, RF = 1.21 kΩ 0.10 Degree

L

= 1 kΩ, RF = 1.21 kΩ 0.01 %

L

= 1 kΩ, RF = 1.21 kΩ 0.04 Degree

L

DC PERFORMANCE

Input Offset Voltage 1.0 3.5 mV

T

MIN–TMAX

1.5 5 mV

Offset Drift 15 µV/°C
–Input Bias Current 35 90 ±µA

T

MIN–TMAX

110 ±µA

+Input Bias Current 40 110 ±µA

120 ±µA

Open-Loop Transresistance V

T

MIN–TMAX

= ±2.5 V 170 290 kΩ

O

T

MIN–TMAX

220 kΩ

INPUT CHARACTERISTICS

Input Resistance +Input 2 MΩ

–Input 50 Ω

Input Capacitance +Input 1.5 pF

Input Common-Mode Voltage Range 3.2 ±V

Common-Mode Rejection Ratio

Offset Voltage V
–Input Current V
+Input Current V

= ±2.5 V 52 58 dB

CM

= ±2.5 V, T

CM

= ±2.5 V, T

CM

MIN–TMAX

MIN–TMAX

1 µA/V
12 µA/V

OUTPUT CHARACTERISTICS

Output Voltage Swing R

= 150 Ω 3.9 ±V

L

Output Current 50 mA
Short Circuit Current 100 180 mA

POWER SUPPLY

Operating Range ±2.0 ±6.0 V

Total Quiescent Current 14 17 mA

16 20 mA

0.5 µA/V
4 µA/V

Power Supply Rejection Ratio ∆V

–Input Current T
+Input Current T

Specifications subject to change without notice.

T

MIN–TMAX

= ±2 V 56 62 dB

S

MIN–TMAX

MIN–TMAX

–2–

REV. B

(@ TA = + 25ⴗC, VS = +5 V, RL = 100 ⍀, unless otherwise noted)

AD8004

AD8004A

Parameter Conditions Min Typ Max Units

DYNAMIC PERFORMANCE

–3 dB Bandwidth, N Package G = +2, R

G = +1, R

Bandwidth for 0.1 dB Flatness

G = +2 30 MHz
Slew Rate G = +2, V
Settling Time to 0.1% G = +2, V

= 698 Ω 150 MHz

F

= 806 Ω

F

= 2 V Step 1100 V/µs

O

= 2 V Step 24 ns

O

200 MHz

Rise & Fall Time (10% to 90%) G = +2, VO = 2 V Step 2.3 ns

NOISE/HARMONIC PERFORMANCE

Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, R
Crosstalk, R Package, Worst Case f = 5 MHz, G = +2, R
Crosstalk, N Package, Worst Case f = 5 MHz, G = +2, R

L

L

= 1 kΩ –65 dBc

L

= 1 kΩ –69 dB

= 1 kΩ –64 dB
Input Voltage Noise f = 10 kHz 1.5 nV/√Hz
Input Current Noise f = 10 kHz, +In 38 pA/√Hz

–In 38 pA/√Hz

Differential Gain Error NTSC, G = +2, R
Differential Phase Error NTSC, G = +2, R
Differential Gain Error NTSC, G = +2, R
Differential Phase Error NTSC, G = +2, R

= 150 Ω, RF = 1.21 kΩ 0.06 %

L

= 150 Ω, RF = 1.21 kΩ 0.25 Degree

L

= 1 kΩ, RF = 1.21 kΩ 0.01 %

L

= 1 kΩ, RF = 1.21 kΩ 0.08 Degree

L

DC PERFORMANCE

Input Offset Voltage 1.0 2.5 mV

T

MIN–TMAX

13 mV

Offset Drift 15 µV/°C
–Input Bias Current 20 80 ±µA

T

MIN–TMAX

100 ±µA

+Input Bias Current 35 100 ±µA

115 ±µA

Open Loop Transresistance V

T

MIN–TMAX

= +1.5 V to +3.5 V 140 230 kΩ

O

T

MIN–TMAX

170 kΩ

INPUT CHARACTERISTICS

Input Resistance +Input 2 MΩ

–Input 50 Ω

Input Capacitance +Input 1.5 pF
Input Common-Mode Voltage Range 3.2 V
Common-Mode Rejection Ratio

Offset Voltage V
–Input Current V
+Input Current VCM = +1 V to +3 V, T

=+1Vto+3V 52 57 dB

CM

= +1 V to +3 V, T

CM

MIN–TMAX

MIN–TMAX

2 µA/V
15 µA/V

OUTPUT CHARACTERISTICS

Output Voltage Swing R

= 150 Ω 0.9 to 4.1 V

L

Output Current 50 mA
Short Circuit Current 95 mA

POWER SUPPLY

Operating Range 0, +4 +12 V
Total Quiescent Current 13 14 mA

Power Supply Rejection Ratio ∆V

–Input Current T
+Input Current T

Specifications subject to change without notice.

T

MIN–TMAX

= +1 V, VCM = +2.5 V 56 62 dB

S

MIN–TMAX

MIN–TMAX

14.5 15.5 mA

1 µA/V
6 µA/V

REV. B –3–

AD8004

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V

Internal Power Dissipation

2

1

Plastic DIP Package (N) . . . . . . . . . Observe Derating Curves

Small Outline Package (R) . . . . . . . . Observe Derating Curves

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±2.5 V

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves

Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C

Operating Temperature Range (A Grade) . . . –40°C to +85°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for device in free air:

14-Lead Plastic DIP Package: θJA = 90°C/W
14-Lead SOIC Package: θJA = 140°C/W

ORDERING GUIDE

Model Range Description Option

AD8004AN –40°C to +85°C 14-Lead Plastic DIP N-14
AD8004AR-14 –40°C to +85°C 14-Lead SOIC R-14
AD8004AR-14-REEL –40°C to +85°C 13" Tape and Reel R-14
AD8004AR-14-REEL7 –40°C to +85°C 7" Tape and Reel R-14

Temperature Package Package

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8004 is limited by the associated rise in junction tempera­ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition tem-

perature of the plastic, approximately +150°C. Exceeding this

limit temporarily may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.

Exceeding a junction temperature of +175°C for an extended

period can result in device failure.

While the AD8004 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction tem­perature is not exceeded under all conditions. To ensure proper
operation, it is necessary to observe the maximum power derat­ing curves (shown below in Figure 3).

2.0

14-LEAD PLASTIC DIP

1.5

1.0

0.5

MAXIMUM POWER DISSIPATION – Watts

0

–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90

AMBIENT TEMPERATURE – 8C

PACKAGE

14-LEAD SOIC

PACKAGE

TJ = +1508C

Figure 3. Maximum Power Dissipation vs. Temperature

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8004 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

AD8004

FREQUENCY – MHz

+1

NORMALIZED FREQUENCY RESPONSE – dB

–4

–9

1 50010 40 100

–3

–2

–1

0

–5
–6

–7
–8

G = –1

G = –2

G = –10

VS = 65V
R

F

= 499V
VIN = 50mV rms
R

L

= 100V

N PACKAGE

604V

V

IN

604V

50V

50V

0.1mF

0.1mF

SCOPE
INPUT

10mF

10mF

50V

+V

S

–V

S

Figure 4. Test Circuit; Gain = +2

Figure 5.* 100 mV Step Response; G = +2, VS = ±2.5 V or ±5 V

SCOPE

V

249V

IN

61.9V

499V

50V

0.1mF

0.1mF

INPUT

10mF

10mF

50V

+V

S

–V

S

Figure 8. Test Circuit; Gain = –2

Figure 9.* 100 mV Step Response; G = –2, VS = ±2.5 V or±5 V

Figure 6.* Step Response; G = +2, VS = ±5 V

+2
+1

0

RL = 100V

–1

V

= 50mV (G = +1, +2)

IN

= 5mV (G = +10)

V

–2

IN

*NOTE: V

REV. B

–3

–4
–5

–6

–7

NORMALIZED FREQUENCY RESPONSE – dB

–8

1 50010

Figure 7. Frequency Response; G = +1, +2, +10, VS =±5 V

= ±2.5 V operation is identical to V

S

G = +1,
R

FREQUENCY – MHz

= 698V

F

G = +2,

= 604V

R

F

G = +10,
R

= 499V

F

40 100

= +5 V single supply operation.

S

Figure 10.* Step Response; G = –2, VS = ±5 V

Figure 11. Frequency Response, G = –1, –2, –10

–5–

AD8004

+9

+6

+3

1V rms

0

–3

–6

–9

–12

OUTPUT LEVEL – dBV

G =+2
VS = 65V

–15

RF = 604V

–18

–21

1 50010

FREQUENCY – MHz

40 100

Figure 12. Large Signal Frequency Response; VS =±5.0 V,

= 604

G = +2

= 2V p-p

V

O

= 698V

R

F

Ω

3RD

= 150V

R

L

= 150V

R

L

2ND

G = +2, R

–40

–50

–60

–70

F

+3

1V rms

0
–3

–6
–9

–12

–15

–18

OUTPUT LEVEL – dBV

G = +2

= +5V

V

S

–21

R

= 604V

F

–24

–27

1 50010 40 100

FREQUENCY – MHz

Figure 15. Large Signal Frequency Response; VS = +5.0 V,

= 604

G = +2, R

–40

–50

–60

–70

F

Ω

G = +2
VO = 2V p-p

= 698V

R

F

3RD

RL = 1kV

2ND

RL = 150V

3RD

RL = 150V

–80

DISTORTION – dBc

2ND

= 1kV

–90

–100

120

3RD

= 1kV

R

L

FREQUENCY – MHz

R

L

10

Figure 13. Distortion vs. Frequency; VS = ±5 V

+1

G = +2
VIN = 50mV rms

R

= 100V

L

= 1.10kV

R

F

R PACKAGE

+0.1

0

–0.1

–0.2

–0.3

–0.4

NORMALIZED FLATNESS – dB

–0.5

1 50010 40 100

+5V

S

FREQUENCY – MHz

+5V

S

65V

65V

S

0
–1

–2

S

–3

–4

–5

–6

–7

–8

NORMALIZED FREQUENCY RESPONSE – dB

–9

Figure 14. Frequency Response and Flatness, G = +2

–80

DISTORTION – dBc

–90

–100

120

Figure 16. Distortion vs. Frequency; VS = +5 V

–10
–15

–20

–25
–30

–35
–40

CMRR – dB

–45

–50
–55
–60

0.03

604V

V

IN

154V

+5V

0.1 5001 10 100

Figure 17. CMRR vs. Frequency; VS = ±5 V or +5 V,
V

= 200 mV rms, Other Sides Are Equal, RTO

IN

604V

154V57.6V

S

65V

2ND

RL = 1kV

FREQUENCY – MHz

50V

V

OUT

S

FREQUENCY – MHz

10

65V

S

+5V

S

–6–

REV. B

AD8004

FREQUENCY – Hz

GAIN – dBV

110

60

10

1M 1G10M 100M

70

80

90

100

50

40

30

20

100k

PHASE

GAIN

0

–50

–100

–150

–200

PHASE – Degree

10

9
8
7
6

5
4

Hz

3

2

10

9
8
7
6
5

4
3

INPUT VOLTAGE NOISE – nV/

2

1

10 100 1k 10k 100k 1M

FREQUENCY – Hz

+ OR – INPUT

CURRENT NOISE

VOLTAGE NOISE

1000

500

300
200

100

70
50

40
30

20

10

Figure 18. Noise vs. Frequency, VS = +5 V or ±5 V

100

G = +2
R

10

POWER = 0dBm
(224mV rms)

1

IMPEDANCE – V

0.1

0.01

0.03

= 698V

F

0.1 5001

RbT = 50V
65V

OR +5V

S

S

+5V

S

65V

S

FREQUENCY – MHz

10

RbT = 0

100

0

–10

Hz

INPUT CURRENT NOISE – pA/

–20

–30

–40

PSRR – dB

–50

–60

–70

–80

10k 500M100k 1M 10M

S

–20

–30

–40

–50

–60

–70

–80

CROSSTALK – dB

–90

–100

–110
–120

0.03

G = +2
65V

OR 62.5V

S

RF = 1kV
100mV rms ON TOP

OF dc BIAS

S

+PSRR

–PSRR

FREQUENCY – Hz

Figure 21. PSRR vs. Frequency

G = +2

= 1.10kV

R

F

65V

S

VIN = 200mV rms
INPUT TO SIDE 1

= 1kV

R

L1

R PACKAGE

0.1 5001 10 100

OUTPUT =

SIDE 4

FREQUENCY – MHz

OUTPUT =

SIDE 2

OUTPUT =

SIDE 3

100M

Figure 19. Output Impedance vs. Frequency

0

GAIN

90

–180

PHASE – Degrees

–240

–360

Figure 20. Open-Loop Voltage Gain and Phase

REV. B

PHASE

VIN = –40dBm

= 65V

V

S

0.1 5001 10 100

0.03
FREQUENCY – MHz

+60

+50

+40

+30

+20

+10

0

–10

GAIN – dB

Figure 22. Crosstalk (Output to Output) vs. Frequency

Figure 23. Open-Loop Transimpedance Gain

–7–

AD8004

Figure 24. Short-Term Settling Time

Figure 25. Long-Term Settling Time

9

G = +2

8

RF = 1.21kV

7

6

5

4

SWING – V p-p

3

2

1

0

10 100 1000 10000

LOAD RESISTANCE – V

65V

+5V

S

S

Figure 27. Output Voltage Swing vs. Load

10

9

G = +2
RF = 1.21kV

8

f = 100kHz

7

6

5
4

3

AT CLIPPING POINT – V

PEAK-TO-PEAK OUTPUT

2

1

0

3456789101112

TOTAL SUPPLY VOLTAGE – V

RL = 1kV

RL = 100V

Figure 28. Output Swing vs. Supply

0.04

0.03

0.02

0.01

0.00
–0.01
–0.02

DIFF GAIN – %

–0.03
–0.04

1

ST2ND3RD4TH5TH6TH7TH8TH9TH10TH11TH

0.12

0.10

0.08

0.06

0.04

0.02

0.00
–0.02

DIFF PHASE – Degrees

–0.04

ST

2ND3RD4TH5TH6TH7TH8TH9TH10TH11

1

80 IRE

= 150V

R

L

= 65V

V

S

= 1.21kV

R

F

80 IRE

= 150V

R

L

= 65V

V

S

= 1.21kV

R

F

Figure 26. Differential Gain/Differential Phase

0.03

0.02

0.01

0.00

–0.01

DIFF GAIN – %

–0.02
–0.03

0.04

0.03

0.02

0.01

0.00
–0.01
–0.02
–0.03

DIFF PHASE – Degrees

TH

–0.04

Figure 29. Differential Gain/Phase, RL = 1 k

–8–

80 IRE

V

= 1k

R

L

V

= 65V

S

V

= 1.21k

R

F

1ST2ND3RD4TH5TH6TH7TH8TH9TH10TH11

80 IRE

V

R

= 1k

L

= 65V

V

S

V

= 1.21k

R

F

ST2ND3RD4TH5TH6TH7TH8TH9TH10TH11TH

1

TH

Ω

REV. B

AD8004

THEORY OF OPERATION

The AD8004 is a member of a new family of high speed current­feedback (CF) amplifiers offering new levels of bandwidth,
distortion, and signal-swing capability vs. power. Its wide dynamic
range capabilities are due to both a complementary high speed
bipolar process and a new design architecture. The AD8004 is
basically a two stage (Figure 30) rather than the conventional
one stage design. Both stages feature the current-on-demand
property associated with current feedback amplifiers. This gives
an unprecedented ratio of quiescent current to dynamic perfor­mance. The important properties of slew rate, and full power
bandwidth benefit from this performance. In addition the
second gain stage buffers the effects of load impedance sig­nificantly reducing distortion.

A full discussion of this new amplifier architecture is available on
the data sheet for the AD8011. This discussion only covers the
basic principles of operation.

DC AND AC CHARACTERISTICS

As with traditional op amp circuits the dc closed-loop gain is
defined as:

R

A

V

A

V

= G =1 +

= G =−

F

R

R

R

N

noninverting operation

N

F

inverting operation

The more exact relationships that take into account open-loop
gain errors are:

A

=

V

1 +

A

=

V

1 +

In these equations the open-loop voltage gain (A

1 −G

A

O

G

(s )

A

O

(s )

G

G

+

TO(s )

+

TO(s )

R

F

for inverting (G is negative)

R

F

for noninverting (G is positive)

(s)) is com-

O

mon to both voltage and current-feedback amplifiers and is the
ratio of output voltage to differential input voltage. The open­loop transimpedance gain (T

(s)) is the ratio of output voltage

O

to inverting input current and is applicable to current-feedback
amplifiers. The open-loop voltage gain and open-loop transim­pedance gain (T

(s)) of the AD8004 are plotted vs. frequency

O

in Figures 20 and 23. These plots and the basic relationships
can be used to predict the first order performance of the AD8004
over frequency. At low closed-loop gains the term (R

/TO(s))

F

dominates the frequency response characteristics. This gives the
result that bandwidth is constant with gain, a familiar property
of current feedback amplifiers.

An R

of 1 kΩ has been chosen as the nominal value to give

F

optimum frequency response with acceptable peaking at gains of
+2/–1. As can be seen from the above relationships, at higher
closed-loop gains reducing R
loop bandwidth. Table I gives optimum values for R

has the effect of increasing closed-

F

and R

F

G

for a variety of gains.

IPP

INP

A1

IPN

IQ1

IE

IQ1

IPN

A1

CP1

Z

I

CP1

Q3

Q1

Q2

V

N

Q4

V

P

CP2

A2

A2

C

D

ICQ +

IO

V

O

´

A3

R

Z2

C

D

AD8004

R

F

R

G

L

V

O

C

L

Figure 30. Simplified Block Diagram

REV. B

–9–

AD8004

DRIVING CAPACITIVE LOADS

The AD8004 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, best
settling response is obtained by the addition of a small series
resistance as shown in Figure 31. The accompanying graph
shows the optimum value for R

vs. capacitive load. It is

SERIES

worth noting that the frequency response of the circuit when
driving large capacitive loads will be dominated by the passive
roll-off of R

SERIES

1kV

and CL.

1kV

AD8004

R

SERIES

1kV

R

L

C

L

Figure 31. Driving Capacitive Load

40

30

– V

SERIES

R

20

10

010152025

Figure 32. Recommended R

≤

30 ns Settling to 0.1%

5

– pF

C

L

vs. Capacitive Load for

SERIES

OPTIMIZING FLATNESS

The fine scale gain flatness and –3 dB bandwidth is affected by
R

FEEDBACK

selection as is normal of current feedback amplifiers.
With exception of gain = +1, the AD8004 can be adjusted for
either maximal flatness with modest closed-loop bandwidth or
for mildly peaked-up frequency response with much more band­width. Figure 33 shows the effect of three evenly spaced R

F

changes upon gain = +1 and gain = +2. Table I shows the
recommended component values for achieving maximally flat
frequency response as well as a faster slightly peaked-up fre­quency response.

Printed circuit board parasitics and device lead frame parasitics
also control fine scale gain flatness. The AD8004R package
because of its small lead frame offers superior parasitics relative
to the N package. In the printed circuit board environment,
parasitics such as extra capacitance caused by two parallel and
vertical flat conductors on opposite PC board sides in the

region of the summing junction will cause some bandwidth
extension and/or increased peaking. In noninverting gains, the
effect of extra capacitance on summing junctions is far more
pronounced than versus inverting gains. Figure 34 shows an
example of this. Note that only 1 pF of added junction capaci­tance causes about a 70% bandwidth extension and additional
peaking on a gain = +2. For an inverting gain = –2, 5 pF of
additional summing junction capacitance caused a small 10%
bandwidth extension.

Extra output capacitive loading also causes bandwidth exten­sions and peaking. The effect is more pronounced with less
resistive loading from the next stage. Figure 35 shows the effect
of direct output capacitive loads for gains of +2 and –2. For both
gains C

was set to 10 pF or 0 pF (no extra capacitive loading).

LOAD

For each of the four traces in Figure 35 the resistive loads were

100 Ω. Figure 36 also shows capacitive loading effects only

with a lighter output resistive load. Note that even though

bandwidth is extended 2×, the flatness dramatically suffers.

CJ = 0

+2

+1

0

–1

–2

–3

–4

GAIN – dB, G = +1

–5

–6

–7

–8

500

+2

0

–2

–4

–6

–8

–10

–12

NORMALIZED GAIN – dB, G = +2

–14

G = +1

+1

G = +2

0

–1

VIN = 50mV rms
V

= 65V

–2

S

R

= 100V

L

–3

R PACKAGE
–4

–5

NORMALIZED GAIN – dB, G = +2

1

Figure 33. R

NORMALIZED GAIN – dB, G = –2

FEEDBACK

G = +2

+2

G = –2

0

–2

VIN = 50mV rms

–4

R

= 100V

L

65V

–6

–8

–10

–12

–14

S

1 50010 40 100

RF = 698V

RF = 1.1kV

RF = 909V

RF = 604V

RF = 1.10kV

RF = 845V

10

FREQUENCY – MHz

100

40

vs. Frequency Response, G = +1/+2

CJ = 1pF

CJ = 5.1pF

CJ = 0

FREQUENCY – MHz

Figure 34. Frequency Response vs. Added Summing
Junction Capacitance

–10–

REV. B

AD8004

,

G = +2, RF = 1.10kV

+2

G = –2, RF = 698V

0

–2

–4

VIN = 50mV

–6

65V

S

RL = 100V

–8

–10

–12

NORMALIZED GAIN – dB, G = –2

–14

1 50010 40 100

FREQUENCY – MHz

CL = 10pF

CL = 0

CL = 10pF

CL = 0

+2

0

–2

G = +2

–4

–6

–8

–10
–12

NORMALIZED GAIN – dB

–14

Figure 35. Frequency Response vs. Capacitive Loading,
R

= 100 Ω Output

L

+2

0

G = +2

–2

= 1kV

R

L

65V

–4

–6

–8

–10

NORMALIZED GAIN – dB, G = 2

–12

–14

S

VIN = 50mV rms
R

= 1.2kV

F

1 50010 40 100

FREQUENCY – MHz

CL = 10pF

CL = 0

Figure 36. Flatness with 10 pF Capacitive Load

DRIVING A SINGLE-SUPPLY A/D CONVERTER

New CMOS A/D converters are placing greater demands on the
amplifiers that drive them. Higher resolutions, faster conversion
rates and input switching irregularities require superior settling
characteristics. In addition, these devices run off a single +5 V
supply and consume little power, so good single-supply operation
with low power consumption are very important. The AD8004
is well positioned for driving this new class of A/D converters.

Figure 37 shows a circuit that uses an AD8004 to drive an
AD876, a single supply, 10-bit, 20 MSPS A/D converter that
requires only 140 mW. Using the AD8004 for level shifting and
driving, the A/D exhibits no degradation in performance com­pared to when it is driven from a signal generator.

The analog input of the AD876 spans 2 V centered at about

2.6 V. The resistor network and bias voltages provide the level
shifting and gain required to convert the 0 V to 1 V input signal
to a 3.6 V to 1.6 V range that the AD876 wants to see.

Biasing the noninverting input of the AD8004 at 1.6 V dc forces
the inverting input to be at 1.6 V dc for linear operation of the
amplifier. When the input is at 0 V, there is 3.2 mA flowing out

of the summing junction via R1 (1.6 V/499 Ω). R3 has a current

of 1.2 mA flowing into the summing junction (3.6 V–1.6 V)/

1.65 kΩ. The difference of these two currents (2 mA) must flow

through R2. This current flows toward the summing junction
and requires that the output be 2 V higher than the summing
junction or at 3.6 V.

When the input is at 1 V, there is 1.2 mA flowing into the sum­ming junction through R3 and 1.2 mA flowing out through R1.
These currents balance and leave no current to flow through
R2. Thus the output is at the same potential as the inverting
input or 1.6 V.

The input of the AD876 has a series MOSFET switch that turns
on and off at the sampling rate. This MOSFET is connected to
a hold capacitor internal to the device. The on impedance of the

MOSFET is about 50 Ω, while the hold capacitor is about 5 pF.

In a worst case condition, the input voltage to the AD876 will
change by a full-scale value (2 V) in one sampling cycle. When
the input MOSFET turns on, the output of the op amp will be
connected to the charged hold capacitor through the series
resistance of the MOSFET. Without any other series resistance,
the instantaneous current that flows would be 40 mA. This
would cause settling problems for the op amp.

The series 100 Ω resistor limits the current that flows instanta-

neously after the MOSFET turns on to about 13 mA. This
resistor cannot be made too large or the high frequency perfor­mance will be affected.

The sampling MOSFET of the AD876 is closed for only half of
each cycle or for 25 ns. Approximately seven time constants are

required for settling to 10 bits. The series 100 Ω resistor along
with the 50 Ω on resistance and the hold capacitor, create a

750 ps time constant. These values leave a comfortable margin
for settling. Obtaining the same results with the op amp A/D
combination as compared to driving with a signal generator
indicates that the op amp is settling fast enough.

Overall the AD8004 provides adequate buffering for the AD876
A/D converter without introducing distortion greater than that
of the A/D converter by itself.

+5V

R3

0.1mF

50V

0.1mF

1.65kV

R1

499kV

3.6V

V

1V
0V

IN

1.6V

R2

1kV

AD8004

1/4

0.1mF

3.6V

1.6V

100V

10mF

+3.6V

REFT

AD876

REFB

+1.6V

Figure 37. AD8004 Driving the AD876

LAYOUT CONSIDERATIONS

The specified high speed performance of the AD8004 requires
careful attention to board layout and component selection.
Table I shows the recommended component values for the
AD8004 and Figures 39–41 show the layout for the AD8004
evaluation boards (14-lead DIP and SOIC). Proper R

design

F

techniques and low parasitic component selection are mandatory.

REV. B

–11–

AD8004

The PCB should have a ground plane covering all unused por­tions of the component side of the board to provide a low im­pedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.

Chip capacitors should be used for supply bypassing (see
Figure 38). One end should be connected to the ground plane
and the other within 1/8 in. of each power pin. An additional

(4.7 µF–10 µF) tantalum electrolytic capacitor should be con-

nected in parallel.

The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance greater than 1 pF at the inverting input
will significantly affect high speed performance when operating
at low noninverting gains. An example of extra inverting input
capacitance can be seen on Figure 35 plot.

Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with the
proper system characteristic impedance and be properly termi-

R

V

IN

V

IN

G

R

T

R

NONINVERTING CONFIGURATION

Figure 38. Inverting and Noninverting Configurations

R

F

1/4

INVERTING CONFIGURATION

R

G

R

F

1/4

T

C1

0.1mF
C2

0.1mF

C1

0.1mF
C2

0.1mF

RbT, 50V

RbT, 50V

C3
10mF

C4
10mF

C3
10mF

C4
10mF

V

OUT

+V

S

–V

S

V

OUT

+V

S

–V

S

nated at each end.

Table I. Recommended Component Values and Typical Bandwidths

Alternate Alternate Alternate Alternate

Gain –10 –2 –2 –1 –1 +1 +1 +2 +2 +10

AD8004AN (DIP)
PACKAGE TYPE

R

(Ω) 499 698 499 649 499 1.21 k 806 1.10 k 698 499

F

(Ω) 49.9 348 249 649 499 – – 1.10 k 698 54.9

R

G

R

(Ω) None 57.6 61.9 53.6 54.9 50 50 50 50 50

T

Small Signal BW

@ ±5 V

Peaking @ ±5 V

(MHz) 155 125 180 135 190 150 250 115 185 135

S

S

< 0.3 dB None 0.3 dB None 0.3 dB 1.3 dB 1.7 dB < 0.14 dB 0.4 dB < 0.3 dB

0.1 dB Flatness

@ ±5 V

(MHz) – 25 – 30 – – – 35 – –

S

Small Signal BW

@ +5 VS (MHz) 135 105 155 120 160 130 200 95 150 120

AD8004AR (SOIC)
PACKAGE TYPE

R

(Ω) 499 698 499 750 499 1.10 k 698 1.10 k 604 499

F

(Ω) 49.9 348 249 750 499 – – 1.10 k 604 54.9

R

G

R

(Ω) None 57.6 61.9 53.6 54.9 50 50 50 50 50

T

Small Signal BW

@ ±5 V

Peaking @ ±5 V

(MHz) 155 130 190 125 195 150 225 110 175 135

S

S

< 0.7 dB < 0.1 dB 0.5 dB None 0.4 dB 1.3 dB 1.8 dB < 0.1 dB 0.5 dB < 0.2 dB

0.1 dB Flatness

@ ±5 V

(MHz) – 35 – 25 – – – 30 – –

S

Small Signal BW

@ +5 VS (MHz) 135 115 175 110 165 130 195 95 155 120

NOTES

1

R

chosen for 50 Ω characteristic input impedance.

T

2

Resistor values listed are standard 1% tolerance.

–12–

REV. B

AD8004

Figure 39. Evaluation Board Silkscreen (Top)

REV. B

–13–

AD8004

Figure 40 Evaluation Board Layout (Top Side)

Figure 41. Evaluation Board Layout (Bottom Side, Looking Through the Board)

–14–

REV. B

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

14-Lead Plastic DIP

(N-14)

AD8004

PIN 1

0.210
(5.33)

MAX

0.160 (4.06)

0.115 (2.93)

0.1574 (4.00)

0.1497 (3.80)

0.0098 (0.25)

0.0040 (0.10)

14

1

0.022 (0.558)

0.014 (0.356)

8

0.280 (7.11)

0.240 (6.10)

7

0.795 (20.19)

0.725 (18.42)

0.100
(2.54)

BSC

0.070 (1.77)

0.045 (1.15)

0.060 (1.52)

0.015 (0.38)

14-Lead Plastic SOIC

(R-14)

0.3444 (8.75)

0.3367 (8.55)

14 8

PIN 1

0.2440 (6.20)

71

0.2284 (5.80)

0.0688 (1.75)

0.0532 (1.35)

0.130
(3.30)
MIN

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.0196 (0.50)

0.0099 (0.25)

0.195 (4.95)

0.115 (2.93)

x 45°

C2078a–0–8/99

REV. B

SEATING

PLANE

0.0500
(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

–15–

0.0099 (0.25)

0.0075 (0.19)

8°
0°

0.0500 (1.27)

0.0160 (0.41)

PRINTED IN U.S.A.

C2078a–0–8/99

–16–

PRINTED IN U.S.A.