Datasheet AD8002 Datasheet (Analog Devices)

Dual 600 MHz, 50 mW

1M 10M 1G100M

0

–0.5

–0.1

–0.2

–0.3

–0.4

0.1

1

–4

–9

–5

–6

–7

–8

–3

–2

–1

0

NORMALIZED FLATNESS – dB

FREQUENCY – Hz

NORMALIZED FREQUENCY RESPONSE – dB

G = +2
R

L

= 100V

VIN = 50mV

SIDE 1

SIDE 2

SIDE 1

SIDE 2

a

FEATURES
Excellent Video Specifications (R

Gain Flatness 0.1 dB to 60 MHz

0.01% Differential Gain Error

0.02ⴗ Differential Phase Error

Low Power

5.5 mA/Amp Max Power Supply Current (55 mW)

High Speed and Fast Settling

600 MHz, –3 dB Bandwidth (G = +1)
500 MHz, –3 dB Bandwidth (G = +2)
1200 V/␮s Slew Rate
16 ns Settling Time to 0.1%

Low Distortion

–65 dBc THD, f

= 5 MHz

C

33 dBm 3rd Order Intercept, F
–66 dB SFDR, f = 5 MHz
–60 dB Crosstalk, f = 5 MHz

High Output Drive

Over 70 mA Output Current
Drives Up to Eight Back-Terminated 75 ⍀ Loads

(Four Loads/Side) While Maintaining Good
Differential Gain/Phase Performance (0.01%/0.17ⴗ)

Available in 8-Lead Plastic DIP, SOIC and ␮SOIC Packages

= 150 ⍀, G = +2)

L

= 10 MHz

1

Current Feedback Amplifier

AD8002

FUNCTIONAL BLOCK DIAGRAM

8-Lead Plastic DIP, SOIC and ␮SOIC

OUT1

1

2

–IN1

3

+IN1

4

V–

AD8002

The outstanding bandwidth of 600 MHz along with 1200 V/µs

of slew rate make the AD8002 useful in many general purpose

high speed applications where dual power supplies of up to ±6 V

and single supplies from 6 V to 12 V are needed. The AD8002 is

available in the industrial temperature range of –40°C to +85°C.

V+

8

7

OUT2

–IN2

6

+IN2

5

APPLICATIONS
A-to-D Driver
Video Line Driver
Differential Line Driver
Professional Cameras
Video Switchers
Special Effects
RF Receivers

PRODUCT DESCRIPTION

The AD8002 is a dual, low power, high speed amplifier de-

signed to operate on ±5 V supplies. The AD8002 features

unique transimpedance linearization circuitry. This allows it to
drive video loads with excellent differential gain and phase per­formance on only 50 mW of power per amplifier. The AD8002
is a current feedback amplifier and features gain flatness of 0.1 dB
to 60 MHz while offering differential gain and phase error of

0.01% and 0.02°. This makes the AD8002 ideal for professional

video electronics such as cameras and video switchers. Addition­ally, the AD8002’s low distortion and fast settling make it ideal
for buffer high speed A-to-D converters.

The AD8002 offers low power of 5.5 mA/amplifier max (V

±5 V) and can run on a single +12 V power supply, while ca-

pable of delivering over 70 mA of load current. It is offered in

an 8-lead plastic DIP, SOIC and µSOIC package. These features

make this amplifier ideal for portable and battery powered appli­cations where size and power is critical.

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

=

S

Figure 1. Frequency Response and Flatness, G = +2

Figure 2. 1 V Step Response, G = +1

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD8002–SPECIFICATIONS

(@ TA = + 25ⴗC, VS = ⴞ5 V, RL = 100 ⍀, R

1

= 75 ⍀, unless otherwise noted)

C

Model AD8002A

Conditions Min Typ Max Units

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth, N Package G = +2, R

G = +1, R

R Package G = +2, R

G = +1, R

RM Package G = +2, R

G = +1, R

= 750 Ω 500 MHz

F

= 1.21 kΩ 600 MHz

F

= 681 Ω 500 MHz

F

= 953 Ω 600 MHz

F

= 681 Ω 500 MHz

F

= 1 kΩ 600 MHz

F

Bandwidth for 0.1 dB Flatness

N Package G = +2, R
R Package G = +2, R
RM Package G = +2, R

Slew Rate G = +2, V

G = –1, V
Settling Time to 0.1% G = +2, V
Rise & Fall Time G = +2, VO = 2 V Step, R

= 750 Ω 60 MHz

F

= 681 Ω 90 MHz

F

= 681 Ω 60 MHz

F

= 2 V Step 700 V/µs

O

= 2 V Step 1200 V/µs

O

= 2 V Step 16 ns

O

= 750 Ω 2.4 ns

F

NOISE/HARMONIC PERFORMANCE

Total Harmonic Distortion f

= 5 MHz, VO = 2 V p-p –65 dBc

C

G = +2, R

= 100 Ω

L

Crosstalk, Output to Output f = 5 MHz, G = +2 –60 dB
Input Voltage Noise f = 10 kHz, R

= 0 Ω 2.0 nV/√Hz

C

Input Current Noise f = 10 kHz, +In 2.0 pA/√Hz

–In 18 pA/√Hz

Differential Gain Error NTSC, G = +2, R
Differential Phase Error NTSC, G = +2, R

= 150 Ω 0.01 %

L

= 150 Ω 0.02 Degree

L

Third Order Intercept f = 10 MHz 33 dBm
1 dB Gain Compression f = 10 MHz 14 dBm
SFDR f = 5 MHz –66 dB

DC PERFORMANCE

Input Offset Voltage 2.0 6 mV

T

MIN–TMAX

2.0 9 mV

Offset Drift 10 µV/°C
–Input Bias Current 5.0 25 ±µA

T

MIN–TMAX

35 ±µA

+Input Bias Current 3.0 6.0 ±µA

10 ±µA

Open Loop Transresistance V

T

MIN–TMAX

= ±2.5 V 250 900 kΩ

O

T

MIN–TMAX

175 kΩ

INPUT CHARACTERISTICS

Input Resistance +Input 10 MΩ

–Input 50 Ω

Input Capacitance +Input 1.5 pF

Input Common-Mode Voltage Range 3.2 ±V

Common-Mode Rejection Ratio

Offset Voltage V
–Input Current V
+Input Current V

= ±2.5 V 49 54 dB

CM

= ±2.5 V, T

CM

= ±2.5 V, T

CM

MIN–TMAX

MIN–TMAX

0.3 1.0 µA/V

0.2 0.9 µA/V

OUTPUT CHARACTERISTICS

Output Voltage Swing R
Output Current
Short Circuit Current

2

2

= 150 Ω 2.7 3.1 ±V

L

70 mA

85 110 mA

POWER SUPPLY

Operating Range ±3.0 ±6.0 V

Quiescent Current/Both Amplifiers T
Power Supply Rejection Ratio +V

–Input Current T
+Input Current T

NOTES

1

RC is recommended to reduce peaking and minimize input reflections at frequencies above 300 MHz. However, R

2

Output current is limited by the maximum power dissipation in the package. See the power derating curves.

Specifications subject to change without notice.

MIN–TMAX

= +4 V to +6 V, –VS = –5 V 60 75 dB

S

= – 4 V to –6 V, +VS = +5 V 49 56 dB

–V

S

MIN–TMAX

MIN–TMAX

is not required.

C

10.0 11.5 mA

0.5 2.5 µA/V

0.1 0.5 µA/V

–2–

REV. C

AD8002

2.0

0
–50 80

1.5

0.5

–40

1.0

010–10–20–30 20 30 40 50 60 70 90

MAXIMUM POWER DISSIPATION – Watts

AMBIENT TEMPERATURE – 8C

8-LEAD PLASTIC-DIP PACKAGE

8-LEAD SOIC PACKAGE

TJ = +1508C

8-LEAD mSOIC

PACKAGE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V

Internal Power Dissipation

2

1

Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . . . . . 1.3 W

Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . .0.9 W

µSOIC Package (RM) . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±1.2 V

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves

Storage Temperature Range N, R, RM . . . . . –65°C to +125°C

Operating Temperature Range (A Grade) . . . –40°C to +85°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for device in free air:

8-Lead Plastic DIP Package: θJA = 90°C/W
8-Lead SOIC Package: θJA = 155°C/W
8-Lead µSOIC Package: θJA = 200°C/W

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8002 is limited by the associated rise in junction tempera­ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition tem-

perature of the plastic, approximately +150°C. Exceeding this

limit temporarily may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.

Exceeding a junction temperature of +175°C for an extended

period can result in device failure.

While the AD8002 is internally short circuit protected, this
may not be sufficient to guarantee that the maximum junction

temperature (+150°C) is not exceeded under all conditions. To

ensure proper operation, it is necessary to observe the maximum
power derating curves.

Figure 3. Plot of Maximum Power Dissipation vs.
Temperature

ORDERING GUIDE

Model Temperature Range Package Description Package Option Brand Code

AD8002AN –40°C to +85°C 8-Lead PDIP N-8 Standard
AD8002AR –40°C to +85°C 8-Lead SOIC SO-8 Standard
AD8002AR-REEL –40°C to +85°C 8-Lead SOIC 13" REEL SO-8 Standard
AD8002AR-REEL7 –40°C to +85°C 8-Lead SOIC 7" REEL SO-8 Standard
AD8002ARM –40°C to +85°C 8-Lead µSOIC RM-8 HFA
AD8002ARM-REEL –40°C to +85°C 8-Lead µSOIC 13" REEL RM-8 HFA
AD8002ARM-REEL7 –40°C to +85°C 8-Lead µSOIC 7" REEL RM-8 HFA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8002 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. C

–3–

AD8002

PULSE

GENERATOR

750V

+5V

RL = 100V

–5V

50V

V

IN

0.1mF

10mF

AD8002

0.1mF

10mF

TR/TF = 250ps

75V

750V

V

GENERATOR

TR/TF = 250ps

953V

10mF

0.1mF

0.1mF

10mF

IN

PULSE

75V

50V

+5V

AD8002

–5V

Figure 4. Test Circuit , Gain = +1

RL = 100V

Figure 7. Test Circuit, Gain = +2

Figure 5. 100 mV Step Response, G = +1

Figure 6. 1 V Step Response, G = +1

Figure 8. 100 mV Step Response, G = +2

Figure 9. 1 V Step Response, G = +2

–4–

REV. C

1

–70

1M 100M10M100k

–60

–100

–90

–80

OUTPUT SIDE 1

OUTPUT SIDE 2

CROSSTALK – dB

–50

–40

–30

–20

–110

–120

FREQUENCY – Hz

VIN = –4dBV
R

L

= 100V

V

S

= 65.0V

G = +2
R

F

= 750V

0.02

0.06

0.02

1

0.04

–0.02

0.08

–0.01

0.00

0.01

IRE

DIFF GAIN – %

DIFF PHASE – Degrees

0.00

G = +2
RF = 750V

NTSC

234567891011

2 BACK TERMINATED

LOADS (75V)

1 BACK TERMINATED

LOAD (150V)

2 BACK TERMINATED

LOADS (75V)

1 BACK TERMINATED

LOAD (150V)

G = +2
RL = 100V

= 50mV

V

IN

0.1

0

–0.1

–0.2

NORMALIZED FLATNESS – dB

–0.3

–0.4

–0.5

1M 10M 1G100M

50V

681V

75V

50V

R

F

681V

FREQUENCY – Hz

SIDE 1

SIDE 2

SIDE 1

SIDE 2

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

Figure 10. Frequency Response and Flatness, G = +2

–50

G = +2
RL = 100V

–60

–70

–80

–90

DISTORTION – dBc

2ND HARMONIC

3RD HARMONIC

AD8002

NORMALIZED FREQUENCY RESPONSE – dB

Figure 13. Crosstalk (Output-to-Output) vs. Frequency

REV. C

–100

–110

10k 100M100k 1M 10M

FREQUENCY – Hz

Figure 11. Distortion vs. Frequency, G = +2, RL = 100

–60

G = +2
RL = 1kV

= 2V p-p

V

–70

OUT

–80

–90

–100

DISTORTION – dBc

–110

–120

10k 100M100k 1M 10M

2ND HARMONIC

FREQUENCY – Hz

3RD HARMONIC

Figure 12. Distortion vs. Frequency, G = +2, RL = 1 k

NOTES: SIDE 1: VIN = 0V; 8mV/div RTO

SIDE 2: 1V STEP RTO; 400mV/div

Ω

Ω

Figure 14. Pulse Crosstalk, Worst Case, 1 V Step

Figure 15. Differential Gain and Differential Phase
(per Amplifier)

–5–

AD8002

0

–3

–27

10M 500M100M

–18

–21

–24

–15

–12

–9

–6

INPUT LEVEL – dBV

FREQUENCY – Hz

+6

+3

0

–3

–6

–9

–12

–15

–18

–21

OUTPUT LEVEL – dBV

1M

G = +2
RF = 681V

V

S

= 65V

R

L

= 100V

INPUT/OUTPUT LEVEL – dBV

FREQUENCY – Hz

+6

+3

–27

–12

–15

–18

–9

–6

–3

0

+9

10M 500M100M1M

RL = 100V
G = +1

R

F

= 1.21kV

75V

50V

50V

1.21kV

+2

+1

0

–1

–2

GAIN – dB

–3

–4

–5

VIN = 50mV
G = +1

= 953V

R

F

= 100V

R

L

50V

75V

SIDE 1

SIDE 2

50V

953V

–6

Figure 16. Frequency Response, G = +1

–40

–50

–60

–70

–80

DISTORTION – dBc

–90

–100

Figure 17. Distortion vs. Frequency, G = +1, RL = 100

–40

–50

–60

–70

–80

DISTORTION – dBc

–90

–100

–110

Figure 18. Distortion vs. Frequency, G = +1, RL = 1 k

10M 1G100M1M

FREQUENCY – Hz

G = +1
RL = 100V

V

= 2V p-p

OUT

2ND HARMONIC

100k 100M10M1M10k

FREQUENCY – Hz

G = +1
R

= 1kV

L

2ND HARMONIC

100k 100M10M1M10k

FREQUENCY – Hz

3RD HARMONIC

3RD HARMONIC

Figure 19. Large Signal Frequency Response, G = +2

Ω

Ω

Figure 20. Large Signal Frequency Response, G = +1

+45

+40

+35
+30

+25
+20

GAIN – dB

+15

+10

+5

0

–5

1M 10M 100M

G = +100
RF = 1000V

G = +10
RF = 499V

FREQUENCY – Hz

VS = 65V
RL = 100V

Figure 21. Frequency Response, G = +10, G = +100

–6–

1G

REV. C

AD8002

4

–3

0

–2

–1

3

1

2

125–35–55 105856545255–15

JUNCTION TEMPERATURE – 8C

INPUT OFFSET VOLTAGE – mV

DEVICE #1

DEVICE #2

DEVICE #3

11.5

9.0
125

10.5

9.5

–35

10.0

–55

11.0

105856545255–15

JUNCTION TEMPERATURE – 8C

TOTAL SUPPLY CURRENT – mA

VS = 65V

Figure 22. Short-Term Settling Time

3.4

3.3

3.2

3.1

3.0

2.9

2.8

OUTPUT SWING – Volts

2.7

2.6

2.5

+V

+V

OUT

–35–55

OUT

|–V

|–V

OUT

JUNCTION TEMPERATURE – 8C

OUT

|

RL = 150V

VS = 65V

|

RL = 50V

VS = 65V

Figure 23. Output Swing vs. Temperature

5

4

3

–IN

Figure 25. Long-Term Settling Time

105856545255–15

125

Figure 26. Input Offset Voltage vs. Temperature

2

1

0

–1

INPUT BIAS CURRENT – mA

–2

–3

Figure 24. Input Bias Current vs. Temperature

REV. C

+IN

JUNCTION TEMPERATURE – 8C

125–35–55 105856545255–15

Figure 27. Total Supply Current vs. Temperature

–7–

AD8002

FREQUENCY – Hz

1

10k 100k 1G100M10M1M

10

100

0.01

0.1

RESISTANCE – V

RF = 750V
R

C

= 75V

V

S

= 65.0V

POWER = 0dBm
(223.6mVrms)
G = +2

RbT = 0V

RbT = 50V

–50.0

–72.5

125

–67.5

–70.0

–35–55

–65.0

–62.5

–60.0

–57.5

–55.0

–52.5

105856545255–15

JUNCTION TEMPERATURE – 8C

PSRR – dB

–75.0

–PSRR

+PSRR

2V SPAN
CURVES ARE FOR WORST

CASE CONDITION WHERE
ONE SUPPLY IS VARIED
WHILE THE OTHER IS
HELD CONSTANT.

120

115
110

105

100

95
90

85

80

SHORT CIRCUIT CURRENT – mA

75

70

–35–55

Figure 28. Short Circuit Current vs. Temperature

|SINK ISC|

JUNCTION TEMPERATURE – 8C

SOURCE I

SC

125

105856545255–15

Figure 31. Output Resistance vs. Frequency

100

10

NOISE VOLTAGE – nV/ Hz

1

10

–48

–49

–50

–51

–52

CMRR – dB

–53

INVERTING CURRENT VS = 65V

NONINVERTING CURRENT VS = 65V

VOLTAGE NOISE VS = 65V

100 100k10k1k

FREQUENCY – Hz

Figure 29. Noise vs. Frequency

–CMRR

+CMRR

100

10

1

–3dB BANDWIDTH

+0.2

+0.1

0.1dB FLATNESS

0

–0.1

VS = 65V

–0.2

V

= 50mV

IN

G = –1

–0.3

R

= 100V

L

R

NOISE CURRENT – pA/ Hz

= 549V

F

1M 10M 1G100M

FREQUENCY – Hz

SIDE 2

SIDE 2

SIDE 1

SIDE 1

1

0

–1

–2

–3

–4

–5

–6

OUTPUT VOLTAGE – dB

–7

–8

–9

Figure 32. –3 dB Bandwidth vs. Frequency, G = –1

–54

–55

–56

JUNCTION TEMPERATURE – 8C

Figure 30. CMRR vs. Temperature

125–35–55 105856545255–15

Figure 33. PSRR vs. Temperature

–8–

REV. C

AD8002

0

–10

–20

–30

CMRR – dB

–40

–50

–60

57.6V

V

IN

604V

604V

154Ω

50V

154V

–5V

FREQUENCY – Hz

0.1mF

SIDE 1

Figure 34. CMRR vs. Frequency

SIDE 2

100M10M1M

VS = 65.0V

= 100V

R

L

= 200mV

V

IN

1G

0

VIN = 200mV

–10

G = +2

–20

–30

–40

–50

PSRR – dB

–60

–70

–80

–90

100k 1M 10M

30k 500M

–PSRR

+PSRR

100M

FREQUENCY – Hz

Figure 37. PSRR vs. Frequency

Figure 35. 2 V Step Response, G = –1

576V

576V

54.9V
50V

50V

Figure 36. 100 mV Step Response, G = –1

Figure 38. 2 V Step Response, G = –2

549V

274V

61.9V
50V

50V

Figure 39. 100 mV Step Response, G = –2

REV. C

–9–

AD8002

R

F

R

I

R

N

I

BN

V

OUT

I

BI

THEORY OF OPERATION

A very simple analysis can put the operation of the AD8002, a
current feedback amplifier, in familiar terms. Being a current
feedback amplifier, the AD8002’s open-loop behavior is ex-

/∆I

pressed as transimpedance, ∆V

, or TZ. The open-loop

O

–IN

transimpedance behaves just as the open-loop voltage gain of a
voltage feedback amplifier, that is, it has a large dc value and
decreases at roughly 6 dB/octave in frequency.

Since the R
gain is just T

is proportional to 1/gM, the equivalent voltage

IN

× g

, where the gM in question is the trans-

Z

M

conductance of the input stage. This results in a low open-loop
input impedance at the inverting input, a now familiar result.
Using this amplifier as a follower with gain, Figure 40, basic
analysis yields the following result.

()

V

O

=×

G

V

IN

=+ = ≈

G

R2

V

IN

TS G R R

1

R

1

2

R

TS

Z

+× +

()

ZIN

/

150Ω

Rg

IN M

R1

R

IN

1

V

OUT

Figure 40.

Recognizing that G × R

<< R1 for low gains, it can be seen to

IN

the first order that bandwidth for this amplifier is independent
of gain (G).

Considering that additional poles contribute excess phase at
high frequencies, there is a minimum feedback resistance below
which peaking or oscillation may result. This fact is used to
determine the optimum feedback resistance, R

. In practice

F

parasitic capacitance at the inverting input terminal will also add
phase in the feedback loop, so picking an optimum value for R

F

can be difficult.

Achieving and maintaining gain flatness of better than 0.1 dB at
frequencies above 10 MHz requires careful consideration of
several issues.

Choice of Feedback and Gain Resistors

The fine scale gain flatness will, to some extent, vary with feed­back resistance. It, therefore, is recommended that once opti­mum resistor values have been determined, 1% tolerance values
should be used if it is desired to maintain flatness over a wide
range of production lots. In addition, resistors of different con­struction have different associated parasitic capacitance and
inductance. Surface mount resistors were used for the bulk of
the characterization for this data sheet. It is not recommended
that leaded components be used with the AD8002.

Printed Circuit Board Layout Considerations

As to be expected for a wideband amplifier, PC board parasitics
can affect the overall closed-loop performance. Of concern are
stray capacitances at the output and the inverting input nodes. If
a ground plane is to be used on the same side of the board as
the signal traces, a space (5 mm min) should be left around the
signal lines to minimize coupling. Additionally, signal lines
connecting the feedback and gain resistors should be short
enough so that their associated inductance does not cause high
frequency gain errors. Line lengths on the order of less than 5
mm are recommended. If long runs of coaxial cable are being
driven, dispersion and loss must be considered.

Power Supply Bypassing

Adequate power supply bypassing can be critical when optimiz­ing the performance of a high frequency circuit. Inductance in
the power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors

(typically greater than 1 µF) will be required to provide the best

settling time and lowest distortion. A parallel combination of

4.7 µF and 0.1 µF is recommended. Some brands of electrolytic
capacitors will require a small series damping resistor ≈4.7 Ω for

optimum results.

DC Errors and Noise

There are three major noise and offset terms to consider in a
current feedback amplifier. For offset errors refer to the equa­tion below. For noise error the terms are root-sum-squared to
give a net output error. In the circuit below (Figure 41) they are
input offset (V
noise gain of the circuit (1 + R

× R

(I

BN

N

input current, which when divided between R

) which appears at the output multiplied by the

IO

), noninverting input current

F/RI

) also multiplied by the noise gain, and the inverting

and RI and sub-

F

sequently multiplied by the noise gain always appears at the

× R

output as I

. The input voltage noise of the AD8002 is a

BN

F

low 2 nV/√Hz. At low gains though the inverting input current

noise times R

is the dominant noise source. Careful layout and

F

device matching contribute to better offset and drift specifica­tions for the AD8002 compared to many other current feedback
amplifiers. The typical performance curves in conjunction with
the equations below can be used to predict the performance of
the AD8002 in any application.

VV

=×+

OUT IO








R

F

±××+

IR

BN N




R

I








R

F

±×11

IR

BI F




R

I

Figure 41. Output Offset Voltage

–10–

REV. C

Driving Capacitive Loads

–80

3–7

–75

210–4–5 6–2

–70

–65

–60

–55

–50

–45

–1

THIRD ORDER IMD – dBc

INPUT POWER – dBm

–6–8 4 5–3

2F2 – F

1

2F1 – F

2

G = +2
F1 = 10MHz

F

2

= 12MHz

750V

750V

75V

CABLE

75V

75V

V

OUT

#1

V

OUT

#2

+V

S

–V

S

V

IN

0.1mF

4.7mF

1/2

AD8002

0.1mF

4.7mF

75V

CABLE

75V

75V

75V

CABLE

75V

75V

V

OUT

#3

V

OUT

#4

75V

CABLE

75V

75V

1/2

AD8002

750V

750V

75V

CABLE

75V

+

The AD8002 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, best
frequency response is obtained by the addition of a small series
resistance as shown in Figure 42. The accompanying graph

909V

R

I

N

SERIES

500V

R

L

C

L

Figure 42. Driving Capacitive Loads

shows the optimum value for R

vs. capacitive load. It is

SERIES

worth noting that the frequency response of the circuit when
driving large capacitive loads will be dominated by the passive
roll-off of R

40

30

– V

20

SERIES

R

SERIES

and CL.

AD8002

Figure 44. Third Order IMD; F1 = 10 MHz, F2 = 12 MHz

Operation as a Video Line Driver

The AD8002 has been designed to offer outstanding perfor­mance as a video line driver. The important specifications of

differential gain (0.01%) and differential phase (0.02°) meet the

most exacting HDTV demands for driving one video load with
each amplifier. The AD8002 also drives four back terminated
loads (two each), as shown in Figure 45, with equally impressive

performance (0.01%, 0.07°). Another important consideration

is isolation between loads in a multiple load application. The
AD8002 has more than 40 dB of isolation at 5 MHz when driv-

ing two 75 Ω back terminated loads.

Communications

Distortion is a key specification in communications applications.
Intermodulation distortion (IMD) is a measure of the ability of
an amplifier to pass complex signals without the generation of
spurious harmonics. The third order products are usually the
most problematic since several of them fall near the fundamen­tals and do not lend themselves to filtering. Theory predicts that
the third order harmonic distortion components increase in
power at three times the rate of the fundamental tones. The
specification of third order intercept as the virtual point where
fundamental and harmonic power are equal is one standard
measure of distortion performance. Op amps used in closed­loop applications do not always obey this simple theory. At a
gain of two, the AD8002 has performance summarized in Fig­ure 44. Here the worst third order products are plotted vs. input
power. The third order intercept of the AD8002 is +33 dBm at
10 MHz.

REV. C

10

0

025

Figure 43. Recommended R

5

CL – pF

15 2010

vs. Capacitive Load

SERIES

–11–

Figure 45. Video Line Driver

AD8002

Driving A-to-D Converters

The AD8002 is well suited for driving high speed analog-to­digital converters such as the AD9058. The AD9058 is a dual
8-bit 50 MSPS ADC. In the circuit below the AD8002 is shown
driving the inputs of the AD9058 which are configured for 0 V
to +2 V ranges. Bipolar input signals are buffered, amplified

(–2×), and offset (by +1.0 V) into the proper input range of the

ENCODE

ENCODE A ENCODE B

8

–V

38

–V

6

A

2

+V

3

+V

43

+V

40

A

1

COMP

ANALOG

IN A

60.5V

ANALOG

IN B

60.5V

274V

1.1kV

0.1mF

1.1kV

274V

50V

–2V

50V

RZ1, RZ2 = 2,000V SIP (8-PKG)

549V

1/2

AD8002

AD707

20kV

549V

1/2

AD8002

20V

20kV

0.1mF

20V

0.1mF

ADC. Using the AD9058’s internal +2 V reference connected
to both ADCs as shown in Figure 46 reduces the number of
external components required to create a complete data

acquisition system. The 20 Ω resistors in series with ADC in-

puts are used to help the AD8002s drive the 10 pF ADC input
capacitance. The AD8002 only adds 100 mW to the power
consumption while not limiting the performance of the circuit.

0.1mF
RZ1

RZ2

1N4001

1kV

+5V

–5V

10pF

8

74ACT 273

8

74ACT 273

CLOCK

10

REF A

REF B

IN A

INT

REF A

REF B

AD9058

(J-LEAD)

IN B

4,19, 21 25, 27, 42

36

+V

D0A (LSB)

D

(MSB)

7A

(LSB)

D

0B

D

(MSB)

7B

–V

50V

S

S

74ACT04

5, 9, 22,
24, 37, 41

18
17
16
15
14
13
12
11

28
29
30
31
32
33
34
35

7, 20,
26, 39

0.1mF

Figure 46. AD8002 Driving a Dual A-to-D Converter

–12–

REV. C

AD8002

+6

–4

–14

1M 10M 1G100M

–6

–8

–10
–12

–2

0

+2

+4

OUTPUT – dB

FREQUENCY – Hz

CC = 0.9pF

OUT+

OUT–

Single-Ended to Differential Driver Using an AD8002

The two halves of an AD8002 can be configured to create a
single-ended to differential high speed driver with a –3 dB band­width in excess of 200 MHz as shown in Figure 47. Although
the individual op amps are each current feedback, the overall
architecture yields a circuit with attributes normally associated
with voltage feedback amplifiers, while offering the speed advan­tages inherent in current feedback amplifiers. In addition, the
gain of the circuit can be changed by varying a single resistor,

, which is often not possible in a dual op amp differential

R

F

driver.

R

G

V

511V

IN

AD8002

AD8002

Figure 47. Differential Line Driver

The current feedback nature of the op amps, in addition to
enabling the wide bandwidth, provides an output drive of more

than 3 V p-p into a 20 Ω load for each output at 20 MHz. On

the other hand, the voltage feedback nature provides symmetri­cal high impedance inputs and allows the use of reactive compo­nents in the feedback network.

The circuit consists of the two op amps each configured as a

unity gain follower by the 511 Ω R

each op amp’s output and inverting input. The output of each

op amp has a 511 Ω R

other op amp. Thus, each output drives the other op amp
through a unity gain inverter configuration. By connecting the
two amplifiers as cross-coupled inverters, their outputs are freed
to be equal and opposite, assuring zero-output common-mode
voltage.

With this circuit configuration, the common-mode signal of the
outputs is reduced. If one output moves slightly higher, the
negative input to the other op amp drives its output to go
slightly lower and thus preserves the symmetry of the comple­mentary outputs which reduces the common-mode signal. The
common-mode output signal was measured to be –50 dB at
1 MHz.

Looking at this configuration overall, there are two high imped­ance inputs (the + inputs of each op amp), two low impedance
outputs and high open loop gain. If we consider the two nonin­verting inputs and just the output of Op Amp #2, the structure
looks like a voltage feedback op amp having two symmetrical,
high impedance inputs and one output. The +input to Op Amp
#2 is the noninverting input (it has the same polarity as Output
#2) and the +input to Amplifier #1 is the inverting input (oppo­site polarity of Output #2).

REV. C

C

0.5–1.5pF

C

R

511V

F

OP AMP #1

1/2

R

A

511V

R

B

511V

1/2

resistor to the inverting input of the

B

R

A

511V

OP AMP #2

R

511V

A

50V

B

50V

OUTPUT #1

OUTPUT #2

feedback resistors between

With a feedback resistor R

, an input resistor RG, and grounding

F

of the +input of Op Amp #2, a feedback amplifier is formed.
This configuration is just like a voltage feedback amplifier in an
inverting configuration if only Output #2 is considered. The
addition of Output #1 makes the amplifier differential output.

The differential gain of this circuit is:

=×+



R



G



R

F

G



R

A

1



R



B

The RF/RG term is the gain of the overall op amp configuration
and is the same as for an inverting op amp except for the polar­ity. If Output #1 is used as the output reference, then the gain is
positive. The 1+R

term is the noise gain of each individual

A/RB

op amp in its noninverting configuration.

The resulting architecture offers several advantages. First, the
gain can be changed by changing a single resistor. Changing
either R

or RG will change the gain as in an inverting op amp

F

circuit. For most types of differential circuits, more than one
resistor must be changed to change gain and still maintain good
CMR.

Reactive elements can be used in the feedback network. This is
in contrast to current feedback amplifiers that restrict the use of
reactive elements in the feedback. The circuit described requires
about 0.9 pF of capacitance in shunt across R

in order to opti-

F

mize peaking and realize a –3 dB bandwidth of more than
200 MHz.

The peaking exhibited by the circuit is very sensitive to the value
of this capacitor. Parasitics in the board layout on the order of
tenths of picofarads will influence the frequency response and
the value required for the feedback capacitor, so a good layout is
essential.

The shunt capacitor type selection is also critical. A good micro­wave type chip capacitor with high Q was found to yield best
performance. The part selected for this circuit was a muRata
Erie part no. MA280R9B.

The distortion was measured at 20 MHz with a 3 V p-p input

and a 100 Ω load on each output. For Output #1 the distortion

is –37 dBc and –41 dBc for the second and third harmonics
respectively. For Output #2 the second harmonic is –35 dBc
and the third harmonic is –43 dBc.

Figure 48. Differential Driver Frequency Response

–13–

AD8002

g

Layout Considerations

The specified high speed performance of the AD8002 requires
careful attention to board layout and component selection.
Proper R
tion are mandatory.

The PCB should have a ground plane covering all unused por­tions of the component side of the board to provide a low im­pedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.

Chip capacitors should be used for supply bypassing (see Figure

49). One end should be connected to the ground plane and the
other within 1/8 in. of each power pin. An additional large

(4.7 µF–10 µF) tantalum electrolytic capacitor should be con-

nected in parallel, but not necessarily so close, to supply current
for fast, large-signal changes at the output.

The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the invert­ing input will significantly affect high speed performance.

Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with a

characteristic impedance of 50 Ω or 75 Ω and be properly termi-

nated at each end.

design techniques and low parasitic component selec-

F

R

F

+V

R

IN

G

R

T

R

S

S

R

BT

OUT

–V

S

Inverting Configuration

+V

S

–V

S

C1

0.1mF

C2

0.1mF

C3
10mF

C4
10mF

Supply Bypassing

R

F

+V

S

R

BT

–V

S

*SEE TABLE I

Configuration

OUT

IN

Noninvertin

R

G

*R

C

R

T

Figure 49. Inverting and Noninverting Configurations

Table I. Recommended Component Values

AD8002AN (DIP) AD8002AR (SOIC)

Gain Gain

Component –10 –2 –1 +1 +2 +10 +100 –10 –2 –1 +1 +2 +10 +100

R

(Ω) 499 549 576 1210 750 499 1000 499 499 549 953 681 499 1000

F

(Ω) 49.9 274 576 – 750 54.9 10 49.9 249 549 – 681 54.9 10

R

G

(Nominal) (Ω) 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9

R

BT

(Ω)* 75 75 0 0 75 75 0 0

R

C

(Ω) 49.9 49.9 49.9 49.9 49.9 49.9

R

S

(Nominal) (Ω) – 61.9 54.9 49.9 49.9 49.9 49.9 – 61.9 54.9 49.9 49.9 49.9 49.9

R

T

Small Signal BW (MHz) 270 380 410 600 500 170 17 250 410 410 600 500 170 17

0.1 dB Flatness (MHz) 45 80 130 35 60 24 3 50 100 100 35 90 24 3

AD8002ARM (␮SOIC)

Gain

Component –10 –2 –1 +1 +2 +10 +100

R

(Ω) 499 499 590 1000 681 499 1000

F

(Ω) 49.9 249 590 – 681 54.9 10

R

G

(Nominal) (Ω) 49.9 49.9 49.9 49.9 49.9 49.9 49.9

R

BT

(Ω)* 75 75 0 0

R

C

(Ω) 49.9 49.9 49.9

R

S

(Nominal) (Ω) – 61.9 49.9 49.9 49.9 49.9 49.9

R

T

Small Signal BW (MHz) 270 400 410 600 450 170 19

0.1 dB Flatness (MHz) 60 100 100 35 70 35 3

*RC is recommended to reduce peaking and minimizes input reflections at frequencies above 300 MHz. However, R

is not required.

C

–14–

REV. C

AD8002

REV. C

Figure 50. Board Layout (Silkscreen)

–15–

AD8002

Figure 51. Board Layout (Component Layer)

–16–

REV. C

AD8002

REV. C

Figure 52. Board Layout (Solder Side) (Looking Through the Board)

–17–

AD8002

PIN 1

0.210

(5.33)

MAX

0.160 (4.06)

0.115 (2.93)

0.022 (0.558)

0.014 (0.356)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead Plastic DIP (N-8)

0.430 (10.92)

0.348 (8.84)

8

0.100 (2.54)

5

0.280 (7.11)

14

BSC

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.070 (1.77)

0.045 (1.15)

0.130
(3.30)
MIN

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

8-Lead SOIC (SO-8)

0.195 ( 4.95)

0.115 (2.93)

C2004b–0–7/99

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0098 (0.25)

0.0040 (0.10)
SEATING

0.122 (3.10)

0.114 (2.90)

0.006 (0.15)

0.002 (0.05)
SEATING

0.1 968 (5.00)

0.1 890 (4.80)

85

0.0500 (1.27)
BSC

PLANE

0.122 (3.10)

0.114 (2.90)

85

1

PIN 1

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.018 (0.46)

0.008 (0.20)

PLANE

0.2440 (6.20)

0.2284 (5.80)

41

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

0.0098 (0.25)

0.0075 (0.19)

8-Lead ␮SOIC (RM-8)

0.199 (5.05)

0.187 (4.75)

4

0.043 (1.09)

0.037 (0.94)

0.011 (0.28)

0.003 (0.08)

0.0196 (0.50)

0.0099 (0.25)

88

0.0500 (1.27)

08

0.0160 (0.41)

0.120 (3.05)

0.112 (2.84)

338
278

0.028 (0.71)

0.016 (0.41)

3 458

PRINTED IN U.S.A.

–18–

REV. C