Datasheet AD8001 Datasheet (Analog Devices)

800 MHz, 50 mW

a

FEATURES
Excellent Video Specifications (R

Gain Flatness 0.1 dB to 100 MHz

0.01% Differential Gain Error

0.025ⴗ Differential Phase Error

Low Power

5.5 mA Max Power Supply Current (55 mW)

High Speed and Fast Settling

880 MHz, –3 dB Bandwidth (G = +1)
440 MHz, –3 dB Bandwidth (G = +2)
1200 V/␮s Slew Rate
10 ns Settling Time to 0.1%

Low Distortion

–65 dBc THD, f

= 5 MHz

C

33 dBm 3rd Order Intercept, F
–66 dB SFDR, f = 5 MHz

High Output Drive

70 mA Output Current
Drives Up to Four Back-Terminated Loads (75 ⍀ Each)

While Maintaining Good Differential Gain/Phase
Performance (0.05%/0.25ⴗ)

APPLICATIONS
A-to-D Driver
Video Line Driver
Professional Cameras
Video Switchers
Special Effects
RF Receivers

PRODUCT DESCRIPTION

The AD8001 is a low power, high-speed amplifier designed

to operate on ±5 V supplies. The AD8001 features unique

9

6

G = +2

3

R

= 100V

L

0

–3

GAIN – dB

VS = 65V
R

FB

= 150 ⍀, G = +2)

L

= 10 MHz

1

= 1kV

VS = 65V

= 820V

R

FB

Current Feedback Amplifier

AD8001

FUNCTIONAL BLOCK DIAGRAMS

8-Lead DIP (N-8, Q-8) 5-Lead
and SOIC (SO-8) SOT-23-5

NC

1

–IN

2

+IN

3

4

V–

AD8001

NC = NO CONNECT

NC

8

V+

7

6

OUT

NC

5

transimpedance linearization circuitry. This allows it to drive
video loads with excellent differential gain and phase perfor­mance on only 50 mW of power. The AD8001 is a current
feedback amplifier and features gain flatness of 0.1 dB to 100 MHz
while offering differential gain and phase error of 0.01% and

0.025°. This makes the AD8001 ideal for professional video

electronics such as cameras and video switchers. Additionally,
the AD8001’s low distortion and fast settling make it ideal for
buffer high-speed A-to-D converters.

The AD8001 offers low power of 5.5 mA max (V
can run on a single +12 V power supply, while being capable of
delivering over 70 mA of load current. These features make this
amplifier ideal for portable and battery-powered applications
where size and power are critical.

The outstanding bandwidth of 800 MHz along with 1200 V/µs

of slew rate make the AD8001 useful in many general purpose

high-speed applications where dual power supplies of up to ±6 V

and single supplies from 6 V to 12 V are needed. The AD8001 is

available in the industrial temperature range of –40°C to +85°C.

AD8001

1V

OUT

–V

2

S

34

+IN

+V

5

–IN

= ±5 V) and

S

S

–6

–9

–12

10M 100M 1G

FREQUENCY – Hz

Figure 1. Frequency Response of AD8001

REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Figure 2. Transient Response of AD8001; 2 V Step, G = +2

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD8001–SPECIFICATIONS

(@ TA = + 25ⴗC, VS = ⴞ5 V, RL = 100 ⍀, unless otherwise noted)

Model AD8001A

Conditions Min Typ Max Units

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth, N Package G = +2, < 0.1 dB Peaking, R

G = +1, < 1 dB Peaking, R

R Package G = +2, < 0.1 dB Peaking, R

G = +1, < 0.1 dB Peaking, R

RT Package G = +2, < 0.1 dB Peaking, R

G = +1, < 0.1 dB Peaking, R

= 750 Ω 350 440 MHz

F

= 1 kΩ 650 880 MHz

F

= 681 Ω 350 440 MHz

F

= 845 Ω 575 715 MHz

F

= 768 Ω 300 380 MHz

F

= 1 kΩ 575 795 MHz

F

Bandwidth for 0.1 dB Flatness

N Package G = +2, R
R Package G = +2, R
RT Package G = +2, R

Slew Rate G = +2, V

G = –1, V
Settling Time to 0.1% G = –1, V
Rise and Fall Time G = +2, VO = 2 V Step, R

= 750 Ω 85 110 MHz

F

= 681 Ω 100 125 MHz

F

= 768 Ω 120 145 MHz

F

= 2 V Step 800 1000 V/µs

O

= 2 V Step 960 1200 V/µs

O

= 2 V Step 10 ns

O

= 649 Ω 1.4 ns

F

NOISE/HARMONIC PERFORMANCE

Total Harmonic Distortion f

= 5 MHz, VO = 2 V p-p –65 dBc

C

G = +2, R

= 100 Ω

L

Input Voltage Noise f = 10 kHz 2.0 nV/√Hz
Input Current Noise f = 10 kHz, +In 2.0 pA/√Hz

–In 18 pA/√Hz

Differential Gain Error NTSC, G = +2, R
Differential Phase Error NTSC, G = +2, R

= 150 Ω 0.01 0.025 %

L

= 150 Ω 0.025 0.04 Degree

L

Third Order Intercept f = 10 MHz 33 dBm
1 dB Gain Compression f = 10 MHz 14 dBm
SFDR f = 5 MHz –66 dB

DC PERFORMANCE

Input Offset Voltage 2.0 5.5 mV

T

MIN–TMAX

2.0 9.0 mV

Offset Drift 10 µV/°C
–Input Bias Current 5.0 25 ±µA

T

MIN–TMAX

35 ±µA

+Input Bias Current 3.0 6.0 ±µA

Open Loop Transresistance V

T

MIN–TMAX

= ±2.5 V 250 900 kΩ

O

T

MIN–TMAX

175 kΩ

10 ±µA

INPUT CHARACTERISTICS

Input Resistance +Input 10 MΩ

–Input 50 Ω

Input Capacitance +Input 1.5 pF

Input Common-Mode Voltage Range 3.2 ±V

Common-Mode Rejection Ratio

Offset Voltage V
–Input Current V
+Input Current V

= ±2.5 V 50 54 dB

CM

= ±2.5 V, T

CM

= ±2.5 V, T

CM

MIN–TMAX

MIN–TMAX

0.3 1.0 µA/V

0.2 0.7 µA/V

OUTPUT CHARACTERISTICS

Output Voltage Swing R
Output Current R

= 150 Ω 2.7 3.1 ±V

L

= 37.5 Ω 50 70 mA

L

Short Circuit Current 85 110 mA

POWER SUPPLY

Operating Range ±3.0 ±6.0 V

Quiescent Current T
Power Supply Rejection Ratio +V

–Input Current T
+Input Current T

Specifications subject to change without notice.

MIN–TMAX

= +4 V to +6 V, –VS = –5 V 60 75 dB

S

= – 4 V to –6 V, +VS = +5 V 50 56 dB

–V

S

MIN–TMAX

MIN–TMAX

5.0 5.5 mA

0.5 2.5 µA/V

0.1 0.5 µA/V

–2–

REV. C

AD8001

2.0

0
–50 80

1.5

0.5

–40

1.0

010–10–20–30 20 30 40 50 60 70

90

AMBIENT TEMPERATURE – 8C

MAXIMUM POWER DISSIPATION – Watts

8-LEAD

PLASTIC DIP PACKAGE

8-LEAD

SOIC PACKAGE

TJ = +1508C

5-LEAD

SOT-23-5 PACKAGE

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V

Internal Power Dissipation

2

1

Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . . . . . 1.3 W

Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . . 0.9 W

SOT-23-5 Package (RT) . . . . . . . . . . . . . . . . . . . . . . . 0.5 W

Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±1.2 V

Output Short Circuit Duration

. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves

Storage Temperature Range N, R . . . . . . . . . –65°C to +125°C

Operating Temperature Range (A Grade) . . . –40°C to +85°C

Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for device in free air:

8-Lead Plastic DIP Package: θJA = 90°C/W
8-Lead SOIC Package: θJA = 155°C/W
8-Lead Cerdip Package: θJA = 110°C/W
5-Lead SOT-23-5 Package: θJA = 260°C/W

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8001 is limited by the associated rise in junction tempera­ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition tem-

perature of the plastic, approximately +150°C. Exceeding this

limit temporarily may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.

Exceeding a junction temperature of +175°C for an extended

period can result in device failure.

While the AD8001 is internally short circuit protected, this
may not be sufficient to guarantee that the maximum junction

temperature (+150°C) is not exceeded under all conditions. To

ensure proper operation, it is necessary to observe the maximum
power derating curves.

Figure 3. Plot of Maximum Power Dissipation vs.
Temperature

ORDERING GUIDE

Temperature Package Package Brand

Model Range Description Option Code

AD8001AN –40°C to +85°C 8-Lead Plastic DIP N-8
AD8001AQ –55°C to +125°C 8-Lead Cerdip Q-8
AD8001AR –40°C to +85°C 8-Lead SOIC SO-8
AD8001AR-REEL –40°C to +85°C 13" Tape and REEL SO-8
AD8001AR-REEL7 –40°C to +85°C 7" Tape and REEL SO-8
AD8001ART-REEL –40°C to +85°C 13" Tape and REEL RT-5 HEA
AD8001ART-REEL7 –40°C to +85°C 7" Tape and REEL RT-5 HEA
AD8001ACHIPS –40°C to +85°C Die Form

5962-9459301MPA
AD8001R-EB+2

NOTES

1

Standard Military Drawing Device.

2

Refer to Evaluation Board section.

CAUTION

1

2

–55°C to +125°C 8-Lead Cerdip Q-8

SOIC Evaluation Board, G = +2

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8001 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. C

–3–

AD8001

5ns400mV

LeCROY 9210

PULSE

GENERATOR

909V

+V

S

RL = 100V

–V

S

50V

V

IN

0.1mF

0.001mF

AD8001

0.1mF

0.001mF

TR/TF = 350ps

V

OUT

TO

TEKTRONIX
CSA 404 COMM.
SIGNAL
ANALYZER

V

IN

HP8133A

PULSE

GENERATOR

TR/TF = 50ps

806V

50V

806V

+V

S

AD8001

–V

S

0.001mF

0.1mF

0.1mF

0.001mF

V

TO

OUT

TEKTRONIX
CSA 404 COMM.
SIGNAL
ANALYZER

RL = 100V

Figure 4. Test Circuit , Gain = +2

Figure 5. 1 V Step Response, G = +2

Figure 7. 2 V Step Response, G = +2

Figure 8. Test Circuit, Gain = +1

0.5V

5ns

Figure 6. 2 V Step Response, G = +1

–4–

Figure 9. 100 mV Step Response, G = +1

REV. C

9

VALUE OF FEEDBACK RESISTOR (RF) – V

–3dB BANDWIDTH – MHz

1000

0

1000

600

200

600

400

500

800

900800700

R

PACKAGE

N

PACKAGE

VS = 65V
R

L

= 100V

G = +2

–50

–70

–100

100k 100M10M1M10k

–80

–90

–60

FREQUENCY – Hz

HARMONIC DISTORTION – dBc

V

OUT

= 2V p-p
RL = 100V
G = +2

65V SUPPLIES

2ND HARMONIC

3RD HARMONIC

0.08

0.01

–0.01

0

0.00

0.00

0.02

0.02

0.04

0.06

100

IRE

DIFF GAIN – %

DIFF PHASE – Degrees

–0.02

G = +2
RF = 806V

1 BACK TERMINATED

LOAD (150V)

2 BACK TERMINATED

LOADS (75V)

1 AND 2 BACK TERMINATED

LOADS (150V AND 75V)

VS = 65V

6

G = +2

3

= 100V

R

L

0

–3

GAIN – dB

–6

–9

–12

10M 100M 1G

VS = 65V
R

= 1kV

FB

FREQUENCY – Hz

R

FB

AD8001

= 820V

Figure 10. Frequency Response, G = +2

0.1

0
–0.1

–0.2

–0.3

G = +2
RL = 100V

–0.4

–0.5

OUTPUT – dB

–0.6

–0.7

–0.8

–0.9

= 50mV

V

IN

1M 10M 100M

FREQUENCY – Hz

RF = 698V

RF = 750V

RF =
649V

Figure 11. 0.1 dB Flatness, R Package (for N Package Add

50

Ω

to RF)

–50

65V SUPPLIES

–60

–70

–80

V

= 2V p-p

OUT

RL = 1kV
G = +2

2ND HARMONIC

Figure 13. –3 dB Bandwidth vs. R

F

Figure 14. Distortion vs. Frequency, RL = 100

Ω

–90

HARMONIC DISTORTION – dBc

–100

–110

Figure 12. Distortion vs. Frequency, RL = 1 k

REV. C

100k 100M10M1M10k

3RD HARMONIC

FREQUENCY – Hz

Ω

Figure 15. Differential Gain and Differential Phase

–5–

AD8001

1000

900

500

600

700

1100

800

900

800

700

600

1000

VALUE OF FEEDBACK RESISTOR (RF) – V

–3dB BANDWIDTH – MHz

N PACKAGE

R PACKAGE

V

IN

= 50mV

R

L

= 100V

G = +1

FREQUENCY – Hz

10k 100k 1M 10M 100M

–40

–70

–100

–80

–90

–60

–50

DISTORTION – dBc

RL = 100V
G = +1
V

OUT

= 2V p-p

2ND HARMONIC

3RD HARMONIC

3

–9

–24

1M 100M10M

–12

–15

–6

–3

FREQUENCY – Hz

–27

0

–18

–21

OUTPUT – dBV

RL = 100V
G = +1

5

0

–5

–10

–15

GAIN – dB

–20

–25

–30

–35

100M

VIN = –26dBm
RF = 909V

FREQUENCY – Hz

1G 3G

Figure 16. Frequency Response, G = +1

+1

0

–1

–2

–3

–4

–5

OUTPUT – dB

–6

–7

–8

–9

G = +1
RL = 100V

= 50mV

V

IN

10M 1G100M2M

FREQUENCY – Hz

RF = 649V

RF = 953V

Figure 17. Flatness, R Package, G = +1 (for N Package Add
100

Ω

to RF)

–40

–50

–60

G = +1
R

= 1kV

L

V

OUT

= 2V p-p

Figure 19. –3 dB Bandwidth vs. RF, G = +1

Figure 20. Distortion vs. Frequency, RL = 100

Ω

–70

–80

DISTORTION – dBc

–90

–100

–110

Figure 18. Distortion vs. Frequency, RL = 1 k

100k 100M10M1M10k

2ND HARMONIC

FREQUENCY – Hz

3RD HARMONIC

Ω

Figure 21. Large Signal Frequency Response, G = +1

–6–

REV. C

45

2.2

0.4
100

0.8

0.6

–40–60

1.0

1.2

1.4

1.6

1.8

2.0

806040200–20

INPUT OFFSET VOLTAGE – mV

JUNCTION TEMPERATURE – 8C

DEVICE #1

DEVICE #2

DEVICE #3

–60

JUNCTION TEMPERATURE – 8C

SUPPLY CURRENT

– mA

4.4

4.8

5.8

–40 –20 0 20 40 60 80 100 120 140

5.2

5.4

4.6

5.6

5.0

VS = 65V

125

85

100

95

90

–40–60

105

100

110

115

120

806040200–20

JUNCTION TEMPERATURE – 8C

SHORT CIRCUIT CURRENT – mA

SOURCE I

SC

| SINK ISC |

40
35
30
25
20
15
10

5

GAIN – dB

0

–5
–10
–15
–20
–25

G = +100

G = +10

RF = 470V

RL = 100V

1M 10M 100M

FREQUENCY – Hz

= 1000V

R

F

AD8001

1G

Figure 22. Frequency Response, G = +10, G = +100

3.35

3.25

3.15

3.05

2.95

2.85

OUTPUT SWING – Volts

2.75

2.65

2.55

+V

OUT

+V

OUT

–40–60

JUNCTION TEMPERATURE – 8C

Figure 23. Output Swing vs. Temperature

5

4

3

– mA

2

1

0

–1

INPUT BIAS CURRENT

–2

REV. C

–3

–4

–60

–40 –20 0 20 40 60 80 100 120 140

JUNCTION TEMPERATURE – 8C

Figure 24. Input Bias Current vs. Temperature

| –V

| –V

OUT

OUT

–IN

+IN

Figure 25. Input Offset vs. Temperature

RL = 150V
VS = 65V

|

RL = 50V
VS = 65V

|

100

806040200–20

Figure 26. Supply Current vs. Temperature

Figure 27. Short Circuit Current vs. Temperature

–7–

AD8001

–60

JUNCTION TEMPERATURE – 8C

PSRR

– dB

–52.5

–40 –20 0 20 40 60 80 100

–62.5

–60.0

–57.5

–67.5

–75.0

–72.5

–65.0

–77.5

–70.0

–55.0

+PSRR

–PSRR

3V SPAN

CURVES ARE FOR WORST
CASE CONDITION WHERE
ONE SUPPLY IS VARIED
WHILE THE OTHER IS
HELD CONSTANT.

6

5

– kV

4

3

–T

2

TRANSRESISTANCE

1

0
–60

Z

+T

Z

–40 –20 0 20 40 60 80 100 120 140

JUNCTION TEMPERATURE – 8C

VS = 65V

= 150V

R

L

= 62.5V

V

OUT

Figure 28. Transresistance vs. Temperature

100

INVERTING CURRENT VS = 65V

10

NONINVERTING CURRENT VS = 65V

NOISE VOLTAGE – nV/√Hz

1

10

VOLTAGE NOISE VS = 65V

100 10k1k

FREQUENCY – Hz

Figure 29. Noise vs. Frequency

100k

100

10

1

1k

100

10

– V

OUT

R

1

0.1

0.01
100k

FREQUENCY – Hz

G = +2
R

= 909V

F

1M10k

100M10M

Figure 31. Output Resistance vs. Frequency

1

0

–1

–2

–3

G = –1
R

= 100V

–4

–5

OUTPUT – dB

NOISE CURRENT – pA/√Hz

–6

–7

–8

–9

L

V

= 50mV

IN

1M 10M 1G100M

FREQUENCY – Hz

RF = 649V

RF = 750V

RF = 576V

Figure 32. –3 dB Bandwidth vs. Frequency, G = –1

–48

–49

–50

–51

– dB

–52

CMRR

–53

–54

–55

–56

–60

–40 –20 0 20 40 60 80 100 120 140

JUNCTION TEMPERATURE – 8C

Figure 30. CMRR vs. Temperature

–CMRR

+CMRR

2.5V SPAN

–8–

Figure 33. PSRR vs. Temperature

REV. C

–10

3–4–5 210–1–2–3 54

100

20

0

10

80

90

70

60

50

40

30

100

20

0

10

80

90

70

60

50

40

30

COUNT

PERCENT

INPUT OFFSET VOLTAGE – mV

3 WAFER LOTS
COUNT = 895
MEAN = 1.37
STD DEV = 1.13
MIN = –2.45
MAX = +4.69

FREQ DIST

CUMULATIVE

–20

–30

CMRR – dB

–40

–50

300k 100M10M1M

V

IN

910V
150V

62V

910V

51V

150V

FREQUENCY – Hz

Figure 34. CMRR vs. Frequency

AD8001

30

20

CURVES ARE FOR WORST
CASE CONDITION WHERE

10

ONE SUPPLY IS VARIED

V

OUT

PSRR – dB

1G

WHILE THE OTHER IS
HELD CONSTANT.

0

–10

–20

–30

–40

–50

–60

–PSRR

1M 10M 100M

+PSRR

FREQUENCY – Hz

Figure 37. PSRR vs. Frequency

+PSRR

–PSRR

RF = 909V
G = +2

1G

1

0

–1

–2

–3

G = –2
R

= 100V

–4

L

V

= 50mV

IN

–5

OUTPUT – dB

–6

–7

–8

–9

1M 10M 1G100M

rms

RF = 649V

FREQUENCY – Hz

RF = 750V

R

F

= 549V

Figure 35. –3 dB Bandwidth vs. Frequency, G = –2

Figure 38. 2 V Step Response, G = –1

REV. C

Figure 36. 100 mV Step Response, G = –1

Figure 39. Input Offset Voltage Distribution

–9–

AD8001

FREQUENCY – Hz

1M

10

100k

1M 1G100M10M

100

100k

10k

1k

T

Z

– V

OUTPUT – dB

0.1

0

–0.9

1M 10M 100M

–0.1

–0.2
–0.3

–0.4

–0.5

FREQUENCY – Hz

–0.6

–0.7
–0.8

G = +2

RF =
649V

RF = 698V

RF = 750V

THEORY OF OPERATION

A very simple analysis can put the operation of the AD8001, a
current feedback amplifier, in familiar terms. Being a current
feedback amplifier, the AD8001’s open-loop behavior is ex-

/∆I

pressed as transimpedance, ∆V

, or TZ. The open-loop

O

–IN

transimpedance behaves just as the open-loop voltage gain of a
voltage feedback amplifier, that is, it has a large dc value and
decreases at roughly 6 dB/octave in frequency.

Since the R
gain is just T

is proportional to 1/gM, the equivalent voltage

IN

× g

, where the gM in question is the trans-

Z

M

conductance of the input stage. This results in a low open-loop
input impedance at the inverting input, a now familiar result.
Using this amplifier as a follower with gain, Figure 40, basic
analysis yields the following result.

()

V

O

=×

G

V

IN

=+ = ≈

1

G

Recognizing that G × R

TS GR R

1

R

2

R

<< R1 for low gains, it can be seen to

IN

TS

Z

+× +

()

ZIN

/

150Ω

Rg

IN M

1

the first order that bandwidth for this amplifier is independent
of gain (G). This simple analysis in conjunction with Figure 41
can, in fact, predict the behavior of the AD8001 over a wide
range of conditions.

Achieving and maintaining gain flatness of better than 0.1 dB at
frequencies above 10 MHz requires careful consideration of
several issues.

Figure 41. Transimpedance vs. Frequency

R1

R2

R

IN

V

IN

V

OUT

Figure 40.

Considering that additional poles contribute excess phase at
high frequencies, there is a minimum feedback resistance below
which peaking or oscillation may result. This fact is used to
determine the optimum feedback resistance, R

. In practice

F

parasitic capacitance at Pin 2 will also add phase in the feedback
loop, so picking an optimum value for R

can be difficult. Fig-

F

ure 42 illustrates this problem. Here the fine scale (0.1 dB/div)
flatness is plotted vs feedback resistance. These plots were taken
using an evaluation card which is available to customers so that
these results may readily be duplicated (see Evaluation Board
section).

Figure 42. 0.1 dB Flatness vs. Frequency

Choice of Feedback and Gain Resistors

Because of the above-mentioned relationship between the band­width and feedback resistor, the fine scale gain flatness will, to
some extent, vary with feedback resistance. It, therefore, is
recommended that once optimum resistor values have been
determined, 1% tolerance values should be used if it is desired
to maintain flatness over a wide range of production lots. In
addition, resistors of different construction have different associ­ated parasitic capacitance and inductance. Surface mount resis­tors were used for the bulk of the characterization for this data
sheet. It is not recommended that leaded components be used
with the AD8001.

–10–

REV. C

AD8001

909V

R

SERIES

R

L

500V

I

N

C

L

40

0

0

25

30

10

5

20

15 2010

CL – pF

G = +1

R

SERIES

– V

Printed Circuit Board Layout Considerations

As to be expected for a wideband amplifier, PC board parasitics
can affect the overall closed-loop performance. Of concern are
stray capacitances at the output and the inverting input nodes. If
a ground plane is to be used on the same side of the board as
the signal traces, a space (5 mm min) should be left around the
signal lines to minimize coupling. Additionally, signal lines
connecting the feedback and gain resistors should be short
enough so that their associated inductance does not cause high
frequency gain errors. Line lengths on the order of less than
5 mm are recommended. If long runs of coaxial cable are being
driven, dispersion and loss must be considered.

Power Supply Bypassing

Adequate power supply bypassing can be critical when optimiz­ing the performance of a high frequency circuit. Inductance in
the power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors

(typically greater than 1 µF) will be required to provide the best

settling time and lowest distortion. A parallel combination of

4.7 µF and 0.1 µF is recommended. Some brands of electrolytic
capacitors will require a small series damping resistor ≈4.7 Ω for

optimum results.

DC Errors and Noise

There are three major noise and offset terms to consider in a
current feedback amplifier. For offset errors refer to the equa­tion below. For noise error the terms are root-sum-squared to
give a net output error. In the circuit below (Figure 43) they are
input offset (V
noise gain of the circuit (1 + R

× R

(I

BN

N

input current, which when divided between R

) which appears at the output multiplied by the

IO

), noninverting input current

F/RI

) also multiplied by the noise gain, and the inverting

and RI and sub-

F

sequently multiplied by the noise gain always appears at the

× R

output as I

. The input voltage noise of the AD8001 is a

BN

F

low 2 nV/√Hz. At low gains though the inverting input current

noise times R

is the dominant noise source. Careful layout and

F

device matching contribute to better offset and drift specifica­tions for the AD8001 compared to many other current feedback
amplifiers. The typical performance curves in conjunction with
the equations below can be used to predict the performance of
the AD8001 in any application.

Driving Capacitive Loads

The AD8001 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, best
frequency response is obtained by the addition of a small series
resistance as shown in Figure 44. The accompanying graph
shows the optimum value for R

vs. capacitive load. It is

SERIES

worth noting that the frequency response of the circuit when
driving large capacitive loads will be dominated by the passive
roll-off of R

SERIES

and CL.

Figure 44. Driving Capacitive Loads

Figure 45. Recommended R

vs. Capacitive Load

SERIES

VV

=×+

OUT IO

REV. C






R

R



R

F

±××+

IR

BN N




R

I

R

F

I

BI

I

I

BN

N



R

F




R

I

V

OUT

Figure 43. Output Offset Voltage



±×11

IR

BI F




–11–

AD8001

909V909V

75V

CABLE

75V

75V

V

OUT

#1

V

OUT

#2

+V

S

–V

S

V

IN

0.1mF

0.001mF

AD8001

0.1mF

75V

CABLE

75V

75V

75V

CABLE

+

0.001mF

75V

Communications

Distortion is a key specification in communications applications.
Intermodulation distortion (IMD) is a measure of the ability of
an amplifier to pass complex signals without the generation of
spurious harmonics. The third order products are usually the
most problematic since several of them fall near the fundamen­tals and do not lend themselves to filtering. Theory predicts that
the third order harmonic distortion components increase in
power at three times the rate of the fundamental tones. The
specification of third order intercept as the virtual point where
fundamental and harmonic power are equal is one standard
measure of distortion performance. Op amps used in closed­loop applications do not always obey this simple theory. At a
gain of two, the AD8001 has performance summarized in Fig­ure 46. Here the worst third order products are plotted vs. input
power. The third order intercept of the AD8001 is +33 dBm at
10 MHz.

–45

G = +2

–50

–55

–60

–65

–70

THIRD ORDER IMD – dBc

F1 = 10MHz

= 12MHz

F

2

2F2 – F

1

2F1 – F

2

Operation as a Video Line Driver

The AD8001 has been designed to offer outstanding perfor­mance as a video line driver. The important specifications of

differential gain (0.01%) and differential phase (0.025°) meet

the most exacting HDTV demands for driving one video load.
The AD8001 also drives up to two back terminated loads as
shown in Figure 47, with equally impressive performance (0.01%,

0.07°). Another important consideration is isolation between

loads in a multiple load application. The AD8001 has more

than 40 dB of isolation at 5 MHz when driving two 75 Ω back

terminated loads.

Figure 47. Video Line Driver

–75

–80

–6–8 4 5–3

–1

INPUT POWER – dBm

3–7

210–4–5 6–2

Figure 46. Third Order IMD; F1 = 10 MHz, F2 = 12 MHz

–12–

REV. C

AD8001

Driving A-to-D Converters

The AD8001 is well suited for driving high speed analog-to­digital converters such as the AD9058. The AD9058 is a dual
8-bit 50 MSPS ADC. In the circuit below the AD8001 is shown
driving the inputs of the AD9058, which are configured for 0 V
to +2 V ranges. Bipolar input signals are buffered, amplified

(–2×), and offset (by +1.0 V) into the proper input range of the

ADC. Using the AD9058’s internal +2 V reference connected

ENCODE

ENCODE A ENCODE B

8

–V

REF A

38

–V

REF B

6

A

IN A

2

+V

3

+V

43

+V

40

A

IN B

1

COMP

IN A

60.5V

ANALOG

IN B

60.5V

324VANALOG

1.3kV

–2V

0.1mF

1.3kV

324V

RZ1, RZ2 = 2,000V SIP (8-PKG)

649V

AD8001

AD707

20kV

649V

AD8001

20V

20kV

0.1mF

20V

0.1mF

to both ADCs as shown in Figure 48 reduces the number of
external components required to create a complete data

acquisition system. The 20 Ω resistors in series with ADC in-

puts are used to help the AD8001s drive the 10 pF ADC input
capacitance. The AD8001 only adds 100 mW to the power
consumption while not limiting the performance of the circuit.

0.1mF
RZ1

RZ2

1N4001

–5V

1kV

10pF

+5V

8

74ACT 273

8

74ACT 273

CLOCK

10

INT

REF A

REF B

4,19, 21 25, 27, 42

AD9058

(J-LEAD)

36

D0A (LSB)

D

7A

D

0B

D

7B

+V

(MSB)

(LSB)

(MSB)

–V

50V

S

S

74ACT04

5, 9, 22,
24, 37, 41

18
17
16
15
14
13
12
11

28
29
30
31
32
33
34
35

7, 20,
26, 39

0.1mF

REV. C

Figure 48. AD8001 Driving a Dual A-to-D Converter

–13–

AD8001

Layout Considerations

The specified high speed performance of the AD8001 requires
careful attention to board layout and component selection.
Proper R

design techniques and low parasitic component selec-

F

tion are mandatory.

The PCB should have a ground plane covering all unused por­tions of the component side of the board to provide a low im­pedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.

Chip capacitors should be used for supply bypassing (see Figure

49). One end should be connected to the ground plane and the
other within 1/8-inch of each power pin. An additional large

R

F

+V

+V

R

IN

G

R

T

R

S

S

R

O

OUT

–V

S

S

–V

S

C1

0.1mF

C2

0.1mF

Inverting Configuration Supply Bypassing

Figure 49. Inverting and Noninverting Configurations for Evaluation Boards

(4.7 µF–10 µF) tantalum electrolytic capacitor should be con-

nected in parallel, but not necessarily so close, to supply current
for fast, large-signal changes at the output.

The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the invert­ing input will significantly affect high speed performance.

Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with a

characteristic impedance of 50 Ω or 75 Ω and be properly termi-

nated at each end.

R

F

+V

C3
10mF

C4
10mF

R

G

IN

R

T

S

R

O

OUT

–V

S

Noninverting Configuration

Table I. Recommended Component Values

AD8001AN (DIP) AD8001AR (SOIC) AD8001ART (SOT-23-5)

Gain Gain Gain

Component –1 +1 +2 +10 +100 –1 +1 +2 +10 +100 –1 +1 +2 +10 +100

R

(Ω) 649 1050 750 470 1000 604 953 681 470 1000 845 1000 768 470 1000

F

(Ω) 649 750 51 10 604 681 51 10 845 768 51 10

R

G

(Nominal) (Ω) 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9

R

O

(Ω)0 0 0

R

S

(Nominal) (Ω) 54.9 49.9 49.9 49.9 49.9 54.9 49.9 49.9 49.9 49.9 54.9 49.9 49.9 49.9 49.9

R

T

Small Signal 340 880 460 260 20 370 710 440 260 20 240 795 380 260 20

BW (MHz)

0.1 dB Flatness 105 70 105 130 100 120 110 300 145
(MHz)

–14–

REV. C

AD8001

Evaluation Board

An evaluation board for the AD8001 is available that has been
carefully laid-out and tested to demonstrate that the specified
high speed performance of the device can be realized. For

Figure 50. Evaluation Board
Silkscreen (Top)

Figure 51. Evaluation Board Layout
(Solder Side)

ordering information, please refer to the Ordering Guide. The
layout of the evaluation board can be used as shown or serve as
a guide for a board layout.

Figure 52. Evaluation Board Layout
(Component Side)

REV. C

–15–

AD8001

0.1181 (3.00)

0.1102 (2.80)

PIN 1

0.0669 (1.70)

0.0590 (1.50)

0.1181 (3.00)

0.1024 (2.60)

1 3

4 5

0.0748 (1.90)
BSC

0.0374 (0.95) BSC

2

0.0079 (0.20)

0.0031 (0.08)

0.0217 (0.55)

0.0138 (0.35)

108

08

0.0197 (0.50)

0.0138 (0.35)

0.0059 (0.15)

0.0019 (0.05)

0.0512 (1.30)

0.0354 (0.90)

SEATING
PLANE

0.0571 (1.45)

0.0374 (0.95)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

PIN 1

0.210

(5.33)

MAX

0.160 (4.06)

0.115 (2.93)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0098 (0.25)

0.0040 (0.10)
SEATING

0.430 (10.92)

0.348 (8.84)

8

14

0.100 (2.54)

0.022 (0.558)

0.014 (0.356)

0.1 968 (5.00)

0.1 890 (4.80)

85

0.0500 (1.27)

PLANE

8-Lead Plastic DIP

(N-8)

5

0.280 (7.11)

0.240 (6.10)

BSC

0.060 (1.52)

0.015 (0.38)

0.070 (1.77)

0.045 (1.15)

0.130
(3.30)
MIN

SEATING
PLANE

8-Lead Plastic SOIC

(SO-8)

0.2440 (6.20)

0.2284 (5.80)

41

BSC

0.0192 (0.49)

0.0138 (0.35)

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0075 (0.19)

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

88
08

0.195 ( 4.95)

0.115 (2.93)

0.0196 (0.50)

0.0099 (0.25)

0.0500 (1.27)

0.0160 (0.41)

3 458

8-Lead Cerdip

(Q-8)

0.005 (0.13)

PIN 1

0.200.(5.08)
MAX

0.200 (5.08)

0.125 (3.18)

MIN

0.023 (0.58)

0.014 (0.36)

0.055 (1.4)
MAX

85

1

4

0.100 (2.54) BSC

0.405 (10.29) MAX

0.070 (1.78)

0.030 (0.76)

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

SEATING
PLANE

0.320 (8.13)

0.290 (7.37)

15°

0°

5-Lead Plastic Surface Mount (SOT-23)

(RT-5)

C1886c–0–12/99

0.015 (0.38)

0.008 (0.20)

–16–

PRINTED IN U.S.A.

REV. C