Datasheet AD8000 Datasheet (Analog Devices)

1.5 GHz Ultrahigh Speed Op Amp

FEATURES

High speed

1.5 GHz, −3 dB bandwidth (G = +1) 650 MHz, full power bandwidth (G = +2, V Slew rate: 4100 V/µs

0.1% settling time: 12 ns

Excellent video specifications

0.1 dB flatness: 170 MHz Differential gain: 0.02%

Differential phase: 0.01° Output overdrive recovery: 22 ns Low noise: 1.6 nV/√Hz input voltage noise Low distortion over wide bandwidth

75 dBc SFDR @ 20 MHz

62 dBc SFDR @ 50 MHz Input offset voltage: 1 mV typ High output current: 100 mA Wide supply voltage range: 4.5 V to 12 V Supply current: 13.5 mA Power-down mode

APPLICATIONS

Professional video High speed instrumentation Video switching IF/RF gain stage CCD imaging

GENERAL DESCRIPTION

The AD8000 is an ultrahigh speed, high performance, current feedback amplifier. Using ADI’s proprietary eXtra Fast Complementary Bipolar (XFCB) process, the amplifier can achieve a small signal bandwidth of 1.5 GHz and a slew rate of 4100 V/µs.

The AD8000 has low spurious-free dynamic range (SFDR) of 75 dBc @ 20 MHz and input voltage noise of 1.6 nV/√Hz. The AD8000 can drive over 100 mA of load current with minimal distortion. The amplifier can operate on +5 V to ±6 V. These specifications make the AD8000 ideal for a variety of applications, including high speed instrumentation.

With a differential gain of 0.02%, differential phase of 0.01°, and

0.1 dB flatness out to 170 MHz, the AD8000 has excellent video specifications, which ensure that even the most demanding video systems maintain excellent fidelity.

= 2 V p-p)

O

AD8000

CONNECTION DIAGRAMS

1POWER DOWN 2FEEDBACK 3–IN 4+IN

Figure 1. 8-Lead AD8000, 3 mm × 3 mm LFCSP (CP-8-2)

FEEDBACK 1

2

–IN +IN 3

4

–V

S

Figure 2. 8-Lead AD8000 SOIC/EP (RD-8-1)

3

VS = ±5V

2

= 150Ω

R

L

= 2V p-p

V

OUT

1

0

–1

–2

–3

–4

NORMALIZED GAIN (dB)

–5

–6

–7

1 10010 1000

Figure 3. Large S ignal Frequenc y Respons e

The AD8000 power-down mode reduces the supply current to

1.3 mA. The amplifier is available in a tiny 8-lead LFCSP package, as well as in an 8-lead SOIC package. The AD8000 is rated to work over the extended industrial temperature range (−40°C to +125°C). A triple version of the AD8000 (AD8003) is underdevelopment.

AD8000

NC = NO CONNECT

AD8000

NC = NO CONNECT

FREQUENCY (MHz)

7

5

G = +2, R

POWER DOWN8 +V

S

OUTPUT6 NC

= 432Ω

F

8+V

S

7 OUTPUT 6NC 5–V

S

05321-001

05321-002

05321-003

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

AD8000

SPECIFICATIONS WITH ±5 V SUPPLY

At TA = 25°C, VS = ±5 V, RL = 150 Ω, Gain = +2, RF = RG = 432 Ω, unless otherwise noted. Exposed paddle should be connected to ground.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, VO = 0.2 V p-p, SOIC/LFCSP 1580/1350 MHz G = +2, VO = 2 V p-p, SOIC/LFCSP 650/610 MHz Bandwidth for 0.1 dB Flatness VO = 2 V p-p, SOIC/LFCSP 190/170 MHz Slew Rate G = +2, VO = 4 V step 4100 V/µs Settling Time to 0.1% G = +2, VO = 2 V step 12 ns

NOISE/HARMONIC PERFORMANCE

Second/Third Harmonic VO = 2 V p-p, f = 5 MHz, LFCSP only 86/89 dBc Second/Third Harmonic VO = 2 V p-p, f = 20 MHz, LFCSP only 75/79 dBc Input Voltage Noise f = 100 kHz 1.6 nV/√Hz Input Current Noise f = 100 kHz, −IN 26 pA/√Hz f = 100 kHz, +IN 3.4 pA/√Hz Differential Gain Error NTSC, G = +2 0.02 % Differential Phase Error NTSC, G = +2 0.01 Degree

DC PERFORMANCE

Input Offset Voltage 1 10 mV Input Offset Voltage Drift 11 µV/°C Input Bias Current (Enabled) +I

−I Transimpedance 570 890 1600 kΩ

INPUT CHARACTERISTICS

Noninverting Input Impedance 2/3.6 MΩ/pF Input Common-Mode Voltage Range −3.5 to +3.5 V Common-Mode Rejection Ratio VCM = ±2.5 V −52 −54 −56 dB Overdrive Recovery G = +1, f = 1 MHz, triangle wave 30 ns

POWER DOWN PIN

Power-Down Input Voltage Power-down < +VS – 3.1 V Enabled > +VS – 1.9 V Turn-Off Time

Turn-On Time

Input Bias Current

Enabled −1.1 +0.17 +1.4 µA Power-Down −300 −235 −160 µA

OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 100 Ω ±3.7 ±3.9 V Output Voltage Swing RL = 1 kΩ ±3.9 ±4.1 V Linear Output Current VO = 2 V p-p, second HD < −50 dBc 100 mA Overdrive Recovery G = + 2, f = 1 MHz, triangle wave 45 ns G = +2, VIN = 2.5 V to 0 V step 22 ns

POWER SUPPLY

Operating Range 4.5 12 V Quiescent Current 12.7 13.5 14.3 mA Quiescent Current (Power-Down) 1.1 1.3 1.65 mA Power Supply Rejection Ratio −PSRR/+PSRR −56/−61 −59/−63 dB

B

50% of power-down voltage to 10% of V

50% of power-down voltage to 90% of V

final, VIN = 0.3 V p-p

OUT

final, VIN = 0.3 V p-p

OUT

−5 +4 µA

−3 +45 µA

150 ns

300 ns

Rev. 0 | Page 3 of 20

AD8000

SPECIFICATIONS WITH +5 V SUPPLY

At TA = 25°C, VS = +5 V, RL = 150 Ω, Gain = +2, RF = RG = 432 Ω, unless otherwise noted. Exposed paddle should be connected to ground.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth G = +1, VO = 0.2 V p-p 980 MHz G = +2, VO = 2 V p-p 477 MHz G = +10, VO = 0.2 V p-p 328 MHz Bandwidth for 0.1 dB Flatness VO = 0.2 V p-p 136 MHz V Slew Rate G = +2, VO = 2 V step 2700 V/µs Settling Time to 0.1% G = +2, VO = 2 V step 16 ns

NOISE/HARMONIC PERFORMANCE

Second/Third Harmonic VO = 2 V p-p, 5 MHz, LFCSP only 71/71 dBc Second/Third Harmonic VO = 2 V p-p, 20 MHz, LFCSP only 60/62 dBc Input Voltage Noise f = 100 kHz 1.6 nV/√Hz Input Current Noise f = 100 kHz, −IN 26 pA/√Hz f = 100 kHz, +IN 3.4 pA/√Hz Differential Gain Error NTSC, G = +2 0.01 % Differential Phase Error NTSC, G = +2 0.06 Degree

DC PERFORMANCE

Input Offset Voltage 1.3 10 mV Input Offset Voltage Drift 18 µV/°C Input Bias Current (Enabled) +I

−I

Transimpedance 440 800 1500 kΩ

INPUT CHARACTERISTICS

Noninverting Input Impedance 2/3.6 MΩ/pF Input Common-Mode Voltage Range 1.5 to 3.6 V Common-Mode Rejection Ratio VCM = ±2.5 V −51 −52 −54 dB Overdrive Recovery G = +1, f = 1 MHz, triangle wave 60 ns

POWER DOWN PIN

Power-Down Input Voltage Power-down < +VS − 3.1 V Enable > +VS − 1.9 V Turn-Off Time

Turn-On Time

Input Current

Enabled −1.1 +0.17 +1.4 µA Power-Down −50 −40 −30 µA

OUTPUT CHARACTERISTICS

Output Voltage Swing RL = 100 Ω 1.1 to 3.9 1.05 to 4.1 V R Linear Output Current VO = 2 V p-p, second HD < −50 dBc 70 mA Overdrive Recovery G = +2, f = 100 kHz, triangle wave 65 ns

POWER SUPPLY

Operating Range 4.5 12 V Quiescent Current 11 12 13 mA Quiescent Current (Power-Down) 0.7 0.95 1.25 mA Power Supply Rejection Ratio −PSRR/+PSRR −55/−60 −57/−62 dB

= 2 V p-p 136 MHz

O

B

50% of power-down voltage to 10% of V

final, VIN = 0.3 V p-p

OUT

50% of power-down voltage to 90% of V

= 1 kΩ 1 to 3.1 0.85 to 4.15 V

L

final, VIN = 0.3 V p-p

OUT

−5 +3 µA

−1 +45 µA

200 ns

300 ns

Rev. 0 | Page 4 of 20

AD8000

(

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage 12.6 V Power Dissipation See Figure 4 Common-Mode Input Voltage −VS − 0.7 V to +VS + 0.7 V Differential Input Voltage

Exposed Paddle Voltage −V

±V

S

The power dissipated in the package (P quiescent power dissipation and the power dissipated in the die due to the AD8000 drive at the output. The quiescent power is the voltage between the supply pins (V current (I

= Quiescent Power + (Tot a l Dri v e P o w er – Load Power)

P

D

Storage Temperature −65°C to +125°C Operating Temperature Range −40°C to +125°C Lead Temperature Range

300°C

D

(Soldering, 10 sec)

Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any

RMS output voltages should be considered. If R to −V

, as in single-supply operation, the total drive power is

S

× I

V

S

OUT

the worst case, when V

other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute

D

maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, θJA is specified for device soldered in the circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θ

JA

SOIC-8 80 30 °C/W 3 mm × 3 mm LFCSP 93 35 °C/W

θ

JC

Unit

In single-supply operation with R

= VS/2.

is V

OUT

Airflow increases heat dissipation, effectively reducing θ Also, more metal directly in contact with the package leads and exposed paddle from metal traces, through holes, ground, and power planes reduces θ

Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the exposed paddle SOIC (80°C/W) and the LFCSP (93°C/W) package on a JEDEC standard 4-layer board. θ

Maximum Power Dissipation

The maximum safe power dissipation for the AD8000 is limited by the associated rise in junction temperature (T

) on the die. At

J

approximately 150°C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8000. Exceeding a junction temperature of 175°C for an extended period of time can result in changes in silicon devices, potentially causing degradation or loss of functionality.

MAXIMUM POWER DISSIPATION (W)

Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

).

S

⎛

V

()

⎜

IVP

SS

⎜ ⎝

OUTS

×+×=

R

2

L

. If the rms signal levels are indeterminate, consider

= VS/4 for RL to midsupply.

OUT

2

)

4

/V

()

3.0

2.5

2.0

1.5

1.0

0.5

0

–40

–30 –20 –10 0 10 20 40 8030 50 60 70 10090 120110

S

+×=

IVP

SS

R

L

.

JA

values are approximations.

JA

SOIC

LFCSP

AMBIENT TEMPERATURE (°C)

) is the sum of the

D

) times the quiescent

S

⎞ ⎟

⎟ ⎠

L

2

V

OUT

–

R

L

is referenced

L

referenced to −VS, worst case

.

JA

05321-063

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation and loss of functionality.

Rev. 0 | Page 5 of 20

AD8000

TYPICAL PERFORMANCE CHARACTERISTICS

3

VS = ±5V R

= 150Ω

2

L

= 200mV p-p

V

OUT

1

0

–1

–2

–3

–4

NORMALIZED GAIN (dB)

–5

–6

–7

G = +10, R

= 432Ω, RG = 432Ω

G = +2, R

F

= 357Ω, RG = 40.2Ω

F

101 100 1000

FREQUENCY (MHz)

Figure 5. Small Signal Frequency Response vs. Various Gains

G = +1, R

= 432Ω

F

05321-006

9

6

3

GAIN (dB)

VS = ±5V

0

G = +2 R

= 150Ω

L

V

= 200mV p-p

OUT

LFCSP

–3

101 100 1000

FREQUENCY (MHz)

Figure 8. Small Signal Frequency Respon se vs. R

R

F

= 432Ω

R

= 487Ω

F

RF = 392Ω

05321-011

F

3

2

1

0

–1

–2

–3

–4

NORMALIZED GAIN (dB)

–5

–6

–7

VS = ±5V

= 150Ω

R

L

= 200mV p-p

V

OUT

G = –10, R

= 432Ω, RG = 43.2Ω

F

G = –2, R

= 432Ω, RG = 215Ω

F

101 100 1000

FREQUENCY (MHz)

G = –1, R

= RG = 249Ω

F

Figure 6. Small Signal Frequency Response vs. Various Gains

3

VS = ±5V

2

= 150Ω

R

L

= 2V p-p

V

OUT

1

0

–1

–2

–3

–4

NORMALIZED GAIN (dB)

–5

–6

–7

1 10010 1000

G = +4, R

G = +10, R

= 357Ω, RG = 121Ω

F

FREQUENCY (MHz)

= 432Ω

G = +1, R

F

= 357Ω, RG = 40.2Ω

= RG = 432Ω

G = +2, R

F

Figure 7. Large Signal Frequency Response vs. Various Gains

05321-007

05321-008

9

RF = 392Ω

6

RF = 432Ω

3

GAIN (dB)

VS = ±5V

0

G = +2 R

= 150Ω

L

V

= 2V p-p

OUT

LFCSP

–3

101 100 1000

FREQUENCY (MHz)

RF = 487Ω

Figure 9. Large S ignal Frequenc y Respons e vs. R

1000

100

10

TRANSIMPEDANCE (kΩ)

1

0.1

0.1 1 10 100 1000 10000

VS = ±5V

= 100Ω

R

L

TZ

FREQUENCY (MHz)

PHASE

Figure 10. Transimpedance and Phase vs. Frequency

05321-012

F

200

150

100

50

PHASE (Degrees)

0

50

100

05321-027

Rev. 0 | Page 6 of 20

AD8000

3

RL = 1kΩ G = +1

2

= 432Ω

R

F

V

= 200mV p-p

1

OUT

LFCSP

0

–1

–2

GAIN (dB)

–3

–4

–5

–6

–7

0.1 1 10 100 1000

VS = +5V, RS = 0Ω

= ±5V, RS = 0Ω

V

S

= +5V, RS = 50Ω

V

S

= ±5V, RS = 50Ω

V

S

FREQUENCY (MHz)

Figure 11. Small Signal Frequency Response vs. Supply Voltage

05321-010

9

6

3

GAIN (dB)

VS = ±5V

0

G = +2 R

= 150Ω

L

V

= 200mV p-p

OUT

LFCSP

–3

101 100 1000

FREQUENCY (MHz)

+125°C

+25°C

Figure 14. Small Signal Frequency Response vs. Temperature

–40°C

05321-014

9

RL = 150Ω G = +1

= 432Ω

R

F

6

= 200mV p-p

V

OUT

LFCSP

3

0

GAIN (dB)

–3

–6

–9

101 100 1000

FREQUENCY (MHz)

V

= +5V

S

VS = ±5V

Figure 12. Small Signal Frequency Response vs. Supply Voltage

6.5 VS = ±5V

6.4

= 150Ω

R

L

= 2V p-p

V

OUT

6.3

G = +2

= 432Ω

R

F

6.2

6.1

6.0

GAIN (dB)

5.9

5.8

5.7

5.6

5.5

1 10010

LFCSP

FREQUENCY (MHz)

SOIC

Figure 13. 0.1 dB Flatness

05321-009

05321-013

9

6

+25°C

3

GAIN (dB)

VS = ±5V

0

G = +2 R

= 1kΩ

L

= 200mV p-p

V

OUT

LFCSP

–3

101 100 1000

FREQUENCY (MHz)

+125°C

Figure 15. Small Signal Frequency Response vs. Temperature

9

6

3

GAIN (dB)

VS = ±5V

0

G = +2 R

= 150Ω

L

= 2V p-p

V

OUT

LFCSP

–3

101 100 1000

FREQUENCY (MHz)

–40°C

+25°C

+125°C

Figure 16. Large Signal Frequency Response vs. Temperature

–40°C

05321-015

05321-016

Rev. 0 | Page 7 of 20

AD8000

–

9

V

= 1V p-p

OUT

6

3

V

OUT

= 2V p-p

= 4V p-p

GAIN (dB)

0

VS = ±5V G = +2 R

= 150Ω

L

LFCSP

–3

101 100 1000

FREQUENCY (MHz)

Figure 17. Large Signal Frequency Response vs. Various Outputs

05321-017

40

VS = ±5V V

= 2V p-p

OUT

–50

G = +1 R

= 1kΩ

L

–60

LFCSP

–70

–80

–90

DISTORTION (dBc)

–100

–110

–120

1 10 100

SECOND HD

THIRD HD

FREQUENCY (MHz)

Figure 20. Harmonic Distortion vs. Frequency

05321-042

–40

VS = ±5V

= 2V p-p

V

OUT

–50

G = +1

= 150Ω

R

L

–60

LFCSP

–70

–80

–90

DISTORTION (dBc)

–100

–110

–120

1 10 100

FREQUENCY (MHz)

SECOND HD

Figure 18. Harmonic Distortion vs. Frequency

–40

VS = ±5V G = +10

–50

–60

–70

–80

–90

DISTORTION (dBc)

–100

–110

–120

= 2V p-p

V

OUT

= 1kΩ

R

L

LFCSP

SECOND HD

THIRD HD

1 10 100

FREQUENCY (MHz)

Figure 19. Harmonic Distortion vs. Frequency

THIRD HD

05321-040

05321-039

–20

VS = ±5V

= 4V p-p

V

OUT

–30

G = +1

= 1kΩ

R

L

–40

LFCSP

–50

–60

–70

DISTORTION (dBc)

–80

–90

–100

1 10 100

FREQUENCY (MHz)

SECOND HD

THIRD HD

Figure 21. Harmonic Distortion vs. Frequency

40

VS = ±5V V

= 2V p-p

OUT

G = +2

–50

= 150Ω

R

L

–60

–70

–80

DISTORTION (dBc)

–90

–100

SOIC SECOND HD

1 10 100

LFCSP SECOND HD

LFCSP THIRD HD

SOIC THIRD HD

FREQUENCY (MHz)

Figure 22. Harmonic Distortion vs. Frequency

05321-041

05321-043

Rev. 0 | Page 8 of 20

AD8000

–20

VS = 5V

= 2V p-p

V

–30

OUT

G = +2 R

= 150Ω

L

–40

LFCSP

–50

–60

–70

–80

DISTORTION (dBc)

–90

–100

–110

1 10 100

FREQUENCY (MHz)

SECOND HD

Figure 23. Harmonic Distortion vs. Frequency

THIRD HD

05321-044

–20

VS = ±2.5V

–30

V

= 2V p-p

OUT

G = –1 R

= 150Ω

–40

L

LFCSP

–50

–60

–70

–80

DISTORTION (dBc)

–90

–100

–110

–120

1 10 100

THIRD HD

SECOND HD

FREQUENCY (MHz)

Figure 26. Harmonic Distortion vs. Frequency

05321-048

–20

VS = 5V V

= 2V p-p

OUT

–30

G = +2

= 1kΩ

R

L

LFCSP

–40

–50

–60

–70

DISTORTION (dBc)

–80

–90

–100

1 10 100

THIRD HD

SECOND HD

FREQUENCY (MHz)

Figure 24. Harmonic Distortion vs. Frequency

–20

VS = ±5V

= 2V p-p

V

–30

OUT

G = +2

= 1kΩ

R

–40

L

LFCSP

–50

–60

–70

–80

DISTORTION (dBc)

–90

–100

–110

–120

1 10 100

FREQUENCY (MHz)

SECOND HD

THIRD HD

Figure 25. Harmonic Distortion vs. Frequency

05321-045

05321-047

–20

VS = 5V V

–30

–40

–50

–60

–70

–80

DISTORTION (dBc)

–90

–100

–110

–120

= 2V p-p

OUT

G = –1 R

= 1kΩ

L

LFCSP

THIRD HD

SECOND HD

1 10 100

FREQUENCY (MHz)

Figure 27. Harmonic Distortion vs. Frequency

–40

VS = ±5V V

= 2V p-p

OUT

–50

G = –1 R

= 150Ω

L

LFCSP

–60

–70

–80

DISTORTION (dBc)

–90

–100

–110

1 10 100

FREQUENCY (MHz)

SECOND HD

THIRD HD

Figure 28. Harmonic Distortion vs. Frequency

05321-049

05321-050

Rev. 0 | Page 9 of 20

AD8000

–

40

–50

–60

–70

–80

–90

DISTORTION (dBc)

–100

–110

–120

1 10 100

VS = ±5V V

= 2V p-p

OUT

G = –1 R

= 1kΩ

L

LFCSP

SECOND HD

THIRD HD

FREQUENCY (MHz)

Figure 29. Harmonic Distortion vs. Frequency

05321-051

–10

VS = ±5V

–15

= 2V p-p

V

IN

= 100Ω

R

–20

L

G = +1

–25

= 432Ω

R

–30 –35 –40 –45

PSRR (dB)

–50 –55 –60 –65 –70 –75

F

–PSRR

+PSRR

10.1 10 100

FREQUENCY (MHz)

Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency

05321-021

1k

VS = ±5V V

= 0.2V p-p

IN

R

= 432Ω

F

100

LFCSP

)

Ω

10

1

IMPEDANCE (

G = +1 OR G = +2

FREQUENCY (MHz)

0.01

0.1

10.1 10 100 1000

Figure 30. Output Impedance vs. Frequency

2.65 G = +1

2.60

2.55

2.50

RESPONSE (V)

2.45

2.40

2.35

0 5 10 15 20 25 30 35 40 45 50

TIME (ns)

Figure 31. Small Signal Transient Response

G = +2

VS = 5V

= 432Ω

R

F

R

= 0Ω

S

R

= 100Ω

L

05321-023

05321-072

–25

VS = ±5V V

= 1V p-p

IN

–30

= 100Ω

R

L

LFCSP

–35

–40

–45

CMRR (dB)

–50

–55

–60

–65

10.1 10 100 1000 FREQUENCY (MHz)

Figure 33. Common-Mode Rejection Ratio vs. Frequency

0.175

0.150

0.125

0.100

0.075

0.050

0.025 0

–0.025

RESPONSE (V)

–0.050 –0.075 –0.100 –0.125 –0.150

–0.175

0 5 10 15 20 25 30 35 40 45 50

G = +1

TIME (ns)

Figure 34. Small Signal Transient Response

G = +2

VS = ±5V

= 432Ω

R

F

= 0Ω

R

S

R

= 100Ω

L

05321-031

05321-066

Rev. 0 | Page 10 of 20

AD8000

1.75

1.50

1.25

G = +1

1.00

0.75

0.50

0.25 0

–0.25

RESPONSE (V)

–0.50 –0.75 –1.00 –1.25 –1.50

–1.75

0 5 10 15 20 25 30 35 40 45 50

TIME (ns)

Figure 35. Large Signal Transient Response

G = +2

VS = ±5V

= 432Ω

R

F

R

= 0Ω

S

= 100Ω

R

L

05321-067

5

4

3

VS = ±5V, V

IN

OUT

2

1

0

V

= ±2.5V, V

S

OUT

–1

–2

OUTPUT VOLTAGE (V)

VS = ±2.5V, V

IN

–3

G = +1

–4

= 150Ω

R

L

= 432Ω

R

F

–5

0 200 400 600 800 1000

TIME (ns)

Figure 38. Input Overdrive

05321-019

0.5 V

0.4

0.3

0.2

0.1

–0.1

SETTLING TIME (%)

–0.2

–0.3

–0.4

–0.5

1V

0

t

= 0s

–5 –4 –3 –2 –1 0 1 2 3

IN

V

(V)

CM

Figure 36. Settling Time

6k

G = +2

= 432Ω

R

F

= 150Ω

R

L

5k

4k

3k

SR (V/µs)

2k

1k

LFCSP, V

S

= ±5V

SOIC, V

S

LFCSP, V

SOIC, VS = +5V

= +5V

= ±5V

S

G = +2

5ns/DIV

05321-068

6 5

VS = ±5V, 2 × V

4

VS = ±5V, V

IN

OUT

3 2 1

0 –1 –2

OUTPUT VOLTAGE (V)

–3 –4 –5 –6

VS = ±2.5V, 2 × V

G = +2

= 150Ω

R

L

= 432Ω

R

F

IN

V

= ±2.5V, V

S

OUT

0 200 400 600 800 1000

TIME (ns)

Figure 39. Output Overdrive

100

10

1

INPUT VOLTAGE NOISE (nV/ Hz)

VS = ±5V G = +10

= 432Ω

R

F

= 47.5Ω

R

N

05321-020

0

01234567

(V p-p)

V

OUT

Figure 37. Slew Rate vs. Output Level

05321-018

Rev. 0 | Page 11 of 20

0.1 100k10k100 1k10 1M 10M 100M

FREQUENCY (Hz)

Figure 40. Input Voltage Noise

05321-058

AD8000

1000

100

10

1

INPUT CURRENT NOISE (pA/ Hz)

0.1

VS = ±5V

INVERTING CURRENT NOISE, RF = 1kΩ

NONINVERTING CURRENT NOISE, RF = 432Ω

100k10k100 1k10 1M 10M 100M 1G

FREQUENCY (Hz)

Figure 41. Input Current Noise

05321-055

0

–5

–10

VS = ±5V –15

–20

–25

(µA)

B

I

–30

–35

–40

–45

–50

–5 –4 –3 –2 –1 0 1 2 3 4 5

VS = +5V

VCM (V)

Figure 44. Input Bias Current vs. Common-Mode Voltage

05321-070

20

15

10

V

5

0

(mV)

OS

V

–5

–10

–15

–20

–5 –4 –3 –2 –1 0 1 2 3 4 5

Figure 42. Input V

25

20

15

10

5

A)

µ

0

(

B

I

VS = ±5V

–5

–10

–15

–20

–25

–5 –4 –3 –2 –1 0 1 2 3 4 5

OS

= ±5V

S

VS = +5V

V

(V)

CM

vs. Common-Mode Voltage

VS = +5V

(V)

V

OUT

Figure 43. Input Bias Current vs. Output Voltage

05321-024

05321-069

–5

R

TERM = 50

BACK

= ±5V

V

–10

S

G = +2 P

= –10dBm

OUT

–15

SOIC

–20

–25

–30

S22 (dB)

–35

–40

–45

–50

10 100 1000

FREQUENCY (MHz)

Figure 45. Output Voltage Standing Wave Ratio (S22)

–5

G = +2

G = +10

INPUT RS = 0Ω

= ±5V

V

S

= –10dBm

P

OUT

SOIC

G = +1

–10

–15

–20

–25

–30

S11 (dB)

–35

–40

–45

–50

10 100 1000

FREQUENCY (MHz)

Figure 46. Input Voltage Standing Wave Ratio (S11)

05321-065

05321-064

Rev. 0 | Page 12 of 20

AD8000

T

TEST CIRCUITS

+V

S

10µF

0.1µF

R

F

50Ω

TRANSMISSION

LINE

V

IN

60.4Ω

432Ω

200Ω

Figure 47. CMRR

–V

0.1µF

S

10µF

AD8000

49.9Ω

50Ω

TRANSMISSION

LINE

49.9Ω

05321-028

TRANSMISSION

TERMINATION

50Ω

TRANSMISSION

ERMINATION

50Ω

LINE

50Ω

LINE

VP = VS + V

IN

49.9Ω

AD8000

49.9Ω

R

F

R

432Ω

G

0.1µF

10µF

–V

S

Figure 48. Positive PSRR

+V

S

10µF

0.1µF

AD8000

49.9Ω

R

F

432Ω

R

G

432Ω

49.9Ω

50Ω

TRANSMISSION

LINE

TERMINATION

50Ω

TRANSMISSION

LINE

50Ω

05321-029

49.9Ω

VN =–VS + V

IN

05321-030

Figure 49. Negative PSRR

Rev. 0 | Page 13 of 20

AD8000

V

APPLICATIONS

All current feedback amplifier operational amplifiers are affected by stray capacitance at the inverting input pin. As a practical consideration, the higher the stray capacitance on the inverting input to ground, the higher R minimize peaking and ringing.

CIRCUIT CONFIGURATIONS

Figure 50 and Figure 51 show typical schematics for noninverting and inverting configurations. For current feedback amplifiers, the value of feedback resistance determines the stability and bandwidth of the amplifier. The optimum performance values are shown in Table 5 and should not be deviated from by more than ±10% to ensure stable operation. Figure 8 shows the influence varying R noninverting unity-gain configurations, it is recommended that

of 50 Ω be used, as shown in Figure 50.

an R

S

Table 5 provides a quick reference for the circuit values, gain, and output voltage noise.

+V

S

R

F

0.1µF

R

G

R

V

IN

S

FB

–

AD8000

+

–V

+V

0.1µF

needs to be to

F

has on bandwidth. In

F

10µF

+

V

O

R

L

V

O

+V

S

10µF

FB

–V

S

0.1µF

10µF

+V

+

0.1µF

V

O

R

L

05321-036

R

F

R

IN

G

–

AD8000

+

–V

Figure 51. Inverting Configuration

VIDEO LINE DRIVER

The AD8000 is designed to offer outstanding performance as a video line driver. The important specifications of differential gain (0.02%), differential phase (0.01°), and 650 MHz bandwidth at 2 V p-p meet the most exacting video demands. Figure 52 shows a typical noninverting video driver with a gain of +2.

432Ω

FB

AD8000

+

+V

4.7µF

S

+

0.1µF 75Ω

CABLE

75Ω

0.1µF

75Ω

V

OUT

10µF

+

–V

S

NONINVERTING

05321-035

75Ω

CABLE

IN

75Ω

4.7µF

–V

+

S

Figure 52. Video Line Driver

Figure 50. Noninverting Configuration

Table 5. Typical Values (LFCSP/SOIC)

Gain

Component Values (Ω)

R

F

R

G

−3 dB SS Bandwidth (MHz)

LFCSP SOIC LFCSP SOIC

−3 dB LS Bandwidth (MHz)

Total Output Slew Rate (V/µsec)

Output Noise (nV/√Hz)

Noise Including

Resistors (nV/√Hz)

1 432 --- 1380 1580 550 600 2200 10.9 11.2 2 432 432 600 650 610 650 3700 11.3 11.9 4 357 120 550 550 350 350 3800 10 12 10 357 40 350 365 370 370 3200 18.4 19.9

05321-071

Rev. 0 | Page 14 of 20

AD8000

LOW DISTORTION PINOUT

The AD8000 LFCSP features ADI’s new low distortion pinout. The new pinout lowers the second harmonic distortion and simplifies the circuit layout. The close proximity of the noninverting input and the negative supply pin creates a source of second harmonic distortion. Physical separation of the noninverting input pin and the negative power supply pin reduces this distortion significantly, as seen in Figure 22.

By providing an additional output pin, the feedback resistor can be connected directly across Pin 2 and Pin 3. This greatly simplifies the routing of the feedback resistor and allows a more compact circuit layout, which reduces its size and helps to minimize parasitics and increase stability.

The SOIC also features a dedicated feedback pin. The feedback pin is brought out on Pin 1, which is typically a No Connect on standard SOIC pinouts.

Existing applications that use the standard SOIC pinout can take full advantage of the performance offered by the AD8000. For drop-in replacements, ensure that Pin 1 is not connected to ground or to any other potential because this pin is connected internally to the output of the amplifier. For existing designs, Pin 6 can still be used for the feedback resistor.

EXPOSED PADDLE

The AD8000 features an exposed paddle, which can lower the thermal resistance by 25% compared to a standard SOIC plastic package. The paddle can be soldered directly to the ground plane of the board. Figure 53 shows a typical pad geometry for the LFCSP, the same type of pad geometry can be applied to the SOIC package.

Thermal vias or “heat pipes” can also be incorporated into the design of the mounting pad for the exposed paddle. These additional vias improve the thermal transfer from the package to the PCB. Using a heavier weight copper on the surface to which the amplifier’s exposed paddle is soldered also reduces the overall thermal resistance “seen” by the AD8000.

05321-034

Figure 53. LFCSP Exposed Paddle Layout

PRINTED CIRCUIT BOARD LAYOUT

Laying out the printed circuit board (PCB) is usually the last step in the design process and often proves to be one of the most critical. A brilliant design can be rendered useless because of a poor or sloppy layout. Since the AD8000 can operate into

frequency spectrum, high frequency board layout con-

the R

F

siderations must be taken into account. The PCB layout, signal routing, power supply bypassing, and grounding all must be addressed to ensure optimal performance.

SIGNAL ROUTING

The AD8000 LFCSP features the new low distortion pinout with a dedicated feedback pin and allows a compact layout. The dedicated feedback pin reduces the distance from the output to the inverting input, which greatly simplifies the routing of the feedback network.

To minimize parasitic inductances, ground planes should be used under high frequency signal traces. However, the ground plane should be removed from under the input and output pins to minimize the formation of parasitic capacitors, which degrades phase margin. Signals that are susceptible to noise pickup should be run on the internal layers of the PCB, which can provide maximum shielding.

POWER SUPPLY BYPASSING

Power supply bypassing is a critical aspect of the PCB design process. For best performance, the AD8000 power supply pins need to be properly bypassed.

A parallel connection of capacitors from each of the power supply pins to ground works best. Paralleling different values and sizes of capacitors helps to ensure that the power supply pins “see” a low ac impedance across a wide band of frequencies. This is important for minimizing the coupling of noise into the amplifier. Starting directly at the power supply pins, the smallest value and sized component should be placed on the same side of the board as the amplifier, and as close as possible to the amplifier, and connected to the ground plane. This process should be repeated for the next larger value capacitor. It is recommended for the AD8000 that a 0.1 µF ceramic 0508 case be used. The 0508 offers low series inductance and excellent high frequency performance. The 0.1 µF case provides low impedance at high frequencies. A 10 µF electrolytic capacitor should be placed in parallel with the 0.1 µF. The 10 µf capacitor provides low ac impedance at low frequencies. Smaller values of electrolytic capacitors can be used, depending on the circuit requirements. Additional smaller value capacitors help to provide a low impedance path for unwanted noise out to higher frequencies but are not always necessary.

Rev. 0 | Page 15 of 20

AD8000

Placement of the capacitor returns (grounds), where the capacitors enter into the ground plane, is also important. Returning the capacitors grounds close to the amplifier load is critical for distortion performance. Keeping the capacitors distance short, but equal from the load, is optimal for performance.

In some cases, bypassing between the two supplies can help to improve PSRR and to maintain distortion performance in crowded or difficult layouts. This is as another option to improve performance.

Minimizing the trace length and widening the trace from the capacitors to the amplifier reduce the trace inductance. A series inductance with the parallel capacitance can form a tank circuit, which can introduce high frequency ringing at the output. This additional inductance can also contribute to increased distortion due to high frequency compression at the output. The use of vias should be minimized in the direct path to the amplifier power supply pins since vias can introduce parasitic inductance, which can lead to instability. When required, use multiple large diameter vias because this lowers the equivalent parasitic inductance.

GROUNDING

The use of ground and power planes is encouraged as a method of proving low impedance returns for power supply and signal currents. Ground and power planes can also help to reduce stray trace inductance and to provide a low thermal path for the amplifier. Ground and power planes should not be used under any of the pins of the AD8000. The mounting pads and the ground or power planes can form a parasitic capacitance at the amplifiers input. Stray capacitance on the inverting input and the feedback resistor form a pole, which degrades the phase margin, leading to instability. Excessive stray capacitance on the output also forms a pole, which degrades phase margin.

Rev. 0 | Page 16 of 20

AD8000

Y

R

OUTLINE DIMENSIONS

4.00 (0.157)

3.90 (0.154)

3.80 (0.150)

5.00 (0.197)

4.90 (0.193)

4.80 (0.189)

85

TOP VIEW

6.20 (0.244)

6.00 (0.236)

41

5.80 (0.228)

BOTTOM VIEW

(PINS UP)

2.29 (0.092)

1.27 (0.05) BSC

0.25 (0.0098)

0.10 (0.0039)

COPLANARIT

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012

1.75 (0.069)

1.35 (0.053)

0.51 (0.020)

0.31 (0.012)

0.25 (0.0098)

0.17 (0.0068)

0.50 (0.020)

0.25 (0.010)

8°

1.27 (0.050)

0°

0.40 (0.016)

Figure 54. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]

Narrow Body (RD-8-1)

Dimensions shown in millimeters and (inches)

0.50

0.40

PAD

0.30

4

1

1.60

1.45

1.30

PIN 1

INDICATO

0.90

0.85

0.80

SEATING

PLANE

12° MAX

3.00

BSC SQ

TOP

VIEW

0.30

0.23

0.18

0.80 MAX

0.65TYP

2.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.45

0.50

BSC

0.60 MAX

0.25 MIN

8

EXPOSED

(BOTTOMVIEW)

5

Figure 55. 8-Lead Lead Frame Chip Scale Package [LFCSP]

3 mm × 3 mm Body (CP-8-2)

Dimensions shown in millimeters

1.50 REF

× 45°

PIN 1 INDICATOR

1.90

1.75

1.60

ORDERING GUIDE

Model Minimum Ordering Quantity Temperature Range Package Description Branding Package Option

AD8000YRDZ1 1 –40°C to +125°C 8-Lead SOIC/EP RD-8-1 AD8000YRDZ-REEL1 2,500 –40°C to +125°C 8-Lead SOIC/EP RD-8-1 AD8000YRDZ-REEL71 1,000 –40°C to +125°C 8-Lead SOIC/EP RD-8-1 AD8000YCPZ-R21 250 –40°C to +125°C 8-Lead LFCSP HNB CP-8-2 AD8000YCPZ-REEL1 5,000 –40°C to +125°C 8-Lead LFCSP HNB CP-8-2 AD8000YCPZ-REEL71 1,500 –40°C to +125°C 8-Lead LFCSP HNB CP-8-2

1

Z = Pb-free part.

Rev. 0 | Page 17 of 20

AD8000

NOTES

Rev. 0 | Page 18 of 20

AD8000

NOTES

Rev. 0 | Page 19 of 20

AD8000

NOTES

D05321–0–1/05(0)

Rev. 0 | Page 20 of 20

Datasheet AD8000 Datasheet (Analog Devices)

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

CONNECTION DIAGRAMS

TABLE OF CONTENTS

SPECIFICATIONS WITH ±5 V SUPPLY

SPECIFICATIONS WITH +5 V SUPPLY

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Maximum Power Dissipation

ESD CAUTION

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

APPLICATIONS

CIRCUIT CONFIGURATIONS

VIDEO LINE DRIVER

LOW DISTORTION PINOUT

EXPOSED PADDLE

PRINTED CIRCUIT BOARD LAYOUT

SIGNAL ROUTING

POWER SUPPLY BYPASSING

GROUNDING

OUTLINE DIMENSIONS

ORDERING GUIDE