Datasheet AD7997 Datasheet (Analog Devices)

Page 1

8-Channel, 10- and 12-Bit ADCs with I2C-

Compatible Interface in 20-Lead TSSOP

FEATURES

10- and 12-bit ADC with fast conversion time: 2 µs typ 8 single-ended analog input channels Specified for V Low power consumption Fast throughput rate: up to 188 kSPS Sequencer operation Automatic cycle mode

C®-compatible serial interface supports standard, fast,

and high speed modes Out-of-range indicator/alert function Pin-selectable addressing via AS Shutdown mode: 1 µA max Temperature range: −40°C to +85°C

20-lead TSSOP package See the AD7992 and AD7994 for 2-channel and 4-channel

equivalent devices, respectively

GENERAL DESCRIPTION

The AD7997/AD7998 are 8-channel, 10- and 12-bit, low power, successive approximation ADCs with an I interface. The parts operate from a single 2.7 V to 5.5 V power supply and feature a 2 µs conversion time. The parts contain an 8-channel multiplexer and track-and-hold amplifier that can handle input frequencies up to 11 MHz.

The AD7997/AD7998 provide a 2-wire serial interface that is compatible with I AD7997-0/AD7998-0 and AD7997-1/AD7998-1, and each version allows at least two different I interface on the AD7997-0/AD7998-0 supports standard and

C interface modes. The I2C interface on the AD7997-1/

fast I AD7998-1 supports standard, fast, and high speed I modes.

The AD7997/AD7998 normally remain in a shutdown state while not converting, and power up only for conversions. The conversion process can be controlled using the

by a command mode where conversions occur across I operations or an automatic conversion interval mode selected through software control.

The AD7997/AD7998 require an external reference that should be applied to the REF

. This allows the widest dynamic input range to the ADC.

of 2.7 V to 5.5 V

C-compatible

C interfaces. Each part comes in two versions,

C addresses. The I2C

C interface

CONVST

C write

pin and can be in the range of 1.2 V to

pin,

AD7997/AD7998

FUNCTIONAL BLOCK DIAGRAM

AD7997/AD7998

VIN1

VIN8

AGND

8:1 I/P

MUX

DATA

LOW

DATA

HIGH

HYSTERESIS

T/H

LIMIT

On-chip limit registers can be programmed with high and low limits for the conversion result, and an open-drain, out-ofrange indicator output (ALERT) becomes active when the programmed high or low limits are violated by the conversion result. This output can be used as an interrupt.

PRODUCT HIGHLIGHTS

1. 2 µs conversion time with low power consumption.

2. I

C-compatible serial interface with pin-selectable addresses. Two AD7997/AD7998 versions allow five AD7997/AD7998 devices to be connected to the same serial bus.

3. The parts feature automatic shutdown while not converting

to maximize power efficiency. Current consumption is 1 µA max when in shutdown mode at 3V.

4. Reference can be driven up to the power supply.

5. Out-of-range indicator that can be software disabled or

enabled.

6. One-shot and automatic conversion rates.

7. Registers store minimum and maximum conversion

results.

REF

AGND

10-/12-BIT

SUCCESSIVE

APPROXIMATION

ADC

I2C INTERFACE

Figure 1.

CONFIGURATION

CONVST

CONTROL

LOGIC

OSCILLATOR

CONVERSION

RESULT

ALERT STATUS

CYCLE TIMER

ALERT/BUSY

SCL SDA

03473-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

Page 2

AD7997/AD7998

TABLE OF CONTENTS

AD7997 Specifications..................................................................... 3

AD7998 Specifications..................................................................... 5

C Timing Specifications................................................................ 7

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Pin Function Descriptions.................... 10

Te r m in o l o g y .................................................................................... 11

Typical Performance Characteristics........................................... 12

Circuit Information........................................................................ 15

Converter Operation.................................................................. 15

Typical C o n nec t i o n D iagr a m ................................................... 16

Analog Input ............................................................................... 16

Internal Register Structure ............................................................ 18

Address Pointer Register ...........................................................18

Configuration Register .............................................................. 19

Serial Bus Address...................................................................... 23

Writing to the AD7997/AD7998 .................................................. 24

Writing to the Address Pointer Register for a Subsequent

.............................................................................................. 24

Read

Writing a Single Byte of Data to the Alert Status Register or Cycle Register

Writing Two Bytes of Data to a Limit, Hysteresis, or Configuration Register

Reading Data from the AD7997/AD7998................................... 26

ALERT/BUSY Pin .......................................................................... 27

SMBus ALERT ............................................................................ 27

BUSY ............................................................................................ 27

Placing the AD7997-1/AD7998-1 into High Speed Mode ... 27

The Address Select (AS) Pin ..................................................... 27

Modes of Operation ....................................................................... 28

Mode 1—Using the

.............................................................................. 24

.............................................................. 24

CONVST

Pin ........................................... 28

Conversion Result Register....................................................... 20

Limit Registers ............................................................................ 20

Alert Status Register (CH1 to CH4) ........................................ 21

Cycle Timer Register.................................................................. 22

Sample Delay and Bit Trial Delay............................................. 22

Serial Interface ................................................................................ 23

REVISION HISTORY

9/04—Revision 0: Initial Version

Mode 2 – COMMAND MODE ............................................... 29

Mode 3—Automatic Cycle Interval Mode.............................. 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

Related Parts in I

C-Compatible ADC Product Family........ 31

Rev. 0 | Page 2 of 32

Page 3

AD7997/AD7998

AD7997 SPECIFICATIONS

Temperature range for B version is −40°C to +85°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V; For the AD7997-0, all specifications apply for f T

= T

to T

MIN

MAX

up to 400 kHz; for the AD7997-1, all specifications apply for f

SCL

Table 1.

Parameter B Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE1

Signal to Noise + Distortion (SINAD)2 61 dB min Total Harmonic Distortion (THD) 2 –75 dB max Peak Harmonic or Spurious Noise (SFDR) 2 –76 dB max Intermodulation Distortion (IMD)

Second-Order Terms –86 dB typ

Third-Order Terms –86 dB typ Aperture Delay2 10 ns max Aperture Jitter2 50 ps typ Channel-to-Channel Isolation2 –90 dB typ FIN = 108 Hz, see the Terminology section Full-Power Bandwidth2 11 MHz typ @ 3 dB

2 MHz typ @ 0.1 dB DC ACCURACY

Resolution 10 Bits Integral Nonlinearity Differential Nonlinearity

1, 2

±0.5 LSB max

1, 2

±0.5 LSB max Guaranteed no missed codes to 10 bits

Offset Error2 ±1.5 LSB max ±2.5 LSB max Mode 2 (Command Mode)

Offset Error Match2 ±0.5 LSB max Gain Error

±1.5 LSB max

Gain Error Match2 ±0.5 LSB max

ANALOG INPUT

Input Voltage Range 0 to REF

V DC Leakage Current ±1 µA max Input Capacitance 30 pF typ

REFERENCE INPUT

REFIN Input Voltage Range 1.2 to VDD V min/V max DC Leakage Current ±1 µA max Input Impedance 69 kΩ typ During a conversion

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V Input Low Voltage, V

0.7 (VDD) V min

INH

0.3 (VDD) V max

INL

Input Leakage Current, IIN ±1 µA max VIN = 0 V or VDD Input Capacitance, C Input Hysteresis, V

0.1 (VDD) V min

HYST

10 pF max

up to 3.4 MHz, unless otherwise noted;

SCL

= 10 kHz sine wave for f

from 1.7 MHz to

SCL

3.4 MHz = 1 kHz sine wave for f

fa = 10.1 kHz, fb = 9.9 kHz for f

up to 400 kHz

SCL

from 1.7 MHz

SCL

to 3.4 MHz fa = 1.1 kHz, fb = 0.9 kHz for f

Mode 1 (

CONVST Mode)

up to 400 kHz

SCL

Rev. 0 | Page 3 of 32

Page 4

AD7997/AD7998

Parameter B Version Unit Test Conditions/Comments

LOGIC INPUTS (CONVST)

Input High Voltage, V

2.4 V min VDD = 5 V

INH

2.0 V min VDD = 3 V Input Low Voltage, V

0.8 V max VDD = 5 V

INL

0.4 V max VDD = 3 V Input Leakage Current, IIN ±1 µA max VIN = 0 V or V Input Capacitance, C

10 pF max

LOGIC OUTPUTS (OPEN-DRAIN)

Output Low Voltage, VOL 0.4 V max I

0.6 V max I Floating-State Leakage Current ± 1 µA max Floating-State Output Capacitance

Output Coding Straight (Natural) Binary

CONVERSION RATE See the Modes of Operation section

Conversion Time 2 µs typ Throughput Rate

Mode 1 (Reading after the Conversion) 5 kSPS typ f 21 kSPS typ f 121 kSPS typ f

Mode 2 5.5 kSPS typ f 22 kSPS typ f 147 kSPS typ f POWER REQUIREMENTS

Power-Down Mode, Interface Inactive 1/2 µA max VDD = 3.3 V/5.5 V Power-Down Mode, Interface Active 0.07/0.3 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f

Operating, Interface Inactive 0.06/0.1 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f

Operating, Interface Active 0.15/0.4 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.6/1.1 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f

0.7/1.4 mA typ VDD = 3.3 V/5.5 V, 3.4 MHz f Mode 3 (I2C Inactive, T

x 32) 0.7/1.5 mA max VDD = 3.3 V/5.5 V

CONVERT

Power Dissipation

Fully Operational Operating, Interface Active 0.495/2.2 mW max VDD = 3.3 V/5.5 V, 400 kHz f

1.98/6.05 mW max VDD = 3.3 V/5.5 V, 3.4 MHz f

2.31/7.7 mW typ VDD = 3.3 V/5.5 V, 3.4 MHz f Power Down, Interface Inactive 3.3/11 µW max VDD = 3.3 V/5.5 V

Max/min ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C Hs-Mode SCL frequencies. Specifications

outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.

See the Terminology section.

Guaranteed by initial characterization.

= 3 mA

SINK

= 6 mA

SINK

10 pF max

= 100 kHz

SCL

= 400 kHz

SCL

= 3.4 MHz

SCL

= 100 kHz

SCL

= 400 kHz

SCL

= 3.4 MHz, 188 kSPS typ @ 5 V

SCL

2.7/5.5 V min/max Digital inputs = 0 V or V

SCL

Mode 1

SCL

Mode 2

SCL

Mode 1

SCL

Mode 2

SCL

Rev. 0 | Page 4 of 32

Page 5

AD7997/AD7998

AD7998 SPECIFICATIONS

Temperature range for B version is −40°C to +85°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V; For the AD7998-0, all

specifications apply for f

= T

to T

MIN

MAX

up to 400 kHz; for the AD7998-1, all specifications apply for f

SCL

Table 2.

Parameter B Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE1

Signal-to-Noise + Distortion (SINAD)2 70.5 dB min Signal to Noise Ratio (SNR)

71 dB min Total Harmonic Distortion (THD)2 –78 dB max Peak Harmonic or Spurious Noise (SFDR)2 –79 dB max Intermodulation Distortion (IMD)2

Second-Order Terms –90 dB typ

Third-Order Terms –90 dB typ Aperture Delay2 10 ns max Aperture Jitter2 50 ps typ Channel-to-Channel Isolation2 –90 dB typ FIN = 108 Hz, see the Terminology section Full-Power Bandwidth2 11 MHz typ @ 3 dB

2 MHz typ @ 0.1 dB DC ACCURACY

Resolution 12 Bits Integral Nonlinearity

1,2

±1 LSB max

±0.2 LSB typ

Differential Nonlinearity

1,2

+1/–0.9 LSB max Guaranteed no missed codes to 12 bits

±0.2 LSB typ

Offset Error2 ±4 LSB max ±6 LSB max Mode 2 (Command Mode)

Offset Error Match2 ±1 LSB max Gain Error2 ±2 LSB max Gain Error Match2 ±1 LSB max

ANALOG INPUT

Input Voltage Range 0 to REF

DC Leakage Current ± 1 µA max Input Capacitance 30 pF typ

REFERENCE INPUT

REFIN Input Voltage Range 1.2 to V

V min/V max DC Leakage Current ± 1 µA max Input Impedance 69 kΩ typ

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V Input Low Voltage, V

0.7 (VDD) V min

INH

0.3 (VDD) V max

INL

Input Leakage Current, IIN ± 1 µA max VIN = 0 V or V Input Capacitance, C Input Hysteresis, V

0.1 (VDD) V min

HYST

10 pF max

up to 3.4 MHz, unless otherwise noted;

SCL

= 10 kHz sine wave for f

from 1.7 MHz to

SCL

3.4 MHz = 1 kHz sine wave for f

fa = 10.1 kHz, fb = 9.9 kHz f

up to 400 kHz

SCL

from 1.7 MHz to

SCL

3.4 MHz

fa = 1.1 kHz, fb = 0.9 kHz for f

Mode 1 (

CONVST Mode)

up to 400 kHz

SCL

Rev. 0 | Page 5 of 32

Page 6

AD7997/AD7998

Parameter B Version Unit Test Conditions/Comments

LOGIC INPUTS (CONVST)

Input High Voltage, V

2.4 V min VDD = 5 V

INH

2.0 V min VDD = 3 V Input Low Voltage, V

0.8 V max VDD = 5 V

INL

0.4 V max VDD = 3 V Input Leakage Current, IIN ±1 µA max VIN = 0 V or V Input Capacitance, C

10 pF max

LOGIC OUTPUTS (OPEN-DRAIN)

Output Low Voltage, VOL 0.4 V max I

0.6 V max I Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance3 10 pF max Output Coding Straight (Natural) Binary

CONVERSION RATE See the Modes of Operation section

Conversion Time 2 µs typ Throughput Rate

Mode 1 (Reading after the Conversion) 5 kSPS typ f 21 kSPS typ f 121 kSPS typ f

Mode 2 5.5 kSPS typ f 22 kSPS typ f 147 kSPS typ f POWER REQUIREMENTS

Power-Down Mode, Interface Inactive 1/2 µA max VDD = 3.3 V/5.5 V Power-Down Mode, Interface Active 0.07/0.3 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f Operating, Interface Inactive 0.06/0.1 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f Operating, Interface Active 0.15/0.4 mA max VDD = 3.3 V/5.5 V, 400 kHz f

0.6/1.1 mA max VDD = 3.3 V/5.5 V, 3.4 MHz f

0.7/1.4 mA typ VDD = 3.3 V/5.5 V, 3.4 MHz f Mode 3 (I2C Inactive, T

x 32) 0.7/1.5 mA max VDD = 3.3 V/5.5 V

CONVERT

Power Dissipation

Fully Operational Operating, Interface Active 0.495/2.2 mW max VDD = 3.3 V/5.5 V, 400 kHz f

1.98/6.05 mW max VDD = 3.3 V/5.5 V, 3.4 MHz f

2.31/7.7 mW typ VDD = 3.3 V/5.5 V, 3.4 MHz f Power Down, Interface Inactive 3.3/11 µW max VDD = 3.3 V/5.5 V

Max/min ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C Hs-Mode SCL frequencies. Specifications

outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.

See the section. Terminology

Guaranteed by initial characterization.

= 3 mA

SINK

= 6 mA

SINK

= 100 kHz

SCL

= 400 kHz

SCL

= 3.4 MHz

SCL

= 100 kHz

SCL

= 400 kHz

SCL

= 3.4 MHz , 188 kSPS typ @ 5 V

SCL

2.7/5.5 V min/max Digital inputs = 0 V or V

SCL

Mode 1

SCL

Mode 2

SCL

Mode 1

SCL

Mode 2

SCL

Rev. 0 | Page 6 of 32

Page 7

AD7997/AD7998

I2C TIMING SPECIFICATIONS

Guaranteed by initial characterization. All values measured with input filtering enabled. CB refers to capacitive load on the bus line. tr and

measured between 0.3 VDD and 0.7 VDD.

High speed mode timing specifications apply to the AD7997-1/AD7998-1 only. Standard and fast mode timing specifications apply to both the AD7997-0/AD7998-0 and the AD7997-1/AD7998-1. See Figure 2. Unless otherwise noted, V

to T

MIN

MAX

Table 3.

AD7997/AD7998 Limit at T Parameter Conditions Min Max Unit Description

Standard mode 100 kHz Serial clock frequency

SCL

Fast mode 400 kHz High speed mode C C

= 100 pF max 3.4 MHz

= 400 pF max 1.7 MHz

t1 Standard mode 4 µs t Fast mode 0.6 µs High speed mode C C

= 100 pF max 60 ns

= 400 pF max 120 ns

t2 Standard mode 4.7 µs t Fast mode 1.3 µs High speed mode C C

= 100 pF max 160 ns

= 400 pF max 320 ns

t3 Standard mode 250 ns t Fast mode 100 ns High speed mode 10 ns

Standard mode 0 3.45 µs t Fast mode 0 0.9 µs High speed mode C C

= 100 pF max 0 70

= 400 pF max 0 150 ns

t5 Standard mode 4.7 µs t Fast mode 0.6 µs High speed mode 160 ns t6 Standard mode 4 µs t Fast mode 0.6 µs High speed mode 160 ns t7 Standard mode 4.7 µs t Fast mode 1.3 µs t8 Standard mode 4 µs t Fast mode 0.6 µs High speed mode 160 ns t9 Standard mode 1000 ns t Fast mode 20 + 0.1 CB 300 ns High speed mode C C

= 100 pF max 10 80 ns

= 400 pF max 20 160 ns

MIN

, T

MAX

, SCL high time

HIGH

, SCL low time

LOW

, data setup time

SU;DAT

, data hold time

HD;DAT

, setup time for a repeated start condition

SU;STA

, hold time (repeated) start condition

HD;STA

, bus free time between a stop and a start condition

BUF

, setup time for stop condition

SU;STO

, rise time of SDA signal

RDA

= 2.7 V to 5.5 V; REFIN = 2.5 V;

Rev. 0 | Page 7 of 32

Page 8

AD7997/AD7998

AD7997/AD7998 Limit at T Parameter Conditions Min Max Unit Description

Standard mode 300 ns t Fast mode 20 + 0.1 CB300 ns High speed mode C C

= 100 pF max 10 80 ns

= 400 pF max 20 160 ns

t11 Standard mode 1000 ns t Fast mode 20 + 0.1 CB300 ns High speed mode C C t

11A

= 100 pF max 10 40 ns

= 400 pF max 20 80 ns

Standard mode 1000 ns t

Fast mode 20 + 0.1 CB300 ns High speed mode C C t

= 100 pF max 10 80 ns

= 400 pF max 20 160 ns

Standard mode 300 ns t Fast mode 20 + 0.1 CB 300 ns High speed mode C C t

= 100 pF max 10 40 ns

= 400 pF max 20 80 ns

Fast mode 0 50 ns Pulse width of suppressed spike High speed mode 0 10 ns t

POWER-UP

1 typ µs Power-up time

A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.

For 3 V supplies, the maximum hold time with CB = 100 pF max is 100 ns max.

MIN

, T

MAX

, fall time of SDA signal

FDA

, rise time of SCL signal

RCL

, rise time of SCL signal after a repeated start

RCL1

condition and after an Acknowledge bit

, fall time of SCL signal

FCL

03473-0-002

SCL

SDA

S = START CONDITION P = STOP CONDITION

Figure 2. Timing Diagram for 2-Wire Serial Interface

Rev. 0 | Page 8 of 32

Page 9

AD7997/AD7998

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to 7 V Analog Input Voltage to GND −0.3 V to VDD + 0.3 V Reference Input Voltage to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies1±10 mA Operating Temperature Range

Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150° Junction Temperature 150°C 20-Lead TSSOP

θJA Thermal Impedance 143°C/W

θJC Thermal Impedance 45°C/W Pb/SN Temperature, Soldering

Reflow (10 s to 30 s) 240 (+0/-5)°C Pb-free Temperature, Soldering

Reflow 260 (+0)°C ESD 1.5 kV

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 9 of 32

Page 10

AD7997/AD7998

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

AGND

AD7997/

AD7998

TOP VIEW

(Not to Scale)

5 6 7 8 9

AGND AGND

REF

VIN1 VIN3 V VIN7

Figure 3. AD7998/AD7997 Pin Configuration

AGND SCL

SDA

ALERT/BUSY

CONVST

VIN2

VIN6

VIN8

03473-0-003

Table 5. Pin Function Descriptions

Pin No. Mnemonic Function

1, 3, 4, 20

AGND Analog Ground. Ground reference point for all circuitry on the AD7997/AD7998. All analog input signals should be

referred to this AGND voltage. 2, 5 VDD Power Supply Input. The VDD range for the AD7997/AD7998 is from 2.7 V to 5.5 V. 6 REFIN Voltage Reference Input. The external reference for the AD7997/AD7998 should be applied to this input pin. The

voltage range for the external reference is 1.2 V to V

. A 0.1 µF and 1 µF capacitors should be placed between REFIN

and AGND. See Typical Connection Diagram. 7 VIN1 Analog Input 1. Single-ended analog input channel. The input range is 0 V to REFIN. 8 VIN3 Analog Input 3. Single-ended analog input channel. The input range is 0 V to REFIN. 9 VIN5 Analog Input 5. Single-ended analog input channel. The input range is 0 V to REFIN. 10 VIN7 Analog Input 7. Single-ended analog input channel. The input range is 0 V to REFIN. 11 VIN8 Analog Input 8. Single-ended analog input channel. The input range is 0 V to REFIN. 12 VIN6 Analog Input 6. Single-ended analog input channel. The input range is 0 V to REFIN. 13 VIN4 Analog Input 4. Single-ended analog input channel. The input range is 0 V to REFIN. 14 VIN2 Analog Input 2. Single-ended analog input channel. The input range is 0 V to REFIN. 15 AS

Logic Input. Address select input that selects one of three I

C addresses for the AD7997/AD7998, as shown in Table 6.

The device address depends on the voltage applied to this pin. 16

CONVST

Logic Input Signal. Convert start signal. This is an edge-triggered logic input. The rising edge of this signal powers up

the part. The power-up time for the part is 1 µs. The falling edge of

initiates a conversion. A power-up time of at least 1 µs must be allowed for the

CONVST

places the track/hold into hold mode and

CONVST

high pulse; otherwise, the

conversion result is invalid (see the Modes of Operation section). 17 ALERT/BUSY Digital Output. Selectable as an ALERT or BUSY output function. When configured as an ALERT, this pin acts as an out-

of-range indicator and, if enabled, becomes active when the conversion result violates the DATAHIGH or DATALOW

conversion is in progress. Open-drain output. 18 SDA Digital I/O. Serial bus bidirectional data. Open-drain output. External pull-up resistor required. 19 SCL Digital Input. Serial bus clock. Open-drain input. External pull-up resistor required.

Table 6. I2C Address Selection

Part Number AS Pin I2C Address

AD7997-0 AGND 010 0001 AD7997-0 VDD 010 0010 AD7997-1 AGND 010 0011 AD7997-1 VDD 010 0100 AD7997-x

Float 010 0000 AD7998-0 AGND 010 0001 AD7998-0 VDD 010 0010 AD7998-1 AGND 010 0011 AD7998-1 VDD 010 0100 AD7998-x1

Float 010 0000

If the AS pin is left floating on any of the AD7997/AD7998 parts, the device address is 010 0000.

Rev. 0 | Page 10 of 32

Page 11

AD7997/AD7998

TERMINOLOGY

Signal-to-Noise and Distortion Ratio (SINAD)

The measured ratio of signal-to-noise and distortion at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f

/2), excluding dc. The ratio is

dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-noise and distortion ratio for an ideal N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Thus, the SINAD is 61.96 dB for a 10-bit converter and 74 dB for a 12-bit converter.

Total Harmonic Distortion (THD)

The ratio of the rms sum of harmonics to the fundamental. For the AD7997/AD7998, it is defined as

22222

++++

VVVVV

THD

log20)dB(

65432

Channel-to-Channel Isolation

A measure of the level of crosstalk between channels, taken by applying a full-scale sine wave signal to the unselected input channels, and determining how much the 108 Hz signal is attenuated in the selected channel. The sine wave signal applied to the unselected channels is then varied from 1 kHz up to 2 MHz, each time determining how much the 108 Hz signal in the selected channel is attenuated. This figure represents the worst-case level across all channels.

Aperture Delay

The measured interval between the sampling clock’s leading edge and the point at which the ADC takes the sample.

Aperture Jitter

This is the sample-to-sample variation in the effective point in time at which the sample is taken.

Full-Power Bandwidth

The input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 dB or 3 dB for a full-scale input.

where V

is the rms amplitude of the fundamental and V2, V3,

, V5, and V6 are the rms amplitudes of the second through

sixth harmonics.

Peak Harmonic or Spurious Noise

The ratio of the rms value of the next largest component in the ADC output spectrum (up to f

/2 and excluding dc) to the rms

value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n equal zero. For example, second-order terms include (fa + fb) and (fa − fb), while third-order terms include (2fa + fb), (2fa − fb),(fa + 2fb) and (fa − 2fb).

The AD7997/AD7998 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second and third-order terms are specified separately. The calculation of intermodulation distortion is, like the THD specification, the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in dB.

Power Supply Rejection Ratio (PSRR)

The ratio of the power in the ADC output at the full-scale frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC V

PSRR (dB) = 10 log (Pf/Pf

where Pf is the power at frequency f in the ADC output; Pf the power at frequency f

supply of frequency fS:

)

coupled onto the ADC VDD supply.

Integral Nonlinearity

The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition.

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Offset Error

The deviation of the first code transition (00…000) to (00…001) from the ideal—that is, AGND + 1 LSB.

Offset Error Match

The difference in offset error between any two channels.

Gain Error

The deviation of the last code transition (111…110) to (111…111) from the ideal (that is, REF

− 1 LSB) after the

offset error has been adjusted out.

Gain Error Match

The difference in gain error between any two channels.

Rev. 0 | Page 11 of 32

Page 12

AD7997/AD7998

TYPICAL PERFORMANCE CHARACTERISTICS

–20

–40

–60

SINAD (dB)

–80

FS = 121kSPS FSCL = 3.4MHz FIN = 10kHz SNR = 71.84dB SINAD = 71.68dB THD = 86.18dB SFDR = –88.70dB

SINAD (dB)

VDD = 4.5V

VDD = 3V

VDD = 3.3V

VDD = 5V

VDD = 2.7V

= 5.5V

–100

–120

20 40060

FREQUENCY (kHz)

Figure 4. AD7998 Dynamic Performance with 5 V Supply and

2.5 V Reference, 121 kSPS, Mode 1

FS = 121kSPS

–10

–30

–50

SINAD (dB)

–70

–90

–110

10 40060

20 30 50

INPUT FREQUENCY (kHz)

FSCL = 3.4MHz FIN = 10kHz SINAD = 61.63dB THD = 91.82dB SFDR = –94.95dB

Figure 5. AD7997 Dynamic Performance with 5 V Supply and

2.5 V Reference, 121 kSPS, Mode 1

100

VDD = 3V

PSRR (dB)

10 1000

VDD = 5V

VDD = 3V/5V 200mV p-p SINE WAVE ON V

2nF CAPACITOR ON V

100

SUPPLY RIPPLE FREQUENCY(kHz)

Figure 6. PSRR vs. Supply Ripple Frequency

03473-0-004

1 1000

FREQUENCY(kHz)

10010

03473-0-007

Figure 7. AD7998 SINAD vs. Analog Input Frequency for

, 136 kSPS

SCL

, 121 kSPS

SCL

03473-0-008

03473-0-005

Various Supply Voltages, 3.4 MHz f

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

Figure 8. Typical I NL, V

20001500500 10000 2500 3000 3500 4000 CODE

= 5.5 V, Mode 1, 3.4 MHz f

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4



03473-0-006

–0.6

–0.8

–1.0

Figure 9. Typical D NL, V

20001500500 10000 2500 3000 3500 4000 CODE

= 5.5 V, Mode 1, 3.4 MHz f

, 121 kSPS

SCL

03473-0-009

Rev. 0 | Page 12 of 32

Page 13

AD7997/AD7998

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

Figure 10. Typical INL, V

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

Figure 11. Typical DNL, V

20001500500 10000 2500 3000 3500 4000 CODE

= 2.7 V, Mode 1, 3.4 MHz f

20001500500 10000 2500 3000 3500 4000 CODE

= 2.7 V, Mode 1, 3.4 MHz f

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

-0.6

–0.8

–1.0

1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 REFERENCE VOLTAGE (V)

POSITIVE INL

NEGATIVE INL

Figure 12. AD7998 Change in INL vs. Reference Voltage V

Mode 1, 121 kSPS

, 121 kSPS

SCL

, 121 kSPS

SCL

= 5 V,

03473-0-010

03473-0-011

03473-0-012

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

-0.6

–0.8

–1.0

1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 REFERENCE VOLTAGE (V)

POSITIVE DNL

NEGATIVE DNL

Figure 13. AD7998 Change in DNL vs. Reference Voltage V

Mode 1, 121 kSPS

0.0007

0.0006

0.0005

0.0004

0.0003

0.0002

SUPPLY CURRENT (mA)

0.0001

2.7 3.2 3.7 4.2 4.7 5.2 SUPPLY VOLTAGE (V)

–40°C

+25°C

+85°C

Figure 14. AD7998 Shutdown Current vs. Supply Voltage,

–40°C, +25°C, and +85°C

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

SUPPLY CURRENT (mA)

0.4

0.2

100 600 1100 1600 2100 2600 3100

SCL FREQUENCY (kHz)

MODE 2 VDD = 5V

MODE 2 VDD = 3V

Figure 15. AD7998 Average Supply Current vs. I

= 3 V and 5 V

= 5 V,

MODE 1 VDD = 5V

MODE 1 VDD = 3V

C Bus Rate for

03473-0-013

03473-0-014

03473-0-015

Rev. 0 | Page 13 of 32

Page 14

AD7997/AD7998

2.0 TEMPERATURE = +85°C

1.8

TEMPERATURE = +25 TEMPERATURE = –40

1.6

TEMPERATURE = +85 TEMPERATURE = +25

1.4

TEMPERATURE = –40

1.2

1.0

0.8

0.6

SUPPLY CURRENT (mA)

0.4

0.2

2.7 3.2 3.7 4.2 4.7 5.2

SUPPLY VOLTAGE (V)

MODE 2 - 147kSPS

MODE 1 - 121kSPS

Figure 16. AD7998 Average Supply Current vs. Supply Voltage

for Various Temperatures

03473-0-016

12.0

11.8

11.6

11.4

11.2

ENOB (BITS)

11.0

10.8

10.6

10.4

1.200 2.048 2.500 2.700 3.000 3.300 4.096 4.500 5.000

ENOB VDD = 3V

SINAD VDD = 3V

REFERENCE VOLTAGE (V)

ENOB VDD = 5V

SINAD VDD = 5V

Figure 17. SINAD/ENOB vs. Reference Voltage, Mode 1, 121 kSPS

SINAD (dB)

03473-0-017

Rev. 0 | Page 14 of 32

Page 15

AD7997/AD7998

CIRCUIT INFORMATION

The AD7997/AD7998 are low power, 10- and 12-bit, singlesupply, 8-channel A/D converters. The parts can be operated from a 2.7 V to 5.5 V supply.

The AD7997/AD7998 have an 8-channel multiplexer, an onchip track-and-hold, an A/D converter, an on-chip oscillator, internal data registers, and an I

C-compatible serial interface, all housed in a 20-lead TSSOP. This package offers considerable space-saving advantages over alternative solutions. The AD7997/AD7998 require an external reference in the range of

1.2 V to V

The AD7997/AD7998 typically remain in a power-down state while not converting. When supplies are first applied, the parts come up in a power-down state. Power-up is initiated prior to a conversion, and the device returns to shutdown when the conversion is complete. Conversions can be initiated on the AD7997/AD7998 by pulsing the

CONVST

signal, using an

automatic cycle interval mode, or a command mode where wake-up and a conversion occur during a write address function (see the Modes of Operation section). When the conversion is complete, the AD7997/AD7998 again enter shutdown mode. This automatic shutdown feature allows power saving between conversions. This means any read or write

operation across the I

C interface can occur while the device is

in shutdown.

At the beginning of a conversion, SW2 opens and SW1 moves to position B, causing the comparator to become unbalanced, as shown in Figure 19. The input is disconnected once the conversion begins. The control logic and the capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 20 shows the ADC transfer characteristic.

CAPACITIVE

DAC

GND

SW1

SW2

COMPARATOR

CONTROL

LOGIC

Figure 19. ADC Conversion Phase

ADC Transfer Function

The output coding of the AD7997/AD7998 is straight binary. The designed code transitions occur at successive integer LSB values (1 LSB, 2 LSB, and so on). The LSB size is REF the AD7997 and REF

/4096 for the AD7998. Figure 20 shows

/1024 for

the ideal transfer characteristic for the AD7997/AD7998.

03473-0-019

CONVERTER OPERATION

The AD7997/AD7998 are successive approximation analog-todigital converters based around a capacitive DAC. Figure 18 and Figure 19 show simplified schematics of the ADC during the acquisition and conversion phase, respectively. Figure 18 shows the acquisition phase. SW2 is closed and SW1 is in position A, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on V

AGND

SW1

SW2

COMPARATOR

Figure 18. ADC Acquisition Phase

CAPACITIVE

DAC

CONTROL

LOGIC

03473-0-018

111...111

111...110

111...000

011...111

ADC CODE

000...010

000...001

000...000 AGND + 1LSB

AD7997 1LSB = REFIN/1024 AD7998 1LSB = REF

ANALOG INPUT

0V TO REF

+REFIN– 1LSB

Figure 20. AD7997/AD7998 Transfer Characteristic

/4096

03473-0-020

Rev. 0 | Page 15 of 32

Page 16

AD7997/AD7998

TYPICAL CONNECTION DIAGRAM

The typical connection diagram for the AD7997/AD7998 is shown in Figure 22. In this figure, the address select pin (AS) is tied to V floating, allowing the user to select up to five AD7997/AD7998 devices on the same serial bus. An external reference must be applied to the AD7997/AD7998. This reference can be in the range of 1.2 V to V family, AD780, ADR03, or ADR381 can be used to supply the reference voltage to the ADC.

SDA and SCL form the 2-wire I interface. External pull-up resisters are required for both SDA and SCL lines.

The AD7998-0/AD7997-0 support standard and fast I interface modes. The AD7998-1/AD7997-1 support standard, fast, and high speed I in either standard or fast mode, up to five AD7997/AD7998 devices can be connected to the bus, as noted:

3 × AD7997-0/AD7998-0 and 2 × AD7997-1/ AD7998-1 or 3 × AD7997-1/AD7998-1 and 2 × AD7997-0/AD7998-0

In high speed mode, up to three AD7997-1/AD7998-1 devices can be connected to the bus.

Wake-up from shutdown and acquisition prior to a conversion is approximately 1 µs, and conversion time is approximately 2 µs. The AD7997/AD7998 enters shutdown mode again after each conversion, which is useful in applications where power consumption is a concern.

; however, AS can also be tied to AGND or left

. A precision reference like the REF 19x

C-/SMBus-compatible

C interface modes. Therefore if operating

ANALOG INPUT

Figure 21 shows an equivalent circuit of the AD7997/AD7998 analog input structure. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 300 mV. This causes the diodes to become forward biased and start conducting current into the substrate. These diodes can conduct a maximum current of 10 mA without causing irreversible damage to the part.

4pF

CONVERSION PHASE—SWITCH OPEN TRACK PHASE—SWITCH CLOSED

Figure 21. Equivalent Analog Input Circuit

Capacitor C1 in Figure 21 is typically about 4 pF and can primarily be attributed to pin capacitance. Resistor R1 is a lumped component made up of the on resistance (R a track-and-hold switch, and also includes the R input multiplexer. The total resistance is typically about 400 Ω. C2, the ADC sampling capacitor, has a typical capacitance of 30 pF.

30pF

of the

03473-0-022

) of

5V SUPPLY

2-WIRE SERIAL INTERFACE

µC/µP

03473-0-021

REF 19x

0.1µF

0V to REF

INPUT

1µF

0.1µF10µF

RPRPR

AD7997/

AD7998

AGND

SDA

SCL

ALERT

CONVST

VIN1

REF

Figure 22. AD7997/AD7998 Typical Connection Diagram

Rev. 0 | Page 16 of 32

Page 17

AD7997/AD7998

For ac applications, removing high frequency components from the analog input signal is recommended, by using an RC bandpass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application.

When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. THD increases as the source impedance increases, and performance degrades. Figure 23 shows the THD vs. the analog input signal frequency when using supply voltages of 3 V ± 10% and 5 V ± 10%. Figure 24 shows the THD vs. the analog input signal frequency for different source impedances.

–40

–50

VDD = 4.5V

VDD = 5V

100

VDD = 3V

VDD = 3.3V

VDD = 5.5V

–60

–70

THD (dB)

–80

–90

–100

VDD = 2.7V

10 1000

INPUT FREQUENCY(kHz)

Figure 23. THD vs. Analog Input Frequency for Various

Supply Voltages, F

= 136 kSPS, Mode 1

–40

–50

–60

–70

THD (dB)

–80

–90

RIN = 1000Ω

RIN = 100Ω

RIN = 10Ω

VDD = 5V

RIN = 50Ω

03473-0-023

–100

10 1000

INPUT FREQUENCY(kHz)

Figure 24. THD vs. Analog Input Frequency for Various

Source Impedances for V

100

= 5 V, 136 kSPS, Mode 1

03473-0-024

Rev. 0 | Page 17 of 32

Page 18

AD7997/AD7998

INTERNAL REGISTER STRUCTURE

The AD7997/AD7998 contain 17 internal registers that are used to store conversion results, high and low conversion limits, and information to configure and control the device (see Figure 25). Sixteen are data registers and one is an address pointer register.

Each data register has an address that the address pointer register points to when communicating with it. The conversion result register is the only data register that is read only.

ADDRESS POINTER REGISTER

Because it is the register to which the first data byte of every write operation is written automatically, the address pointer register does not have and does not require an address. The address pointer register is an 8-bit register in which the 4 LSBs are used as pointer bits to store an address that points to one of the AD7997/AD7998’s data registers. The 4 MSBs are used as command bits when operating in Mode 2 (see the Modes of Operation section). The first byte following each write address is to the address pointer register, containing the address of one of the data registers. The 4 LSBs select the data register to which subsequent data bytes are written. Only the 4 LSBs of this register are used to select a data register. On power-up, the address pointer register contains all 0s, pointing to the conversion result register.

Table 7. Address Pointer Register

C4 C3 C2 C1 P3 P2 P1 P0

0 0 0 0 Register Select

Table 8. AD7997/AD7998 Register Addresses

P3 P2 P1 P0 Registers

0 0 0 0 Conversion Result Register (Read) 0 0 0 1 Alert Status Register (Read/Write) 0 0 1 0 Configuration Register (Read/Write) 0 0 1 1 Cycle Timer Register (Read/Write) 0 1 0 0 DATA 0 1 0 1 DATA 0 1 1 0 Hysteresis Reg CH1 (Read/Write) 0 1 1 1 DATA 1 0 0 0 DATA 1 0 0 1 Hysteresis Reg CH2 (Read/Write) 1 0 1 0 DATA 1 0 1 1 DATA 1 1 0 0 Hysteresis Reg CH3 (Read/Write) 1 1 0 1 DATA 1 1 1 0 DATA 1 1 1 1 Hysteresis Reg CH4 (Read/Write)

Reg CH1 (Read/Write)

LOW

Reg CH1 (Read/Write)

HIGH

Reg CH2 (Read/Write)

LOW

Reg CH2 (Read/Write)

HIGH

Reg CH3 (Read/Write)

LOW

Reg CH3 (Read/Write)

HIGH

Reg CH4 (Read/Write)

LOW

Reg CH4 (Read/Write)

HIGH

ADDRESS

POINTER

CONVERSION

RESULT REGISTER

ALERT STATUS

CONFIGURATION

CYCLE TIMER

DATA

LOW

DATA

HIGH

HYSTERESIS

DATA

LOW

DATA

HIGH

HYSTERESIS

DATA

LOW

DATA

HIGH

HYSTERESIS

DATA

LOW

DATA

HIGH

HYSTERESIS

SERIAL BUS INTERFACE

D A T A

Figure 25. AD7997/AD7998 Register Structure

SDA

SCL

03473-0-025

Rev. 0 | Page 18 of 32

Page 19

AD7997/AD7998

CONFIGURATION REGISTER

The configuration register is a 16-bit read/write register that is used to set the operating mode of the AD7997/AD7998. The 4 MSBs of the register are unused. The bit functions of all 12 LSBs of the configuration register are outlined in Table 9. A 2-byte write is necessary when writing to the configuration register.

Table 9. Configuration Register Bits and Default Settings at Power-Up

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

ALERT

DONTC DONTC DONTC DONTC CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 FLTR 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

Table 10. Bit Function Descriptions

Bit Mnemonic Comment

D11 to D4 CH8 to CH1

D3 FLTR

D2 ALERT EN

D1 BUSY/ALERT

BUSY/ALERT POLARITY

These 8-channel address bits select the analog input channel(s) to be converted. A 1 in any of Bits D11 to D4 selects a channel for conversion. If more than one channel bit is set to 1, the AD7997/AD7998 sequence through the selected channels, starting with the lowest channel. All unused channels should be set to 0. Prior to initiating a conversion, a channel or channels for conversion must be selected in the configuration register.

The value written to this bit of the control register determines whether the filtering on SDA and SCL is enabled or is to be bypassed. If this bit is a 1, then the filtering is enabled; if it is a 0, the filtering is bypassed.

The hardware ALERT function is enabled if this bit is set to 1, and disabled if this bit is set to 0. This bit is used in conjunction with the BUSY/ALERT bit to determine if the ALERT/BUSY pin acts as an ALERT or a BUSY output (see Table 12).

This bit is used in conjunction with the ALERT EN bit to determine if the ALERT/ BUSY output, Pin 17, acts as an ALERT or BUSY output (see Table 12), and if Pin 17 is configured as an ALERT output pin, if it is to be reset.

This bit determines the active polarity of the ALERT/BUSY pin regardless of whether it is configured as an ALERT or BUSY output. It is active low if this bit is set to 0, and active high if set to 1.

Table 11. Channel Selection

D11 D10 D9 D8 D7 D6 D5 D4 Selected Analog Input Channel Comments

0 0 0 0 0 0 0 1 Convert on Channel 1 (VIN1) 0 0 0 0 0 0 1 0 Convert on Channel 2 (VIN2) 0 0 0 0 0 1 0 0 Convert on Channel 3 (VIN3) 0 0 0 0 1 0 0 0 Convert on Channel 4 (VIN4) 0 0 0 1 0 0 0 0 Convert on Channel 5 (VIN5) 0 0 1 0 0 0 0 0 Convert on Channel 6 (VIN6) 0 1 0 0 0 0 0 0 Convert on Channel 7 (VIN7) 1 0 0 0 0 0 0 0 Convert on Channel 8 (VIN8)

If more than one channel is selected, the AD7997/AD7998 start converting on the selected sequence of channels starting with the lowest channel in the sequence.

Table 12. ALERT/BUSY Function

D2 D1 ALERT/BUSY Pin Configuration

0 0 Pin does not provide any interrupt signal. 0 1 Pin configured as a BUSY output. 1 0 Pin configured as an ALERT output.

Resets the ALERT output pin, the Alert_Flag bit in the conversion result register, and the entire alert status register

1 1

(if any is active). If 1/1 is written to Bits D2/D1 in the configuration register to reset the ALERT pin, the Alert_Flag bit, and the alert status register, the contents of the configuration register read 1/0 for D2/D1, respectively, if read back.

BUSY/ ALERT

ALERT/BUSY POLARITY

Rev. 0 | Page 19 of 32

Page 20

AD7997/AD7998

CONVERSION RESULT REGISTER

The conversion result register is a 16-bit, read-only register that stores the conversion result from the ADC in straight binary format. A 2-byte read is necessary to read data from this register. Table 13 shows the contents of the first byte to be read from the AD7997/AD7998, and Table 14 shows the contents of the second byte to be read.

Table 13. Conversion Value Register (First Read)

D15 D14 D13 D12 D11 D10 D9 D8

Alert_Flag CH

Table 14. Conversion Value Register (Second Read)

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

The AD7997/AD7998 conversion result consists of an Alert_Flag bit, three channel identifier bits, and the 10- and 12-bit data result (MSB first). For the AD7997, the 2 LSBs (D1 and D0) of the second read contain two 0s. The three channel identification bits can be used to identify to which of the eight analog input channels the conversion result corresponds.

The Alert_Flag bit indicates whether the conversion result being read or any other channel result has violated the limit registers associated with it. If an ALERT occurs, the master can read the ALERT status register to obtain more information on where the ALERT occurred.

LIMIT REGISTERS

The AD7997/AD7998 have four pairs of limit registers. Each pair stores high and low conversion limits for the first four analog input channels, CH1 to CH4. Each pair of limit registers has one associated hysteresis register. All 12 registers are 16 bits wide; only the 12 LSBs of the registers are used for the AD7997 and AD7998. For the AD7997, the 2 LSBs, D1 and D0 in these registers, should contain 0s. On power-up, the contents of the DATA contents of the DATA AD7997/AD7998 signal an alert (in either hardware, software, or both depending on configuration) if the conversion result moves outside the upper or lower limit set by the limit registers. There are no limit registers or hysteresis registers associated with CH5 to CH8.

HIGH

ID2

ID1

registers is zero scale by default. The

LOW

M S B B10 B9 B8

ID0

DATA

The DATA

HIGH

registers for CH1 to CH 4 are 16-bit read/write

HIGH

registers; only the 12 LSBs of each register are used. This register stores the upper limit that activates the ALERT output and/or the Alert_Flag bit in the conversion result register. If the value in the conversion result register is greater than the value in the DATA

HIGH

When the conversion result returns to a value at least N LSBs below the DATA

HIGH

Alert_Flag bit are reset. The value of N is taken from the hysteresis register associated with that channel. The ALERT pin can also be reset by writing to Bits D2 and D1 in the configuration register. For the AD7997, D1 and D0 of the DATA

Table 15. DATA

HIGH

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 0 B11 B10 B9 B8

Table 16. DATA

HIGH

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

DATA

The DATA

LOW

register; only the 12 LSBs of each register are used. The register stores the lower limit that activates the ALERT output and/or the Alert_Flag bit in the conversion result register. If the value in the conversion result register is less than the value in the DATA

LOW

conversion result returns to a value at least N LSBs above the DATA

LOW

bit are reset. The value of N is taken from the hysteresis register associated with that channel. The ALERT output pin can also be reset by writing to Bits D2 and D1 in the configuration register. For the AD7997, D1 to D0 of the DATA

LOW

contain 0s.

Table 17. DATA

LOW

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 0 B11 B10 B9 B8

Table 18. DATA

LOW

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

Rev. 0 | Page 20 of 32

Page 21

AD7997/AD7998

Hysteresis Register (CH1/CH2/CH3/CH4)

Each hysteresis register is a 16-bit read/write register, of which only the 12 LSBs are used. The hysteresis register stores the hysteresis value, N, when using the limit registers. Each pair of limit registers has a dedicated hysteresis register. The hysteresis value determines the reset point for the ALERT pin/Alert_Flag if a violation of the limits has occurred. For example, if a hysteresis value of 8 LSBs is required on the upper and lower limits of Channel 1, the 12-bit word, 0000 0000 0000 1000, should be written to the hysteresis register of CH1, the address of which is shown in Table 8. On power-up, the hysteresis registers contain a value of 2 for the AD7997 and a value of 8 for the AD7998. If a different hysteresis value is required, that value must be written to the hysteresis register for the channel in question. For the AD7997, D1 and D0 of the hysteresis register should contain 0s.

Table 19. Hysteresis Register (First Read/Write)

D15 D14 D13 D12 D11 D10 D9 D8

0 0 0 0 B11 B10 B9 B8

Table 20. Hysteresis Register (Second Read/Write)

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3 B2 B1 B0

Using the Limit Registers to Store Min/Max Conversion Results for CH1 to CH4

If full scale, that is, all 1s, is written to the hysteresis register for a particular channel, the DATA

and DATA

HIGH

registers for

LOW

that channel no longer act as limit registers as previously described, but instead act as storage registers for the maximum and minimum conversion results returned from conversions on a channel over any given period of time. This function is useful in applications where the widest span of actual conversion results is required rather than using the ALERT to signal that an intervention is necessary. This function could be useful for monitoring temperature extremes during refrigerated goods transportation. It must be noted that on power-up, the contents of the DATA contents of the DATA

HIGH

registers are zero scale by default.

LOW

Therefore, minimum and maximum conversion values being stored in this way are lost if power is removed or cycled.

ALERT STATUS REGISTER (CH1 TO CH4)

The alert status register is an 8-bit, read/write register that provides information on an alert event. If a conversion result activates the ALERT pin or the Alert_Flag bit in the conversion result register, as described in the Limit Registers section, the alert status register may be read to gain further information. The Alert Status Register contains two status bits per channel, one corresponding to the DATA DATA

limit. The bit with a status of 1 shows where the

LOW

violation occurred—that is, on which channel—and whether the violation occurred on the upper or lower limit. If a second alert event occurs on the other channel between receiving the first alert and interrogating the alert status register, the corresponding bit for that alert event is also set.

The alert status register only contains information for CH1 to CH4 because these are the only channels with associated limit registers.

The entire contents of the alert status register can be cleared by writing 1,1, to Bits D2 and D1 in the configuration register, as shown in Table 12. This may also be done by writing all 1s to the alert status register itself. Thus, if the alert status register is addressed for a write operation, which is all 1s, the contents of the alert status register are cleared or reset to all 0s.

Table 21. Alert Status Register

D7 D6 D5 D4 D3 D2 D1 D0

CH4HI CH4LO CH3HI CH3LO CH2HI CH2LO CH1HI CH1LO

Table 22. Alert Status Register Bit Function Description

Bit Mnemonic If bit is set to 1, violation of…

D0 CH1

D1 CH1

D2 CH2

D3 CH2

D4 CH3

D5 CH3

D6 CH4

D7 CH4

limit and the other to the

HIGH

DATA

limit on Channel 1.

LOW