Datasheet AD7991, AD7995, AD7999 Datasheet (ANALOG DEVICES)

4-Channel, 12-/10-/8-Bit ADC with

V

I2C-Compatible Interface in 8-Lead SOT-23

FEATURES

12-/10-/8-bit ADCs with fast conversion time: 1 μs typical 4 analog input channels/3 analog input channels with

reference input Specified for V Sequencer operation Temperature range: −40°C to +125°C

2

I

C-compatible serial interface supports standard, fast,

and high speed modes 2 versions allow 2 I Low power consumption

Shutdown mode: 1 μA maximum 8-lead SOT-23 package

APPLICATIONS

System monitoring Battery-powered systems Data acquisition Medical instruments

GENERAL DESCRIPTION

The AD7991/AD7995/AD7999 are 12-/10-/8-bit, low power, successive approximation ADCs with an I Each part operates from a single 2.7 V to 5.5 V power supply and features a 1 µs conversion time. The track-and-hold amplifier allows each part to handle input frequencies of up to 14 MHz, and a multiplexer allows taking samples from four channels.

Each AD7991/AD7995/AD7999 provides a 2-wire serial interface compatible with I AD7995 come in two versions and each version has an individual I connected to the same I fast, and high speed I one version.

The AD7991/AD7995/AD7999 normally remain in a shutdown state, powering up only for conversions. The conversion process is controlled by a command mode, during which each I operation initiates a conversion and returns the result over the

2

I

C bus.

When four channels are used as analog inputs, the reference for the part is taken from V range to the ADC. Therefore, the analog input range to the ADC is 0 V to V V

input, can also be used with this part.

IN3/VREF

of 2.7 V to 5.5 V

DD

2

C addresses

2

C®-compatible interface.

2

C interfaces. The AD7991 and

2

C address. This allows two of the same devices to be

2

C bus. Both versions support standard,

2

C interface modes. The AD7999 comes in

2

; this allows the widest dynamic input

DD

. An external reference, applied through the

DD

C read

AD7991/AD7995/AD7999

FUNCTIONAL BLOCK DIAGRAM

DD

V

IN0

V

IN3/VREF

V

IN1

V

IN2

I/P

T/H

MUX

AD7991/AD7995/AD7999

PRODUCT HIGHLIGHTS

1. Four single-ended analog input channels, or three single-

ended analog input channels and one reference input channel.

2

2. I

C-compatible serial interface. Standard, fast, and high

speed modes.

3. Automatic shutdown.

4. Reference derived from the power supply or external

reference.

5. 8-lead SOT-23 package.

Table 1. Related Devices

Device Resolution Input Channels

AD7998 12 8 AD7997 10 8 AD7994 12 4 AD7993 10 4 AD7992 12 2

12-/10-/8-BIT

CONTROL

LOGIC AND INTERFACE

Figure 1.

SAR

ADC

2

I

GND

C

SCL SDA

06461-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD7991/AD7995/AD7999

REVISION HISTORY

10/09—Rev. 0 to Rev. A

Changes to Table 3 ............................................................................ 5

Changes to Table 4 ............................................................................ 7

Updated Ordering Guide ............................................................... 27

12/07—Revision 0: Initial Version

Rev. A | Page 2 of 28

AD7991/AD7995/AD7999

SPECIFICATIONS

AD79911

The temperature range of the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, V and T

= T

MIN

to T

A

MAX

.

Table 2.

Y Version Parameter Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

2, 3

See the Sample Delay and Bit Trial Delay section, f from 1.7 MHz to 3.4 MHz

f

= 1 kHz sine wave for f

IN

Signal-to-Noise and Distortion (SINAD)4 69.5 70 dB

Signal-to-Noise Ratio (SNR)4 70 71 dB

Total Harmonic Distortion (THD)4 −75.5 dB

Peak Harmonic or Spurious Noise (SFDR)4 −77.5 dB

Intermodulation Distortion (IMD)4

fa = 11 kHz, fb = 9 kHz for f

1.7 MHz to 3.4 MHz fa = 5.4 kHz, fb = 4.6 kHz for f

to 400 kHz Second-Order Terms −92 dB Third-Order Terms −88 dB

Channel-to-Channel Isolation4 −90 dB fIN = 10 kHz Full-Power Bandwidth4 14 MHz @ 3 dB

1.5 MHz @ 0.1 dB DC ACCURACY

2, 5

Resolution 12 Bits Integral Nonlinearity4 ±1 LSB

±0.5 LSB

Differential Nonlinearity4 ±0.9 LSB Guaranteed no missed codes to 12 bits

±0.5 LSB

Offset Error4 ±1 ±5 LSB Offset Error Matching ±0.5 LSB Offset Temperature Drift 4.43 ppm/°C Gain Error4 ±2 LSB Gain Error Matching ±0.7 LSB Gain Temperature Drift 0.69 ppm/°C

ANALOG INPUT

Input Voltage Range 0 V

V V

REF

= V DC Leakage Current ±1 μA Input Capacitance 34 pF

Channel 0 to Channel 2—during acquisition phase

4 pF

Channel 0 to Channel 2—outside

acquisition phase 35 pF Channel 3—during acquisition phase 5 pF Channel 3—outside acquisition phase

REFERENCE INPUT

V

Input Voltage Range 1.2 VDD V

REF

DC Leakage Current ±1 μA V

Input Capacitance 5 pF Outside conversion phase

REF

35 pF During conversion phase Input Impedance 69 kΩ

= 2.5 V, f

REF

= 10 kHz sine wave for f

IN

or VDD

IN3/VREF

= 3.4 MHz,

SCL

up to 400 kHz

SCL

from

up

SCL

Rev. A | Page 3 of 28

AD7991/AD7995/AD7999

Y Version Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V

0.9 (VDD) V VDD = 2.35 V to 2.7 V Input Low Voltage, V

0.1 (VDD) V VDD = 2.35 V to 2.7 V Input Leakage Current, IIN ±1 μA VIN = 0 V or VDD Input Capacitance, C Input Hysteresis, V

LOGIC OUTPUTS (OPEN DRAIN)

Output Low Voltage, VOL 0.4 V I

0.6 V I Floating-State Leakage Current ±1 μA Floating-State Output Capacitance6 10 pF Output Coding Straight (natural) binary

THROUGHPUT RATE 18 × (1/f

POWER REQUIREMENTS2

VDD 2.7 5.5 V IDD Digital inputs = 0 V or VDD

ADC Operating, Interface Active

(Fully Operational)

0.25/0.8 mA VDD = 3.3 V/5.5 V, 3.4 MHz f

Power-Down, Interface Active7 0.07/0.16 mA VDD = 3.3 V/5.5 V, 400 kHz f

0.26/0.85 mA VDD = 3.3 V/5.5 V, 3.4 MHz f

Power-Down, Interface Inactive7 1/1.6 μA VDD = 3.3 V/5.5 V

Power Dissipation

ADC Operating, Interface Active

(Fully Operational)

0.83/4.4 mW VDD = 3.3 V/5.5 V, 3.4 MHz f

Power-Down, Interface Active7 0.24/0.88 mW VDD = 3.3 V/5.5 V, 400 kHz f

0.86/4.68 mW VDD = 3.3 V/5.5 V, 3.4 MHz f

Power-Down, Interface Inactive7 3.3/8.8 μW VDD = 3.3 V/5.5 V

1

Functional from VDD = 2.35 V.

2

Sample delay and bit trial delay enabled, t1 = t2 = 0.5/f

3

For f

up to 400 kHz, clock stretching is not implemented. Above f

SCL

4

See the Terminology section.

5

For f

≤ 1.7 MHz, clock stretching is not implemented; for f

SCL

6

Guaranteed by initial characterization.

7

See the Reading from the AD7991/AD7995/AD7999 section.

0.7 (VDD) V VDD = 2.7 V to 5.5 V

INH

0.3 (VDD) V VDD = 2.7 V to 5.5 V

INL

6

10 pF

IN

0.1 (VDD) V

HYST

= 3 mA

SINK

= 6 mA

SINK

)

SCL

≤ 1.7 MHz; see the Serial Interface

f

SCL

section

17.5 × (1/f + 2 μs

)

SCL

f

> 1.7 MHz; see the Serial Interface

SCL

section

= VDD; for f

V

REF

clock stretching is implemented

0.09/0.25 mA V

0.3/1.38 mW V

.

SCL

= 400 kHz, clock stretching is implemented.

SCL

> 1.7 MHz, clock stretching is implemented.

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.4 MHz,

SCL

Rev. A | Page 4 of 28

AD7991/AD7995/AD7999

AD79951

The temperature range for the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, V and T

= T

MIN

to T

A

MAX

.

Table 3.

A Version2 Y Version Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

f

Signal-to-Noise and

Distortion (SINAD)

Total Harmonic Distortion

5

(THD)

Peak Harmonic or Spurious

Noise (SFDR)

Intermodulation

Distortion (IMD)

fa = 5.4 kHz, fb = 4.6 kHz for f

Second-Order Terms −90 −90 dB Third-Order Terms −86 −86 dB

Channel-to-Channel

Isolation

5

Full-Power Bandwidth5 14 14 MHz @ 3 dB

1.5 1.5 MHz @ 0.1 dB DC ACCURACY

3, 6

Resolution 10 10 Bits Integral Nonlinearity5 ±0.4 ±0.4 LSB Differential Nonlinearity5 ±0.4 ±0.4 LSB Guaranteed no missed codes to 10 bits Offset Error5 ±1 ±1.5 LSB Offset Error Matching ±0.04 ±0.2 LSB Offset Temperature Drift 4.13 4.13 ppm/°C Gain Error5 ±0.15 ±0.5 LSB Gain Error Matching ±0.06 ±0.25 LSB Gain Temperature Drift 0.50 0.50 ppm/°C

ANALOG INPUT

Input Voltage Range 0 V DC Leakage Current ±1 ±1 μA Input Capacitance 34 34 pF Channel 0 to Channel 2—during acquisition

4 4 pF Channel 0 to Channel 2—outside acquisition

35 35 pF Channel 3—during acquisition phase 5 5 pF Channel 3—outside acquisition phase

REFERENCE INPUT

V

Input Voltage Range 1.2 VDD 1.2 VDD V

REF

DC Leakage Current ±1 ±1 μA V

Input Capacitance 5 5 pF Outside conversion phase

REF

35 35 pF During conversion phase Input Impedance 69 69 kΩ

3, 4

See the Sample Delay and Bit Trial Delay

section, f

1.7 MHz to 3.4 MHz = 1 kHz sine wave for f

IN

5

61.5 61 dB

−85 −75 dB

5

−85 −76 dB

fa = 11 kHz, fb = 9 kHz for f

3.4 MHz

−90 −90 dB f

= 10 kHz

IN

0 V

REF

V V

REF

= V

REF

phase

= 2.5 V, f

REF

= 10 kHz sine wave for f

IN

or VDD

IN3/VREF

SCL

= 3.4 MHz,

from

SCL

up to 400 kHz

from 1.7 MHz to

up to 400 kHz

SCL

Rev. A | Page 5 of 28

AD7991/AD7995/AD7999

A Version2 Y Version Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V

0.9 (VDD) V VDD = 2.35 V to 2.7 V Input Low Voltage, V

0.1 (VDD) V VDD = 2.35 V to 2.7 V Input Leakage Current, IIN ±1 ±1 μA VIN = 0 V or VDD Input Capacitance, C Input Hysteresis, V

LOGIC OUTPUTS (OPEN DRAIN)

Output Low Voltage, VOL 0.4 0.4 V I

0.6 0.6 V I Floating-State Leakage

Current

Floating-State Output

Capacitance

Output Coding Straight (natural) binary Straight (natural) binary

THROUGHPUT RATE 18 × (1/f

17.5 × (1/f

POWER REQUIREMENTS3 V

VDD 2.7 5.5 2.7 5.5 V IDD Digital inputs = 0 V or VDD

ADC Operating,

Interface Active (Fully Operational)

Power-Down, Interface

Active

Inactive

8

Power Dissipation

ADC Operating,

Interface Active (Fully Operational)

Power-Down, Interface

1

Functional from VDD = 2.35 V.

2

A Version tested at VDD = 3.3 V and f

3

Sample delay and bit trial delay enabled, t1 = t2 = 0.5/f

4

For f

SCL

5

See the Terminology section.

6

For f

SCL

7

Guaranteed by initial characterization.

8

See the Reading from the AD7991/AD7995/AD7999 section.

8

Active

8

Inactive

up to 400 kHz, clock stretching is not implemented. Above f

≤ 1.7 MHz, clock stretching is not implemented; for f

0.7 (VDD) 0.7 (VDD) V VDD = 2.7 V to 5.5 V

INH

0.3 (VDD) 0.3 (VDD) V VDD = 2.7 V to 5.5 V

INL

7

10 10 pF

IN

0.1 (VDD) 0.1 (VDD) V

HYST

SINK

±1 ±1 μA

7

10 10 pF

2 μs

) 18 × (1/f

SCL

) +

17.5 × (1/f

SCL

2 μs

) f

SCL

) +

f

SCL

clock stretching is implemented

0.09/0.25 mA VDD = 3.3 V/5.5 V, 400 kHz f

0.25 0.25/0.8 mA VDD = 3.3 V/5.5 V, 3.4 MHz f

0.07/0.16 mA V

0.26 0.26/0.85 mA VDD = 3.3 V/5.5 V, 3.4 MHz f 1 1/1.6 μA V

0.3/1.38 mW V

0.83 0.83/4.4 mW VDD = 3.3 V/5.5 V, 3.4 MHz f

0.24/0.88 mW V

0.86 0.86/4.68 mW VDD = 3.3 V/5.5 V, 3.4 MHz f

3.3 3.3/8.8 μW V

= 3.4 MHz. Functionality tested at f

SCL

.

SCL

> 1.7 MHz, clock stretching is implemented.

SCL

= 400 kHz.

SCL

= 400 kHz, clock stretching is implemented.

SCL

= 3 mA = 6 mA

≤ 1.7 MHz; see the Serial Interface section

SCL

> 1.7 MHz; see the Serial Interface section

SCL

= VDD; for f

REF

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.3 V/5.5 V

DD

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.3 V/5.5 V

DD

= 3.4 MHz,

SCL

Rev. A | Page 6 of 28

AD7991/AD7995/AD7999

AD79991

The temperature range for the Y version is −40°C to +125°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V, V and T

= T

MIN

to T

A

MAX

.

Table 4.

A Version2 Y Version Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

f

Signal-to-Noise and

Distortion (SINAD)

Total Harmonic

Distortion (THD)

Peak Harmonic or

Spurious Noise (SFDR)

Intermodulation

Distortion (IMD) fa = 5.4 kHz, fb = 4.6 kHz for f Second-Order Terms −83 −83 dB Third-Order Terms −75 −75 dB Channel-to-Channel

Isolation

5

Full-Power Bandwidth5 14 14 MHz @ 3 dB

1.5 1.5 MHz @ 0.1 dB DC ACCURACY

3, 6

Resolution 8 8 Bits Integral Nonlinearity5 ±0.04 ±0.1 LSB Differential Nonlinearity5 ±0.05 ±0.1 LSB Guaranteed no missed codes to eight bits Offset Error5 ±0.3 ±0.35 LSB Offset Error Matching ±0.02 ±0.05 LSB Offset Temperature Drift 4.26 4.26 ppm/°C Gain Error5 ±0.06 ±0.175 LSB Gain Error Matching ±0.03 ±0.06 LSB Gain Temperature Drift 0.59 0.59 ppm/°C

ANALOG INPUT

Input Voltage Range 0 V DC Leakage Current ±1 ±1 μA Input Capacitance 34 34 pF Channel 0 to Channel 2—during acquisition phase 4 4 pF Channel 0 to Channel 2—outside acquisition phase 35 35 pF Channel 3—during acquisition phase 5 5 pF Channel 3—outside acquisition phase

REFERENCE INPUT

V

Input Voltage Range 1.2 VDD 1.2 VDD V

REF

DC Leakage Current ±1 ±1 μA V

Input Capacitance 5 5 pF Outside conversion phase

REF

35 35 pF During conversion phase Input Impedance 69 69 kΩ

3, 4

See the Sample Delay and Bit Trial Delay section,

49.5 49.5 dB

5

−65 −65 dB

5

fa = 11 kHz, fb = 9 kHz for f

−90 −90 dB f

= 10 kHz sine wave for f

f

IN

= 1 kHz sine wave for f

IN

3.4 MHz

= 10 kHz

IN

0 V

REF

V V

REF

= V

REF

IN3/VREF

REF

or VDD

= 2.5 V, f

SCL

= 3.4 MHz,

SCL

from 1.7 MHz to 3.4 MHz

up to 400 kHz

from 1.7 MHz to

SCL

up to 400 kHz

SCL

Rev. A | Page 7 of 28

AD7991/AD7995/AD7999

A Version2 Y Version Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS (SDA, SCL)

Input High Voltage, V

0.9 (VDD) V VDD = 2.35 V to 2.7 V Input Low Voltage, V

0.1 (VDD) V VDD = 2.35 V to 2.7 V Input Leakage Current, IIN ±1 ±1 μA VIN = 0 V or VDD Input Capacitance, C Input Hysteresis, V

LOGIC OUTPUTS (OPEN DRAIN)

Output Low Voltage, VOL 0.4 0.4 V I

0.6 0.6 V I Floating-State Leakage

Current

Floating-State Output

Capacitance

Output Coding Straight (natural) binary Straight (natural) binary

THROUGHPUT RATE 18×(1/f

17.5×(1/f

POWER REQUIREMENTS3 V

VDD 2.7 5.5 2.7 5.5 V IDD Digital inputs = 0 V or VDD

ADC Operating,

Interface Active (Fully Operational)

Power-Down,

Interface Active

Power-Down ,

Interface Inactive

Power Dissipation

ADC Operating, Interface Active (Fully Operational)

Power-Down,

Interface Active

Power-Down ,

Interface Inactive

1

Functional from VDD = 2.35 V.

2

A Version tested at VDD=3.3 V and f

3

Sample delay and bit trial delay enabled, t1 = t2 = 0.5/f

4

For f

up to 400 kHz, clock stretching is not implemented. Above f

SCL

5

See the Terminology section.

6

For f

≤ 1.7 MHz, clock stretching is not implemented; for f

SCL

7

Guaranteed by initial characterization.

8

See the Reading from the AD7991/AD7995/AD7999 section.

0.7 (VDD) 0.7 (VDD) V VDD = 2.7 V to 5.5 V

INH

0.3 (VDD) 0.3 (VDD) V VDD = 2.7 V to 5.5 V

INL

7

10 10 pF

IN

0.1 (VDD) 0.1 (VDD) V

HYST

SINK

±1 ±1 μA

7

10 10 pF

+ 2 μs

) 18×(1/f

SCL

)

17.5×(1/f

SCL

+ 2 μs

) f

SCL

)

f

SCL

clock stretching is implemented

0.09/0.25 mA VDD = 3.3 V/5.5 V, 400 kHz f

0.25 0.25/0.8 mA VDD = 3.3 V/5.5 V, 3.4 MHz f

0.07/0.16 mA V

8

0.26 0.26/0.85 mA VDD = 3.3 V/5.5 V, 3.4 MHz f 1 1/1.6 μA V

8

0.24/0.88 mW V

8

0.86 0.86/4.68 mW VDD = 3.3 V/5.5 V, 3.4 MHz f

3.3 3.3/8.8 μW V

8

= 3.4 MHz. Functionality tested at f

SCL

0.83

SCL

.

0.3/1.38

0.83/4.4

= 400 kHz.

SCL

= 400 kHz, clock stretching is implemented.

SCL

> 1.7 MHz, clock stretching is implemented.

SCL

mW mW

V VDD = 3.3 V/5.5 V, 3.4 MHz f

= 3 mA = 6 mA

≤ 1.7 MHz; see the Serial Interface section > 1.7 MHz; see the Serial Interface section

= VDD; for f

REF

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.3 V/5.5 V

DD

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.3 V/5.5 V, 400 kHz f

DD

= 3.3 V/5.5 V

DD

= 3.4 MHz,

SCL

Rev. A | Page 8 of 28

AD7991/AD7995/AD7999

I2C TIMING SPECIFICATIONS

Guaranteed by initial characterization. All values were measured with the input filtering enabled. CB refers to the capacitive load on the bus line, with t

and tf measured between 0.3 VDD and 0.7 VDD (see Figure 2). Unless otherwise noted, VDD = 2.7 V to 5.5 V and TA = T

r

Table 5.

Limit at t

, t

MIN

MAX

Parameter Conditions Min Typ Max Unit Description

1

f

Standard mode 100 kHz Serial clock frequency

SCL

Fast mode 400 kHz High speed mode C C

1

t

Standard mode 4 μs t

1

= 100 pF maximum 3.4 MHz

B

= 400 pF maximum 1.7 MHz

B

, SCL high time

HIGH

Fast mode 0.6 μs High speed mode C C

1

t

Standard mode 4.7 μs t

2

= 100 pF maximum 60 ns

B

= 400 pF maximum 120 ns

B

, SCL low time

LOW

Fast mode 1.3 μs High speed mode C C

1

t

Standard mode 250 ns t

3

= 100 pF maximum 160 ns

B

= 400 pF maximum 320 ns

B

, data setup time

SU;DAT

Fast mode 100 ns High speed mode 10 ns

1, 2

t

Standard mode 0 3.45 μs t

4

, data hold time

HD;DAT

Fast mode 0 0.9 μs High Speed mode C C

1

t

Standard mode 4.7 μs t

5

= 100 pF maximum 0 703 ns

B

= 400 pF maximum 0 150 ns

B

, setup time for a repeated start condition

SU;STA

Fast mode 0.6 μs High Speed mode 160 ns

1

t

Standard mode 4 μs t

6

, hold time for a repeated start condition

HD;STA

Fast mode 0.6 μs High speed mode 160 ns

1

t

Standard mode 4.7 μs t

7

, bus-free time between a stop and a start condition

BUF

Fast mode 1.3 μs

1

t

Standard mode 4 μs t

8

, setup time for a stop condition

SU;STO

Fast mode 0.6 μs High speed mode 160 ns t9 Standard mode 1000 ns t

, rise time of the SDA signal

RDA

Fast mode 20 + 0.1 CB 300 ns High speed mode C C

= 100 pF maximum 10 80 ns

B

= 400 pF maximum 20 160 ns

B

MIN

to T

MAX

.

Rev. A | Page 9 of 28

AD7991/AD7995/AD7999

Limit at t Parameter Conditions Min Typ Max Unit Description

t10 Standard mode 300 ns t Fast mode 20 + 0.1 CB 300 ns High speed mode C C

= 100 pF maximum 10 80 ns

B

= 400 pF maximum 20 160 ns

B

t11 Standard mode 1000 ns t Fast mode 20 + 0.1 CB 300 ns High speed mode C C t

Standard mode 1000 ns

11A

= 100 pF maximum 10 40 ns

B

= 400 pF maximum 20 80 ns

B

Fast mode 20 + 0.1 CB 300 ns High speed mode C C

= 100 pF maximum 10 80 ns

B

= 400 pF maximum 20 160 ns

B

t12 Standard mode 300 ns t Fast mode 20 + 0.1 CB 300 ns High speed mode C C

1

t

Fast mode 0 50 ns Pulse width of the suppressed spike

SP

= 100 pF maximum 10 40 ns

B

= 400 pF maximum 20 80 ns

B

High speed mode 0 10 ns t

0.6 μs Power-up and acquisition time

POWER-UP

1

Functionality is tested during production.

2

A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.

3

For 3 V supplies, the maximum hold time with CB = 100 pF maximum is 100 ns maximum.

t

11

t

2

, t

MIN

MAX

, fall time of the SDA signal

FDA

, rise time of the SCL signal

RCL

, rise time of the SCL signal after a repeated

t

RCL1

start condition and after an acknowledge bit

, fall time of the SCL signal

FCL

t

12

t

6

SCL

SDA

P PS

S = START CONDITION P = STOP CONDITI ON

t

6

t

7

t

4

t

3

t

1

t

5

t

10

S

t

8

t

9

6461-002

Figure 2. 2-Wire Serial Interface Timing Diagram

Rev. A | Page 10 of 28

AD7991/AD7995/AD7999

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

VDD to GND −0.3 V to 7 V Analog Input Voltage to GND −0.3 V to VDD + 0.3 V Reference Input Voltage to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies1 ±10 mA Operating Temperature Ranges

Industrial (Y Version) Temperature Range −40°C to +125°C

Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 8-Lead SOT-23 Package

θJA Thermal Impedance 170°C/W

θJC Thermal Impedance 90°C/W RoHS Compliant Temperature,

Soldering Reflow ESD 1 kV

1

Transient currents of up to 100 mA do not cause SCR latch-up.

260 + 0°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 11 of 28

AD7991/AD7995/AD7999

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCL SDA

V V

IN0

IN1

1

AD7991/ AD7995/

2

AD7999

3

TOP VIEW

(Not to Scale)

4

8

7

6

5

V

DD

GND V

IN3/VREF

V

IN2

06461-003

Figure 3. SOT-23 Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 SCL Digital Input. Serial bus clock. External pull-up resistor required. 2 SDA Digital I/O. Serial bus bidirectional data. Open-drain output. External pull-up resistor required. 3 V 4 V 5 V 6 V

7 GND

Analog Input 1. Single-ended analog input channel. The input range is 0 V to V

IN0

Analog Input 2. Single-ended analog input channel. The input range is 0 V to V

IN1

Analog Input 3. Single-ended analog input channel. The input range is 0 V to V

IN2

IN3/VREF

Analog Input 4. Single-ended analog input channel. The input range is 0 V to V external V

signal.

REF

Analog Ground. Ground reference point for all circuitry on the AD7991/AD7995/AD7999. All analog input signals

.

REF

.

REF

.

REF

. Can also be used to input an

REF

should be referred to this AGND voltage.

8 VDD Power Supply Input. The VDD range for the AD7991/AD7995/AD7999 is from 2.7 V to 5.5 V.

Table 8. I2C Address Selection

Part Number I2C Address

AD7991-0 010 1000 AD7991-1 010 1001 AD7995-0 010 1000 AD7995-1 010 1001 AD7999-1 010 1001

Rev. A | Page 12 of 28

AD7991/AD7995/AD7999

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 500 1000 1500 2000 2500 3000 3500 4000

Figure 4. DNL Error, V

= 2.7 V, V

DD

CODE

= 2.35 V, f

REF

VDD = 2.7V V

REF

f

SCL

Without Clock Stretching

= 2.35V

= 1.7MHz

= 1.7 MHz

SCL

6461-005

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

1.2

1.7 2.2 2.7 3.2 3.7 4.2 4.7

POSITIVE INL

NEGATIVE INL

REFERENCE VOLTAGE (V)

Figure 7. INL Error vs. Reference Voltage , f

Without Clock Stretching

= 1.7 MHz

SCL

06461-033

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 500 1000 1500 2000 2500 3000 3500 4000

Figure 5. INL Error, V

= 2.7 V, V

DD

CODE

REF

VDD = 2.7V V

f

= 2.35 V, f

REF

SCL

= 2.35V = 1.7MHz

= 1.7 MHz

SCL

6461-006

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB )

–0.4

–0.6

–0.8

–1.0

1.2

1.7 2.2 2.7 3.2 3.7 4.2 4.7

Figure 8. DNL Error vs. Reference Voltage, f

Without Clock Stretching

12.0

11.5

ENOB VDD = 3V

11.0

10.5

10.0

ENOB (Bits)

9.5

9.0

8.5

8.0 06

SINAD VDD = 3V

12345

Figure 6. ENOB/SINAD vs. Reference Voltage, f

ENOB VDD = 5V

SINAD VDD = 5V

REFERENCE VOL T AG E (V)

= 1.7 MHz

SCL

74

72

70

68

66

SINAD (dB)

64

62

60

06461-036

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

VDD = 5V V

–0.8

–1.0

= 2.5V

REF

f

= 1.7MHz

SCL

0 500 1000 1500 2000 2500 3000 3500 4000

Figure 9. INL Error, V

Without Clock Stretching

POSITIVE DNL

NEGATIVE DNL

REFERENCE VOLTAGE (V)

Without Clock Stretching

CODE

= 5 V, V

DD

= 2.5 V, f

REF

Without Clock Stretching

= 1.7 MHz

SCL

= 1.7 MHz

SCL

06461-037

6461-013

Rev. A | Page 13 of 28

AD7991/AD7995/AD7999

–

A

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

VDD = 5V V

–0.8

–1.0

= 2.5V

REF

f

= 1.7MHz

SCL

0 500 1000 1500 2000 2500 3000 3500 4000

Figure 10. DNL Error, V

= 5 V, V

DD

CODE

= 2.5 V, f

REF

SCL

Without Clock Stretching

= 1.7 MHz

6461-014

70

f

= 1.7MHz

SCL

–80

VDD = 5V

VDD = 3V

THD (dB)

–90

–100

1 100

INPUT FREQUE NCY (kHz )

Figure 13. THD vs. Input Frequency, V

10

= 2.5 V, f

REF

SCL

Without Clock Stretching

06461-031

= 1.7 MHz

800

f

= 1.7MHz

SCL

+125°C

600

400

(μA)

DD

I

200

0

26

345

V

(V)

DD

Figure 11. IDD Supply Current vs. Supply Voltage, f

+85°C +25°C –40°C

= 1.7 MHz

SCL

06461-035

96

95

TION (dB)

94

93

92

91

90

V

= V

REF

CHANNEL-TO - CHANNEL ISOL

89

0102030405060708090100

DD

f

= 1.7MHz

SCL

TEMPERATURE = T

Figure 14. AD7991 Channel-to-Channel Isolation , f

Without Clock Stretching, −40°C to +125°C

(μA)

DD

I

1000

800

600

400

f

SCL

= 3.4MHz

+125°C +85°C +25°C –40°C

0

–20

–40

–60

SINAD (dB)

–80

VDD = 3V

V

= 5V

DD

A

f

(kHz)

NOISE

Without Clock Stretching

= 1.7 MHz

SCL

16384 POINT FFT

f

= 22.5kSPS

S

f

= 405kHz

SCL

f

= 5.13kHz

IN

SNR = 71.83dB SINAD = 71.39d B THD = –81.26d B SFDR = –93.7 1dB

6461-017

200

0

26

Figure 12. IDD Supply Current vs. Supply Voltage, f

345

V

(V)

DD

= 3.4 MHz

SCL

06461-034

with Clock Stretching, −40°C to +125°C

–100

–120

0246810

Figure 15. Dynamic Performance, f

Without Clock Stretching, V

FREQUENCY ( kHz)

= 5 V, Full-Scale Input,

DD

= 405 kHz

SCL

06461-018

Seven-Term Blackman-Harris Window

Rev. A | Page 14 of 28

AD7991/AD7995/AD7999

0

–20

–40

–60

SINAD (dB)

–80

–100

–120

0 5 10 15 20 25 30 35 40 45

Figure 16. Dynamic Performance, f

Without Clock Stretching, V

FREQUENCY ( kHz )

= 5 V, Full-Scale Input,

DD

= 1.71 MHz

SCL

Seven-Term Blackman-Harris Window

16384 POINT F F T

f

= 95kSPS

S

f

= 1.71MHz

SCL

f

= 10.13kHz

IN

SNR = 71.77dB SINAD = 71.45dB THD = –82.43dB SFDR = –95.02dB

6461-019

3

2

POWER (mW)

1

0

500 1000 1500

SCL FREQUENCY (kHz)

Figure 17. Power vs. SCL Frequency, V

VDD = 5V

VDD = 3V

= 2.5 V

REF

06461-032

Rev. A | Page 15 of 28

AD7991/AD7995/AD7999

TERMINOLOGY

Signal-to-Noise and Distortion (SINAD) Ratio

The measured ratio of signal-to-noise and distortion at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of the nonfundamental signals excluding dc, up to half the sampling frequency (f

/2). The ratio is dependent

S

on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical SINAD ratio for an ideal N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Therefore, SINAD is 49.92 dB for an 8-bit converter, 61.96 dB for a 10-bit converter, and 74 dB for a 12-bit converter.

Total Harmonic Distortion (THD)

The ratio of the rms sum of harmonics to the fundamental. For the AD7991/AD7995/AD7999, it is defined as

22222

65432

VVVVV

THD

log20)dB(

=

1

V

++++

where:

V

is the rms amplitude of the fundamental.

1

, V3, V4, V5, and V6 are the rms amplitudes of the second

V

2

through sixth harmonics.

Peak Harmonic or Spurious Noise

The ratio of the rms value of the next largest component in the ADC output spectrum (up to f

/2 and excluding dc) to the rms

S

value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, the largest harmonic may be a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n equals 0. For example, second-order terms include (fa + fb) and (fa − fb), and third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The AD7991/AD7995/AD7999 are tested using the CCIF standard, where two input frequencies near the maximum input bandwidth are used. In this case, the second-order terms are usually distanced

in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of intermodulation distortion is, like the THD specification, the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in decibels.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale sine wave signal to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 10 kHz signal. The frequency of the signal in each of the unselected channels is increased from 2 kHz up to 92 kHz. Figure 14 shows the worst-case across all four channels for the AD7991.

Full-Power Bandwidth

The input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 dB or 3 dB for a full-scale input.

Integral Nonlinearity

The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints are at zero scale (a point 1 LSB below the first code transition) and full scale (a point 1 LSB above the last code transition).

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Offset Error

The deviation of the first code transition (00 … 000 to 00 … 001) from the ideal—that is, AGND + 1 LSB.

Offset Error Match

The difference in offset error between any two channels.

Gain Error

The deviation of the last code transition (111 … 110 to 111 … 111) from the ideal (that is, V

− 1 LSB) after

REF

the offset error has been adjusted out.

Gain Error Match

The difference in gain error between any two channels.

Rev. A | Page 16 of 28

AD7991/AD7995/AD7999

THEORY OF OPERATION

The AD7991/AD7995/AD7999 are low power, 12-/10-/8-bit, single-supply, 4-channel ADCs. Each part can be operated from a single 2.35 V to 5.5 V supply.

The AD7991/AD7995/AD7999 provide the user with a 4-channel multiplexer, an on-chip track-and-hold, an ADC, and an I

2

Ccompatible serial interface, all housed in an 8-lead SOT-23 package that offers the user considerable space-saving advantages over alternative solutions.

The AD7991/AD7995/AD7999 normally remains in a powerdown state while not converting. Therefore, when supplies are first applied, the part is in a power-down state. Power-up is initiated prior to a conversion, and the device returns to the power-down state upon completion of the conversion. This automatic powerdown feature allows the device to save power between conversions.

2

This means any read or write operations across the I

C interface

can occur while the device is in power-down.

CONVERTER OPERATION

The AD7991/AD7995/AD7999 are successive approximation ADCs built around a capacitive DAC. Figure 18 and Figure 19 show simplified schematics of the ADC during its acquisition and conversion phases, respectively. Figure 18 shows the ADC during its acquisition phase: SW2 is closed, SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on V analog input needs to settle the analog input signal to within one LSB in 0.6 s, which is equivalent to the duration of the power-up and acquisition time.

. The source driving the

IN

When the ADC starts a conversion, as shown in Figure 19, SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The input is disconnected when the conversion begins. The control logic and the capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 20 shows the ADC transfer function.

CAPACITIVE

DAC

A

V

AGND

IN

SW1

B

SW2

COMPARATOR

CONTROL

LOGIC

Figure 19. ADC Conversion Phase

ADC Transfer Function

The output coding of the AD7991/AD7995/AD7999 is straight binary. The designed code transitions occur at successive integer LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size for the AD7991/AD7995/AD7999 is V

/256, respectively. Figure 20 shows the ideal transfer

V

REF

/4096, V

REF

/1024, and

REF

characteristics for the AD7991/AD7995/AD7999.

111 ... 111 111 ... 110

06461-021

AGND

CAPACITIVE

DAC

A

V

IN

SW1

B

SW2

COMPARATOR

CONTROL

LOGIC

06461-020

Figure 18. ADC Acquisition Phase

111 ... 000

011 ... 111

ADC CODE

000 ... 010 000 ... 001 000 ... 000

AGND + 1 LSB

AD7991 1 LSB = REFIN/4096 AD7995 1 LSB = REF AD7999 1 LSB = REF

+REF

ANALOG INPUT

0V TO REF

IN IN

– 1 LSB

IN

/1024 /256

06461-022

Figure 20. AD7991/AD7995/AD7999 Transfer Characteristics

Rev. A | Page 17 of 28

AD7991/AD7995/AD7999

V

TYPICAL CONNECTION DIAGRAM

Figure 22 shows the typical connection diagram for the AD7991/AD7995/AD7999.

The reference voltage can be taken from the supply voltage,

. However, the AD7991/AD7995/AD7999 can be configured

V

DD

to be a 3-channel device with the reference voltage applied to the V the V

SDA and SCL form the 2-wire I pull-up resistors are required for both the SDA and SCL lines.

The AD7991-0/AD7995-0 and the AD7991-1/AD7995-1/ AD7999-1 support standard, fast, and high speed I modes. Both the -0 and -1 devices have independent I which allows the devices to connect to the same I contention issues.

The part requires approximately 0.6 µs to wake up from powerdown and to acquire the analog input. Once the acquisition phase ends, the conversion phase starts and takes approximately 1 µs to complete. The AD7991/AD7995/AD7999 enters shutdown mode after each conversion, which is useful in applications where power consumption is a concern.

pin. In this case, a 1 F decoupling capacitor on

IN3/VREF

pin is recommended.

IN3/VREF

2

C compatible interface. External

IN0 IN1 IN2 IN3/VREF

GND

Figure 22. AD7991/AD7995/AD7999 Typical Connection Diagram

2

C interface

2

C addresses,

2

C bus without

10µF 0.1µF

V

DD

SDA

AD7991/ AD7995/ AD7999

SCL

ANALOG INPUT

Figure 21 shows an equivalent circuit of the AD7991/AD7995/ AD7999 analog input structure. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 300 mV. If the signal does exceed this level, the diodes become forward-biased and start conducting current into the substrate. Each diode can conduct a maximum current of 10 mA without causing irreversible damage to the part.

DD

D1

IN

C1

4pF

D2

CONVERSION PHASE—SWITCH OPEN TRACK PHASE—SWITCH CLOSE D

R1

Figure 21. Equivalent Analog Input Circuit

Capacitor C1 in Figure 21 is typically about 4 pF and can primarily be attributed to pin capacitance. Resistor R1 is a lumped component composed of the on resistance (R both a track-and-hold switch and the input multiplexer. The total resistor is typically about 400 Ω. Capacitor C2, the ADC sampling capacitor, has a typical capacitance of 30 pF.

RPR

5V SUPPLY

2-WIRE SERIAL INTERFACE

MICROCONTROLLER/ MICROPROCESSOR

06461-024

++

P

C2

30pF

ON

) of

06461-023

Rev. A | Page 18 of 28

AD7991/AD7995/AD7999

For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC bandpass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application.

When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of THD that can be tolerated. THD increases as the source impedance increases and performance degrades. Figure 23 shows the THD vs. the analog input signal frequency for different source impedances at a supply voltage of 5 V.

0

–10

–20

–30

–40

–50

THD (dB)

–60

–70

–80

–90

–100

1 10 100

ANALOG INPUT FREQUENCY ( kHz)

VDD = 5V

= V

V

REF

DD

TEMPERATURE = T

f

= 1.7MHz

SCL

5.1kΩ

2kΩ

1.3kΩ

240Ω 56Ω

A

Figure 23. THD vs. Analog Input Frequency for Various Source Impedances

= 5 V, f

for V

DD

= 1.7 MHz Without Clock Stretching

SCL

6461-025

Rev. A | Page 19 of 28

AD7991/AD7995/AD7999

INTERNAL REGISTER STRUCTURE

CONFIGURATION REGISTER

The configuration register is an 8-bit write-only register that is used to set the operating modes of the AD7991/AD7995/AD7999. The bit functions are outlined in Ta b le 1 0. A single-byte write is necessary when writing to the configuration register. D7 is the MSB. When the master writes to the AD7991/AD7995/AD7999, the first byte is written to the configuration register.

Table 9. Configuration Register Bit Map and Default Settings at Power-Up

D7 D6 D5 D4 D3 D2 D1 D0

CH3 CH2 CH1 CH0 REF_SEL FLTR Bit trial delay Sample delay 1 1 1 1 0 0 0 0

Table 10. Bit Function Descriptions

Bit Mnemonic Comment

D7 to D4 CH3 to CH0

D3 REF_SEL

D2 FLTR

D1 Bit trial delay See the Sample Delay and Bit Trial Delay section. D0 Sample delay See the Sample Delay and Bit Trial Delay section.

These four channel address bits select the analog input channel(s) to be converted. If a channel address bit (Bit D7 to Bit D4) is set to 1, a channel is selected for conversion. If more than one channel bit is set to 1, the AD7991/AD7995/AD7999 sequence through the selected channels, starting with the lowest channel. All unused channels should be set to 0. Table 11 shows how these four channel address bits are decoded. Prior to the device initiating a conversion, the channel(s) must be selected in the configuration register.

This bit allows the user to select the supply voltage as the reference or choose to use an external reference. If this bit is 0, the supply is used as the reference, and the device acts as a 4-channel input part. If this bit is set to 1, an external reference must be used and applied to the V

pin, and the device acts as a 3-channel

IN3/VREF

input part. The value written to this bit of the control register determines whether the filtering on SDA and SCL is

enabled or bypassed. If this bit is set to 0, the filtering is enabled; if it set to 1, the filtering is bypassed.

Table 11. Channel Selection

D7 D6 D5 D4 Analog Input Channel1

0 0 0 0 No channel selected 0 0 0 1 Convert on V 0 0 1 0 Convert on V 0 0 1 1 Sequence between V 0 1 0 0 Convert on V 0 1 0 1 Sequence between V 0 1 1 0 Sequence between V 0 1 1 1 Sequence among V 1 0 0 0 Convert on V 1 0 0 1 Sequence between V 1 0 1 0 Sequence between V 1 0 1 1 Sequence among V 1 1 0 0 Sequence between V 1 1 0 1 Sequence among V 1 1 1 0 Sequence among V 1 1 1 1 Sequence among V

1

The AD7991/AD7995/AD7999 converts on the selected channel in the sequence in ascending order, starting with the lowest channel in the sequence.

IN0

IN1

and V

IN0

IN2

and V

IN0

and V

IN1

, V

IN0

IN3

and V

IN0

and V

IN1

, V

IN0

and V

IN2

, V

IN0

, V

IN1

, V

IN0

IN1

IN2

IN1

IN2

, and V

IN3

, and V

IN3

, and V , and V , V

, and V

IN2

IN3

Rev. A | Page 20 of 28

AD7991/AD7995/AD7999

SAMPLE DELAY AND BIT TRIAL DELAY

It is recommended that no I2C bus activity occur while a conversion is taking place (see Figure 27 and the Placing the AD7991/AD7995/AD7999 into High Speed Mode section). However, if this is not always possible, then in order to maintain the performance of the ADC, Bits D0 and D1 in the configuration register are used to delay critical sample intervals and bit trials from occurring while there is activity on the I a quiet period for each bit decision. However, the sample delay protection may introduce excessive jitter, degrading the SNR for large signals above 300 Hz. For guaranteed ac performance, use of clock stretching is recommended.

When Bit D0 and Bit D1 are both 0, the bit trial and sample interval delay mechanism is implemented. The default setting of D0 and D1 is 0. To turn off both delay mechanisms, set D0 and D1 to 1.

Table 12. Conversion Value Register (First Read)

D15 D14 D13 D12 D11 D10 D9 D8

Leading 0 Leading 0 CH

Table 13. Conversion Value Register (Second Read)

D7 D6 D5 D4 D3 D2 D1 D0

B7 B6 B5 B4 B3/0 B2/0 B1/0 B0/0

2

C bus. This results in

CH

ID1

MSB B10 B9 B8

ID0

CONVERSION RESULT REGISTER

The conversion result register is a 16-bit read-only register that stores the conversion result from the ADC in straight binary format. A 2-byte read is necessary to read data from this register. Tabl e 12 shows the contents of the first byte to be read from AD7991/AD7995/AD7999, and Tabl e 13 shows the contents of the second byte to be read.

Each AD7991/AD7995/AD7999 conversion result consists of two leading 0s, two channel identifier bits, and the 12-/10-/8-bit data result. For the AD7995, the two LSBs (D1 and D0) of the second read contain two trailing 0s. For the AD7999, the four LSBs (D3, D2, D1, and D0) of the second read contain four trailing 0s.

Rev. A | Page 21 of 28

AD7991/AD7995/AD7999

SERIAL INTERFACE

Control of the AD7991/AD7995/AD7999 is accomplished via

2

C-compatible serial bus. The AD7991/AD7995/AD7999 is

the I connected to this bus as a slave device under the control of a master device, such as the processor.

SERIAL BUS ADDRESS

Like all I2C-compatible devices, the AD7991/AD7995/AD7999 has a 7-bit serial address. The devices are available in two versions, the AD7991-0/AD7995-0 and the AD7991-1/AD7995-1/AD7999-1. Each version has a different address (see Tab le 8), which allows up to two AD7991/AD7995 devices to be connected to a single serial bus. AD7999 has only one version.

The serial bus protocol operates as follows:

The master initiates a data transfer by establishing a start

1. condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line, SCL, remains high. This indicates that an address/data stream follows.

2.

All slave peripherals connected to the serial bus respond to

the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/

the direction of the data transfer—that is, whether data is written to or read from the slave device.

The peripheral whose address corresponds to the transmitted

3. address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/

the slave device. If the R/

bit is set to 0, the master writes to

W

bit is set to 1, the master reads

W

from the slave device.

bit that determines

W

4.

Data is sent over the serial bus in sequences of nine clock

pulses—eight bits of data followed by an acknowledge bit from the receiver of data. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to-high transition when the clock is high may be interpreted as a stop signal.

When all data bytes have been read or written, stop conditions

5. are established. In write mode, the master pulls the data line

th

high during the 10

clock pulse to assert a stop condition. In read mode, the master device pulls the data line high during the low period before the ninth clock pulse. This is known as a no acknowledge. The master takes the data line

th

low during the low period before the 10 then high during the 10

6.

Any number of bytes of data can be transferred over the serial

th

clock pulse to assert a stop condition.

clock pulse, and

bus in one operation, but it is not possible to mix reads and writes in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.

Rev. A | Page 22 of 28

AD7991/AD7995/AD7999

WRITING TO THE AD7991/AD7995/AD7999

By default, each part operates in read-only mode and all four channels are selected as enabled in the configuration register. To write to the AD7991/AD7995/AD7999 configuration register, the user must first address the device.

1

SCL

The configuration register is an 8-bit register; therefore, only one byte of data can be written to this register. However, writing a single byte of data to this register consists of writing the serial bus write address, followed by the data byte written (see Figure 24).

991

SDA START BY

MASTER

0 0 0 0 A0 D7 D6 D5 D4 D3 D2 D1 D011

FRAME 1

SERIAL BUS ADDRESS BY TE

Figure 24. Writing to the AD7991/AD7995/AD7999 Configuration Register

R/W

ACK BY

ADC

CONFIGURATION REGI S TER BYTE

ACK BY

ADC

STOP

06461-026

Rev. A | Page 23 of 28

AD7991/AD7995/AD7999

READING FROM THE AD7991/AD7995/AD7999

Reading data from the conversion result register is a 2-byte operation, as shown in Figure 25. Therefore, a read operation always involves two bytes.

After the AD7991/AD7995/AD7999 have received a read address, any number of reads can be performed from the conversion result register.

Following a start condition, the master writes the 7-bit address of the AD7991/AD7995/AD7999 and then sets R/

to 1. The

W

AD7991/AD7995/AD7999 acknowledge this by pulling the SDA line low. They then output the conversion result over the

2

I

C bus, preceded by four status bits. The status bits are two leading 0s followed by the channel identifier bits. For the AD7995 there are two trailing 0s, and for the AD7999 there are four trailing 0s.

After the master has addressed the AD7991/AD7995/AD7999, the part begins to power up on the ninth SCLK rising edge. At the same time, the acquisition phase begins. When approximately

0.6 µs have elapsed, the acquisition phase ends. The input is sampled and a conversion begins. This is done in parallel to the

119 9

SCL

read operation and should not affect the read operation. The master reads back two bytes of data. On the ninth SCLK rising edge of the second byte, if the master sends an ACK, it keeps reading conversion results and the AD7991/AD7995/AD7999 powers up and performs a second conversion. If the master sends a NO ACK, the AD7991/AD7995/AD7999 does not power up on the ninth SCLK rising edge of the second byte. If a further conversion is required, the part converts on the next channel, as selected in the configuration register. See Table 11 for information about the channel selection.

If the master sends a NO ACK on the ninth SCLK rising edge of the second byte, the conversion is finished and no further conversion is preformed.

To put the part into full shutdown mode, the user should issue a stop condition to the AD7991/AD7995/AD7999. If the AD7991/ AD7995/AD7999 is not put into full shutdown mode, it will draw a few tens of microamperes from the supply.

SDA

START BY

MASTER

1 D11

FRAME 1

SERIAL BUS ADDRESS BYTE

SCL (CONTINUED)

SDA (CONTINUED)

Figure 25. Reading Two Bytes of Data from the AD7991Conversion Result Register

R/W

ACK BY

ADC

CH

ID1CHID0

MOST SIG NI F ICANT DATA BYTE FROM ADC

1

D7 D6 D5 D2 D1 D0D4 D3

LEAST SIGNIFICANT DATA BYTE FROMADC

FRAME 2

FRAME 3

D10 D9 D8A01000 000

ACK BY

MASTER

9

NO ACK BY

MASTER

STOP BY

MASTER

06461-027

Rev. A | Page 24 of 28

AD7991/AD7995/AD7999

S

PLACING THE AD7991/AD7995/AD7999 INTO HIGH SPEED MODE

High speed mode communication commences after the master addresses all devices connected to the bus with the master code, 00001XXX, to indicate that a high speed mode transfer is to begin. No device connected to the bus is allowed to acknowledge the high speed master code; therefore, the code is followed by a NO ACK (see Figure 26). The master must then issue a repeated start, followed by the device address and an R/

bit. The selected

W

device then acknowledges its address.

191 9

SCL

FAS T MODE

All devices continue to operate in high speed mode until the master issues a stop condition. When the stop condition is issued, the devices return to fast mode.

To guarantee performance above f

= 1.7 MHz, the user must

SCL

perform clock stretching—that is, the clock must be held high—for 2 µs after the ninth clock rising edge (see Figure 27). Therefore, the clock must be held high for 2 µs after the device starts to power up (see the Reading from the AD7991/AD7995/AD7999 section).

HIGH SPEED MODE

SDA

START BY

MASTER

0

HS MODE MASTE R CODE SERIAL BUS ADDRESS BYT E

X

NO ACK

01 0 0A0XX1000

Sr

1

0

ACK BY

ADC

6461-028

Figure 26. Placing the Part into High Speed Mode

CLOCK HIGH TIME = 2µs

119 9

SCL

FRAME 2

FRAME 3

D10 D9 D8A01000 000

ACK BY

MASTER

9

NO ACK BY

MASTER

STOP BY MASTER

06461-030

DA

START BY

MASTER

1 D11

FRAME 1

SERIAL BUS ADDRESS BYT E

SCL (CONTINUE D)

SDA (CONTINUED)

R/W

ACK BY

ADC

CH

ID1CHID0

MOST SIGNIFICANT DATA BYTE FROMADC

1

D7 D6 D5 D2 D1 D0D4 D3

LEAST SIG NI FICANT DATA BYTE FROM ADC

Figure 27. Reading Two Bytes of Data from the Conversion Result Register in High Speed Mode for AD7991

Rev. A | Page 25 of 28

AD7991/AD7995/AD7999

S

MODE OF OPERATION

The AD7991/AD7995/AD7999 powers up in shutdown mode. After the master addresses the AD7991/AD7995/AD7999 with

2

the correct I

C address, the ADC acknowledges the address. In

response, the AD7991/AD7995/AD7999 power up.

During this wake up time, the AD7991/AD7995/AD7999 exit shutdown mode and begin to acquire the analog input (acquisition phase). By default, all channels are selected. Which channels are converted depends on the status of the channel bits in the configuration register.

When the read address is acknowledged, the ADC outputs two bytes of conversion data. The first byte contains four status bits and the four MSBs of the conversion result. The status bits contain two leading 0s and two channel-identifier bits. After this first byte, the AD7991/AD7995/AD7999 outputs the

SCL

1199 9

second byte of the conversion result. For the AD7991, this second byte contains the lower eight bits of conversion data. For the AD7995, this second byte contains six bits of conversion data plus two trailing 0s. For the AD7999, this second byte contains four bits of conversion data and four trailing 0s.

The master then sends a NO ACK to the AD7991/AD7995/ AD7999, as long as no further reads are required. If the master instead sends an ACK to the AD7991/AD7995/AD7999, the ADC powers up and completes another conversion. When more than one channel bit has been set in the configuration register, this conversion is performed on the second channel in the selected sequence. If only one channel is selected, the ADC converts again on the selected channel.

DA

Sr RA A

7-BIT ADDRESS

ACK. BY

ADC

Figure 28. Mode of Operation, Single-Channel Conversion

FIRST DAT A BY TE

(MSB)

ACK. BY MASTER

SECOND DATA BYTE

(LSB)

A

Sr/P

NO ACK. BY

MASTER

06461-029

Rev. A | Page 26 of 28

AD7991/AD7995/AD7999

0

OUTLINE DIMENSIONS

3.00

2.90

2.80

76

1.70

1.60

1.50

PIN 1

INDICATOR

1.30

1.15

0.90

.15 MAX .05 MIN

8

1234

1.95 BSC

5

0.38 MAX

0.22 MIN

0.65 BSC

1.45 MAX

0.95 MIN

3.00

2.80

2.60

SEATING PLANE

0.22 MAX

0.08 MIN

8°

0.60

4°

BSC

0°

0.60

0.45

0.30

COMPLIANT TO JEDEC STANDARDS MO-178-BA

121608-A

Figure 29. 8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD7991YRJZ-1RL1 −40°C to +125°C 8-Lead SOT-23 RJ-8 C56 AD7991YRJZ-1500RL71 −40°C to +125°C 8-Lead SOT-23 RJ-8 C56 AD7991YRJZ-0RL AD7991YRJZ-0500RL7 AD7995YRJZ-1RL AD7995YRJZ-1500RL7 AD7995YRJZ-0RL AD7995YRJZ-0500RL7 AD7995ARJZ-0RL AD7999YRJZ-1RL AD7999YRJZ-1500RL7 AD7999ARJZ-1RL EVAL-AD7991EBZ

1

Z = RoHS Compliant Part.

1

−40°C to +125°C 8-Lead SOT-23 RJ-8 C55

1

−40°C to +125°C 8-Lead SOT-23 RJ-8 C55

1

−40°C to +125°C 8-Lead SOT-23 RJ-8 C58

1

−40°C to +125°C 8-Lead SOT-23 RJ-8 C58

1

−40°C to +125°C 8-Lead SOT-23 RJ-8 C57

1

−40°C to +125°C 8-Lead SOT-23 RJ-8 C57

1

−40°C to +125°C 8-Lead SOT-23 RJ-8 C6Y

1

−40°C to +125°C 8-Lead SOT-23 RJ-8 C5B

1

−40°C to +125°C 8-Lead SOT-23 RJ-8 C5B

1

−40°C to +125°C 8-Lead SOT-23 RJ-8 C70

1

Evaluation Board

Rev. A | Page 27 of 28

AD7991/AD7995/AD7999

NOTES

Rev. A | Page 28 of 28

Datasheet AD7991, AD7995, AD7999 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

I2C TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

THEORY OF OPERATION

CONVERTER OPERATION

ADC Transfer Function

TYPICAL CONNECTION DIAGRAM

ANALOG INPUT

INTERNAL REGISTER STRUCTURE

CONFIGURATION REGISTER

SAMPLE DELAY AND BIT TRIAL DELAY

CONVERSION RESULT REGISTER

SERIAL INTERFACE

SERIAL BUS ADDRESS

WRITING TO THE AD7991/AD7995/AD7999

READING FROM THE AD7991/AD7995/AD7999

PLACING THE AD7991/AD7995/AD7999 INTO HIGH SPEED MODE

MODE OF OPERATION

OUTLINE DIMENSIONS

ORDERING GUIDE