Datasheet AD7988-5 Datasheet (ANALOG DEVICES)

PulSAR ADCs in MSOP/LFCSP (QFN)

AD7988-1/AD7988-5

Rev. B

Trademarks and registered trademarks are the prop erty of their respective owner s.

Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.

REF

GND

VDD

IN+
IN–

VIO

SDI
SCK
SDO
CNV

1.8V TO 5.5V

3- OR 4-WI RE INTERFACE
(SPI, DAISY CHAIN, CS)

2.5V TO 5V 2.5V

0V TO V

REF

10231-001

AD7988-1/
AD7988-5

Data Sheet

FEATURES

Low power dissipation

AD7988-5: 3.5 mW @ 500 kSPS

AD7988-1: 700 µW @ 100 kSPS

16-bit resolution with no missing codes
Throughput: 100 kSPS/500 kSPS options
INL: ±0.6 LSB typical, ±1.25 LSB maximum
SINAD: 91.5 dB @ 10 kHz
THD: −114 dB @ 10 kHz
Pseudo differential analog input range

0 V to V

Any input range and easy to drive with the ADA4841-1
No pipeline delay
Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V

logic interface
SPI-/QSPI-/MICROWIRE™-/DSP-compatible serial interface
Daisy-chain multiple ADCs
10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP (QFN),

same space as SOT-23
Wide operating temperature range: −40°C to +125°C

APPLICATIONS

Battery-powered equipment
Low power data acquisition systems
Portable medical instruments
ATE equipment
Data acquisitions
Communications

with V

REF

from 2.5 V to 5.5 V

REF

16-Bit Lower Power

GENERAL DESCRIPTION

The AD7988-1/AD7988-5 are 16-bit, successive approximation,
analog-to-digital converters (ADC) that operate from a single
power supply, VDD. The AD7988-1 offers a 100 kSPS throughput,
and the AD7988-5 offers a 500 kSPS throughput. They are low
power, 16-bit sampling ADCs with a versatile serial interface
port. On the CNV rising edge, they sample an analog input,
IN+, between 0 V to V
The reference voltage, REF, is applied externally and can be set
independent of the supply voltage, VDD.

The SPI-compatible serial interface also features the ability to
daisy-chain several ADCs on a single 3-wire bus using the SDI
input. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using
the separate supply, VIO.

The AD7988-1/AD7988-5 generics are housed in a 10-lead
MSOP or a 10-lead LFCSP (QFN) with operation specified
from −40°C to +125°C.

Table 1. MSOP, LFCSP (QFN) 14-/16-/18-Bit PulSAR® ADCs

Bits 100 kSPS 250 kSPS

181 AD76912 AD76902 AD79822

161 AD7684 AD76872 AD76882

163 AD7680

AD7683
AD7988-1

143 AD7940 AD79422 AD79462 ADA4841-1

1

True differential.

2

Pin-for-pin compatible.

3

Pseudo differential.

2

with respect to a ground sense, IN−.

REF

AD7685
AD7694

2

400 kSPS to
500 kSPS

AD7693
AD76862
AD7988-5

≥1000
kSPS

AD7984

ADA4941-1

2

AD7980

2

ADC Driver

ADA4941-1

2

ADA4841-1

ADA4841-1

2

ADA4841-1

ADA4841-1
ADA4841-1

TYPICAL APPLICATION DIAGRAM

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com

AD7988-1/AD7988-5 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Typical Application Diagram .......................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings ............................................................ 7

ESD Caution .................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Terminology ...................................................................................... 9

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 14

Circuit Information .................................................................... 14

Converter Operation .................................................................. 14

Typical Connection Diagram ................................................... 15

Analog Inputs ............................................................................. 16

Driver Amplifier Choice ........................................................... 16

Voltage Reference Input ............................................................ 17

Power Supply ............................................................................... 17

Digital Interface .......................................................................... 17

CS

Mode, 3-Wire ........................................................................ 18

CS

Mode 4-Wire ......................................................................... 19

Chain Mode ................................................................................ 20

Applications Information .............................................................. 21

Interfacing to Blackfin® DSP ..................................................... 21

Layout .......................................................................................... 21

Evaluating the Performance of the AD7988-x ........................ 21

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 23

REVISION HISTORY

5/12—Rev. A to Rev. B

Changes to Table 3 ............................................................................. 4

Updated Outline Dimensions ........................................................ 22

2/12—Rev. 0 to R e v. A

Added LFCSP Thermal Impedance Values ................................... 7

Updated Outline Dimensions ....................................................... 23

Changes to Ordering Guide .......................................................... 23

2/12—Revision 0: Initial Ve rs i on

Rev. B | Page 2 of 24

Data Sheet AD7988-1/AD7988-5

Absolute Input Voltage

IN+

−0.1 V

+ 0.1

V

Integral Linearity Error

V

= 5 V

−1.25

±0.6

+1.25

LSB1

Gain Error Temperature Drift

±0.35

ppm/°C

Transient Response

Full-scale step

500

ns

fIN = 10 kHz, V

= 2.5 V

87.0 dB3

SPECIFICATIONS

VDD = 2.5 V, VIO = 2.3 V to 5.5 V, V

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

RESOLUTION 16 Bits
ANALOG INPUT

Voltage Range IN+ − IN− 0 V

IN− −0.1 +0.1 V
Analog Input CMRR fIN = 1 kHz 60 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance See the Analog Inputs section

ACCURACY

No Missing Codes 16 Bits
Differential Linearity Error V
V

V
Transition Noise V
V
Gain Error, T

MIN

2

to T

±2 LSB1

MAX

= 5 V, TA = –40°C to +125°C, unless otherwise noted.

REF

REF

REF

= 5 V −0.9 ±0.4 +0.9 LSB1

REF

= 2.5 V ±0.55 LSB1

REF

REF

= 2.5 V ±0.65 LSB1

REF

= 5 V 0.6 LSB1

REF

= 2.5 V 1.0 LSB1

REF

V

Zero Error, T

MIN

2

to T

−0.5 ±0.08 +0.5 mV

MAX

Zero Temperature Drift 0.54 ppm/°C
Power Supply Sensitivity

VDD = 2.5 V ± 5%

±0.1 LSB1

THROUGHPUT

AD7988-1

Conversion Rate

VIO ≥ 2.3 V up to 85°C, VIO ≥ 3.3 V above 85°C up to

0 100 kSPS

125°C

AD7988-5

Conversion Rate

VIO ≥ 2.3 V up to 85°C, VIO ≥ 3.3 V above 85°C up to

0 500 kSPS

125°C

Transient Response Full-scale step 400 ns

AC ACCURACY

Dynamic Range V
V

= 5 V 92 dB3

REF

= 2.5 V 87 dB3

REF

Oversampled Dynamic Range fO = 10 kSPS 111 dB3
Signal-to-Noise Ratio, SNR fIN = 10 kHz, V
fIN = 10 kHz, V

= 5 V 90 91 dB3

REF

= 2.5 V 86.5 dB3

REF

Spurious-Free Dynamic Range, SFDR fIN = 10 kHz −110 dB3
Total Harmonic Distortion, THD fIN = 10 kHz −114 dB3
Signal-to-(Noise + Distortion), SINAD fIN = 10 kHz, V

1

LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV.

2

See the Terminology section. These specifications include full temperature range variation, but not the error contribution from the external reference.

3

All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

= 5 V 91.5 dB3

REF

REF

Rev. B | Page 3 of 24

AD7988-1/AD7988-5 Data Sheet

POWER SUPPLIES

AD7988-1 Power Dissipation

10 kSPS throughput

70 µW

VDD = 2.5 V, VIO = 2.3 V to 5.5 V, V

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

REFERENCE

Voltage Range 2.4 5.1 V

Load Current V
SAMPLING DYNAMICS

−3 dB Input Bandwidth 10 MHz

Aperture Delay VDD = 2.5 V 2.0 ns
DIGITAL INPUTS

Logic Levels

VIL VIO > 3 V –0.3 0.3 × VIO V
VIH VIO > 3 V 0.7 × VIO VIO + 0.3 V
VIL VIO ≤ 3 V –0.3 0.1 × VIO V
VIH VIO ≤ 3 V 0.9 × VIO VIO + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA

DIGITAL OUTPUTS

Data Format Serial 16 bits straight binary

Pipeline Delay

VOL I
VOH I

= 5 V, TA = –40°C to +125°C, unless otherwise noted.

REF

= 5 V 250 µA

REF

Conversion results available immediately

after completed conversion

= 500 µA 0.4 V

SINK

= −500 µA VIO − 0.3 V

SOURCE

VDD 2.375 2.5 2.625 V

VIO Specified performance 2.3 5.5 V

VIO Range 1.8 5.5 V

Standby Current

1, 2

VDD and VIO = 2.5 V, 25°C 0.35 nA

100 kSPS throughput 700 µW

1 mW

AD7988-5 Power Dissipation 500 kSPS throughput 3.5 5 mW

Energy per Conversion 7.0 nJ/sample
TEMPERATURE RANGE

Specified Performance T

1

With all digital inputs forced to VIO or GND as required.

2

During the acquisition phase.

MIN

to T

−40 +125 °C

MAX

Rev. B | Page 4 of 24

Data Sheet AD7988-1/AD7988-5

AD7988-5

SCK Period (Chain Mode)

t

SCK High Time

t

4.5

ns

SDI Valid Setup Time from CNV Rising Edge

t

5

ns

TIMING SPECIFICATIONS

VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, −40°C to +125°C unless otherwise stated. See Figure 2 and Figure 3 for load conditions.

Table 4.

Parameter Symbol Min Typ Max Unit

AD7988-1

Throughput Rate 100 kHz
Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time Between Conversions t

Throughput Rate 500 kHz
Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t

Time Between Conversions t
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)

VIO Above 4.5 V 10.5 ns
VIO Above 3 V 12 ns
VIO Above 2.7 V 13 ns
VIO Above 2.3 V 15 ns

VIO Above 4.5 V 11.5 ns
VIO Above 3 V 13 ns
VIO Above 2.7 V 14 ns
VIO Above 2.3 V 16 ns

SCK Low Time t

SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t

VIO Above 4.5 V 9.5 ns
VIO Above 3 V 11 ns
VIO Above 2.7 V 12 ns
VIO Above 2.3 V 14 ns

CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO Above 3 V 10 ns
VIO Above 2.3V 15 ns

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)

SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode) t
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t

9.5 μs

CONV

500 ns

ACQ

10 μs

CYC

1.6 μs

CONV

400 ns

ACQ

2 μs

CYC

t

500 ns

CNVH

t

SCK

SCK

4.5 ns

SCKL

SCKH

3 ns

HSDO

DSDO

t

EN

t

20 ns

DIS

SSDICNV

t

2 ns

HSDICNV

0 ns

HSDICNV

5 ns

SSCKCNV

5 ns

HSCKCNV

2 ns

SSDISCK

3 ns

HSDISCK

Rev. B | Page 5 of 24

AD7988-1/AD7988-5 Data Sheet

500µA I

OL

500µA I

OH

1.4V

TO SDO

C

L

20pF

10231-002

X% VIO

1

Y% VIO

1

V

IH

2

V

IL

2

V

IL

2

V

IH

2

t

DELAY

t

DELAY

1

FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.

2

MINIMUM V

IH

AND MAXIMUM VIL USED. SEE DIGITAL INPUTS

SPECIFICATIONS IN TABLE 3.

10231-003

Figure 2. Load Circuit for Digital Interface Timing

Figure 3. Voltage Levels for Timing

Rev. B | Page 6 of 24

Data Sheet AD7988-1/AD7988-5

IN+,1 IN−1 to GND

−0.3 V to V

+ 0.3 V or ±130 mA

Digital Outputs to GND

−0.3 V to VIO + 0.3 V

θJC Thermal Impedance

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs

REF

Supply Voltage

REF, VIO to GND −0.3 V to +6 V
VDD to GND −0.3 V to +3 V
VDD to VIO +3 V to −6 V

Digital Inputs to GND −0.3 V to VIO + 0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Storage Temperature Range −65°C to +125°C
Junction Temperature 150°C
θJA Thermal Impedance

10-Lead MSOP 200°C/W
10-Lead LFCSP 80°C/W

10-Lead MSOP 44°C/W
10-Lead LFCSP 15°C/W

Reflow Soldering JEDEC Standard (J-STD-020)

1

See the Analog Inputs section.

ESD CAUTION

Rev. B | Page 7 of 24

AD7988-1/AD7988-5 Data Sheet

REF

1

VDD

2

IN+

3

IN–

4

GND

5

VIO

10

SDI

9

SCK

8

SDO

7

CNV

6

10231-004

AD7988-1/
AD7988-5

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPOSED P

AD CAN BE CONNECTED TO GND.

1REF
2VDD
3IN+
4IN–
5GND

10 VIO
9 SDI
8 SCK
7 SDO
6 CNV

10231-005

AD7988-1/
AD7988-5

TO

P VI

EW

(Not to Scale)

6

CNV

DI

9

SDI

DI

Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 4. 10-Lead MSOP Pin Configuration

Figure 5. 10-Lead LFCSP (QFN) Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1 REF AI

Reference Input Voltage. The V

range is from 2.4 V to 5.1 V. It is referred to the GND pin. The GND pin

REF

should be decoupled closely to the REF pin with a 10 µF capacitor.
2 VDD P Power Supply.
3 IN+ AI

Analog Input. It is referred to IN−. The voltage range, for example, the difference between IN+ and IN−, is

REF

.

0 V to V
4 IN− AI Analog Input Ground Sense. Connect to the analog ground plane or to a remote sense ground.
5 GND P Power Supply Ground.

Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and

selects the interface mode of the part: chain mode or

CS mode. In CS mode, the SDO pin is enabled when

CNV is low. In chain mode, the data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.

follows:

Chain mode is selected if this pin is low during the CNV rising edge. In this mode, SDI is used as a data

input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data

level on SDI is output on SDO with a delay of 16 SCK cycles.

CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable

the serial output signals when low.
10 VIO P

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,

or 5 V).
EP Exposed Pad. The exposed pad can be connected to GND.

1

AI = analog input, DI = digital input, DO = digital output, and P = power.

Rev. B | Page 8 of 24

Data Sheet AD7988-1/AD7988-5

TERMINOLOGY

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 30).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.

Offset Error

The first transition should occur at a level ½ LSB above analog
ground (38.1 µV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.

Gain Error

The last transition (from 111 … 10 to 111 … 11) should
occur for an analog voltage 1½ LSB below the nominal full
scale (4.999886 V for the 0 V to 5 V range). The gain error is
the deviation of the actual level of the last transition from the
ideal level after the offset is adjusted out.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:

ENOB = (SINAD

− 1.76)/6.02

dB

and is expressed in bits.

Noise-Free Code Resolution

Noise-free code resolution is the number of bits beyond which
it is impossible to distinctly resolve individual codes. It is
calculated as

Noise-Free Code Resolution = log

(2N/Peak-to-Peak Noise)

2

and is expressed in bits.

Effective Resolution

Effective resolution is calculated as

Effective Resolution = log

(2N/RMS Input Noise)

2

and is expressed in bits.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in dB. It is measured
with a signal at −60 dBFS to include all noise sources and DNL
artifacts.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.

Signal-to-(Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.

Aperture Delay

Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.

Transient Response

Transient response is the time required for the ADC to
accurately acquire its input after a full-scale step function is
applied.

Rev. B | Page 9 of 24

AD7988-1/AD7988-5 Data Sheet

0

–180

FREQUENCY (kHz)

–20

–40

–60

–80

–100

–120

–140

–160

f

S

= 500kSPS

f

IN

= 10kHz
SNR = 91.17dB
THD = –113.63dB
SFDR = 110.30dB
SINAD = 91.15dB

AMPLITUDE (dB of FULL SCALE)

0 50 100 150 200 250

10231-046

0

–180

FREQUENCY (kHz)

–20

–40

–60

–80

–100

–120

–140

–160

f

S

= 500kSPS

f

IN

= 10kHz
SNR = 86.8dB
THD = –111.4dB
SFDR = 105.9dB
SINAD = 86.8dB

AMPLITUDE (dB of FULL SCALE)

0 50 100 150 200 250

10231-047

0

–180

FREQUENCY (kHz)

–20

–40

–60

–80

–100

–120

–140

–160

f

S

= 100kSPS

f

IN

= 10kHz
SNR = 91.09dB
THD = –113.12dB
SFDR = 110.30dB
SINAD = 91.05dB

AMPLITUDE (dB of FULL SCALE)

0 10 20 30 40 50

10231-048

0

–180

FREQUENCY (kHz)

–20

–40

–60

–80

–100

–120

–140

–160

f

S

= 100kSPS

f

IN

= 10kHz
SNR = 86.7dB
THD = –110.4dB
SFDR = 103.9dB
SINAD = 86.6dB

AMPLITUDE (dB of FULL SCALE)

0 10 20 30 40 50

10231-049

1.25

–1.25

CODE

INL (LSB)

1.00

0.75

0.50

0.25

–

0.25

–0.75

0

–0.50

–1.00

POSITIVE INL: +0.40 LSB
NE

GATIVE INL: –0.35 LSB

0 16384 32768 49152 65536

10231-010

1.25

1.00

–1.25

–1.00

INL (LSB)

0.7

5

0.50

0.25

–0.25

–0.75

0

–

0.50

POSITIVE INL: +0.45 LS

B

NEGATIVE INL: –0.29 LSB

CODE

0 16384 32768 49152 65536

10231-011

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = 2.5 V, V

= 5.0 V, VIO = 3.3 V, unless otherwise noted.

REF

Figure 6. AD7988-5 FFT Plot, V

Figure 7. AD7988-5 FFT Plot, V

= 5 V

REF

= 2.5 V

REF

Figure 9. AD7988-1 FFT Plot, V

= 2.5 V

REF

Figure 10. Integral Nonlinearity vs. Code, V

REF

= 5 V

Figure 8. AD7988-1 FFT Plot, V

REF

= 5 V

Figure 11. Integral Nonlinearity vs. Code, V

= 2.5 V

REF

Rev. B | Page 10 of 24

Data Sheet AD7988-1/AD7988-5

CODE

0 16384 32768 49152 65536

1.00

–1.00

DNL (LSB)

0.75

0.50

0.25

–0.25

–0.75

0

–0.

50

PO

SITIVE INL: +0.18 LSB

NEGATIVE INL: –0.21 LSB

10231-012

CODE

0 16384 32768 49152 65536

1.00

–1.00

DNL (LSB)

0.75

0.50

0.25

–0.25

–0.75

0

–0.50

POSITIVE INL: +0.25 LSB
NEGATIVE INL: –0.22 LSB

10231-013

180k

0

000 0022

CODE IN HEX

COUNTS

8003 8004 8005 8006 8007 8008 8009 800A 800B 800C 800D 800E 800F

1291

852

29

2

10231-050

160k

140k

120k

100k

80k

60k

40k

20k

52720

162595

42731

60k

0

000 0

94 30

1

CODE IN HEX

COUNTS

50k

30k

10k

40k

20k

7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006

2290

18848

50970

45198

12424

1217

10231-015

100

80

85

90

95

REFERENCE VOLTAGE (V)

SNR, SINAD (dB)

16

12

13

14

15

ENOB (Bits)

SNR
SINAD
ENOB

2.25 2.75 3.25 3.75 4.25 4.75 5.25

10231-016

60k

0

000 0

590

11

19

CODE IN HEX

COUNTS

50k

30k

10k

40k

20k

7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006

7285

37417

53412

31540

5807

512

10231-051

Figure 12. Differential Nonlinearity vs. Code, V

Figure 13. Differential Nonlinearity vs. Code, V

REF

= 2.5 V

REF

= 5 V

Figure 15. Histogram of a DC Input at the Code Transition, V

Figure 16. SNR, SINAD, and ENOB vs. Reference Voltage

= 2.5 V

REF

Figure 14. Histogram of a DC Input at the Code Center, V

= 5 V

REF

Figure 17. Histogram of a DC Input at the Code Center, V

= 2.5 V

REF

Rev. B | Page 11 of 24

AD7988-1/AD7988-5 Data Sheet

95

85

87

89

92

91

93

94

86

88

90

INPUT LEVEL (dB OF FULL SCALE)

SNR (dB)

–10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0

10231-018

–95

–125

–110

–115

–105

–100

–120

115

85

100

95

105

110

90

REFERENCE VOLTAGE (V)

THD (dB)

SFDR (dB)

THD

SFDR

2.25 2.75 3.25 3.75 4.25 4.75 5.25

10231-019

100

80

10 1k

FREQUENCY ( kHz )

SINAD (dB)

95

90

85

100

10231-052

10231-053

95

85

89

87

91

93

–55 125

TEMPERATURE (°C)

SNR (dB)

–35 –15 5 25 65 8545 105

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

VDD VOLTAGE (V)

I

VDD

I

REF

I

VIO

CURRENT (mA)

2.375 2.425 2.475 2.525 2.575 2.625

10231-023

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

VDD VOLTAGE (V)

I

VDD

I

REF

I

VIO

CURRENT (mA)

2.375 2.425 2.475 2.525 2.575 2.625

10231-024

Figure 18. SNR vs. Input Level

Figure 19. THD, SFDR vs. Reference Voltage

Figure 21. SNR vs. Temperature

Figure 22. Operating Currents vs. Supply (AD7988-5)

Figure 20. SINAD vs. Frequency

Figure 23. Operating Currents vs. Supply (AD7988-1)

Rev. B | Page 12 of 24

Data Sheet AD7988-1/AD7988-5

10231-054

–85

–125

10 1k

FREQUENCY ( kHz )

THD (dB)

100

–90

–95

–100

–105

–110

–115

–120

–110

–120

THD (dB)

TEMPERATURE (°C)

–112

–114

–116

–118

–55 –35 –15 5 25 45 65 85 105 125

10231-026

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

CURRENT (mA)

I

VDD

I

REF

I

VIO

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

10231-027

0.14

0.12

0.10

008

0.06

0.04

0.02

0

CURRENT (mA)

I

VDD

I

REF

I

VIO

TEMPERATURE (°C)

–55 –35 –15 5 25 45 65 85 105 125

10231-028

8

7

6

5

4

3

2

1

0

CURRENT (µA)

TEMPERATURE (°C)

I

VDD

+ I

VIO

–55 –35 –15 5 25 45 65 85 105 125

10231-029

Figure 24. THD vs. Frequency

Figure 25. THD vs. Temperature

Figure 27. Operating Currents vs. Temperature (AD7988-1)

Figure 28. Power-Down Currents vs. Temperature

Figure 26. Operating Currents vs. Temperature (AD7988-5)

Rev. B | Page 13 of 24

AD7988-1/AD7988-5 Data Sheet

COMP

SWITCHE S CONTROL

BUSY

OUTPUT CODE

CNV

CONTROL

LOGIC

SW+LSB

SW–LSB

IN+

REF

GND

IN–

MSB

MSB

CC4C 2C16,384C

32,768C

CC4C 2C16,384C32,768C

10231-030

THEORY OF OPERATION

Figure 29. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7988-1/AD7988-5 devices are fast, low power, single-
supply, precise 16-bit ADCs that use a successive approximation
architecture.

The AD7988-1 is capable of converting 100,000 samples per
second (100 kSPS), whereas the AD7988-5 is capable of a
throughput of 500 kSPS, and they power down between
conversions. When operating at 10 kSPS, for example, the
ADC consumes 70 µW typically, ideal for battery-powered
applications.

The AD7988-x provides the user with on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.

The AD7988-x can be interfaced to any 1.8 V to 5 V digital logic
family. It is housed in a 10-lead MSOP or a tiny 10-lead LFCSP
(QFN) that combines space savings and allows flexible
configurations.

CONVERTER OPERATION

The AD7988-x is a successive approximation ADC based on a
charge redistribution DAC. Figure 29 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is completed and the CNV input goes high, a
conversion phase is initiated. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are then
disconnected from the inputs and connected to the GND input.
Therefore, the differential voltage between the IN+ and IN−
inputs captured at the end of the acquisition phase are applied
to the comparator inputs, causing the comparator to become
unbalanced. By switching each element of the capacitor array
between GND and REF, the comparator input varies by binary
weighted voltage steps (V

REF

/2, V

/4 … V

REF

/65,536). The

REF

control logic toggles these switches, starting with the MSB, to
bring the comparator back into a balanced condition. After the
completion of this process, the part returns to the acquisition phase
and the control logic generates the ADC output code.

Because the AD7988-x has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.

Rev. B | Page 14 of 24

Data Sheet AD7988-1/AD7988-5

000 ... 000

000 ... 001

000 ... 010

111 ... 101

111 ... 110

111 ... 111

–FSR –FS R + 1LSB

–FSR + 0.5LS B

+FSR – 1 LSB

+FSR – 1.5 LS B

ANALOG INP UT

ADC CODE (STRAI GHT BINARY)

10231-031

AD7988-1/
AD7988-5

2.5VV+

20Ω

V+

V–

0V TO V

REF

1.8V TO 5.5V

100nF

10µF

2

2.7nF

4

3

100nF

REF

IN+

IN–

VDD VIO

GND

3- OR 4-WI RE INTERFACE

5

REF

1

1

SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.

2

C

REF

IS USUALL Y A 10µ F CERAMIC CAPACI TOR (X5R).

3

SEE THE DRIVER AMPLIFIER CHOICE SECTION.

4

OPTIONAL FILTER. SEE THE ANALOG INPUTS SECTION.

5

SEE THE DIGITAL INTERFACE SECTION FOR THE MOST CONVENIENT INTERFACE MODE.

10231-032

CNV

SCK
SDO

SDI

Transfer Functions

The ideal transfer characteristic for the AD7988-x is shown in
Figure 30 and Table 7.

Figure 30. ADC Ideal Transfer Function

Table 7. Output Codes and Ideal Input Voltages

Analog Input
Description V

= 5 V Digital Output Code (Hex)

REF

FSR – 1 LSB 4.999924 V FFFF1
Midscale + 1 LSB 2.500076 V 8001
Midscale 2.5 V 8000
Midscale – 1 LSB 2.499924 V 7FFF
–FSR + 1 LSB 76.3 µV 0001
–FSR 0 V 00002

1

This is also the code for an overranged analog input (V

2

This is also the code for an underranged analog input (V

− V

above V

IN+

IN−

− V

IN+

below V

IN−

− V

REF

GND

GND

TYPICAL CONNECTION DIAGRAM

Figure 31 shows an example of the recommended connection
diagram for the AD7988-x when multiple supplies are available.

).

).

Figure 31. Typical Application Diagram with Multiple Supplies

Rev. B | Page 15 of 24

AD7988-1/AD7988-5 Data Sheet

REF

R

IN

C

IN

IN+

OR IN–

GND

D2C

PIN

D1

10231-033

AD8605, AD8615

5 V single-supply, low power

ANALOG INPUTS

Figure 32 shows an equivalent circuit of the input structure of
the AD7988-x.

The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V, because this causes these diodes to become forward­biased and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions may eventually occur when the input buffer’s
supplies are different from VDD. In such a case (for example, an
input buffer with a short circuit), the current limitation can be
used to protect the part.

Figure 32. Equivalent Analog Input Circuit

The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.

During the acquisition phase, the impedance of the analog
inputs (IN+ and IN−) can be modeled as a parallel combination of
Capacitor C
R

and CIN. C

IN

and the network formed by the series connection of

PIN

is primarily the pin capacitance. RIN is typically

PIN

400 Ω and is a lumped component made up of serial resistors
and the on resistance of the switches. C

is typically 30 pF and

IN

is mainly the ADC sampling capacitor. During the conversion
phase, when the switches are opened, the input impedance is
limited to C

. RIN and CIN make a one-pole, low-pass filter that

PIN

reduces undesirable aliasing effects and limits the noise.
When the source impedance of the driving circuit is low, the

AD7988-x can be driven directly. Large source impedances

significantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency.

DRIVER AMPLIFIER CHOICE

Although the AD7988-x is easy to drive, the driver amplifier
needs to meet the following requirements:

• The noise generated by the driver amplifier must be kept as

low as possible to preserve the SNR and transition noise
performance of the AD7988-x. The noise coming from the
driver is filtered by the AD7988-x analog input circuit’s
one-pole, low-pass filter made by R
external filter, if one is used. Because the typical noise of
the AD7988-x is 47.3 µV rms, the SNR degradation due to
the amplifier is






SNR

LOSS

log20

=



47.3




where:

f

is the input bandwidth in MHz of the AD7988-x

–3dB

(10 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).

e

is the equivalent input noise voltage of the op amp,

N

in nV/√Hz.

• For ac applications, the driver should have a THD

performance commensurate with the AD7988-x.

• For multichannel multiplexed applications, the driver ampli-

fier and the AD7988-x analog input circuit must settle for
a full-scale step onto the capacitor array at a 16-bit level
(0.0015%, 15 ppm). In the amplifier data sheet, settling at

0.1% to 0.01% is more commonly specified. This may
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.

Table 8. Recommended Driver Amplifiers

Amplifier Typical Application

ADA4841-1 Very low noise, small size, and low power
AD8021 Very low noise and high frequency
AD8022 Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8655 5 V single-supply, low noise

and CIN or by the

IN

47.3

π

2

+

Nef

−23dB

2







)(



N



Rev. B | Page 16 of 24

Data Sheet AD7988-1/AD7988-5

80

55

1 1k

FREQUENCY ( kHz )

PSRR (dB)

10 100

75

70

65

60

10231-034

VOLTAGE REFERENCE INPUT

The AD7988-x voltage reference input, REF, has a dynamic
input impedance and should therefore be driven by a low
impedance source with efficient decoupling between the REF
and GND pins, as explained in the Layout section.

When REF is driven by a very low impedance source, for example,
a reference buffer using the AD8031 or the AD8605, a ceramic
chip capacitor is appropriate for optimum performance.

If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For example, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.

If desired, a reference-decoupling capacitor value as small as

2.2 µF can be used with a minimal impact on performance,
especially DNL.

Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.

POWER SUPPLY

The AD7988-x uses two power supply pins: a core supply, VDD,
and a digital input/output interface supply, VIO. VIO allows
direct interface with any logic between 1.8 V and 5.0 V. To
reduce the number of supplies needed, VIO and VDD can be
tied together. The AD7988-x is independent of power supply
sequencing between VIO and VDD. Additionally, it is very
insensitive to power supply variations over a wide frequency
range, as shown in Figure 33.

To ensure optimum performance, VDD should be roughly half
of REF, the voltage reference input. For example, if REF is 5.0 V,
VDD should be set to 2.5 V (±5%). If REF = 2.5V, and VDD =

2.5 V, performance is degraded as can be seen in Tab le 2.
The AD7988-x powers down automatically at the end of each

conversion phase.

DIGITAL INTERFACE

Although the AD7988-x has a reduced number of pins, it offers
flexibility in its serial interface modes.

CS

The AD7988-x, when in
and digital hosts. This interface can use either a 3-wire or 4-wire
interface. A 3-wire interface using the CNV, SCK, and SDO
signals minimizes wiring connections and is useful, for
instance, in isolated applications. A 4-wire interface using the
SDI, CNV, SCK, and SDO signals allows CNV, which initiates
the conversions, to be independent of the readback timing
(SDI). This is useful in low jitter sampling or simultaneous
sampling applications.

The AD7988-x, when in chain mode, provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line, similar to a shift register.

The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs.
high, and chain mode is selected if SDI is low. The SDI hold
time is such that when SDI and CNV are connected together,
the chain mode is selected.

The user must time out the maximum conversion time prior to
readback.

mode, is compatible with SPI, QSPI™,

CS

mode is selected if SDI is

Figure 33. PSRR vs. Frequency

Rev. B | Page 17 of 24

AD7988-1/AD7988-5 Data Sheet

AD7988-1/
AD7988-5

SDO

DATA IN

DIGITAL HOST

CONVERT

CLK

VIO

CNV

SCK

SDI

10231-035

t

CONV

t

CYC

CNV

ACQUISITION ACQUISITION

t

ACQ

t

SCK

t

SCKL

CONVERSION

SCK

SDO D15 D14 D13 D1 D0

t

EN

t

HSDO

1 2 3 14 15 16

t

DSDO

t

DIS

t

SCKH

t

CNVH

SDI = 1

10231-036

CS MODE, 3-WIRE

This mode is typically used when a single AD7988-x is
connected to an SPI-compatible digital host. The connection
diagram is shown in Figure 34, and the corresponding timing is
given in Figure 35.

With SDI tied to VIO, a rising edge on CNV initiates a conver­sion, selects the
When the conversion is complete, the AD7988-x enters the
acquisition phase and powers down.

CS

mode, and forces SDO to high impedance.

Figure 34. 3-Wire

CS

Mode Connection Diagram

When CNV goes low, the MSB is output onto SDO. The remaining
data bits are then clocked by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided that it has an acceptable
hold time. After the 16th SCK falling edge or when CNV goes
high, whichever is earlier, SDO returns to high impedance.

Figure 35. 3-Wire

CS

Mode Serial Interface Timing (SDI High)

Rev. B | Page 18 of 24

Data Sheet AD7988-1/AD7988-5

DIGITAL HOST

CONVERT

CLK

DATA IN

AD7988-1/
AD7988-5

SDO

CNV

SCK

AD7988-1/
AD7988-5

SDO

CNV

SCK

CS1

CS2

SDI SDI

10231-037

t

CONV

t

CYC

ACQUISITION

ACQUISITION

t

ACQ

t

SCK

t

SCKH

t

SCKL

CONVERSION

SCK

CNV

t

SSDICNV

t

HSDICNV

SDO

D15 D13D14 D1 D0 D15 D14 D1

D0

t

HSDO

t

EN

1 2 3 14 15 16 17 18 30 31 32

t

DSDO

t

DIS

SDI (CS1)

SDI (CS2)

10231-038

CS MODE 4-WIRE

This mode is typically used when multiple AD7988-x devices
are connected to an SPI-compatible digital host.

A connection diagram example using two AD7988-x devices is
shown in Figure 36, and the corresponding timing is given in
Figure 37.

With SDI high, a rising edge on CNV initiates a conversion,
selects the
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum conversion time.

CS

mode, and forces SDO to high impedance. In this

When the conversion is complete, the AD7988-x enters the
acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided that it has an acceptable hold time. After
the 16th SCK falling edge or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7988-x
can be read.

CS

Figure 36. 4-Wire

Figure 37. 4-Wire

Mode Connection Diagram

CS

Mode Serial Interface Timing

Rev. B | Page 19 of 24

AD7988-1/AD7988-5 Data Sheet

DIGITAL HOST

CONVERT

CLK

DATA IN

AD7988-1/
AD7988-5

SDO

CNV

A

SCK

AD7988-1/
AD7988-5

SDO

CNV

B

SCK

10231-039

SDISDI

t

CONV

t

CYC

t

SSDISCK

t

SCKL

t

SCK

t

HSDISCK

t

ACQ

ACQUISITION

t

SSCKCNV

ACQUISITION

t

SCKH

CONVERSION

t

HSCKCNV

SCK

CNV

SDO

B

t

EN

DA15 D

A

14 DA13

D

B

15 DB14 DB13 DB1 DB0 DA15 DA14 DA0DA1

D

A

1 DA0

t

HSDO

1 2 3 15 16 1714 18 30 31 32

t

DSDO

10231-040

SDIA = 0

SDO

A

= SDI

B

CHAIN MODE

This mode can be used to daisy-chain multiple AD7988-x
devices on a 3-wire serial interface. This feature is useful for
reducing component count and wiring connections, for example,
in isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.

A connection diagram example using two AD7988-x devices is
shown in Figure 38, and the corresponding timing is given in
Figure 39.

When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion and selects the chain
mode. In this mode, CNV is held high during the conversion

phase and the subsequent data readback. When the conversion
is complete, the MSB is output onto SDO and the AD7988-x
enters the acquisition phase and powers down. The remaining
data bits stored in the internal shift register are clocked by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first,
and 16 × N clocks are required to read back the N ADCs. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate and, consequently, more

AD7988-x devices in the chain, provided that the digital host

has an acceptable hold time. The maximum conversion rate
may be reduced due to the total readback time.

Figure 38. Chain Mode Connection Diagram

Figure 39. Chain Mode Serial Interface Timing

Rev. B | Page 20 of 24

Data Sheet AD7988-1/AD7988-5

AD7988-1/
AD7988-5

SCK
SDO
CNV

SPI_CLK
SPI_MISO
SPI_MOSI

10231-041

BLACKFIN

DSP

SCK

SDO

CNV

TSCLK

DR

TFS

RFS

RSCLK

VDRIVE

AD7988-1/
AD7988-5

10231-045

BLACKFIN

DSP

AD7988-1/
AD7988-5

10231-043

10231-044

APPLICATIONS INFORMATION

INTERFACING TO BLACKFIN® DSP

The AD7988-x can easily connect to a DSP SPI or SPORT. The
SPI configuration is straightforward, using the standard SPI
interface as shown in Figure 40.

Figure 40. Typical Connection to Blackfin SPI Interface

Similarly, the SPORT interface can be used to interface to this
ADC. The SPORT interface has some benefits in that it can use
direct memory access (DMA) and provides a lower jitter CNV
signal generated from a hardware counter.

Some glue logic may be required between SPORT and the

AD7988-x interface. The evaluation board for the AD7988-x

interfaces directly to the SPORT of the Blackfin-based (ADSP­BF-527) SDP board. The configuration used for the SPORT
interface requires the addition of some glue logic as shown in
Figure 41. The SCK input to the ADC was gated off when CNV
was high to keep the SCK line static while converting the data,
thereby ensuring the best integrity of the result. This approach
uses an AND gate and a NOT gate for the SCK path. The other
logic gates used on the RSCLK and RFS paths are for delay
matching purposes and may not be necessary where path
lengths are short.

This is one approach to using the SPORT interface for this ADC;
there may be other solutions equal to this approach.

Using at least one ground plane is recommended. It can be
common or split between the digital and analog section. In the
latter case, join the planes underneath the AD7988-x devices.

The AD7988-x voltage reference input, REF, has a dynamic input
impedance. Decouple REF with minimal parasitic inductances
by placing the reference decoupling ceramic capacitor close to,
but ideally right up against, the REF and GND pins and connect­ing them with wide, low impedance traces.

Finally, decouple the power supplies of the AD7988-x, VDD and
VIO, with ceramic capacitors, typically 100 nF, placed close to
the AD7988-x and connected using short and wide traces to
provide low impedance paths and to reduce the effect of glitches
on the power supply lines.

An example of a layout following these rules is shown in Figure 42
and Figure 43.

EVALUATING THE PERFORMANCE OF THE

AD7988-x

The evaluation board package for the AD7988-x (EVA L-AD7988-

5SDZ) includes a fully assembled and tested evaluation board,

documentation, and software for controlling the board from a
PC via the EVA L-SDP-CB1Z.

Figure 41. Evaluation Board Connection to Blackfin Sport Interface

LAYOUT

Design the printed circuit board (PCB) that houses the AD7988-x
so that the analog and digital sections are separated and confined
to certain areas of the board. The pinout of the AD7988-x, with all
the analog signals on the left side and all the digital signals on
the right side, eases this task.

Avoid running digital lines under the device because these couple
noise onto the die, unless a ground plane under the AD7988-x is
used as a shield. Fast switching signals, such as CNV or clocks,
should never run near analog signal paths. Avoid crossover of
digital and analog signals.

Figure 42. Example Layout of the AD7988-x (Top Layer)

Figure 43. Example Layout of the AD7988-x (Bottom Layer)

Rev. B | Page 21 of 24

AD7988-1/AD7988-5 Data Sheet

COMPLIANT TO JEDEC STANDARDS MO-187-BA

091709-A

6°
0°

0.70

0.55

0.40

5

10

1

6

0.50 BSC

0.30

0.15

1.10 MAX

3.10

3.00

2.90

COPLANARITY

0.10

0.23

0.13

3.10

3.00

2.90

5.15

4.90

4.65

PIN 1

IDENTIFIER

15° MAX

0.95

0.85

0.75

0.15

0.05

2.48

2.38

2.23

0.50

0.40

0.30

TOP VIEW

10

1

6

5

0.30

0.25

0.20

BOTTOM VIEW

PIN 1 INDEX

AREA

SEATING

PLANE

0.80

0.75

0.70

1.74

1.64

1.49

0.20 REF

0.05 MAX

0.02 NOM

0.50 BSC

EXPOSED

PAD

3.10

3.00 SQ

2.90

PIN 1

INDICATOR
(R 0.15)

FOR PROP E R CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATI ON AND
FUNCTIO N DE S CRIPTIONS
SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

02-27-2012-B

OUTLINE DIMENSIONS

Figure 44.10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

Figure 45. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

Rev. B | Page 22 of 24

Data Sheet AD7988-1/AD7988-5

2

ORDERING GUIDE

Model1 Notes

Nonlinearity

AD7988-1BRMZ ±1.25 LSB max −40°C to +125°C Tube, 50 10-Lead MSOP RM-10 C7E
AD7988-1BRMZ-RL7 ±1.25 LSB max −40°C to +125°C Reel, 1,000 10-Lead MSOP RM-10 C7E
AD7988-1BCPZ-RL ±1.25 LSB max −40°C to +125°C Reel, 5,000 10-Lead QFN (LFCSP_WD) CP-10-9 C7X
AD7988-1BCPZ-RL7 ±1.25 LSB max −40°C to +125°C Reel, 1,500 10-Lead QFN (LFCSP_WD) CP-10-9 C7X
AD7988-5BRMZ ±1.25 LSB max −40°C to +125°C Tube, 50 10-Lead MSOP RM-10 C7Q
AD7988-5BRMZ-RL7 ±1.25 LSB max −40°C to +125°C Reel, 1,000 10-Lead MSOP RM-10 C7Q
AD7988-5BCPZ-RL ±1.25 LSB max −40°C to +125°C Reel, 5,000 10-Lead QFN (LFCSP_WD) CP-10-9 C7Y
AD7988-5BCPZ-RL7 ±1.25 LSB max −40°C to +125°C Reel, 1,500 10-Lead QFN (LFCSP_WD) CP-10-9 C7Y

Integral

EVAL-AD7988-5SDZ

EVAL-SDP-CB1Z

1

Z = RoHS Compliant Part.

2

This board can be used as a standalone evaluation board or in conjunction with the EVAL-SDZ-CB1Z for evaluation/demonstration purposes.

3

This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SD designator.

3

Evaluation Board with AD7988-5

System Demonstration Board, Used as a

Temperature
Range

Ordering
Quantity Package Description

Populated; Use for Evaluation of Both
AD7988-1 and AD7988-5.

Controller Board for Data Transfer via
USB Interface to PC.

Package
Option Branding

Rev. B | Page 23 of 24

AD7988-1/AD7988-5 Data Sheet

©2012 Analog Devices, Inc. All rights reserved. Trademarks and

NOTES

registered trademarks are the property of their respective owners.
D10231-0-5/12(B)

Rev. B | Page 24 of 24