Datasheet AD797BR-REEL7, AD797BR-REEL, AD797BR, AD797BN, AD797AR-REEL7 Datasheet (Analog Devices)
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AD797
DECOMPENSATION &
DISTORTION
NEUTRALIZATION
OUTPUT
OFFSET NULL
–IN
+IN
+V
S
–V
S
OFFSET NULL
TOP VIEW
Ultralow Distortion,
a
FEATURES
Low Noise
0.9 nV/√Hz typ (1.2 nV/√Hz max) Input Voltage
Noise at 1 kHz
50 nV p-p Input Voltage Noise, 0.1 Hz to 10 Hz
Low Distortion
–120 dB Total Harmonic Distortion at 20 kHz
Excellent AC Characteristics
800 ns Settling Time to 16 Bits (10 V Step)
110 MHz Gain Bandwidth (G = 1000)
8 MHz Bandwidth (G = 10)
280 kHz Full Power Bandwidth at 20 V p-p
20 V/ms Slew Rate
Excellent DC Precision
80 mV max Input Offset Voltage
1.0 mV/8C V
Specified for 65 V and 615 V Power Supplies
High Output Drive Current of 50 mA
APPLICATIONS
Professional Audio Preamplifiers
IR, CCD, and Sonar Imaging Systems
Spectrum Analyzers
Ultrasound Preamplifiers
Seismic Detectors
SD ADC/DAC Buffers
PRODUCT DESCRIPTION
The AD797 is a very low noise, low distortion operational
amplifier ideal for use as a preamplifier. The low noise of
0.9 nV/√
Hz and low total harmonic distortion of –120 dB at
audio bandwidths give the AD797 the wide dynamic range
OS
Drift
Ultralow Noise Op Amp
AD797*
CONNECTION DIAGRAM
8-Pin Plastic Mini-DIP (N),
Cerdip (Q) and SOIC (R) Packages
necessary for preamps in microphones and mixing consoles.
Furthermore, the AD797’s excellent slew rate of 20 V/µs and
110 MHz gain bandwidth make it highly suitable for low frequency ultrasound applications.
The AD797 is also useful in IR and Sonar Imaging applications
where the widest dynamic range is necessary. The low distortion and 16-bit settling time of the AD797 make it ideal for
buffering the inputs to Σ∆ ADCs or the outputs of high resolution DACs especially when they are used in critical applications
such as seismic detection and spectrum analyzers. Key features
such as a 50 mA output current drive and the specified power
supply voltage range of ±5 to ±15 volts make the AD797 an
excellent general purpose amplifier.
5
Hz
4
3
2
1
INPUT VOLTAGE NOISE – nV/
0
100
10
FREQUENCY – Hz
1M100k10k1k
AD797 Voltage Noise Spectral Density
*Patent pending.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
10M
–90
–100
–110
THD – dB
–120
–130
MEASUREMENT
LIMIT
300100
FREQUENCY – Hz
100k30k10k3k1k
0.001
0.0003
0.0001
300k
THD vs. Frequency
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
THD – %
Page 2
AD797–SPECIFICATIONS
(@ TA = +258C and VS = 615 V dc, unless otherwise noted)
1
AD797B
Model Conditions V
AD797A/S
S
Min Typ Max Min Typ Max Units
INPUT OFFSET VOLTAGE ±5 V, ±15 V 25 80 10 40 µV
T
MIN
to T
MAX
50 125/180 30 60 µV
Offset Voltage Drift ±5 V, ±15 V 0.2 1.0 0.2 0.6 µV/°C
INPUT BIAS CURRENT ±5 V, ±15 V 0.25 1.5 0.25 0.9 µA
T
MIN
to T
MAX
0.5 3.0 0.25 2.0 µA
INPUT OFFSET CURRENT ±5 V, ±15 V 100 400 80 200 nA
T
OPEN-LOOP GAIN V
to T
MIN
MAX
= ±10 V ±15 V
OUT
R
= 2 kΩ 120 220 V/µV
LOAD
T
to T
MIN
R
T
@ 20 kHz
MAX
= 600 Ω 115 215 V/µV
LOAD
to T
MIN
MAX
2
16 210 V/µV
15 27 V/µV
14000 20000 14000 20000 V/V
120 600/700 120 300 nA
DYNAMIC PERFORMANCE
Gain Bandwidth Product G = 1000 ±15 V 110 110 MHz
G = 1000
–3 dB Bandwidth G = 10 ±15 V 8 8 MHz
Full Power Bandwidth
3
VO = 20 V p-p,
R
Slew Rate R
2
= 1 kΩ±15 V 280 280 kHz
LOAD
= 1 kΩ±15 V 12.5 20 12.5 20 V/µs
LOAD
±15 V 450 450 MHz
Settling Time to 0.0015% 10 V Step ±15 V 800 1200 800 1200 ns
COMMON-MODE REJECTION V
POWER SUPPLY REJECTION V
= CMVR ±5 V, ±15 V 114 130 120 130 dB
CM
T
to T
MIN
MAX
= ±5 V to ±18 V 114 130 120 130 dB
S
T
to T
MIN
MAX
110 120 114 120 dB
110 120 114 120 dB
INPUT VOLTAGE NOISE f = 0. 1 Hz to 10 Hz ±15 V 50 50 nV p-p
f = 10 Hz ±15 V 1.7 1.7 2.5 nV/√
f = 1 kHz ±15 V 0.9 1.2 0.9 1.2 nV/√
Hz
Hz
f = 10 Hz–1 MHz ±15 V 1.0 1.3 1.0 1.2 µV rms
INPUT CURRENT NOISE f = 1 kHz ±15 V 2.0 2.0 pA/√Hz
INPUT COMMON-MODE ±15 V ±11 ±12 ±11 ±12 V
VOLTAGE RANGE ±5 V ±2.5 ±3 ±2.5 ±3V
OUTPUT VOLTAGE SWING R
Short-Circuit Current ±5 V, ±15 V 80 80 mA
Output Current
4
TOTAL HARMONIC DISTORTION R
= 2 kΩ±15 V ±12 ±13 ±12 ±13 V
LOAD
R
= 600 Ω±15 V ±11 ±13 ±11 ±13 V
LOAD
R
= 600 Ω±5 V ±2.5 ±3 ±2.5 ±3V
LOAD
±5 V, ±15 V 30 50 30 50 mA
= 1 kΩ, CN = 50 pF ±15 V –98 –90 –98 –90 dB
LOAD
f = 250 kHz, 3 V rms
R
= 1 kΩ±15 V –120 –110 –120 –110 dB
LOAD
f = 20 kHz, 3 V rms
INPUT CHARACTERISTICS
Input Resistance (Differential) 7.5 7.5 kΩ
Input Resistance (Common Mode) 100 100 MΩ
Input Capacitance (Differential)
5
20 20 pF
Input Capacitance (Common Mode) 5 5 pF
OUTPUT RESISTANCE AV = +1, f = 1 kHz 3 3 mΩ
POWER SUPPLY
Operating Range ±5 ±18 ±5 ±18 V
Quiescent Current ±5 V, ±15 V 8.2 10.5 8.2 10.5 mA
NOTES
1
See standard military drawing for 883B specifications.
2
Specified using external decompensation capacitor, see Applications section.
3
Full Power Bandwidth = Slew Rate/2 π V
4
Output Current for |VS – V
5
Differential input capacitance consists of 1.5 pF package capacitance and 18.5 pF from the input differential pair.
Specifications subject to change without notice.
| >4 V, AOL > 200 kΩ.
OUT
PEAK
.
–2–
REV. C
Page 3
AD797
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation @ +25°C
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±V
1
2
S
Differential Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . ±0.7 V
Output Short Circuit Duration . . . . . . .Indefinite Within max
Internal Power Dissipation
Storage Temperature Range (Cerdip) . . . . . . –65°C to +150°C
Storage Temperature Range (N, R Suffix) . . –65 °C to +125°C
Operating Temperature Range
AD797A/B . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD797S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . +300°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Internal Power Dissipation:
8-Pin SOIC = 0.9 Watts (TA–25°C)/θ
8-Pin Plastic DIP and Cerdip = 1.3 Watts – (TA–25°C)/θ
Thermal Characteristics
8-Pin Plastic DIP Package: θJA = 95°C/W
8-Pin Cerdip Package: θJA = 110°C/W
8-Pin Small Outline Package: θJA = 155°C/W
JA
JA
3
The AD797’s inputs are protected by back-to-back diodes. To achieve low noise,
internal current limiting resistors are not incorporated into the design of this
amplifier. If the differential input voltage exceeds ±0.7 V, the input current should
be limited to less than 25 mA by series protection resistors. Note, however, that this
will degrade the low noise performance of the device.
ESD SUSCEPTIBILITY
ESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without
detection. Although the AD797 features proprietary ESD protection circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.
ORDERING GUIDE
Model Range Description Option
AD797AN –40°C to +85°C 8-Pin Plastic DIP N-8
AD797BN –40°C to +85°C 8-Pin Plastic DIP N-8
AD797BR –40°C to +85°C 8-Pin Plastic SOIC SO-8
AD797BR-REEL –40°C to +85°C 8-Pin Plastic SOIC SO-8
AD797BR-REEL7 –40°C to +85°C 8-Pin Plastic SOIC SO-8
AD797AR –40°C to +85°C 8-Pin Plastic SOIC SO-8
AD797AR-REEL –40°C to +85°C 8-Pin Plastic SOIC SO-8
AD797AR-REEL7 –40°C to +85°C 8-Pin Plastic SOIC SO-8
5962-9313301MPA –55°C to +125°C 8-Pin Cerdip Q-8
Temperature Package Package
METALIZATION PHOTO
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
REV. C
NOTE
The AD797 has double layer metal. Only one layer is shown here for clarity.
–3–
Page 4
AD797–Typical Characteristics
HORIZONTAL SCALE – 5 sec/DIV
VERTICAL SCALE – 0.01µV/DIV
–60 140–40 100 120806040200–20
–2.0
–1.5
–1.0
–0.5
0.0
INPUT BIAS CURRENT – µA
TEMPERATURE – °C
140
140
100
60
–40
80
–60
120
120100
80
6040200–20
40
TEMPERATURE – °C
SHORT CIRCUIT CURRENT – mA
SOURCE CURRENT
SINK CURRENT
20
15
10
5
INPUT COMMON-MODE RANGE – ±Volts
0
0
5
SUPPLY VOLTAGE – ±Volts
10
15
20
Figure 1. Common-Mode Voltage Range vs. Supply
20
15
10
–V
OUT
5
OUTPUT VOLTAGE SWING – ±Volts
0
0
5
SUPPLY VOLTAGE – ±Volts
+V
OUT
10
15
20
Figure 2. Output Voltage Swing vs. Supply
30
V = ±15V
S
Figure 4. 0.1 Hz to 10 Hz Noise
Figure 5. Input Bias Current vs. Temperature
20
10
OUTPUT VOLTAGE SWING – Volts p-p
0
10 100 10k1k
Figure 3. Output Voltage Swing vs. Load Resistance
LOAD RESISTANCE –
V = ±5V
S
Ω
Figure 6. Short Circuit Current vs. Temperature
–4–
REV. C
Page 5
AD797
0
±5V SUPPLIES
±15V SUPPLIES
R
L
= 600Ω
11
10
9
8
7
QUIESCENT SUPPLY CURRENT – mA
6
+125°C
+25°C
–55°C
10
SUPPLY VOLTAGE – ±Volts
205015
Figure 7. Quiescent Supply Current vs. Supply Voltage
12
FREQ = 1kHz
= 600Ω
R
L
G = +10
9
6
3
OUTPUT VOLTAGE – Volts rms
140
120
100
80
60
POWER SUPPLY REJECTION – dB
40
20
10
1
PSR
–SUPPLY
FREQUENCY – Hz
PSR
+SUPPLY
CMR
150
125
100
75
50
100k10k1k100
1M
Figure 10. Power Supply and Common-Mode Rejection
vs. Frequency
–60
RL = 600
Ω
G = +10
FREQ = 10kHz
NOISE BW = 100kHz
–80
V
= ±5V
S
THD + NOISE – dB
–100
V
= ±15V
S
COMMON MODE REJECTION – dB
0
0
±5
SUPPLY VOLTAGE – Volts
±10
±15
Figure 8. Output Voltage vs. Supply for 0.01% Distortion
1.0
0.8
0.0015%
0.6
0.01%
0.4
SETTLING TIME – µs
0.2
0.0
0
Figure 9. Settling Time vs. Step Size (±)
2
STEP SIZE – Volts
864
±20
–120
0.01 0.1 101.0
OUTPUT LEVEL – Volts
Figure 11. Total Harmonic Distortion (THD) + Noise vs.
Output Level
10
Figure 12. Large Signal Frequency Response
REV. C
–5–
Page 6
AD797–Typical Characteristics
100 10k
1k
160
100
120
140
LOAD RESISTANCE – Ohms
OPEN-LOOP GAIN – dB
5
Hz
4
3
2
1
INPUT VOLTAGE NOISE – nV/
0
100
10
FREQUENCY – Hz
10M
1M100k10k1k
Figure 13. Input Voltage Noise Spectral Density
120
100
80
60
40
OPEN-LOOP GAIN – dB
100
*RS = 100Ω
SEE FIGURE 22
1k
20
0
PHASE MARGIN
WITH RS*
GAIN
FREQUENCY – Hz
WITH RS*
WITHOUT
WITHOUT
R
S
10M1M100k10k
+100
+80
R
*
S
+60
+40
+20
*
0
100M
Figure 14. Open-Loop Gain & Phase vs. Frequency
35
30
25
SLEW RATE – V/µs
20
15
–60 140–40 100 120806040200–20
Figure 16. Slew Rate & Gain/Bandwidth Product vs.
Temperature
PHASE MARGIN – DEGREES
Figure 17. Open-Loop Gain vs. Resistive Load
GAIN/BANDWIDTH PRODUCT
SLEW RATE
RISING EDGE
SLEW RATE
FALLING EDGE
TEMPERATURE – °C
120
110
100
90
GAIN/BANDWIDTH PRODUCT – MHz (G = 1000)
80
INPUT OFFSET CURRENT – nA
Figure 15. Input Offset Current vs. Temperature
300
150
0
–150
–300
–60 140–40 100 120806040200–20
OVER COMPENSATED
UNDER COMPENSATED
TEMPERATURE – °C
100
10
* SEE FIGURE 29
1
0.1
MAGNITUDE OF OUTPUT IMPEDANCE – Ohms
0.01
10 1M
100
WITHOUT CN*
WITH CN*
10k 100k1k
FREQUENCY – Hz
Figure 18. Magnitude of Output Impedance vs. Frequency
–6–
REV. C
Page 7
AD797
10
90
100
0%
100ns50mV
10
90
100
0%
100ns50mV
10
90
100
0%
500ns5mV
20pF
1kΩ
+V
S
1kΩ
V
IN
2
7
AD797
3
4
–V
** SEE FIGURE 32
S
Figure 19. Inverter
Connection
100Ω
+V
S
**
2
7
AD797
R
*
S
V
IN
3
* VALUE OF SOURCE RESISTANCE –
SEE TEXT
** SEE FIGURE 32
6
4
**
–V
S
Figure 22. Follower
Connection
1µs
100
90
**
V
6
**
OUT
10
0%
5V
Figure 21. Inverter Small Signal
Pulse Response
Figure 24. Follower Small Signal
Pulse Response
V
OUT
600Ω
Figure 20. Inverter Large Signal
Pulse Response
5V
100
90
10
0%
Figure 23. Follower Large Signal
Pulse Response
1µs
500ns5mV
100
90
See Figure 40 for settling time
test circuit.
10
0%
Figure 25. 16-Bit Settling Time
Positive Input Pulse
Figure 26. 16-Bit Settling Time
Negative Input Pulse
REV. C
–7–
Page 8
AD797
V
O
V
IN
=
gm
jωC
I1 I2
+IN
Q1
Q2
I3
–IN
C
C
I4
OUT
C
N
C
B
CURRENT
MIRROR
1
A
A
THEORY OF OPERATION
The new architecture of the AD797 was developed to overcome
inherent limitations in previous amplifier designs. Previous precision amplifiers used three stages to ensure high open-loop
gain, Figure 27b, at the expense of additional frequency compensation components. Slew rate and settling performance are
usually compromised, and dynamic performance is not adequate beyond audio frequencies. As can be seen in Figure 27b,
the first stage gain is rolled off at high frequencies by the compensation network. Second stage noise and distortion will then
appear at the input and degrade performance. The AD797 on
the other hand, uses a single ultrahigh gain stage to achieve dc
as well as dynamic precision. As shown in the simplified schematic (Figure 28), nodes A, B, and C all track in voltage forcing
the operating points of all pairs of devices in the signal path to
match. By exploiting the inherent matching of devices fabricated
on the same IC chip, high open-loop gain, CMRR, PSRR, and
low V
are all guaranteed by pairwise device matching (i.e.,
OS
NPN to NPN & PNP to PNP), and not absolute parameters
such as beta and early voltage.
gm
R1 C1
GAIN = gmR1 ≈ 5 x 10
BUFFER
6
V
OUT
R
L
a.
C2
This matching benefits not just dc precision but since it holds
up dynamically, both distortion and settling time are also
reduced. This single stage has a voltage gain of >5 × 10
V
<80 µV, while at the same time providing THD + noise of
OS
6
and
less than –120 dB and true 16 bit settling in less than 800 ns.
The elimination of second stage noise effects has the additional
benefit of making the low noise of the AD797 (<0.9 nV/√
Hz)
extend to beyond 1 MHz. This means new levels of performance for sampled data and imaging systems. All of this performance as well as load drive in excess of 30 mA are made
possible by Analog Devices’ advanced Complementary Bipolar
(CB) process.
Another unique feature of this circuit is that the addition of a
single capacitor, C
(Figure 28), enables cancellation of distor-
N
tion due to the output stage. This can best be explained by
referring to a simplified representation of the AD797 using idealized blocks for the different circuit elements (Figure 29).
A single equation yields the open-loop transfer function of this
amplifier, solving it (at Node B) yields:
V
O
=
V
C
IN
N
A
gm
jω–CNjω–
C
C
jω
A
gm = the transconductance of Q1 and Q2
A = the gain of the output stage, (~1)
V
= voltage at the output
O
V
= differential input voltage
IN
When C
is equal to CC this gives the ideal single pole op amp
N
response:
gm
A2
R1
C1
R2
GAIN = gmR1 *A2 *A3
A3
BUFFER
V
OUT
R
L
The terms in A, which include the properties of the output
stage such as output impedance and distortion, cancel by
simple subtraction, and therefore the distortion cancellation
does not affect the stability or frequency response of the amplifier. With only 500 µA of output stage bias the AD797 delivers
b.
Figure 27. Model of AD797 vs. That of a Typical
a 1 kHz sine wave into 600 Ω at 7 V rms with only 1 ppm of
distortion.
Three-Stage Amplifier
V
CC
R2
+IN
R3
Q1 Q2
I1
Figure 28. AD797 Simplified Schematic
C
Q3
–IN
Q5I7Q6 C
C
N
A
R1
Q4
Q7
B
Q8
Q12
C
I4
I5
Q10
Q9
OUT
Q11
I6
V
SS
–8–
Figure 29. AD797 Block Diagram
REV. C
Page 9
AD797
100kΩ
1.5µF
1Ω
HP 3465
DYNAMIC SIGNAL
ANALYZER
(10Hz)
V
OUT
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
AD797
**
2
7
3
4
6
**
–V
S
+V
S
NOISE AND SOURCE IMPEDANCE CONSIDERATIONS
The AD797’s ultralow voltage noise of 0.9 nV/√Hz is achieved
with special input transistors running at nearly 1 mA of collector
current. It is important then to consider the total input referred
noise (e
(e
where r
total), which includes contributions from voltage noise
N
), current noise (iN), and resistor noise (√4 kTrS).
N
total = [e
e
N
= total input source resistance.
S
2
+ 4 kTrS + 4 (iNrS)2]
N
l/2
Equation 1
This equation is plotted for the AD797 in Figure 30. Since optimum dc performance is obtained with matched source resistances, this case is considered even though it is clear from
Equation 1 that eliminating the balancing source resistance will
lower the total noise by reducing the total r
At very low source resistance (r
<50 Ω), the amplifiers’ voltage
S
by a factor of two.
S
noise dominates. As source resistance increases the Johnson
noise of r
dominates until at higher resistances (rS >2 kΩ) the
S
current noise component is larger than the resistor noise.
100
10
Hz
NOISE – nV/
1
TOTAL NOISE
RESISTOR
NOISE
ONLY
LOW FREQUENCY NOISE
Analog Devices specifies low frequency noise as a peak to peak
(p-p) quantity in a 0.1 Hz to 10 Hz bandwidth. Several techniques can be used to make this measurement. The usual technique involves amplifying, filtering, and measuring the amplifiers
noise for a predetermined test time. The noise bandwidth of the
filter is corrected for and the test time is carefully controlled
since the measurement time acts as an additional low frequency
roll-off.
The plot in Figure 4 was made using a slightly different technique. Here an FFT based instrument (Figure 31) is used to
generate a 10 Hz “brickwall” filter. A low frequency pole at
0.1 Hz is generated with an external ac coupling capacitor, the
instrument being dc coupled.
Several precautions are necessary to get optimum low frequency
noise performance:
1. Care must be used to account for the effects of r
10 Ω resistor has 0.4 nV/√
root sum squared with 0.9 nV/√
Hz of noise (an error of 9% when
Hz).
2. The test set up must be fully warmed up to prevent e
, even a
S
OS
drift
from erroneously contributing to input noise.
3. Circuitry must be shielded from air currents. Heat flow out
of the package through its leads creates the opportunity for a
thermoelectric potential at every junction of different metals.
Selective heating and cooling of these by random air currents
will appear as 1/f noise and obscure the true device noise.
4. The results must be interpreted using valid statistical
techniques.
0.1
10 100 1000 10000
SOURCE RESISTANCE – Ω
Figure 30. Noise vs. Source Resistance
The AD797 is the optimum choice for low noise performance
provided the source resistance is kept <1 kΩ. At higher values of
source resistance, optimum performance with respect to noise
alone is obtained with other amplifiers from Analog Devices (see
Table I).
Table I. Recommended Amplifiers for Different Source
Impedances
rS, ohms Recommended Amplifier
0 to <1 k AD797
1 k to <10 k AD707, AD743/AD745, OP27/OP37, OP07
10 k to <100 k AD705, AD743/AD745, OP07
>100 k AD548, AD549, AD645, AD711, AD743/
AD745
REV. C
Figure 31. Test Setup for Measuring 0.1 Hz to 10 Hz Noise
WIDEBAND NOISE
The AD797, due to its single stage design, has the property that
its noise is flat over frequencies from less than 10 Hz to beyond
1 MHz. This is not true of most dc precision amplifiers where
second stage noise contributes to input referred noise beyond
the audio frequency range. The AD797 offers new levels of performance in wideband imaging applications. In sampled data
systems, where aliasing of out of band noise into the signal band
is a problem, the AD797 will out perform all previously available IC op amps.
–9–
Page 10
AD797
R2
R1
R
L
AD797
**
2
7
3
4
6
**
V
OUT
–V
S
+V
S
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
V
IN
C
L
BYPASSING CONSIDERATIONS
To take full advantage of the very wide bandwidth and dynamic
range capabilities of the AD797 requires some precautions.
First, multiple bypassing is recommended in any precision
application. A 1.0 µF–4.7 µF tantalum in parallel with 0.1 µF
ceramic bypass capacitors are sufficient in most applications.
When driving heavy loads a larger demand is placed on the supply bypassing. In this case selective use of larger values of tantalum capacitors and damping of their lead inductance with small
value (1.1 Ω to 4.7 Ω) carbon resistors can be an improvement.
Figure 32 summarizes bypassing recommendations. The symbol
(**) is used throughout this data sheet to represent the parallel
combination of a 0.1 µF and a 4.7 µF capacitor.
V
S
4.7 – 22.0µF
1.1 – 4.7Ω
KELVIN RETURN
LOAD
CURRENT
0.1µF
USE SHORT
LEAD LENGTHS
(<5mm)
V
S
4.7µF
KELVIN RETURN
LOAD
CURRENT
OR
0.1µF
USE SHORT
LEAD RETURNS
(<5mm)
Figure 32. Recommended Power Supply Bypassing
THE NONINVERTING CONFIGURATION
Ultralow noise requires very low values of rBB’ (the internal
parasitic resistance) for the input transistors (≈6 Ω). This implies very little damping of input and output reactive interactions. With the AD797, additional input series damping is
required for stability with direct input to output feedback. A
100 Ω resistor in the inverting input (Figure 33) is sufficient;
the 100 Ω balancing resistor (R2) is recommended, but is not
required for stability. The noise penalty is minimal (e
≈2.1 nV/√
Hz), which is usually insignificant. Best response
N
total
flatness is obtained with the addition of a small capacitor
(C
< 33 pF) in parallel with the 100 Ω resistor (Figure 34).
L
The input source resistance and capacitance will also affect the
response slightly and experimentation may be necessary for best
results.
follower. Operation on 5 volt supplies allows the use of a 100 Ω
or less feedback network (R1 + R2). Since the AD797 shows
no unusual behavior when operating near its maximum rated
current, it is suitable for driving the AD600/AD602 (Figure 47)
while preserving their low noise performance.
Optimum flatness and stability at noise gains >1 sometimes
requires a small capacitor (C
) connected across the feedback
L
resistor (R1, Figure 35). Table II includes recommended values
of C
for several gains. In general, when R2 is greater than
L
100 Ω and C
be placed in series with C
is greater than 33 pF, a 100 Ω resistor should
L
. Source resistance matching is
L
assumed, and the AD797 should never be operated with unbalanced source resistance >200 kΩ/G.
C
L
Ω
100
+V
S
**
2
7
RS*
V
IN
C
S
* SEE TEXT
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
AD797
3
*
6
4
**
–V
S
600
V
OUT
Ω
Figure 34. Alternative Voltage Follower Connection
R1
100Ω
+V
S
**
2
7
R2
100Ω
V
IN
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
Figure 33. Voltage Follower Connection
AD797
3
6
4
**
–V
S
R
L
600Ω
V
Low noise preamplification is usually done in the noninverting
mode (Figure 35). For lowest noise the equivalent resistance of
the feedback network should be as low as possible. The 30 mA
minimum drive current of the AD797 makes it easier to achieve
this. The feedback resistors can be made as low as possible with
due consideration to load drive and power consumption. Table
II gives some representative values for the AD797 as a low noise
OUT
Figure 35. Low Noise Preamplifier
Table II. Values for Follower With Gain Circuit
Noise
Gain R1 R2 C
L
21 kΩ1 kΩ≈20 pF 3.0 nV/√
2 300 Ω 300 Ω≈10 pF 1.8 nV/√
10 33.2 Ω 300 Ω≈5 pF 1.2 nV/√
20 16.5 Ω 316 Ω 1.0 nV/√
(Excluding rS)
Hz
Hz
Hz
Hz
>35 10 Ω (G–1) • 10 Ω 0.98 nV/√Hz
The I-to-V converter is a special case of the follower configura-
tion. When the AD797 is used in an I-to-V converter, for instance as a DAC buffer, the circuit of Figure 36 should be used.
The value of C
–10–
depends on the DAC and again, if CL is
L
REV. C
Page 11
AD797
20–120pF
+V
I
IN
2
AD797
3
C
*
RS*
S
* SEE TEXT
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
–V
Ω
100
R1
S
**
7
600
V
OUT
Ω
6
4
**
S
Figure 36. I-to-V Converter Connection
greater than 33 pF a 100 Ω series resistor is required. A bypassed balancing resistor (R
and CS) can be included to mini-
S
mize dc errors.
THE INVERTING CONFIGURATION
The inverting configuration (Figure 37) presents a low input
impedance, R1, to the source. For this reason, the goals of both
low noise and input buffering are at odds with one another.
Nonetheless, the excellent dynamics of the AD797 will make it
the preferred choice in many inverting applications, and with careful selection of feedback resistors the noise penalties will be minimal. Some examples are presented in Table II and Figure 37.
C
L
R2
+V
S
R1
V
IN
RS*
* SEE TEXT
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
2
AD797
3
**
7
6
4
**
–V
S
V
OUT
R
L
Figure 37. Inverting Amplifier Connection
Table III. Values for Inverting Circuit
Noise
Gain R1 R2 C
L
–1 1 kΩ 1 kΩ≈20 pF 3.0 nV/√
–1 300 Ω 300 Ω≈10 pF 1.8 nV/√
(Excluding rS)
Hz
Hz
–10 150 Ω 1500 Ω≈5 pF 1.8 nV/√Hz
DRIVING CAPACITIVE LOADS
The capacitive load driving capabilities of the AD797 are displayed in Figure 38. At gains over 10 usually no special precautions are necessary. If more drive is desirable the circuit in
Figure 39 should be used. Here a 5000 pF load can be driven
cleanly at any noise gain
100nF
10nF
1nF
100pF
10pF
CAPACITIVE LOAD DRIVE CAPABILITY
1pF
110 1k100
≥
2.
CLOSED-LOOP GAIN
Figure 38. Capacitive Load Drive Capability vs. Closed
Loop Gain
20pF
Ω
1k
200pF
1k
Ω
V
IN
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
2
AD797
3
100
Ω
+V
S
**
7
6
4
**
–V
S
Ω
33
V
OUT
C1
Figure 39. Recommended Circuit for Driving a High
Capacitance Load
SETTLING TIME
The AD797 is unique among ultralow noise amplifiers in that it
settles to 16 bits (<150 µV) in less than 800 ns. Measuring this
performance presents a challenge. A special test setup (Figure
40) was developed for this purpose. The input signal was obtained from a resonant reed switch pulse generator, available
from Tektronix as calibration Fixture No. 067-0608-00. When
open, the switch is simply 50 Ω to ground and settling is purely
a passive pulse decay and inherently flat. The low repetition rate
signal was captured on a digital oscilloscope after being amplified and clamped twice. The selection of plug-in for the oscilloscope was made for minimum overload recovery.
REV. C
–11–
Page 12
AD797
C1, SEE TABLE
C2 = 50pF – C1
R1
V
IN
R2
AD797
2
8
3
6
C1
C2
–80
300k
–120
300100
–110
–100
–90
100k30k10k3k1k
FREQUENCY – Hz
THD – dB
0.01
0.003
0.001
0.0003
0.0001
THD – %
NOISE LIMIT, G=1000
NOISE LIMIT, G=100
G=1000
R
L
=10kΩ
G=1000
R
L
=600Ω
G=10
R
L
=600Ω
G=100
R
L
=600Ω
HP2835
TEKTRONIX
CALIBRATION
FIXTURE
TO TEKTRONIX
7A26
Ω
OSCILLOSCOPE
PREAMP INPUT
226
Ω
4.26k
2
A2
AD829
3
2x
0.47µF
1kΩ
ΩΩ
100Ω
V
IN
Ω
1kΩ
2
AD797
3
1µF
0.1µF
SECTION
Ω
6
7
4
+V
S
–V
S
1kΩ
Ω
1kΩ
Ω
A1
7
4
+V
S
–V
S
1M
(VIA LESS THAN 1FT
50 COAXIAL CABLE)
Ω
250Ω
Ω
0.47µF
20pF
6
1µF
20pF
V
ERROR
2x
HP2835
NOTE:
USE CIRCUIT
BOARD
WITH GROUND
PLANE
51pF
0.1µF
X 5
R2
V
IN
Figure 41. Recommended Connections for Distortion
Cancellation and Bandwidth Enhancement
Table IV. Recommended External Compensation
R1
2
AD797
3
a.
b.
50pF
8
6
Figure 40. Settling Time Test Circuit
DISTORTION REDUCTION
The AD797 has distortion performance (THD < –120 dB, @
20 kHz, 3 V rms, R
= 600 Ω) unequaled by most voltage
L
feedback amplifiers.
At higher gains and higher frequencies THD will increase due
to reduction in loop gain. However in contrast to most conventional voltage feedback amplifiers the AD797 provides two effective means of reducing distortion, as gain and frequency are
increased; cancellation of the output stage’s distortion and gain
bandwidth enhancement by decompensation. By applying these
techniques gain bandwidth can be increased to 450 MHz at
G = 1000 and distortion can be held to –100 dB at 20 kHz for
G = 100.
The unique design of the AD797 provides for cancellation of the
output stage’s distortion (patent pending). To achieve this a capacitance equal to the effective compensation capacitance, usually 50 pF, is connected between Pin 8 and the output (C2 in
Figure 41). Use of this feature will improve distortion performance when the closed loop gain is more than 10 or when frequencies of interest are greater than 30 kHz.
Bandwidth enhancement via decompensation is achieved by
connecting a capacitor from Pin 8 to ground (C1 in Figure 41)
effectively subtracting from the value of the internal compensation capacitance (50 pF), yielding a smaller effective compensation capacitance and, therefore, a larger bandwidth. The
benefits of this begin at closed loop gains of 100 and up. A
maximum value of ≈33 pF at gains of 1000 and up is recommended. At a gain of 1000 the bandwidth is 450 kHz.
Table IV and Figure 42 summarize the performance of the
AD797 with distortion cancellation and decompensation.
A/B A B
R1 R2 C1 C2 3 dB C1 C2 3 dB
ΩΩ (pF) BW (pF) BW
G = 10 909 100 0 50 6 MHz 0 50 6 MHz
G = 100 1 k 10 0 50 1 MHz 15 33 1.5 MHz
G = 1000 10 k 10 0 50 110 kHz 33 15 450 kHz
Figure 42. Total Harmonic Distortion (THD) vs. Frequency
@ 3 V rms for Figure 41b
–12–
REV. C
Page 13
AD797
–90
–130
300k
–120
300100
–110
–100
100k30k10k3k1k
0.003
0.0003
0.001
THD – %
THD – dB
FREQUENCY – Hz
WITH
OPTIONAL
50C
N
MEASUREMENT
LIMIT
WITHOUT
OPTIONAL
50pF C
N
0.0001
Differential Line Receiver
The differential receiver circuit of Figure 43 is useful for many
applications from audio to MRI imaging. It allows extraction of
a low level signal in the presence of common-mode noise. As
shown in Figure 44, the AD797 provides this function with only
9 nV/√
Hz noise at the output. Figure 45 shows the AD797’s
20-bit THD performance over the audio band and 16-bit accuracy to 250 kHz.
20pF
1kΩ
DIFFERENTIAL
INPUT
1kΩ
+V
7
2
AD797
3
** –V
1kΩ
20pF
1kΩ
S
**
50pF*
8
6
4
OUTPUT
*OPTIONAL
S
USE POWER SUPPLY
**
BYPASSING SHOWN IN
FIGURE 32.
Figure 43. Differential Line Receiver
16
14
12
10
8
OUTPUT VOLTAGE NOISE — nV/ Hz
6
100
10
FREQUENCY — Hz
10M
1M100k10k1k
Figure 44. Output Voltage Noise Spectral Density for
Differential Line Receiver
A General Purpose ATE/Instrumentation Input/Output
Driver
The ultralow noise and distortion of the AD797 may be combined with the wide bandwidth, slew rate, and load drive of a
current feedback amplifier to yield a very wide dynamic range
general purpose driver. The circuit of Figure 46 combines the
AD797 with the AD811 in just such an application. Using the
Figure 45. Total Harmonic Distortion (THD) vs. Frequency
for Differential Line Receiver
component values shown, this circuit is capable of better than
–90 dB THD with a ±5 V, 500 kHz output signal. The circuit is
therefore suitable for driving high resolution A/D converters and
as an output driver in automatic test equipment (ATE) systems.
Using a 100 kHz sine wave, the circuit will drive a 600 Ω load to
a level of 7 V rms with less than –109 dB THD, and a 10 kΩ
load at less than –117 dB THD.
22pF
R2
1kΩ
INPUT
USE POWER SUPPLY
**
BYPASSING SHOWN IN
FIGURE 32.
2
AD797
3
+V
S
7
4
–V
S
**
6
**
649Ω
2kΩ
3
AD811
2
2
649Ω
+V
S
**
7
6
4
–V
S
OUTPUT
**
REV. C
Figure 46. A General Purpose ATE/lnstrumentation Input/
Output Driver
–13–
Page 14
AD797
C1
2000pF
C
F
82pF
3kΩ
AD797
**
2
7
3
4
6
**
–V
S
+V
S
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
100Ω
AD1862
DAC
Ultrasound/Sonar Imaging Preamp
The AD600 variable gain amplifier provides the time controlled
gain (TCG) function necessary for very wide dynamic range sonar and low frequency ultrasound applications. Under some circumstances, it is necessary to buffer the input of the AD600 to
preserve its low noise performance. To optimize dynamic range
this buffer should have at most 6 dB of gain. The combination
of low noise and low gain is difficult to achieve. The input
buffer circuit shown in Figure 47 provides 1 nV/√
Hz noise performance at a gain of two (dc to 1 MHz) by using 26.1 Ω resistors
in its feedback path. Distortion is only –50 dBc @ 1 MHz at a
2 volt p-p output level and drops rapidly to better than
–70 dBc at an output level of 200 mV p-p.
Ω
26.1Ω
AD600
**
V
OUT
**
+V
S
26.1Ω
Ω
7
2
AD797
INPUT
* USE POWER SUPPLY
** BYPASSING SHOWN IN FIGURE 32.
3
4
–V
S
**
6
**
V
= ±6Vdc
S
Figure 47. An Ultrasound Preamplifier Circuit
Amorphous (Photodiode) Detector
Large area photodiodes CS ≥ 500 pF and certain image detectors (amorphous Si), have optimum performance when used in
conjunction with amplifiers with very low voltage rather than
very low current noise. Figure 48 shows the AD797 used with
an amorphous Si (C
justed for flatness using capacitor C
= 1000 pF) detector. The response is ad-
S
, while the noise is domi-
L
nated by voltage noise amplified by the ac noise gain. The 797’s
excellent input noise performance gives 27 µV rms total noise in
a 1 MHz bandwidth, as shown by Figure 49.
100M1k100
OUT
100
80
60
40
20
VOLTAGE NOISE – µVrms (0.1Hz – Freq)
0
of
–30
– dB Re 1V/µA
V
OUT
–40
–50
–60
–70
–80
V
OUT
FREQUENCY – Hz
NOISE
10M1M100k10k
Figure 49. Total Integrated Voltage Noise & V
Amorphous Detector Preamp
Professional Audio Signal Processing—DAC Buffers
The low noise and low distortion of the AD797 make it an ideal
choice for professional audio signal processing. An ideal I-to-V
converter for a current output DAC would simply be a resistor
to ground, were it not for the fact that most DACs do not operate linearly with voltage on their output. Standard practice is to
operate an op amp as an I-to-V converter creating a virtual
ground at its inverting input. Normally, clock energy and current steps must be absorbed by the op amp’s output stage.
However, in the configuration of Figure 50, Capacitor C
F
shunts high frequency energy to ground, while correctly reproducing the desired output with extremely low THD and IMD.
100Ω
2
C
I
S
S
1000pF
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
AD797
3
Figure 48. Amorphous Detector Preamp
+V
–V
10kΩ
S
7
4
S
C
50pF
L
**
6
**
Figure 50. A Professional Audio DAC Buffer
Figure 51. Offset Null Configuration
–14–
REV. C
Page 15
OPERATIONAL AMPLIFIERS
LOW NOISE
AD797
AUDIO
AMPLIFIERS
AD797
OP275
SSM2015
SSM2016
SSM2017
SSM2134
SSM2139
(Slew Rate 45 V /µ s)
ULTRALOW V
√
0.9 nV/ Hz
AD797
LOW VOL TAGE NOIS E – V
≤
(VN 10 nV/ Hz @ 1 kHz)
FAST
√
PRECISION
AD797
AD OP27
AD OP37
OP27
OP37
OP227 (Dual)
OP270 (Dual)
OP271 (Dual)
OP275 (Dual)
OP467 (Quad)
OP470 (Quad)
OP471 (Quad)
≥
OP61
OP467 (Quad)
Faster
(Slew Rate 230 V/µs)
N
≥
AD829
AD840
AD844
AD846
AD848
AD849
AD5539
(Slew Rate 1000 V/µs)
High Output
Current
AD797
OP50
Ultrafast
≥
AD810
AD811
AD844
AD9610
AD9617
AD9618
N
FET INPUT
AD645
AD743
AD795
AD796 (Dual)
Fast
AD745
(IN 10 fA/ Hz @ 1 kHz, I
LOW
POWER
AD548
AD795
OP80
AD648 (Dual)
AD796 (Dual)
(Slew Rate 8 V/µs)
PRECISION
AD548
AD795
AD820
AD648 (Dual)
AD796 (Dual)
AD822 (Dual)
LOW CURRENT NOISE – I
LOW INPUT BIAS CURRENT – I
≤√ ≤
LOW V
Faster
≥
OP282 (Dual)
OP482 (Quad)
FAST
AD711
AD712 (Dual)
OP249 (Dual)
AD713 (Quad)
Faster
AD744
OP42
OP44
AD746 (Dual)
100 pA)
BIAS
ELECTROMETER
N
AD645
AD795
AD796 (Dual)
Lower V
N
AD743
Faster
AD745
Lowest I
60 fA Max
N
BIAS
Low
Power
OP80
General
Purpose
AD515A
AD545A
AD546
BIAS
AD549
REV. C
–15–
Page 16
AD797
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Cerdip (Q) Package*
(5.08)
0.200 (5.08)
0.125 (3.18)
0.165 ± 0.01
(4.19 ± 0.25)
SEATING PLANE
0.005 (0.13) MIN
0.200
MAX
0.023 (0.58)
0.014 (0.36)
0.125 (3.18)
MIN
0.018 ± 0.003
(0.46 ± 0.08)
0.055 (1.4) MAX
58
41
0.405 (10.29) MAX
0.100 (2.54)
BSC
SEATING PLANE
Plastic Mini-DIP
(N) Package
8
1
0.39 (9.91)
MAX
0.10
(2.54)
TYP
0.033
(0.84)
NOM
0.310 (7.87)
0.220 (5.59)
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
5
0.25
(6.35)
4
0.035 ± 0.01
(0.89 ± 0.25)
0.18 ± 0.03
(4.57 ± 0.76)
0 - 15
0.31
(7.87)
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
0.011 ± 0.003
0 - 15
0.30 (7.62)
REF
(4.57 ± 0.76)
C1677–24–6/92
0.050 (1.27)
0.010 (0.25)
0.004 (0.10)
8-Pin SOIC (R) Package
0.198 (5.03)
0.188 (4.77)
8
5
0.158 (4.00)
0.150 (3.80)
0.244 (6.200)
1
4
0.228 (5.80)
0.018 (0.46)
TYP
0.014 (0.36)
0.069 (1.75)
0.053 (1.35)
0.015 (0.38)
0.007 (0.18)
0.205 (5.20)
0.181 (4.60)
0.045 (1.15)
0.020 (0.50)
*See military data sheet for 883B specifications.
–16–
PRINTED IN U.S.A.
REV. C
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