Datasheet AD7952 Datasheet (ANALOG DEVICES)

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VCCV

14-Bit, 1 MSPS, Differential,

FEATURES

Multiple pins/software-programmable input ranges

+5 V (10 V p-p), +10 V (20 V p-p), ±5 V (20 V p-p),

±10 V (40 V p-p) Pins or serial SPI®-compatible input ranges/mode selection Throughput

1 MSPS (warp mode)

800 kSPS (normal mode)

670 kSPS (impulse mode) 14-bit resolution with no missing codes INL: ±0.3 LSB typical, ±1 LSB maximum (±61 ppm of FSR) SNR: 85 dB @ 2 kHz iCMOS® process technology 5 V internal reference: typical drift 3 ppm/°C; TEMP output No pipeline delay (SAR architecture) Parallel (14- or 8-bit bus) and serial 5 V/3.3 V interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible Power dissipation

235 mW @ 1 MSPS

10 mW @ 1 kSPS 48-lead LQFP and 48-lead LFCSP (7 mm × 7 mm)

APPLICATIONS

Process controls Medical instruments High speed data acquisition Digital signal processing Instrumentation Spectrum analysis AT E

GENERAL DESCRIPTION

The AD7952 is a 14-bit, charge redistribution, successive approximation register (SAR) architecture analog-to-digital converter (ADC) fabricated on Analog Devices, Inc.’s iCMOS high voltage process. The device is configured through hardware or via a dedicated write-only serial configuration port for input range and operating mode. The AD7952 contains a high speed 14-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. A falling edge on samples the fully differential analog inputs on IN+ and IN−. The AD7952 features four different analog input ranges and three different sampling modes: warp mode for the fastest throughput, normal mode for the fastest asynchronous throughput, and impulse mode where power is scaled with throughput. Operation is specified from −40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

CNVST

Programmable Input PulSAR® ADC

AD7952

FUNCTIONAL BLOCK DIAGRAM

TEMP

REFBUFIN

AGND

AVDD

PDREF

PDBUF

CNVST

RESET

REF

IN+

IN–

CONTROL LOGI C AND

CALIBRATI ON CIRCUI TRY

WARP IMPULSE BI POLAR TEN

REF REFGND

REF AMP

SWITCHED

CAP DAC

CLOCK

Figure 1.

AD7952

SERIAL DATA

CONFIG URATION

PARALLEL

INTERF ACE

Table 1. 48-Lead PulSAR Selection

100 to 250

Res

(kSPS)

Input Type

Bipolar 14 AD7951

Differential

Bipolar

Unipolar 16 AD7651 AD7653

AD7660 AD7650 AD7667

AD7661 AD7652

AD7664

AD7666

Bipolar 16 AD7610 AD7665 AD7612 AD7663 AD7671

Differential 16 AD7675 AD7676 AD7677 AD7621

Unipolar AD7622

AD7623

Simultaneous/ 16 AD7654 Multichannel

Unipolar

Differential 18 AD7678 AD7679 AD7674 AD7641

Unipolar AD7643

Differential

Bipolar

(Bits)

14 AD7952

AD7655

AD7631 AD7634

500 to 570 (kSPS)

PORT

SERIAL

PORT

DGNDDVDD

570 to 1000 (kSPS)

OVDD

OGND

D[13:0]

SER/PAR

BYTESWAP

OB/2C

BUSY

>1000 kSPS

06589-001

Page 2

AD7952

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics........................................... 12

Te r mi n ol o g y .................................................................................... 16

Theory of Operation ...................................................................... 17

Overview...................................................................................... 17

Converter Operation.................................................................. 17

Modes of Operation ................................................................... 18

Transfer Fu nctions ...................................................................... 18

Typical Con ne ction Diag ram ................................................... 18

Analog Inputs.............................................................................. 20

Driver Amplifier Choice ........................................................... 21

Voltage Reference Input/Output.............................................. 22

Power Supplies............................................................................ 22

Conversion Control ................................................................... 23

Interfaces.......................................................................................... 24

Digital Interface.......................................................................... 24

Parallel Interface......................................................................... 24

Serial Interface............................................................................ 25

Master Serial Interface............................................................... 25

Slave Serial Interface .................................................................. 27

Hardware Configuration ...........................................................29

Software Configuration............................................................. 29

Microprocessor Interfacing....................................................... 30

Application Information................................................................ 31

Layout Guidelines....................................................................... 31

Evaluating Performance ............................................................ 31

Outline Dimensions .......................................................................32

Ordering Guide .......................................................................... 32

REVISION HISTORY

2/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

Page 3

AD7952

SPECIFICATIONS

AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V

Table 2.

Parameter Conditions/Comments Min Typ Max Unit RESOLUTION 14 Bits ANALOG INPUTS

Differential Voltage Range, V

0 V to 5 V VIN = 10 V p-p −V 0 V to 10 V VIN = 20 V p-p −2 V ±5 V VIN = 20 V p-p −2 V ±10 V VIN = 40 V p-p −4 V

Operating Voltage Range V

0 V to 5 V −0.1 +5.1 V 0 V to 10 V −0.1 +10.1 V ±5 V −5.1 +5.1 V ±10 V −10.1 +10.1 V

Common-Mode Voltage Range V

5 V V 10 V V

Bipolar Ranges −0.1 0 +0.1 V Analog Input CMRR fIN = 100 kHz 75 dB Input Current V Input Impedance See Analog Inputs section

THROUGHPUT SPEED

Complete Cycle In warp mode 1 µs Throughput Rate In warp mode 1 1 MSPS Time Between Conversions In warp mode 1 ms Complete Cycle In normal mode 1.25 µs Throughput Rate In normal mode 0 800 kSPS Complete Cycle In impulse mode 1.49 µs Throughput Rate In impulse mode 0 670 kSPS

DC ACCURACY

Integral Linearity Error No Missing Codes Differential Linearity Error

Transition Noise 0.55 LSB Zero Error (Unipolar or Bipolar) −15 +15 LSB Zero-Error Temperature Drift ±1 ppm/°C Full-Scale Error (Unipolar or Bipolar) −20 +20 LSB Full-Scale Error Temperature Drift ±1 ppm/°C Power Supply Sensitivity AVDD = 5 V ± 5% ±0.8 LSB

AC ACCURACY

Dynamic Range fIN = 2 kHz, −60 dB 84.5 85.5 dB Signal-to-Noise Ratio, SNR fIN = 2 kHz 84.5 85.5 dB f Signal-to-(Noise + Distortion), SINAD fIN = 2 kHz 83 85.4 dB Total Harmonic Distortion fIN = 2 kHz −105 dB Spurious-Free Dynamic Range fIN = 2 kHz 102 dB

−3 dB Input Bandwidth VIN = 0 V to 5 V 45 MHz Aperture Delay 2 ns Aperture Jitter 5 ps rms Transient Response Full-scale step 500 ns

) − (V

IN+

)

IN−

, V

to AGND

IN−

, V

IN−

= ±5 V, ±10 V @ 670 kSPS 220

−1 ±0.3 +1 LSB 14 Bits

−1 +1 LSB

= 20 kHz 85.5 dB

= 5 V; all specifications T

REF

/2 − 0.1 V

REF

− 0.2 V

REF

to T

MIN

MAX

+V +2 V +2 V +4 V

/2 V

REF

, unless otherwise noted.

REF

/2 + 0.1 V

REF

+ 0.2 V

REF

µA

V V V V

Rev. 0 | Page 3 of 32

Page 4

AD7952

Parameter Conditions/Comments Min Typ Max Unit INTERNAL REFERENCE PDREF = PDBUF = low

Output Voltage REF @ 25°C 4.965 5.000 5.035 V Temperature Drift –40°C to +85°C ±3 ppm/°C Line Regulation AVDD = 5 V ± 5% ±15 ppm/V Long-Term Drift 1000 hours 50 ppm Turn-On Settling Time C

REFERENCE BUFFER PDREF = high

REFBUFIN Input Voltage Range 2.4 2.5 2.6 V

EXTERNAL REFERENCE PDREF = PDBUF = high

Voltage Range REF 4.75 5 AVDD + 0.1 V Current Drain 1 MSPS throughput 200 µA

TEMPERATURE PIN

Voltage Output @ 25°C 311 mV Temperature Sensitivity 1 mV/°C Output Resistance 4.33 kΩ

DIGITAL INPUTS

Logic Levels

DIGITAL OUTPUTS

Data Format Parallel or serial 14-bit Pipeline Delay

POWER SUPPLIES

Specified Performance

AVDD 4.75 DVDD 4.75 5 5.25 V OVDD 2.7 5.25 V VCC 7 15 15.75 V VEE −15.75 −15 0 V

Operating Current

7, 8

AVDD

With Internal Reference 20 mA

With Internal Reference Disabled 18.5 mA DVDD 7 mA OVDD 0.5 mA VCC VCC = 15 V, with internal reference buffer 4 mA VCC = 15 V 3 mA VEE VEE = −15 V 2 mA

Power Dissipation @ 1 MSPS throughput

With Internal Reference PDREF = PDBUF = low 235 260 mW With Internal Reference Disabled PDREF = PDBUF = high 215 240 mW

In Power-Down Mode9 PD = high 10 µW

TEMPERATURE RANGE

Specified Performance T

With VIN = unip olar 5 V or unipolar 10 V ranges, the input current is typically 70 A. In all input ranges, the input current scales with throughput. See the Analog Inputs section.

Linearity is tested using endpoints, not best fit. All linearity is tested with an external 5 V reference.

LSB means least significant bit. All specifications in LSB do not include the error contributed by the reference.

All specifications in dB are referred to a full-scale range input, FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

Conversion results are available immediately after completed conversion.

4.75 V or V

Tested in parallel reading mode.

With internal reference, PDREF = PDBUF = low; with internal reference disabled, PDREF = PDBUF = high. With internal reference buffer, PDBUF = low.

With all digital inputs forced to OVDD.

Consult sales for extended temperature range.

− 0.1 V, whichever is larger.

REF

= 22 µF 10 ms

REF

−0.3 +0.6 V

2.1 OVDD + 0.3 V

−1 +1 µA

= 500 µA 0.4 V

SINK

= −500 µA OVDD − 0.6 V

SOURCE

5 5.25 V

@ 1 MSPS throughput

MIN

to T

MAX

−40 +85 °C

Rev. 0 | Page 4 of 32

Page 5

AD7952

TIMING SPECIFICATIONS

AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; V

Table 3.

Parameter Symbol Min Typ Max Unit

CONVERSION AND RESET (See Figure 34 and Figure 35)

Convert Pulse Width t

Time Between Conversions t

Warp Mode/Normal Mode/Impulse Mode

CNVST Low to BUSY High Delay

BUSY High All Modes (Except Master Serial Read After Convert) t

Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns Aperture Delay t End of Conversion to BUSY Low Delay t Conversion Time t

Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns Acquisition Time t

Warp Mode/Normal Mode/Impulse Mode 200 ns RESET Pulse Width t

PARALLEL INTERFACE MODES (See Figure 36 and Figure 38)

CNVST Low to DATA Valid Delay

Warp Mode/Normal Mode/Impulse Mode 850/1100/1350 ns DATA Valid to BUSY Low Delay t Bus Access Request to DATA Valid t Bus Relinquish Time t

MASTER SERIAL INTERFACE MODES2 (See Figure 40 and Figure 41)

CS Low to SYNC Valid Delay CS Low to Internal SDCLK Valid Delay

CS Low to SDOUT Delay CNVST Low to SYNC Delay, Read During Convert

Warp Mode/Normal Mode/Impulse Mode 50/290/530 ns SYNC Asserted to SDCLK First Edge Delay t Internal SDCLK Period Internal SDCLK High Internal SDCLK Low SDOUT Valid Setup Time SDOUT Valid Hold Time SDCLK Last Edge to SYNC Delay

CS High to SYNC High-Z CS High to Internal SDCLK High-Z CS High to SDOUT High-Z BUSY High in Master Serial Read After Convert

CNVST Low to SYNC Delay, Read After Convert

Warp Mode/Normal Mode/Impulse Mode 710/950/1190 ns SYNC Deasserted to BUSY Low Delay t

= 5 V; all specifications T

REF

10 ns

MIN

to T

, unless otherwise noted.

MAX

1/1.25/1.49 s t

35 ns

2 ns 10 ns

10 ns

20 ns 40 ns 2 15 ns

10 ns 10 ns 10 ns

3 ns 30 45 ns 15 ns 10 ns 4 ns 5 ns 5 ns 10 ns 10 ns

10 ns See Table 4

25 ns

Rev. 0 | Page 5 of 32

Page 6

AD7952

Parameter Symbol Min Typ Max Unit

SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES2

Figure 43, Figure 44, and Figure 46)

(See External SDCLK, SCCLK Setup Time t External SDCLK Active Edge to SDOUT Delay t SDIN/SCIN Setup Time t SDIN/SCIN Hold Time t External SDCLK/SCCLK Period t External SDCLK/SCCLK High t External SDCLK/SCCLK Low t

In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.

In serial interface modes, the SYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

In serial master read during convert mode. See Table 4 for serial master read after convert mode.

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit

SYNC to SDCLK First Edge Delay Minimum t Internal SDCLK Period Minimum t Internal SDCLK Period Maximum t Internal SDCLK High Minimum t Internal SDCLK Low Minimum t SDOUT Valid Setup Time Minimum t SDOUT Valid Hold Time Minimum t SDCLK Last Edge to SYNC Delay Minimum t BUSY High Width Maximum t

Warp Mode 1.60 2.35 3.75 6.75 µs Normal Mode 1.85 2.60 4.00 7.00 µs Impulse Mode 2.10 2.85 4.25 7.25 µs

5 ns 2 18 ns 5 ns 5 ns 25 ns 10 ns 10 ns

3 20 20 20 ns 30 60 120 240 ns 45 90 180 360 ns 12 30 60 120 ns 10 25 55 115 ns 4 20 20 20 ns 5 8 35 90 ns 5 7 35 90 ns

1.6mA I

TO OUTPUT

60pF

500µA I

NOTES

1. IN SERIAL INTERFACE MODES, T HE SYNC, SDCLK, AND SDOUT ARE DEF INED WIT H A MAXIMUM LOAD

OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, and SDCLK Outputs, C

1.4V

0.8V

6589-002

DELAY

0.8V0.8V

06589-003

Figure 3. Voltage Reference Levels for Timing

= 10 pF

Rev. 0 | Page 6 of 32

Page 7

AD7952

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs/Outputs

IN+1, IN−1 to AGND VEE − 0.3 V to VCC + 0.3 V REF, REFBUFIN, TEMP,

REFGND to AGND

AVDD + 0.3 V to AGND − 0.3 V

Ground Voltage Differences

AGND, DGND, OGND ±0.3 V

Supply Voltages

AVDD, DVDD, OVDD −0.3 V to +7 V AVDD to DVDD, AVDD to OVDD ±7 V DVDD to OVDD ±7 V VCC to AGND, DGND –0.3 V to +16.5 V VEE to GND +0.3 V to −16.5 V

Digital Inputs −0.3 V to OVDD + 0.3 V PDREF, PDBUF Internal Power Dissipation Internal Power Dissipation

±20 mA 700 mW

2.5 W Junction Temperature 125°C Storage Temperature Range −65°C to +125°C

See the Analog Inputs section.

Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W,

θJC = 30°C/W.

Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 7 of 32

Page 8

AD7952

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VEE

DGND

IN–

VCC

REFGND

REF

BIPOLAR

CNVST

RESET

TEN

BUSY

D13/SCCS

D12/SCCLK

D11/SCIN

D10/HW/SW

D8/SYNC

D7/SDCLK

D6/SDOUT

D9/RDERRO R

06589-004

AGND

AVD D

AGND

BYTESWAP

OB/2C

WARP

IMPULSE

SER/PAR

D0/DIVSCLK[0]

D1/DIVSCLK[1]

NC = NO CONNECT

REFBUFIN

TEMP

AD7952

TOP VIEW

(Not to Scale)

D4/INVSCLK

D5/RDC/SDIN

IN+

AVD D

AGND

DVDD

OVDD

OGND

PDBUF

PDREF

48 47 46 45 44 43 42 41 40 39 38 37

PIN 1

14 15 16 17 18 19 20 21 22 23 24

D2/EXT/INT

D3/INVSYNC

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Type1Description

1, 3, 42 AGND P

Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be referenced to AGND and should be connected to the analog ground plane of the system. In addition,

the AGND, DGND, and OGND voltages should be at the same potential. 2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 F and 100 nF capacitors. 4 BYTESWAP DI

Parallel Mode Selection (8 Bit/14 Bit). When high, the LSB is output on D[15:8] and the MSB is output

on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. 5

OB/

Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary.

When low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI

Conversion Mode Selection. Used in conjunction with the IMPULSE input per the following.

Conversion Mode WARP IMPULSE

Normal Low Low Impulse Low High Warp High Low Normal High High See the Modes of Operation section for a more detailed description. 7 IMPULSE DI

Conversion Mode Selection. See the WARP pin description in this table. See the Modes of Operation

section for a more detailed description. 8

SER/

PA R

DI Serial/Parallel Selection Input.

When SER/

PA R = low, the parallel mode is selected. PA R = high, the serial modes are selected. Some bits of the data bus are used as a serial

port, and the remaining data bits are high impedance outputs. 9, 10 NC DO No Connect. Do not connect. 11, 12 D[0:1] or DI/O In parallel mode, these outputs are used as Bit 0 and Bit 1 of the parallel port data output bus. DIVSCLK[0:1]

Serial Data Division Clock Selection. In serial master read after convert mode (SER/

INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial

EXT/

PA R = high,

data clock that clocks the data output. In other serial modes, these pins are high impedance outputs.

Rev. 0 | Page 8 of 32

Page 9

AD7952

Pin No. Mnemonic Type1Description

13 D2 or DI/O In parallel mode, this output is used as Bit 2 of the parallel port data output bus.

14 D3 or DI/O In parallel mode, this output is used as Bit 3 of the parallel port data output bus. INVSYNC

15 D4 or DI/O In parallel mode, this output is used as Bit 4 of the parallel port data output bus. INVSCLK

16 D5 or DI/O In parallel mode, this output is used as Bit 5 of the parallel port data output bus. RDC or

SDIN

17 OGND P

18 OVDD P

19 DVDD P

20 DGND P

21 D6 or DO In parallel mode, this output is used as Bit 6 of the parallel port data output bus. SDOUT

22 D7 or DI/O In parallel mode, this output is used as Bit 7 of the parallel port data output bus. SDCLK

23 D8 or DO In parallel mode, this output is used as Bit 8 of the parallel port data output bus. SYNC

INT

EXT/

Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated (master) or external (slave) serial data clock for the AD7952 output data. When EXT/

When EXT/INT = high (slave mode), the output data is synchronized to an external clock signal (gated by

Serial Data Invert Sync Select. In serial master mode (SER/ used to select the active state of the SYNC signal.

When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low.

In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK. When INVSCLK = low, the rising edge of SDCLK/SCCLK are used. When INVSCLK = high, the falling edge of SDCLK/SCCLK are used.

Serial Data Read During Convert. In serial master mode (SER/ used to select the read mode. Refer to the Master Serial Interface section.

When RDC = low, the current result is read after conversion. Note the maximum throughput is not attainable in this mode. When RDC = high, the previous conversion result is read during the current conversion.

Serial Data In. In serial slave mode (SER/ to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence.

Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should be connected to the system digital ground ideally at the same potential as AGND and DGND.

Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface 2.5 V, 3 V, or 5 V and decoupled with 10 F and 100 nF capacitors.

Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 F and 100 nF capacitors. Can be supplied from AVDD.

Digital Power Ground. Ground reference point for digital outputs. Should be connected to system digital ground ideally at the same potential as AGND and OGND.

Serial Data Output. In all serial modes, this pin is used as the serial data output synchronized to SDCLK. Conversion results are stored in an on-chip register. The AD7952 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/

When EXT/ When EXT/INT = high (slave mode): When INVSCLK = low, SDOUT is updated on SDCLK rising edge. When INVSCLK = high, SDOUT is updated on SDCLK falling edge.

Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output, dependent on the logic state of the EXT/ updated depends on the logic state of the INVSCLK pin.

Serial Data Frame Synchronization. In serial master mode (SER/ output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while

the SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while the SDOUT output is valid.

INT = low (master mode), the internal serial data clock is selected on SDCLK output.

CS) connected to the SDCLK input.

PA R = high, EXT/INT = low), this input is

PA R = high, EXT/INT = low), RDC is

PA R = high, EXT/INT = high), SDIN can be used as a data input

2C.

INT = low (master mode), SDOUT is valid on both edges of SDCLK.

INT pin. The active edge where the data SDOUT is

PA R = high, EXT/INT= low), this

Rev. 0 | Page 9 of 32

Page 10

AD7952

Pin No. Mnemonic Type1Description

24 D9 or DO In parallel mode, this output is used as Bit 9 of the parallel port data output bus. RDERROR

Serial Data Read Error. In serial slave mode (SER/

an incomplete data read error flag. If a data read is started and not completed when the current

conversion is completed, the current data is lost and RDERROR is pulsed high. 25 D10 or DI/O In parallel mode, this output is used as Bit 10 of the parallel port data output bus.

HW/

Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure

the AD7952 by hardware or software. See the

Configuration

When HW/

section.

SW = low, the AD7952 is configured through software using the serial configuration register.

When HW/SW = high, the AD7952 is configured through dedicated hardware input pins. 26 D11 or DI/O In parallel mode, this output is used as Bit 11 of the parallel port data output bus. SCIN

Serial Configuration Data Input. In serial software configuration mode (SER/

this input is used to serially write in, MSB first, the configuration data into the serial configuration

register. The data on this input is latched with SCCLK. See the 27 D12 or DI/O In parallel mode, this output is used as Bit 12 of the parallel port data output bus. SCCLK

Serial Configuration Clock. In serial software configuration mode (SER/

input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends

on the logic state of the INVSCLK pin. See the 28 D13 or DI/O In parallel mode, this output is used as Bit 13 of the parallel port data output bus.

SCCS

Serial Configuration Chip Select. In serial software configuration mode (SER/

this input enables the serial configuration port. See the Software Configuration section. 29 BUSY DO

Busy Output. Transitions high when a conversion is started and remains high until the conversion

is completed and the data is latched into the on-chip shift register. The falling edge of BUSY can be

used as a data-ready clock signal. Note that in master read after convert mode (SER/

EXT/

INT = low, RDC = low), the busy time changes according to Table 4.

30 TEN DI

Input Range Select. Used in conjunction with BIPOLAR per the following.

Input Range (V) BIPOLAR TEN

0 to 5 Low Low 0 to 10 Low High ±5 High Low ±10 High High 31

RD CS

DI DI

Read Data. When

Chip Select. When

CS and RD are both low, the interface parallel or serial output bus is enabled.

CS and RD are both low, the interface parallel or serial output bus is enabled. CS

is also used to gate the external clock in slave serial mode (not used for serial configurable port). 33 RESET DI

Reset Input. When high, reset the AD7952. Current conversion, if any, is aborted. The falling edge of

RESET resets the data outputs to all zeros (with OB/

See the

Digital Interface section. If not used, this pin can be tied to OGND.

Power-Down Input. When PD = high, powers down the ADC. Power consumption is reduced and

34 PD DI

conversions are inhibited after the current one is completed. The digital interface remains active

during power-down. 35

CNVST

Conversion Start. A falling edge on

CNVST puts the internal sample-and-hold into the hold state and

initiates a conversion. 36 BIPOLAR DI 37 REF AI/O

Input Range Select. See description for Pin 30.

Reference Input/Output. When PDREF/PDBUF = low, the internal reference and buffer are enabled,

producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled,

allowing an externally supplied voltage reference up to AVDD volts. Decoupling with at least a 22 F

capacitor is required with or without the internal reference and buffer. See the

section. 38 REFGND AI Reference Input Analog Ground. Connected to analog ground plane.

PA R = high, EXT/INT = high), this output is used as

Hardware Configuration section and Software

PA R = high, HW/SW = low),

Software Configuration section.

PA R = high, HW/SW = low), this

Software Configuration section.

PA R = high, HW/SW = low),

PA R = high,

2C = high) and clears the configuration register.

Reference Decoupling

Rev. 0 | Page 10 of 32

Page 11

AD7952

Pin No. Mnemonic Type1Description

39 IN− AI

40 VCC P High Voltage Positive Supply. Normally 7 V to 15 V. 41 VEE P High Voltage Negative Supply. Normally 0 V to −15 V (0 V in unipolar ranges). 43 IN+ AI

45 TEMP AO

46 REFBUFIN AI

47 PDREF DI

48 PDBUF DI

AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.

In serial configuration mode (SER/

Hardware Configuration section and Software Configuration section.

Analog Input. Referenced to IN+. In the 0 V to 5 V input range, IN− is between 0 V and V 10 V range, IN− is between 0 V and 2 V

V centered about V

REF

V centered about V

REF

In the ±5 V and ±10 V ranges, IN− is true bipolar up to ±2 V

REF

V (±5 V range) or ±4 V

REF

/2. In the 0 V to

REF

V (±10 V range)

REF

and centered about 0 V. In all ranges, IN− must be driven 180° out of phase with IN+.

Analog Input. Referenced to IN−. In the 0 V to 5 V input range, IN+ is between 0 V and V 10 V range, IN+ is between 0 V and 2 V

V centered about V

REF

V centered about V

REF

In the ±5 V and ±10 V ranges, IN+ is true bipolar up to ±2 V

REF

V (±5 V range) or ±4 V

REF

/2. In the 0 V to

REF

V (±10 V range)

REF

and centered about 0 V. In all ranges, IN+ must be driven 180° out of phase with IN−.

Temperature Sensor Analog Output. When the internal reference is enabled (PDREF = PDBUF = low), this pin outputs a voltage proportional to the temperature of the AD7952. See the

Temperature Sensor

section. Reference Buffer Input. When using an external reference with the internal reference buffer

(PDBUF = low, PDREF = high), applying 2.5 V on this pin produces 5 V on the REF pin. See the

Single-to-Differential Driver section.

Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down, and an external reference must be used.

Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered down.

PAR

= high, HW/SW = low), this input is programmed with the serial configuration register, and this pin is a don’t care. See the

Rev. 0 | Page 11 of 32

Page 12

AD7952

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = −15 V; V

1.0 POSITIVE INL = +0.15

NEGATIVE INL = –0.15

= 5 V; TA = 25°C.

REF

1.0 POSITIVE DNL = +0.27

NEGATIVE DNL = –0.27

0.5

INL (LSB)

–0.5

–1.0

0 4096 8192 12288 16384

CODE

Figure 5. Integral Nonlinearity vs. Code

250

200

150

100

NUMBER OF UNITS

0 –1.0 –0.8 –0.6 –0. 4 –0. 2 0 0.2 0.4 0.6 0.8 1. 0

INL DISTRIBUTION (LSB)

NEGATIVE INL POSITIVE INL

Figure 6. Integral Nonlinearity Distribution (239 Devices)

300000

261120

250000

0.5

DNL (LSB)

–0.5

–1.0

0 4096 8192 12288 16384

06589-005

CODE

06589-008

Figure 8. Differential Nonlinearity vs. Code

200

180

160

140

120

100

NUMBER OF UNIT S

0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0. 8 1.0

06589-006

DNL DISTRIBUT ION (LSB)

NEGATIVE DNL POSITIVE DNL

06589-009

Figure 9. Differential Nonlinearity Distribution (239 Devices)

140000

120000

132052

129068

200000

150000

COUNTS

100000

50000

1FFF 2000 2001 2002 2003

CODE IN HEX

Figure 7. Histogram of 261,120 Conversions of a DC Input

at the Code Center

6589-007

Rev. 0 | Page 12 of 32

100000

80000

60000

COUNTS

40000

20000

8192 8193 8194 8195 8196 8197

CODE IN HEX

Figure 10. Histogram of 261,120 Conversions of a DC Input

at the Code Transition

6589-010

Page 13

AD7952

–

–20

–40

–60

= 1000kSPS

= 19.94kHz

SNR = 85.4dB THD = –107dB SFDR = 116dB SINAD = 85.4dB

86.5

86.0 SNR

–80

–100

–120

AMPLITUDE ( dB OF FUL L SCALE)

–140

–160

0 100 200 400300 500

FREQUENCY (kHz)

Figure 11. FFT 20 kHz

SNR, SINAD (d B)

1 10 100

ENOB

FREQUENCY (kHz)

Figure 12. SNR, SINAD, and ENOB vs. Frequency

SNR

SINAD

14.5

14.3

14.1

13.9

13.7

13.5

SINAD

85.5

SNR, SINAD REFERRE D TO FULL SCALE (dB)

85.0

–60 –50 –40 –30 –20 –10 0

06589-011

INPUT LEVEL (dB)

06589-014

Figure 14. SNR and SINAD vs. Input Level (Referred to Full Scale)

–80

SFDR

–90

–100

THD

ENOB (Bits)

06589-012

THIRD HARMONIC

–110

THD, HARMONICS (dB)

SECOND HARMONIC

–120

–130

1101

FREQUENCY (kHz)

120

110

100

SFDR (dB)

06589-015

Figure 15. THD, Harmonics, and SFDR vs. Frequency

86.0

85.5

85.0

SNR (dB)

84.5

84.0 –55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE ( °C)

0V TO 5V 0V TO 10V ±5V ±10V

Figure 13. SNR vs. Temperature

06589-013

Rev. 0 | Page 13 of 32

86.0

85.5

85.0

SINAD (dB)

84.5

84.0 –55–35–155 25456585105125

TEMPERATURE ( °C)

0V TO 5V 0V TO 10V ±5V ±10V

Figure 16. SINAD vs. Temperature

06589-016

Page 14

AD7952

–

0V TO 5V 0V TO 10V ±5V ±10V

–100

–104

–108

THD (dB)

–112

–116

–120

–55–35–155 25456585105125

TEMPERATURE ( °C)

Figure 17. THD vs. Temperature

06589-017

124

122

120

118

116

114

SFDR (dB)

112

110

108

106

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE ( °C)

0V TO 5V 0V TO 10V ±5V ±10V

Figure 20. SFDR vs. Temperature (Excludes Harmonics)

06589-020

1.5

NEGATIVE

1.0

0.5

–0.5

–1.0

ZERO ERROR, FULL-SCALE ERROR (L SB)

–1.5

–55 125

POSITIVE

FULL-SCAL E ERROR

TEMPERATURE ( °C)

FULL-SCAL E ERROR

ZERO ERROR

25 65 85 105–35 –15 5 45

06589-018

Figure 18. Zero Error, Positive and Negative Full-Scale Error vs. Temperature

NUMBER OF UNIT S

1234567

REFERENCE DRIF T (ppm/ °C)

06589-019

Figure 19. Reference Voltage Temperature Coefficient Distribution (247 Devices)

5.008

5.006

5.004

5.002

VREF (V)

5.000

4.998

4.996 –55 125

25 65 85 105–35 –15 5 45

TEMPERATURE ( °C)

Figure 21. Typical Reference Voltage Output vs. Temperature (3 Devices)

100000

AVDD, WARP/NORMAL

10000

DVDD, ALL MODE S

1000

100

AVDD, IMPULS E

0.1

OPERATING CURRENTS (µA)

OVDD, ALL MODES

0.01

0.001 10

100 1000 10000 100000

SAMPLING RATE (SPS)

VCC +15V VEE –15V ALL MODES

PDREF = PDBUF = HIGH

1000000

Figure 22. Operating Currents vs. Sample Rate

06589-021

06589-022

Rev. 0 | Page 14 of 32

Page 15

AD7952

700

PD = PDBUF = PDREF = HIGH

VEE = –15V VCC = +15V

600

DVDD OVDD AVDD

500

400

300

200

100

POWER–DOW N OPERATING CURRENTS (nA)

–55 –35 –15 5 25 45 65 85 105

TEMPERATURE ( °C)

Figure 23. Power-Down Operating Currents vs. Temperature

06589-023

DELAY (ns)

0 50 100

OVDD = 2.7V @ 25° C

OVDD = 5V @ 25°C

Figure 24. Typical Delay vs. Load Capacitance C

(pF)

OVDD = 2.7V @ 85°C

OVDD = 5V @ 85°C

150 200

6589-024

Rev. 0 | Page 15 of 32

Page 16

AD7952

TERMINOLOGY

Least Significant Bit (LSB)

The least significant bit, or LSB, is the smallest increment that can be represented by a converter. For a fully differential input ADC with N bits of resolution, the LSB expressed in volts is

INp-p

VLSB2)( =

Integral Nonlinearity Error (INL)

Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs a ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSBs beyond the last code transition. The deviation is measured from the middle of each code to the true straight line.

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.

Bipolar Zero Error

The difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code.

Unipolar Offset Error

The first transition should occur at a level ½ LSB above analog ground. The unipolar offset error is the deviation of the actual transition from that point.

Full-Scale Error

The last transition (from 111…10 to 111…11) should occur for an analog voltage 1½ LSB below the nominal full scale. The fullscale error is the deviation in LSB (or % of full-scale range) of the actual level of the last transition from the ideal level and includes the effect of the offset error. Closely related is the gain error (also in LSB or % of full-scale range), which does not include the effects of the offset error.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to the rms noise measured for an input typically at −60 dB. The value for dynamic range is expressed in decibels.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels.

Spurious-Free Dynamic Range (SFDR)

The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by

ENOB = [(SINAD

− 1.76)/6.02]

Aperture Delay

Aperture delay is a measure of the acquisition performance measured from the falling edge of the

CNVST

input to when

the input signal is held for a conversion.

Transi ent Res p ons e

The time required for the AD7952 to achieve its rated accuracy after a full-scale step function is applied to its input.

Reference Voltage Temperature Coefficient

Reference voltage temperature coefficient is derived from the typical shift of the output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (V ) measured at T , T (25°C), and T . It is expressed in ppm/°C as

TCV

MIN MAX

)Cppm/( ×

REF

=°

REF

MinVMaxV

REFREF

MAX

TTV

MIN

×°

REF

)(–)(

)–(C)(25

where:

(Max) = maximum V

REF

(Min) = minimum V

REF

(25°C) = V

REF

MAX

MIN

= +85°C.

= –40°C.

REF

at 25°C.

REF

at T

MIN

, T (25°C), or T

MAX

Rev. 0 | Page 16 of 32

Page 17

AD7952

THEORY OF OPERATION

IN+

MSB

8192C

4096C 4C 2C C C

REF

REFGND

4C 2C C C

Figure 25. ADC Simplified Schematic

IN–

8192C

MSB

4096C

OVERVIEW

The AD7952 is a very fast, low power, precise, 14-bit ADC using successive approximation, capacitive digital-to-analog (CDAC) converter architecture.

The AD7952 can be configured at any time for one of four input ranges and conversion mode with inputs in parallel and serial hardware modes or by a dedicated write-only, SPI-compatible interface via a configuration register in serial software mode. The AD7952 uses Analog Devices’ patented iCMOS high voltage process to accommodate 0 V to +5 V, 0 V to +10 V, ±5 V, and ±10 V input ranges without the use of conventional thin films. Only one acquisition cycle, t to latch to the correct configuration. Resetting or power cycling is not required for reconfiguring the ADC.

The AD7952 features different modes to optimize performance according to the applications. It is capable of converting 1,000,000 samples per second (1 MSPS) in warp mode, 800 kSPS in normal mode, and 670 kSPS in impulse mode.

The AD7952 provides the user with an on-chip, track-and-hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple, multiplexed channel applications.

For unipolar input ranges, the AD7952 typically requires three supplies: VCC, AVDD (which can supply DVDD), and OVDD (which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic). For bipolar input ranges, the AD7952 requires the use of the additional VEE supply.

The device is housed in Pb-free, 48-lead LQFP or tiny, 48-lead LFCSP (7 mm × 7 mm) that combines space savings with flexibility. In addition, the AD7952 can be configured as either a parallel or a serial SPI-compatible interface.

, is required for the inputs

AGND

SWITCHES

COMP

CONTROL

LOGIC

CNVST

BUSY

OUTPUT

CODE

06589-025

LSB

SW+

SW–

AGND

CONVERTER OPERATION

The AD7952 is a successive approximation ADC based on a charge redistribution DAC. schematic of the ADC. The CDAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the comparator’s input are connected to AGND via SW+ and SW−. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on IN+ and IN− inputs. A conversion phase is initiated once the acquisition phase is completed and the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the inputs (IN+ and IN−) captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies by binary weighted voltage steps (V

/2, V

REF

/4 through V

REF

these switches, starting with the MSB first, to bring the comparator back into a balanced condition.

After the completion of this process, the control logic generates the ADC output code and brings the BUSY output low.

Figure 25 shows the simplified

CNVST

input goes low. When the

/16,384). The control logic toggles

REF

Rev. 0 | Page 17 of 32

Page 18

AD7952

MODES OF OPERATION

The AD7952 features three modes of operation: warp, normal, and impulse. Each of these modes is more suitable to specific applications. The mode is configured with the input pins, WARP and IMPULSE, or via the configuration register. See the pin details and the

Hardware Configuration section and Software Configuration section for programming the mode selection with either pins or configuration register. Note that when using the configuration register, the WARP and IMPULSE inputs are don’t cares and should be tied to either high or low.

Warp Mode

Setting WARP = high and IMPULSE = low allows the fastest conversion rate up to 1 MSPS. However, in this mode, the full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms (after power-up), the first conversion result should be ignored because in warp mode, the ADC performs a background calibration during the SAR conversion process. This calibration can drift if the time between conversions exceeds 1 ms, thus causing the first conversion to appear offset. This mode makes the AD7952 ideal for applications where both high accuracy and fast sample rate are required.

Normal Mode

Setting WARP = IMPULSE = low or WARP = IMPULSE = high allows the fastest mode (800 kSPS) without any limitation on time between conversions. This mode makes the AD7952 ideal for asynchronous applications, such as data acquisition systems, where both high accuracy and fast sample rate are required.

Impulse Mode

Setting WARP = low and IMPULSE = high uses the lowest power dissipation mode and allows power saving between conversions. The maximum throughput in this mode is 670 kSPS, and in this mode, the ADC powers down circuits after conversion, making the AD7952 ideal for battery-powered applications.

Table 6 for

TRANSFER FUNCTIONS

Using the OB/2C digital input or via the configuration register, the AD7952 offers two output codings: straight binary and twos complement. See

Figure 26 and Table 7 for the ideal transfer characteristic and digital output codes for the different analog input ranges, V register, the OB/

. Note that when using the configuration

input is a don’t care and should be tied to

either high or low.

111... 111

111... 110

111... 101

ADC CODE (Straigh t Binary)

000... 010

000... 001

000... 000

–FSR

–FSR + 0.5 LSB

ANALOG INPUT

Figure 26. ADC Ideal Transfer Function

+FSR – 1.5 LSB

+FSR –1LSB–FSR + 1 LSB

06589-026

TYPICAL CONNECTION DIAGRAM

Figure 27 shows a typical connection diagram for the AD7952 using the internal reference, serial data, and serial configuration interfaces. Different circuitry from that shown in optional and is discussed in the following sections.

Figure 27 is

Table 7. Output Codes and Ideal Input Voltages

Description

= 0 V to 5 V

(10 V p-p)

VIN = 0 V to 10 V (20 V p-p)

FSR − 1 LSB 4.999695 V 9.999389 V +4.999389 V +9.998779 V 0x3FFF

= 5 V Digital Output Code

REF

VIN = ±5 V (20 V p-p)

VIN = ±10 V (40 V p-p)

Straight Binary Twos Complement

0x1FFF FSR − 2 LSB 4.999390 V 9.998779 V +4.998779 V +9.997558 V 0x3FFE 0x1FFE Midscale + 1 LSB 2.500610 V 5.000610 V +1.228 mV +2.442 mV 0x2001 0x0001 Midscale 2.5 V 5.000000 V 0 V 0 V 0x2000 0x0000 Midscale − 1 LSB 2.499390 V 4.999389 V −1.228 mV −2.442 mV 0x1FFF 0x3FFF

−FSR + 1 LSB 610.4 µV 1.228 mV −4.999389 V −9.998779 V 0x0001 0x2001

−FSR 0 V 0 V −5 V −10 V 0x0000

This is also the code for overrange analog input (V

− V

above V

IN+

IN−

− V

below V

IN+

IN−

− V

REF

REFGND

− V

REFGND

Rev. 0 | Page 18 of 32

0x2000

Page 19

AD7952

+7V TO +15.75V

–7V TO –15.75V

ANALOG

SUPPLY (5V)

SUPPLY

NOTE 6

INPUT+

INPUT–

ANALOG

10µF

NOTE 4

NOTE 2

10µF 100n F

100nF

REF

22µF

100nF

15Ω

2.7nF

15Ω

DIGIT AL

NOTE 5

10Ω

10µF

AVDD

AGND DGND DV DD OVDD OG ND

VCC

VEE

NOTE 3

REF

REFBUFI N

REFGND

IN+

IN–

PDREF

SUPPLY (5V)

100nF 100nF

AD7952

NOTE 3

PDBUF

RD CS

BUSY

SDCLK

SDOUT

SCCLK

SCIN

SCCS

CNVST

OB/2C

SER/PAR

HW/SW

BIPOL AR

TEN

WAR P

IMPULSE

RESETPD

10µF

DIGITAL INTERFACE SUPPLY (2.5V, 3.3V, OR 5V)

NOTE 7

33Ω

OVDD

CLOCK

MicroConverter®/

MICROPROCESSOR/

DSP

SERIAL PORT 1

SERIAL PORT 2

2.7nF

NOTE 1

NOTES

1. ANALOG INPUTS ARE DIFFERENTIAL (ANTIPHASE). SEE ANALOG INPUTS SECTION.

2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.

3. THE CONFIGURATI ON SHOWN IS USI NG THE INTERNAL REFERENCE. SEE VOLT AGE REFERENCE INPUT/O UTPUT SECTIO N.

4. A 22µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOM MENDED (FOR EXAMPL E, PANASONIC ECJ4YB1A226M). SEE VOL TAGE RE FERENCE INPUT/ OUTPUT SECTI ON.

5. OPTIONAL, SEE POWER SUPPLIES SECTION.

6. THE VCC AND VEE SUPPLIES SHO ULD BE VCC = [VIN(MAX) + 2V] AND VEE = [VI N(MIN) – 2V] FOR BIPO LAR INPUT RANGES. FOR UNIPOLAR INPUT RANGES, VEE CAN BE 0V. SEE POWER SUPPLIES SECTION.

7. OPTIONAL LOW JI TTER CNVST, SEE CONVERSION CO NTROL SECTION.

8. A SEPARATE ANALOG AND DIGITAL GROUND PLANE IS RECOMMENDED, CONNECTED TOG ETHER DIRECTLY UNDER THE ADC. SEE LAYOUT GUIDELINES SECTION.

AGND

DGND

NOTE 8

Figure 27. Typical Connection Diagram Shown with Serial Interface and Serial Programmable Port

06589-027

Rev. 0 | Page 19 of 32

Page 20

AD7952

ANALOG INPUTS

Input Range Selection

In parallel mode and serial hardware mode, the input range is selected by using the BIPOLAR (bipolar) and TEN (10 V range) inputs. See Configuration programming the mode selection with either pins or the configuration register. Note that when using the configuration register, the BIPOLAR and TEN inputs are don’t cares and should be tied high or low.

Input Structure

Figure 28 shows an equivalent circuit for the input structure of the AD7952.

The four diodes, D1 to D4, provide ESD protection for the analog inputs, IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V because this causes the diodes to become forward-biased and to start conducting current. These diodes can handle a forwardbiased current of 120 mA maximum. For instance, these conditions could eventually occur when the input buffer’s U1 supplies are different from AVDD, VCC, and VEE. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part although most op amps’ short-circuit current is <100 mA. Note that D3 and D4 are only used in the 0 V to 5 V range to allow for additional protection in applications that are switching from the higher voltage ranges.

This analog input structure allows the sampling of the differential signal between IN+ and IN−. By using this differential input, small signals common to both inputs are rejected as shown in Figure 29, which represents the typical CMRR over frequency.

Table 6 for pin details and the Hardware

section and Software Configuration section for

VCC

IN+ OR IN–

VEE

Figure 28. Simplified Analog Input

0VTO 5V

RANGE ONLY

AVD D

AGND

6589-028

For instance, by using IN− to sense a remote signal ground, ground potential differences between the sensor and the local ADC ground are eliminated.

100

CMRR (dB)

1 10000

10 100 1000

FREQUENCY (kHz)

Figure 29. Analog Input CMRR vs. Frequency

06589-029

During the acquisition phase for ac signals, the impedance of the analog inputs, IN+ and IN−, can be modeled as a parallel combination of Capacitor C the series connection of R capacitance. R

is typically 70 Ω and is a lumped component

and the network formed by

and CIN. C

is primarily the pin

comprised of serial resistors and the on resistance of the switches. C

is primarily the ADC sampling capacitor and

depending on the input range selected is typically 48 pF in the 0 V to +5 V range, typically 24 pF in the 0 V to +10 V and ±5 V ranges, and typically 12 pF in the ±10 V range. During the conversion phase, when the switches are opened, the input impedance is limited to C

Because the input impedance of the AD7952 is very high, it can be directly driven by a low impedance source without gain error. To further improve the noise filtering achieved by the AD7952 analog input circuit, an external, 1-pole RC filter between the amplifier’s outputs and the ADC analog inputs can be used, as shown in

Figure 27. However, large source impedances significantly affect the ac performance, especially THD. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency.

Rev. 0 | Page 20 of 32

Page 21

AD7952

DRIVER AMPLIFIER CHOICE

Although the AD7952 is easy to drive, the driver amplifier must meet the following requirements:

• For multichannel, multiplexed applications, the driver

amplifier and the AD7952 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 14-bit level (0.006%). For the amplifier, settling at 0.1% to

0.01% is more commonly specified. This differs significantly from the settling time at a 14-bit level and should be verified prior to driver selection. The bines ultralow noise and high gain bandwidth and meets this settling time requirement even when used with gains of up to 13.

• The noise generated by the driver amplifier needs to be

kept as low as possible to preserve the SNR and transition noise performance of the AD7952. The noise coming from the driver is filtered by the external 1-pole, low-pass filter, as shown in

Figure 27. The SNR degradation due to the

amplifier is

⎛ ⎜

⎜

SNR

LOSS

log20

⎜ ⎜

⎝

NADC

where:

is the noise of the ADC, which is:

NADC

INp-p

V =

NADC

is the cutoff frequency of the input filter (3.9 MHz).

–3dB

SNR

N is the noise factor of the amplifier (1 in the buffer configuration).

and eN− are the equivalent input voltage noise densities

N+

of the op amps connected to IN+ and IN−, in nV/√Hz. When the resistances used around the amplifiers are small,

this approximation can be used. If larger resistances are used, their noise contributions should also be root-sum squared.

•

The driver needs to have a THD performance suitable to

that of the AD7952.

Figure 15 shows the THD vs. frequency

that the driver should exceed.

AD8021 meets these requirements and is appropriate for

The almost all applications. The

AD8021 needs a 10 pF external compensation capacitor that should have good linearity as an NPO ceramic or mica type. Moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the best SNR.

AD8022 can also be used when a dual version is needed

The and a gain of 1 is present. The

AD829 is an alternative in

AD8021 op amp com-

NADC

−

3dB

)(f

NeNeV

−

3dB

)(f

−

applications where high frequency performance (above 100 kHz) is not required. In applications with a gain of 1, an 82 pF compensation capacitor is required. The

AD8610 is an option

when low bias current is needed in low frequency applications. Because the AD7952 uses a large geometry, high voltage input

switch, the best linearity performance is obtained when using the amplifier at its maximum full power bandwidth. Gaining the amplifier to make use of the more dynamic range of the ADC results in increased linearity errors. For applications requiring more resolution, the use of an additional amplifier with gain should precede a unity follower driving the AD7952.

Table 8 for a list of recommended op amps.

See

Table 8. Recommended Driver Amplifiers

Amplifier Typical Application

AD829 ±15 V supplies, very low noise, low frequency AD8021 ±12 V supplies, very low noise, high frequency AD8022

±12 V supplies, very low noise, high frequency, dual

ADA4922-1

⎞ ⎟

AD8610/

⎟

AD8620

⎟ ⎟

⎠

Single-to-Differential Driver

±12 V supplies, low noise, high frequency, single-ended-to-differential driver

±13 V supplies, low bias current, low frequency, single/dual

For single-ended sources, a single-to-differential driver, such as the

ADA4922-1, can be used because the AD7952 needs to

be driven differentially. The 1-pole filter using R = 15 Ω and C = 2.7 nF provides a corner frequency of 3.9 MHz.

15Ω

2.7nF

VCC

VEE

OUT+

ADA4922-1

REF

100nF

ANALOG

INPUT

Figure 30. Single-to-Differential Driver Using the ADA4922-1

2.7nF

OUT–

For unipolar 5 V and 10 V input ranges, the internal (or external) reference source can be used to level shift U2 for the correct input span. If using an external reference, the values for R1/R2 can be lowered to reduce resistive Johnson noise (1.29E − 10 × √R). For the bipolar ±5 V and ±10 V input ranges, the reference connection is not required because the common-mode voltage is 0 V. See

Table 9 for R1/R2 for the

different input ranges.

Table 9. R1/R2 Configuration

Input Range (V) R1 (Ω) R2 (Ω) Common-Mode Voltage (V)

5 2.5 k 2.5 k 2.5 10 2.5 k Open 5 ±5, ±10 100 0

IN+

AD7952

IN–

10µF

REF

06589-047

Rev. 0 | Page 21 of 32

Page 22

AD7952

This circuit can also be made discretely, and thus more flexible, using any of the recommended low noise amplifiers in Again, to preserve the SNR of the converter, the resistors, R

, should be kept low.

and R

Table 8.

VOLTAGE REFERENCE INPUT/OUTPUT

The AD7952 allows the choice of either a very low temperature drift internal voltage reference, an external reference, or an external buffered reference.

The internal reference of the AD7952 provides excellent performance and can be used in almost all applications. However, the linearity performance is guaranteed only with an external reference.

Internal Reference (REF = 5 V, PDREF = Low, PDBUF = Low)

To use the internal reference, the PDREF and PDBUF inputs must be low. This enables the on-chip, band gap reference, buffer, and TEMP sensor, resulting in a 5.00 V reference on the REF pin.

The internal reference is temperature-compensated to 5.000 V ± 35 mV. The reference is trimmed to provide a typical drift of 3 ppm/°C. This typical drift characteristic is shown in

External 2.5 V Reference and Internal Buffer (REF = 5 V, PDREF = High, PDBUF = Low)

To use an external reference with the internal buffer, PDREF should be high and PDBUF should be low. This powers down the internal reference and allows the 2.5 V reference to be applied to REFBUFIN, producing 5 V on the REF pin. The internal reference buffer is useful in multiconverter applications because a buffer is typically required in these applications.

External 5 V Reference (PDREF = High, PDBUF = High)

To use an external reference directly on the REF pin, PDREF and PDBUF should both be high. PDREF and PDBUF power down the internal reference and the internal reference buffer, respectively. For improved drift performance, an external reference, such as the

ADR445 or the ADR435, is recommended.

Reference Decoupling

Whether using an internal or external reference, the AD7952 voltage reference input (REF) has a dynamic input impedance; therefore, it should be driven by a low impedance source with efficient decoupling between the REF and REFGND inputs. This decoupling depends on the choice of the voltage reference but usually consists of a low ESR capacitor connected to REF and REFGND with minimum parasitic inductance. A 22 µF (X5R, 1206 size) ceramic chip capacitor (or 47 µF tantalum capacitor) is appropriate when using either the internal reference or the ADR445/ADR435 external reference.

The placement of the reference decoupling is also important to the performance of the AD7952. The decoupling capacitor should be mounted on the same side as the ADC, right at the REF pin with a thick PCB trace. The REFGND should also connect to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias.

Figure 19.

For applications that use multiple AD7952s or other PulSAR devices, it is more effective to use the internal reference buffer to buffer the external 2.5 V reference voltage.

The voltage reference temperature coefficient (TC) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the TC. For instance, a ±60 ppm/°C TC of the reference changes full scale by ±1 LSB/°C.

Temperature Sensor

When the internal reference is enabled (PDREF = PDBUF = low), the on-chip temperature sensor output (TEMP) is enabled and can be use to measure the temperature of the AD7952. To improve the calibration accuracy over the temperature range, the output of the TEMP pin is applied to one of the inputs of the analog switch (such as

ADG779), and the ADC itself is used to

measure its own temperature. This configuration is shown

Figure 31.

ANALOG INPUT

ADG779

Figure 31. Use of the Temperature Sensor

IN+

TEMP

AD7952

TEMPERATURE SENSOR

POWER SUPPLIES

The AD7952 uses five sets of power supply pins:

AVDD: analog 5 V core supply

•

VCC: analog high voltage, positive supply

•

VEE: high voltage, negative supply

•

DVDD: digital 5 V core supply

•

OVDD: digital input/output interface supply

•

Core Supplies

The AVDD and DVDD supply the AD7952 analog and digital cores, respectively. Sufficient decoupling of these supplies is required, consisting of at least a 10 F capacitor and a 100 nF capacitor on each supply. The 100 nF capacitors should be placed as close as possible to the AD7952. To reduce the number of supplies needed, the DVDD can be supplied through a simple RC filter from the analog supply, as shown in

High Voltage Supplies

The high voltage bipolar supplies, VCC and VEE, are required and must be at least 2 V larger than the maximum input, V For example, if using the bipolar 10 V range, the supplies should be ±12 V minimum. Sufficient decoupling of these supplies is also required, consisting of at least a 10 F capacitor and a 100 nF capacitor on each supply. For unipolar operation, the VEE supply can be grounded with some slight THD performance degradation.

Digital Output Supply

The OVDD supplies the digital outputs and allows direct interface with any logic working between 2.3 V and 5.25 V.

Figure 27.

06589-030

Rev. 0 | Page 22 of 32

Page 23

AD7952

OVDD should be set to the same level as the system interface. Sufficient decoupling is required, consisting of at least a 10 F capacitor and a 100 nF capacitor with the 100 nF capacitors placed as close as possible to the AD7952.

Power Sequencing

The AD7952 is independent of power supply sequencing and is very insensitive to power supply variations on AVDD over a wide frequency range, as shown in

(dB)

PSR

1 10000

EXT REF

INT REF

10 100 1000

Figure 32. AVDD PSRR vs. Frequency

Figure 32.

FREQUENCY (kHz)

6589-031

Power Dissipation vs. Throughput

In impulse mode, the AD7952 automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low, which allows a significant power savings when the conversion rate is reduced

Figure 33). This feature makes the AD7952 ideal for very

(see low power, battery-operated applications.

It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, drive the digital inputs close to the power rails (that is, OVDD and OGND).

1000

WARP MODE PO WER

100

Power Down

Setting PD = high powers down the AD7952, thus reducing supply currents to their minimums, as shown in

Figure 23. When the ADC is in power-down, the current conversion (if any) is completed and the digital bus remains active. To further reduce the digital supply currents, drive the inputs to OVDD or OGND.

Power-down can also be programmed with the configuration register. See the

Software Configuration section for details. Note that when using the configuration register, the PD input is a don’t care and should be tied to either high or low.

CONVERSION CONTROL

The AD7952 is controlled by the

CNVST

is all that is necessary to initiate a conversion. A detailed timing diagram of the conversion process is shown in Figure 34. Once initiated, it cannot be restarted or aborted, even by the power-down input, PD, until the conversion is

CNVST

completed. The

signals.

and

CNVST

BUSY

MODE

signal operates independently of the CS

CONVERT ACQ UIREACQUIRE CONVERT

Figure 34. Basic Conversion Timing

Although

CNVST

is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot, undershoot, or ringing.

CNVST

The

trace should be shielded with ground, and a low value (such as 50 Ω) serial resistor termination should be added close to the output of the component that drives this line.

For applications where SNR is critical, the have very low jitter. This can be achieved by using a dedicated

CNVST

oscillator for

generation, or by clocking

high frequency, low jitter clock, as shown in

CNVST

input. A falling edge

CNVST

signal should

CNVST

with a

Figure 27.

6589-033

IMPULSE MODE PO WER

POWER DISSIPATIO N (mW)

10 1000000

100 1000 10000 100000

PDREF = PDBUF = HIG H

06589-032

Figure 33. Power Dissipation vs. Sample Rate

Rev. 0 | Page 23 of 32

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AD7952

INTERFACES

DIGITAL INTERFACE

The AD7952 has a versatile digital interface that can be set up as either a serial or a parallel interface with the host system. The serial interface is multiplexed on the parallel data bus. The AD7952 digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic. In most applications, the OVDD supply pin is connected to the host system interface 2.5 V to 5.25 V digital supply. Finally, by using

the OB/ coding can be used.

Two signals, one of these signals is high, the interface outputs are in high impedance. Usually, multicircuit applications and is held low in a single AD7952 design. the data bus.

RESET

The RESET input is used to reset the AD7952. A rising edge on RESET aborts the current conversion (if any) and tristates the data bus. The falling edge of RESET resets the AD7952 and clears the data bus and configuration register. See the RESET timing details.

input pin, both twos complement or straight binary

and RD, control the interface. When at least

allows the selection of each AD7952 in

is generally used to enable the conversion result on

Figure 35 for

CS = RD = 0

CNVST

BUSY

DATA

BUS

PREVIOUS CONVERS ION DATA NEW DATA

Figure 36. Master Parallel Data Timing for Reading (Continuous Read)

Slave Parallel Interface

In slave parallel reading mode, the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in

Figure 37 and Figure 38, respectively. When the data is read during the conversion, it is recommended that it is read-only during the first half of the conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry.

06589-035

RESET

BUSY

DATA

BUS

CNVST

Figure 35. RESET Timing

PARALLEL INTERFACE

The AD7952 is configured to use the parallel interface when

PA R

SER/

Master Parallel Interface

Data can be continuously read by tying CS and RD low, thus requiring minimal microprocessor connections. However, in this mode, the data bus is always driven and cannot be used in shared bus applications (unless the device is held in RESET). Figure 36 details the timing for this mode.

is held low.

BUSY

DATA

BUS

6589-034

CURRENT

CONVERS ION

06589-036

Figure 37. Slave Parallel Data Timing for Reading (Read After Convert)

CS = 0

CNVST,

BUSY

DATA

BUS

CONVERSION

06589-037

Figure 38. Slave Parallel Data Timing for Reading (Read During Convert)

Rev. 0 | Page 24 of 32

Page 25

AD7952

8-Bit Interface (Master or Slave)

The BYTESWAP pin allows a glueless interface to an 8-bit bus. As shown in

Figure 39, when BYTESWAP is low, the LSB byte is output on D[7:0] and the MSB is output on D[13:8]. When BYTESWAP is high, the LSB and MSB bytes are swapped; the LSB is output on D[13:8] and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 14-bit data can be read in two bytes on either D[13:8] or D[7:0]. This interface can be used in both master and slave parallel reading modes.

BYTESWAP

PINS D[13:8]

PINS D[7:0]

HI-Z

Figure 39. 8-Bit and 14-Bit Parallel Interface

HIGH BYTE LOW BYTE

LOW BYT E HIGH BYTE

HI-Z

SERIAL INTERFACE

The AD7952 has a serial interface (SPI-compatible) multiplexed on the data pins D[13:0]. The AD7952 is configured to use the

PA R

serial interface when SER/

Data Interface

The AD7952 outputs 14 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 14 clock pulses provided on the SDCLK pin. The output data is valid on both the rising and falling edge of the data clock.

Serial Configuration Interface

The AD7952 can be configured through the serial configuration register only in serial mode, because the serial configuration pins are also multiplexed on the data pins D[13:10]. See the Hardware Configuration section and Software Configuration section for more information.

is held high.

06589-038

MASTER SERIAL INTERFACE

The pins multiplexed on D[8:0] and used for master serial

INT

interface are: DIVSCLK[0], DIVSCLK[1], EXT/ INVSCLK, RDC, SDOUT, SDCLK, and SYNC.

Internal Clock (SER/

PAR

= High, EXT/

INT

The AD7952 is configured to generate and provide the serial

INT

data clock, SDCLK, when the EXT/

pin is held low. The AD7952 also generates a SYNC signal to indicate to the host when the serial data is valid. The SDCLK and the SYNC signals can be inverted, if desired, using the INVSCLK and INVSYNC inputs, respectively. Depending on the input, RDC, the data can be read during the following conversion or after each conversion. Figure 40 and Figure 41 show detailed timing diagrams of these two modes.

Read During Convert (RDC = High)

Setting RDC = high allows the master read (previous conversion result) during conversion mode. Usually, because the AD7952 is used with a fast throughput, this mode is the most recommended serial mode. In this mode, the serial clock and data toggle at appropriate instances, minimizing potential feedthrough between digital activity and critical conversion decisions. In this mode, the SDCLK period changes because the LSBs require more time to settle and the SDCLK is derived from the SAR conversion cycle. In this mode, the AD7952 generates a discontinuous SDCLK of two different periods and the host should use an SPI interface.

Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3])

Setting RDC = low allows the read after conversion mode. Unlike the other serial modes, the BUSY signal returns low after the 14 data bits are pulsed out and not at the end of the conversion phase, resulting in a longer BUSY width (refer to Table 4 for BUSY timing specifications). The DIVSCLK[1:0] inputs control the SDCLK period and SDOUT data rate. As a result, the maximum throughput cannot be achieved in this mode. In this mode, the AD7952 also generates a discontinuous SDCLK; however, a fixed period and hosts supporting both SPI and serial ports can also be used.

, INVSYNC,

= Low)

Rev. 0 | Page 25 of 32

Page 26

AD7952

EXT/INT = 0

CS, RD

CNVST

BUSY

SYNC

SDCLK

SDOUT

RDC/SDIN = 0 INVSCLK = INVSYNC = 0

D13 D12 D2 D1 D0

123 121314

06589-039

Figure 40. Master Serial Data Timing for Reading (Read After Convert)

CS, RD

CNVST

BUSY

EXT/INT = 0

RDC/SDIN = 1 I NVSCLK = INVSYNC = 0

SYNC

SDCLK

SDOUT

t20t

123 121314

D13 D12 D2 D1 D0X

06589-040

Figure 41. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)

Rev. 0 | Page 26 of 32

Page 27

AD7952

CNVST

BUSY OUT

DATA OUT

6589-041

SLAVE SERIAL INTERFACE

The pins multiplexed on D[19:2] used for slave serial

INT

interface are: EXT/ SDCLK, and RDERROR.

External Clock (SER/

Setting the EXT/ externally supplied serial data clock on the SDCLK pin. In this mode, several methods can be used to read the data. The external serial clock is gated by low, the data can be read after each conversion or during the following conversion. A clock can be either normally high or normally low when inactive. For detailed timing diagrams,

Figure 43 and Figure 44.

see While the AD7952 is performing a bit decision, it is important

that voltage transients be avoided on digital input/output pins or degradation of the conversion result may occur. This is particularly important during the last 450 ns of the conversion phase because the AD7952 provides error correction circuitry that can correct for an improper bit decision made during the first part of the conversion phase. For this reason, it is recommended that any external clock provided is a discontinuous clock that transitions only when BUSY is low or, more importantly, that it does not transition during the last 450 ns of BUSY high.

External Discontinuous Clock Data Read After Conversion

Though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. Figure 43 shows the detailed timing diagrams for this method. After a conversion is complete, indicated by BUSY returning low, the conversion result can be read while both Data is shifted out MSB first with 14 clock pulses and, depending on the SDCLK frequency, can be valid on the falling and rising edges of the clock.

One advantage of this method is that conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. Another advantage is the ability to read the data at any speed up to 40 MHz, which accommodates both the slow digital host interface and the fastest serial reading.

Daisy-Chain Feature

Also in the read after convert mode, the AD7952 provides a daisy-chain feature for cascading multiple converters together using the serial data input pin, SDIN. This feature is useful for reducing component count and wiring connections when desired, for instance, in isolated multiconverter applications.

Figure 43 for the timing details.

See An example of the concatenation of two devices is shown in

Figure 42.

, INVSCLK, SDIN, SDOUT,

PAR

= High, EXT/

INT

= high allows the AD7952 to accept an

INT

= High)

. When CS and RD are both

and RD are low.

Simultaneous sampling is possible by using a common signal. Note that the SDIN input is latched on the opposite edge of SDCLK used to shift out the data on SDOUT (SDCLK falling edge when INVSCLK = low). Therefore, the MSB of the upstream converter follows the LSB of the downstream converter on the next SDCLK cycle. In this mode, the 40 MHz SDCLK rate cannot be used because the SDIN-to-SDCLK setup

, is less than the minimum time specified. (SDCLK-

time, t

to-SDOUT delay, t

, is the same for all converters when

simultaneously sampled). For proper operation, the SDCLK edge for latching SDIN (or ½ period of SDCLK) needs to be

ttt

SDCLK

2/1

3332

or the maximum SDCLK frequency needs to be

SDCLK

)(2

ttf+

3332

If not using the daisy-chain feature, the SDIN input should always be tied either high or low.

BUSYBUSY

AD7952

(UPSTREAM)

RDC/SDIN SDOUT

CNVST

SDCLK

SDCLK IN

CS IN

CNVST IN

Figure 42. Two AD7952 Devices in a Daisy-Chain Configuration

AD7952

(DOWNSTREAM)

SDOUTRDC/SDIN

CNVST

SDCLK

External Clock Data Read During Previous Conversion

Figure 44 shows the detailed timing diagrams for this method. During a conversion, while both

and RD are low, the result of the previous conversion can be read. The data is shifted out, MSB first, with 14 clock pulses, and depending on the SDCLK frequency, can be valid on both the falling and rising edges of the clock. The 14 bits have to be read before the current conversion is completed; otherwise, RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading.

To reduce performance degradation due to digital activity, a fast discontinuous clock of at least 40 MHz is recommended to ensure that all the bits are read during the first half of the SAR conversion phase.

The daisy-chain feature should not be used in this mode because digital activity occurs during the second half of the SAR conversion phase, likely resulting in performance degradation.

Rev. 0 | Page 27 of 32

Page 28

AD7952

External Clock Data Read After/During Conversion

It is also possible to begin to read data after conversion and continue to read the last bits after a new conversion is initiated. This method allows the full throughput and the use of a slower SDCLK frequency. Again, it is recommended to use a discontinuous SDCLK whenever possible to minimize potential incorrect bit decisions. For the different modes, the use of a slower SDCLK, such as 20 MHz in warp mode, 15 MHz in normal mode, and 13 MHz in impulse mode can be used.

EXT/INT = 1 INVSCLK = 0

D12

D11

BUSY

SDCLK

SDOUT

SER/PAR = 1 RD = 0

1 2 3 13 14

D13

15 16

X13 X12

SDIN

*A DISCONTINUO US SDCLK IS RECOMMENDED.

X13

X12

X11

Y13 Y12

06589-042

Figure 43. Slave Serial Data Timing for Reading (Read After Convert)

SER/PAR = 1 RD = 0

CNVST

BUSY

SDCLK

SDOUT

*A DISCONTINUOUS SDCLK IS RECO MMENDED.

123

D13

Figure 44. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)

EXT/INT = 1 INVSCLK = 0

D12

X* X*

DATA = SDIN

06589-043

Rev. 0 | Page 28 of 32

Page 29

AD7952

HARDWARE CONFIGURATION

The AD7952 can be configured at any time with the dedicated hardware pins WARP, IMPULSE, BIPOLAR, TEN, OB/ PD for parallel mode (SER/

PA R

(SER/

= high, HW/SW = high). Programming the AD7952

PA R

= low) or serial hardware mode

, and

for mode selection and input range configuration can be done before or during conversion. Like the RESET input, the ADC requires at least one acquisition time to settle, as shown in Figure 45. See Table 6 for pin descriptions. Note that these inputs are high impedance when using the software configuration mode.

SOFTWARE CONFIGURATION

The pins multiplexed on D[13:10] used for software configura-

tion are: HW/

, SCIN, SCCLK, and programmed using the dedicated write-only serial configurable port (SCP) for conversion mode, input range selection, output coding, and power-down using the serial configuration register. See

Table 10 for details of each bit in the configuration register.

The SCP can only be used in serial software mode selected with

PA R

SER/

= high and HW/SW = low because the port is

multiplexed on the parallel interface. The SCP is accessed by asserting the port’s chip select,

and then writing SCIN synchronized with SCCLK, which (like SDCLK) is edge sensitive depending on the state of INVSCLK. See

Figure 46 for timing details. SCIN is clocked into the configuration register MSB first. The configuration register is an internal shift register that begins with Bit 8, the START bit. The

SPPCLK edge updates the register and allows the new settings to

9 be used. As indicated in the timing diagram, at least one acquisition

time is required from the 9

SCCLK edge. Bits [1:0] are reserved

bits and are not written to while the SCP is being updated. The SCP can be written to at any time, up to 40 MHz, and it is

recommended to write to while the AD7952 is not busy converting, as detailed in

Figure 46. In this mode, the full

1 MSPS is not attainable because the time required for SCP access

+ 9 × 1/SCCLK + t8) minimum. If the full throughput is

is (t

required, the SCP can be written to during conversion; however,

SCCS

. The AD7952 is

SCCS

HW/SW = 0

it is not recommended to write to the SCP during the last 450 ns of conversion (BUSY = high), or performance degradation can result. In addition, the SCP can be accessed in both serial master and serial slave read during and read after convert modes.

Note that at power-up, the configuration register is undefined. The RESET input clears the configuration register (sets all bits to 0), thus placing the configuration to 0 V to 5 V input, normal mode, and twos complemented output.

Table 10. Configuration Register Description

Bit Name Description

8 START

7 BIPOLAR Input Range Select. Used in conjunction with Bit 6,

0 to 5 Low Low 0 to 10 Low High ±5 High Low ±10 High High 6 TEN Input Range Select. See Bit 7, BIPOLAR. 5 PD Power Down.

4 IMPULSE

Normal Low Low Impulse Low High Warp High Low Normal High High 3 WARP Mode Select. See Bit 4, IMPULSE. 2

1 RSV Reserved. 0 RSV Reserved.

SER/PAR = 0, 1PD = 0

OB/

START bit. With the SCP enabled ( when START is high, the first rising edge of SCCLK (INVSCLK = low) begins to load the register with the new configuration.

TEN, per the following.

Input Range (V) BIPOLAR TEN

PD = low, normal operation. PD = high, power down the ADC. The SCP is accessible while in power-down. To power-up the ADC, write PD = low on the next configuration setting.

Mode Select. Used in conjunction with Bit 3, WARP, per the following.

Mode WARP IMPULSE

Output Coding.

= low, use twos complement output.

OB/

= high, use straight binary output.

SCCS

= low),

CNVST

BUSY

BIPOLAR,

TEN

WAR P,

IMPULSE

Figure 45. Hardware Configuration Timing

Rev. 0 | Page 29 of 32

6589-044

Page 30

AD7952

CNVST

BUSY

SCCS

CCL

SCIN

WARP = 0 OR 1

IMPULSE = 0 OR 1

BIPOLAR = 0 O R 1 TEN = 0 OR 1

123 67

BIPOLAR

START

SER/PAR = 1 HW/SW = 0

INVSCLK = 0

PD = 0

IMPULSE

Figure 46. Serial Configuration Port Timing

MICROPROCESSOR INTERFACING

The AD7952 is ideally suited for traditional dc measurement applications supporting a microprocessor and ac signal processing applications interfacing to a digital signal processor. The AD7952 is designed to interface with a parallel 8-bit or 14-bit wide interface, or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7952 to prevent digital noise from coupling into the ADC.

SPI Interface

The AD7952 is compatible with SPI and QSPI digital hosts and DSPs, such as Blackfin® ADSP-BF53x and ADSP-218x/ADSP-219x. Figure 47 shows an interface diagram between the AD7952 and the SPI-equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7952 acts as a slave device, and data must be read after conversion. This mode also allows the daisy-chain feature. The convert command could be initiated in response to an internal timer interrupt.

OB/2C

WAR PTEN

The reading process can be initiated in response to the end-ofconversion signal (BUSY going low) using an interrupt line of the DSP. The serial peripheral interface (SPI) on the ADSP-219x is configured for master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 0 by writing to the SPI control register (SPICLTx).

It should be noted that to meet all timing requirements, the SPI clock should be limited to 17 Mbps, allowing it to read an ADC result in less than 1 µs. When a higher sampling rate is desired, use one of the parallel interface modes.

AD7952*

SER/PAR

EXT/INT

INVSCLK

*ADDITIONAL PINS OMIT TED FOR CL ARITY.

BUSY

SDOUT

SDCLK

CNVST

ADSP-219x*

PFx

SPIxSEL (PFx)

MISOx

SCKx

PFx OR TFSx

Figure 47. Interfacing the AD7952 to SPI Interface

06589-045

06589-046

Rev. 0 | Page 30 of 32

Page 31

AD7952

APPLICATION INFORMATION

LAYOUT GUIDELINES

While the AD7952 has very good immunity to noise on the power supplies, exercise care with the grounding layout. To facilitate the use of ground planes that can be easily separated, design the printed circuit board that houses the AD7952 so that the analog and digital sections are separated and confined to certain areas of the board. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7952, or as close as possible to the AD7952. If the AD7952 is in a system where multiple devices require analog-to-digital ground connections, the connections should still be made at one point only, a star ground point, established as close as possible to the AD7952.

To prevent coupling noise onto the die, to avoid radiating noise, and to reduce feedthrough:

Do not run digital lines under the device.

•

Do run the analog ground plane under the AD7952.

• Shield fast switching signals, like

digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths.

Avoid crossover of digital and analog signals.

•

Run traces on different but close layers of the board, at right

angles to each other, to reduce the effect of feedthrough through the board.

The power supply lines to the AD7952 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the impedance of the supplies presented to the AD7952, and to reduce the magnitude of the supply spikes. Decoupled ceramic capacitors, typically 100 nF, should be placed on each of the power supplies pins, AVDD, DVDD, OVDD, VCC, and VEE. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 µF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple.

CNVST

or clocks, with

The DVDD supply of the AD7952 can either be a separate supply or come from the analog supply, AVDD, or from the digital interface supply, OVDD. When the system digital supply is noisy, or fast switching digital signals are present, and no separate supply is available, it is recommended to connect the DVDD digital supply to the analog supply AVDD through an RC filter, and to connect the system supply to the interface digital supply OVDD and the remaining digital circuitry. See configuration. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes.

The AD7952 has four different ground pins: REFGND, AGND, DGND, and OGND.

REFGND senses the reference voltage and, because it carries

•

pulsed currents, should be a low impedance return to the reference.

•

AGND is the ground to which most internal ADC analog

signals are referenced; it must be connected with the least resistance to the analog ground plane.

DGND must be tied to the analog or digital ground plane

•

depending on the configuration.

OGND is connected to the digital system ground.

•

The layout of the decoupling of the reference voltage is important. To minimize parasitic inductances, place the decoupling capacitor close to the ADC and connect it with short, thick traces.

Figure 27 for an example of this

EVALUATING PERFORMANCE

A recommended layout for the AD7952 is outlined in the EVAL-AD7952CBZ evaluation board documentation. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3.

Rev. 0 | Page 31 of 32

Page 32

AD7952

OUTLINE DIMENSIONS

1.45

1.40

1.35

0.15

0.05

ROTATED 90° CCW

PIN 1 INDICATOR

SEATING PLANE

VIEW A

7.00

BSC SQ

TOP

VIEW

9.20

0.50

BSC

9.00 SQ

8.80

PIN 1

TOP VIEW

(PINS DO WN)

0.75

0.60

0.45

0.20

0.09 7°

3.5° 0°

0.08 COPLANARIT Y

COMPLIANT TO JEDEC STANDARDS MS-026-BBC

1.60 MAX

VIEW A

LEAD PITCH

Figure 48. 48-Lead Low Profile Quad Flat Package [LQFP]

(ST-48)

Dimensions shown in millimeters

0.30

0.23

0.18

6.75

BSC SQ

0.60 MAX

(BOTTOM VIEW)

EXPOSED

7.20

7.00 SQ

6.80

0.27

0.22

0.17

051706-A

PIN 1

INDICATOR

5.25

5.10 SQ

4.95

1.00

0.85

0.80

12° MAX

SEATING PLANE

0.50

0.40

0.30

0.80 MAX

0.65 TYP

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

0.20 REF

0.05 MAX

0.02 NOM

COPLANARIT Y

0.08

5.50 REF

0.25 MIN

PADDLE CONNECTED TO VEE. THIS CONNECTI ON IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.

Figure 49. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

7 mm × 7 mm Body, Very Thin Quad

(CP-48-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7952BCPZ AD7952BCPZRL AD7952BSTZ AD7952BSTZRL EVAL-AD7952CBZ EVAL-CONTROL BRD3

Z = Pb-free part.

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes.

This board allows a PC to control and communicate with all Analog Devices evaluation boards ending with the CB designators.

1, 2

−40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1

−40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48

−40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48 Evaluation Board

Controller Board

Rev. 0 | Page 32 of 32

TTT

Datasheet AD7952 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual