Page 1
14-Bit, 250 kSPS PulSAR
Pseudo Differential ADC in MSOP/QFN
FEATURES
14-bit resolution with no missing codes
Throughput: 250 kSPS
INL: ±0.4 LSB typ, ±1 LSB max (±0.0061% of FSR)
SINAD: 85 dB @ 20 kHz
THD: −100 dB @ 20 kHz
Pseudo differential analog input range
0 V to V
with V
REF
No pipeline delay
Single-supply 2.3 V to 5.5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®-/QSPI
DSP-compatible
Daisy-chaining for multiple ADCs and busy indicator
Power dissipation
1.25 mW @ 2.5 V/100 kSPS, 3.6 mW @ 5 V/100 kSPS
1.25 µW @ 2.5 V/100 SPS
Standby current: 1 nA
10-lead package: MSOP (MSOP-8 size) and
3 mm × 3 mm QFN
Pin-for-pin compatible with the 16-bit AD7685
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control
GENERAL DESCRIPTION
The AD7942 is a 14-bit, charge redistribution, successive appro-
ximation PulSAR
supply, VDD, between 2.3 V to 5.5 V. It contains a low power,
high speed, 14-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
it samples an analog input IN+ between 0 V to V
to a ground sense IN−. The reference voltage, V
externally and can be set up to be the supply voltage. Its power
scales linearly with the throughput.
up to VDD
REF
™-/MICROWIRE™-/
1
(LFCSP) (SOT-23 size)
® ADC that operates from a single power
with respect
REF
, is applied
REF
AD7942
APPLICATION DIAGRAM
0.5V TO 5V 2.5V TO 5V
0 TO V
REF
IN+
IN–
REF
AD7942
GND
VDD
VIO
SDI
SCK
SDO
CNV
Figure 1.
Table 1. MSOP, QFN1 (LFCSP)/SOT-23, 14 and 16-Bit ADCs
Type 100 kSPS 250 kSPS 500 kSPS
16-Bit True
AD7684 AD7687 AD7688
Differential
16-Bit Pseudo
AD7683
Differential/Unipolar
16-Bit Unipolar AD7680
14-Bit Pseudo
Differential/Unipolar
14-Bit Unipolar AD7940
1
QFN package in development. Contact sales for samples and availability.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single
3-wire bus and provides an optional busy indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate
supply VIO.
The AD7942 is housed in a 10-lead MSOP or a 10-lead
1
(LFCSP) package with operation specified from −40°C
QFN
to +85°C.
1.8V TO VDD
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
AD7685
AD7694
AD7942
AD7686
AD7946
04657-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
www.analog.com
Page 2
AD7942
TABLE OF CONTENTS
Specifications..................................................................................... 3
Converter Operation.................................................................. 13
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Te r m in o l o g y ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Circuit Information.................................................................... 13
REVISION HISTORY
3/05—Revision 0: Initial Version
Typical C o n n e ction D i a g r am ................................................... 14
Digital Interface.......................................................................... 16
Application Hints ........................................................................... 23
Layout .......................................................................................... 23
Evaluating the AD7942’s Performance.................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Rev. 0 | Page 2 of 24
Page 3
AD7942
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 14 Bits
ANALOG INPUT
Voltage Range IN+ − IN− 0 V
Absolute Input Voltage IN+ −0.1 VDD + 0.1 V
IN− −0.1 0.1 V
Analog Input CMRR fIN = 250 kHz 65 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance See the Analog Input section
ACCURACY
No Missing Codes 14 Bits
Differential Linearity Error −0.7 ±0.3 +0.7 LSB
Integral Linearity Error −1 ±0.4 +1 LSB
Transition Noise V
Gain Error2, T
MIN
to T
MAX
±0.7 ±6 LSB
Gain Error Temperature Drift ±1 ppm/°C
Offset Error2, T
MIN
to T
MAX
VDD = 4.5 V to 5.5 V ±0.45 ±3 mV
VDD = 2.3 V to 4.5 V ±0.75 ±4.5 mV
Offset Temperature Drift ±2.5 ppm/°C
Power Supply Sensitivity
VDD = 5 V ± 5%
THROUGHPUT
Conversion Rate VDD = 4.5 V to 5.5 V 0 250 kSPS
VDD = 2.3 V to 4.5 V 0 200 kSPS
Transient Response Full-scale step 1.8 µs
AC ACCURACY
Signal-to-Noise fIN = 20 kHz, V
f
Spurious-Free Dynamic Range fIN = 20 kHz −100 dB
Total Harmonic Distortion fIN = 20 kHz −100 dB
Signal-to-Noise and Distortion fIN = 20 kHz, V
(SINAD)
f
−60 dB input
f
1
LSB means least significant bit. With a 5 V input range, one LSB is 305.2 µV.
2
See the section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. Terminology
3
All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
= VDD, TA = –40°C to +85°C, unless otherwise noted.
REF
REF
= VDD = 5 V 0.33 LSB
REF
±0.1 LSB
= 5 V 84.5 85 dB
REF
= 20 kHz, V
IN
= 20 kHz, V
IN
= 20 kHz, V
IN
= 2.5 V 84 dB
REF
= 5 V 83 85 dB
REF
= 5 V,
REF
= 2.5 V 84 dB
REF
25 dB
V
1
3
Rev. 0 | Page 3 of 24
Page 4
AD7942
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, V
Table 3.
Parameter Conditions Min Typ Max Unit
REFERENCE
Voltage Range 0.5 VDD + 0.3 V
Load Current 250 kSPS, V
SAMPLING DYNAMICS
−3 dB Input Bandwidth 2 MHz
Aperture Delay VDD = 5 V 2.5 ns
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
–0.3 0.3 × VIO V
0.7 × VIO VIO + 0.3 V
−1 +1 µA
−1 +1 µA
DIGITAL OUTPUTS
Data Format Serial 14 bits straight binary
Pipeline Delay
V
OL
V
OH
I
= +500 µA 0.4 V
SINK
I
= −500 µA VIO − 0.3 V
SOURCE
POWER SUPPLIES
VDD Specified performance 2.3 5.5 V
VIO Specified performance 2.3 VDD + 0.3 V
VIO Range 1.8 VDD + 0.3 V
Standby Current
1, 2
VDD and VIO = 5 V, @ 25°C 1 50 nA
Power Dissipation VDD = 2.5 V, 100 SPS throughput 1.25 µW
VDD = 2.5 V, 100 kSPS throughput 1.25 2 mW
VDD = 2.5 V, 200 kSPS throughput 2.5 4 mW
VDD = 5 V, 100 kSPS throughput 3.6 5 mW
VDD = 5 V, 250 kSPS throughput 12.5 mW
TEMPERATURE RANGE
Specified Performance T
3
to T
MIN
1
With all digital inputs forced to VIO or GND as required.
2
During acquisition phase.
3
Contact Analog Devices for extended temperature range.
= VDD, TA = –40°C to +85°C, unless otherwise noted.
REF
= 5 V 50 µA
REF
Conversion results available immediately
after completed conversion
MAX
−40 +85 °C
Rev. 0 | Page 4 of 24
Page 5
AD7942
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V1, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, TA = −40°C to +85°C.
Table 4.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time Between Conversions t
CNV Pulse Width ( CS Mode)
SCK Period ( CS Mode)
SCK Period ( Chain Mode) t
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data-Valid Delay t
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with Busy Indicator) t
1
0.5 2.2 µs
1.8 µs
4 µs
10 ns
15 ns
t
t
CONV
ACQ
CYC
CNVH
SCK
SCK
VIO above 4.5 V 17 ns
VIO above 3 V 18 ns
VIO above 2.7 V 19 ns
VIO above 2.3 V 20 ns
SCKL
SCKH
HSDO
DSDO
7 ns
7 ns
5 ns
VIO above 4.5 V 14 ns
VIO above 3 V 15 ns
VIO above 2.7 V 16 ns
VIO above 2.3 V 17 ns
t
EN
VIO above 4.5 V 15 ns
VIO above 2.7 V 18 ns
VIO above 2.3 V 22 ns
25 ns
15 ns
0 ns
5 ns
5 ns
3 ns
4 ns
CS Mode)
(
t
DIS
t
SSDICNV
t
HSDICNV
SSCKCNV
HSCKCNV
SSDISCK
HSDISCK
DSDOSDI
VIO above 4.5 V 15 ns
VIO above 2.3 V 26 ns
See and for load conditions. Figure 2 Figure 3
Rev. 0 | Page 5 of 24
Page 6
AD7942
VDD = 2.3 V to 4.5 V1, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated, TA = −40°C to +85°C.
Table 5.
Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available t
Acquisition Time t
Time Between Conversions t
CNV Pulse Width ( CS Mode)
SCK Period ( CS Mode)
SCK Period ( Chain Mode) t
t
t
CONV
ACQ
CYC
CNVH
SCK
SCK
VIO Above 3 V 29 ns
VIO Above 2.7 V 35 ns
VIO Above 2.3 V 40 ns
SCK Low Time t
SCK High Time t
SCK Falling Edge to Data Remains Valid t
SCK Falling Edge to Data Valid Delay t
SCKL
SCKH
HSDO
DSDO
VIO Above 3 V 24 ns
VIO Above 2.7 V 30 ns
VIO Above 2.3 V 35 ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
t
EN
VIO Above 2.7 V 18 ns
VIO Above 2.3 V 22 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) t
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) t
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) t
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) t
SDI High to SDO High (Chain Mode with Busy Indicator) t
t
DIS
t
SSDICNV
t
HSDICNV
SSCKCNV
HSCKCNV
SSDISCK
HSDISCK
DSDOSDI
1
See and for load conditions. Figure 2 Figure 3
0.7 3.2 µs
1.8 µs
5 µs
10 ns
25 ns
12 ns
12 ns
5 ns
25 ns
30 ns
0 ns
5 ns
8 ns
5 ns
4 ns
36 ns
Rev. 0 | Page 6 of 24
Page 7
AD7942
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Analog Inputs
IN+1, IN−1
GND − 0.3 V to VDD + 0.3 V
or ±130 mA
REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD, VIO to GND −0.3 V to +7 V
VDD to VIO ±7 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND −0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 200°C/W (MSOP-10)
θJC Thermal Impedance 44°C/W (MSOP-10)
Lead Temperature Range
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1
See the Analog Input section.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
500µAI
TO SDO
50pF
C
L
500µAI
Figure 2. Load Circuit for Digital Interface Timing
30% VIO
t
DELAY
2V OR VIO – 0.5V
0.8V OR 0.5V
NOTES
1
2V IF VIO ABOVE 2.5V, VIO– 0.5V IF VIO BELOW 2.5V.
2
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 3. Voltage Reference Levels for Timing
OL
1.4V
OH
70% VIO
1
2
04657-002
t
DELAY
2V OR VIO – 0.5V
0.8V OR 0.5V
1
2
04657-003
Rev. 0 | Page 7 of 24
Page 8
AD7942
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
REF
2
VDD
IN+
3
AD7942
IN–
4
GND
5
Figure 4.10-Lead MSOP and QFN
10
VIO
9
SDI
SCK
8
SDO
7
CNV
6
1
(LFCSP) Pin Configuration
04657-004
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type2Function
1 REF AI
Reference Input Voltage. The V
range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
REF
be decoupled closely to the pin with a 10 µF capacitor.
2 VDD P Power Supply.
3 IN+ AI
Analog Input. It is referred to IN−. The voltage range, i.e., the difference between IN+ and IN−, is 0 V
to V
.
REF
4 IN− AI Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground.
5 GND P Power Supply Ground.
6 CNV DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode of the part, chain or
CS mode. In CS mode, it enables the SDO pin when low. In
chain mode, the data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9 SDI DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 14 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the busy
indicator feature is enabled.
10 VIO P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).
1
QFN package in development. Contact sales for samples and availability.
2
AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power.
Rev. 0 | Page 8 of 24
Page 9
AD7942
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight
line (see Figure 23).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (152.6 µV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Gain Error
The last transition (from 111...10 to 111...11) should occur
for an analog voltage 1½ LSB below the nominal full scale
(4.999542 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset has been adjusted out.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula
ENOB = (SINAD
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-Noise and Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Transient Response
The time required for the ADC to accurately acquire its input
after a full-scale step function was applied.
− 1.76)/6.02
dB
Rev. 0 | Page 9 of 24
Page 10
AD7942
TYPICAL PERFORMANCE CHARACTERISTICS
1.00
0.75
POSITIVE INL = +0.22LSB
NEGATIVE INL =–0.34LSB
1.00
0.75
POSITIVE DNL = +0.24LSB
NEGATIVE DNL =–0.12LSB
0.50
0.25
0
INL (LSB)
–0.25
–0.50
–0.75
–1.00
0 4096 8192 12288 16384
CODE
Figure 5. Integral Nonlinearity vs. Code
150000
129941
100000
COUNTS
50000
VDD = V
REF
= 2.5V
04657-005
0.50
0.25
0
DNL (LSB)
–0.25
–0.50
–0.75
–1.00
0 4096 8192 12288 16384
CODE
Figure 8. Differential Nonlinearity vs. Code
150000
131072
100000
COUNTS
50000
VDD = V
REF
04657-008
= 5V
0 0 915 216 0 0
0
1FFD 1FFE
1FFF
2000 2001 2002 2003
CODE IN HEX
Figure 6. Histogram of a DC Input at the Code Center
0
–20
–40
–60
–80
–100
–120
–140
AMPLITUDE (dB of Full Scale)
–160
–180
0 25 50 75 100 125
FREQUENCY (kHz)
16384 POINT FFT
VDD = V
f
= 250kSPS
S
f
= 20.43kHz
IN
SNR = 85.1dB
THD = –105dB
SFDR = –105.9dB
Figure 7. FFT Plot
REF
= 5V
04657-006
04657-007
000 0 00
0
1FFD 1FFE
1FFF
2000 2001 2002 2003
CODE IN HEX
Figure 9. Histogram of a DC Input at the Code Center
0
–20
–40
–60
–80
–100
–120
–140
AMPLITUDE (dB of Full Scale)
–160
–180
0 25 50 75 100 125
FREQUENCY (kHz)
16384 POINT FFT
VDD = V
f
= 250kSPS
S
f
= 20.43kHz
IN
SNR = 84.2dB
THD = –101.7dB
SFDR = –104.3dB
Figure 10. FFT Plot
REF
04657-009
= 2.5V
04657-010
Rev. 0 | Page 10 of 24
Page 11
AD7942
86
SNR
85
15.0
14.5
–80
–85
–90
V
= 2.5V,–1dB
REF
SINAD
84
SNR, SINAD (dB)
83
82
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
ENOB
REFERENCE VOLTAGE (V)
Figure 11. SNR, SINAD, and ENOB vs. Reference Voltage
90
V
= 5V, –10dB
85
80
SINAD (dB)
75
70
0 50 100 150 200
FREQUENCY (kHz)
REF
V
REF
V
= 5V, –1dB
REF
= 2.5V, –1dB
14.0
13.5
13.0
ENOB (Bits)
04657-011
04657-012
–95
–100
THD (dB)
–105
–110
–115
0 40 80 120 160 200
V
= 5V,–1dB
REF
FREQUENCY (kHz)
Figure 14. THD vs. Frequency
–90
–100
THD (dB)
–110
–120
–55 –35 –15 5 25 45 65 85 105 125
= 2.5V
V
REF
V
TEMPERATURE (°C)
REF
= 5V
04657-014
04657-015
Figure 12. SINAD vs. Frequency
95
90
V
= 5V
85
SNR (dB)
80
75
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
REF
V
= 2.5V
REF
Figure 13. SNR vs. Temperature
04657-013
Rev. 0 | Page 11 of 24
Figure 15. THD vs. Temperature
1000
fS = 100kSPS
750
VDD
500
250
OPERATING CURRENT (µA)
0
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VIO
SUPPLY (V)
Figure 16. Operating Currents vs. Supply
04657-016
Page 12
AD7942
1000
750
500
250
POWER-DOWN CURRENT (nA)
0
–55 –35 –15 5 25 45 65 85 105 125
VDD+VIO
TEMPERATURE (°C)
Figure 17. Power-Down Currents vs. Temperature
04657-017
6
5
4
3
2
1
0
–1
–2
–3
ZERO ERROR, GAIN ERROR (LSB)
–4
–5
–6
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
ZERO ERROR
GAIN ERROR
Figure 19. Offset and Gain Error vs. Temperature
04657-019
1000
900
800
700
600
500
400
300
OPERATING CURRENT (µA)
200
100
0
–55 –35 –15 5 25 45 65 85 105 125
VDD = 5V
VDD = 2.5V
VIO
TEMPERATURE (°C)
f
= 100kSPS
S
Figure 18. Operating Currents vs. Temperature
04657-018
25
20
15
VDD = 2.5V, 25°C
DELAY (ns)
10
DSDO
t
5
VDD = 3.3V, 25°C
0
Figure 20. t
VDD = 2.5V, 85°C
VDD = 3.3V, 85°C
SDO CAPACITIVE LOAD (pF)
vs. Capacitance Load and Supply
DSDO
VDD = 5V, 25°C
VDD = 5V, 85°C
04657-020
1200 20406080100
Rev. 0 | Page 12 of 24
Page 13
AD7942
IN+
SWITCHES CONTROL
SW+MSB
LSB
REF
GND
4,096C
4,096C
4C 2C C C8,192C
COMP
4C 2C C C8,192C
SW–MSB
LSB
CONTROL
LOGIC
BUSY
OUTPUT CODE
CNV
IN–
Figure 21. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7942 is a fast, low power, single-supply, precise 14-bit
ADC using a successive approximation architecture.
The AD7942 is capable of converting 250,000 samples per
second (250 kSPS) and powers down between conversions.
When operating at 100 SPS, for example, it consumes typically
1.25 µW with a 2.5 V power supply, which is ideal for batterypowered applications.
The AD7942 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7942 is specified from 2.3 V to 5.5 V, and can be
interfaced to either a 5 V, 3.3 V, 2.5 V, or 1.8 V digital logic. It is
housed in a 10-lead MSOP or a tiny 10-lead QFN
offers space saving, yet allows flexible configurations.
It is pin-for-pin-compatible with the 16-bit ADC
1
(LFCSP) that
AD7685.
04657-021
CONVERTER OPERATION
The AD7942 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 14 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase starts,
SW+ and SW− are opened first. The two capacitor arrays are
then disconnected from the inputs and connected to the GND
input. Therefore, the differential voltage between the inputs,
IN+ and IN−, captured at the end of the acquisition phase, is
applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
/2, V
binary weighted voltage steps (V
REF
REF
/4 ... V
control logic toggles these switches, starting with the MSB, in
order to bring the comparator back into a balanced condition.
After the completion of this process, the part returns to the
acquisition phase and the control logic generates the ADC
output code and a busy signal indicator.
/16384). The
REF
Because the AD7942 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
1
QFN package in development. Contact sales for samples and availability.
Rev. 0 | Page 13 of 24
Page 14
AD7942
(NOTE 1)
REF
0 TO V
REF
(NOTE 3)
NOTE 1: SEE REFERENCE SECTION FOR REFERENCE SELECTION.
NOTE 2: C
NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION.
NOTE 4: OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
NOTE 5: SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.
IS USUALLY
REF
A 10µF CERAMIC CAPACITOR (X5R).
Transfer Functions
The ideal transfer characteristic for the AD7942 is shown in
Figure 23 and Table 8.
33Ω
2.7nF
(NOTE 4)
10µF
(NOTE 2)
IN+
IN–
Figure 22. Typical Application Diagram
REF
GND
VDD
AD7942
5V
1.8V TO VDD
3- OR 4-WIRE INTERFACE (NOTE 5)
04657-022
VIO
100nF
100nF
SDI
SCK
SDO
CNV
instance, these conditions could eventually occur when the
input buffer’s (U1) supplies are different from VDD. In such a
case, an input buffer with a short-circuit current limitation can
be used to protect the part.
VDD
111...111
111...110
111...101
ADC CODE (STRAIGHT BINARY)
000...010
000...001
000...000
–FS
–FS + 1 LSB
–FS + 0.5 LSB
ANALOG INPUT
+
+FS – 1.5 LSB
FS – 1 LSB
04657-023
Figure 23. ADC Ideal Transfer Function
TYPICAL CONNECTION DIAGRAM
Figure 22 shows an example of the recommended connection
diagram for the AD7942 when multiple supplies are available.
Analog Input
Figure 24 shows an equivalent circuit of the input structure of
the AD7942.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V because this causes these diodes to become forwardbiased and start conducting current. However, these diodes can
handle a forward-biased current of 130 mA maxi-mum. For
IN+
OR IN–
GND
D1
C
PIN
D2
R
C
IN
IN
04657-024
Figure 24. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the
differential signal between IN+ and IN−. By using this
differential input, small signals common to both inputs are
rejected, as shown in Figure 25, which represents the typical
CMRR over frequency. For instance, by using IN− to sense a
remote signal ground, ground potential differences between the
sensor and the local ADC ground are eliminated.
Table 8. Output Codes and Ideal Input Voltages
Analog Input
Description
V
= 5 V Digital Output Code Hex
REF
FSR – 1 LSB 4.999695 V 0x3FFF1
Midscale + 1 LSB 2.500305 V 0x2001
Midscale 2.5 V 0x2000
Midscale – 1 LSB 2.499695 V 0x1FFF
–FSR + 1 LSB 305.2 µV 0x0001
–FSR 0 V 0x00002
1
This is also the code for an overranged analog input (V
V
– V
).
REF
GND
2
This is also the code for an underranged analog input (V
– V
above
IN+
IN−
– V
below V
IN+
IN−
GND
).
Rev. 0 | Page 14 of 24
Page 15
AD7942
80
70
60
CMRR (dB)
50
40
101 100 1000 10000
FREQUENCY (kHz)
Figure 25. Analog Input C MRR vs. Frequency
VDD = 5V
04657-025
During the acquisition phase, the impedance of the analog
input IN+ can be modeled as a parallel combination of the
capacitor C
of R
IN
and the network formed by the series connection
PIN
and CIN. C
is primarily the pin capacitance. RIN is
PIN
typically 3 kΩ and is a lumped component made up of some
serial resistors and the on resistance of the switches. C
is
IN
typically 30 pF and is mainly the ADC sampling capacitor.
During the conversion phase, when the switches are opened, the
input impedance is limited to C
. RIN and CIN make a 1-pole,
PIN
low-pass filter that reduces undesirable aliasing effects and
limits the noise.
When the source impedance of the driving circuit is low, the
AD7942 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency, as shown
in Figure 26.
–70
–75
–80
–85
R
= 1kΩ
S
–90
R
= 500Ω
S
–95
THD (dB)
Figure 26. THD vs. Analog Input Frequency and Source Resistance
–100
–105
–110
–115
= 250Ω
R
S
R
= 100Ω
S
= 50Ω
R
S
RS = 15Ω
250 50 75 100
FREQUENCY (kHz)
04657-026
Driver Amplifier Choice
Although the AD7942 is easy to drive, the driver amplifier
needs to meet the following requirements:
• The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7942. Note that the
AD7942 produces much less noise than most of the other
14-bit ADCs and therefore can be driven by a noisier op
amp while preserving the same or better system performance. The noise coming from the driver is filtered by the
AD7942 analog input circuit, 1-pole, low-pass filter made
and CIN or by the external filter, if one is used.
by R
IN
• For ac applications, the driver needs to have a THD
performance suitable to that of the AD7942. Figure 14
gives the THD vs. frequency that the driver should exceed.
• For multichannel multiplexed applications, the driver
amplifier and the AD7942 analog input circuit must be able
to settle for a full-scale step of the capacitor array at a
14-bit level (0.006%). In the amplifier’s data sheet, settling
at 0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 14-bit level
and should be verified prior to driver selection.
Table 9. Recommended Driver Amplifiers
Amplifier Typical Application
AD8021 Very low noise and high frequency
AD8022 Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8605, AD8615 5 V single supply, low power
AD8519 Small, low power, and low frequency
AD8031 High frequency and low power
Voltage Reference Input
The AD7942 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source (e.g., a
reference buffer using the
AD8031 or the AD8605), a 10 µF
(X5R, 0805 size), a ceramic chip capacitor is appropriate for
optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance, using a low temperature drift
ADR43x reference.
If desired, smaller reference decoupling capacitor values down
to 2.2 µF can be used with a minimal impact on performance,
especially on DNL.
Rev. 0 | Page 15 of 24
Page 16
AD7942
Power Supply
The AD7942 is specified over a wide operating range from 2.3 V
to 5.5 V. It has, unlike other low voltage converters, a noise low
enough to design a low supply (2.5 V) 14-bit resolution system
with respectable performance. It uses two power supply pins: a
core supply, VDD, and a digital input/output interface supply,
VIO. VIO allows direct interface with any logic between 1.8 V
and VDD. To reduce the supplies needed, the VIO and VDD can
be tied together. The AD7942 is independent of power supply
sequencing between VIO and VDD. Additionally, it is insensitive to power supply variations over a wide frequency range, as
shown in Figure 27.
90
85
80
VDD = 5V
shown in Figure 29. The reference line can be driven by either
• The system power supply directly.
• A reference voltage with enough current output capability,
such as the ADR43x.
• A reference buffer, such as the AD8031, that can also filter
the system power supply (see Figure 29).
5V
10kΩ
5V
1µF
AD8031
(NOTE 1)
5V
10Ω
10µF 1µF
VIOREF VDD
AD7942
75
70
PSRR (dB)
65
60
55
10 1000100 10000
FREQUENCY (kHz)
Figure 27. PSRR v s. Frequency
04657-027
The AD7942 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 28. This makes the part
ideal for low sampling rates (even rates of a few Hz) and low
battery-powered applications.
0
1000
VDD = 5V
10
VDD = 2.5V
VIO
NOTE 1: OPTIONAL REFERENCE BUFFER AND FILTER
Figure 29. Example of Application Circuit
04657-029
DIGITAL INTERFACE
Although the AD7942 has a reduced number of pins, it offers
flexibility in its serial interface modes. When in
compatible with SPI, QSPI, digital hosts, and DSPs (e.g., Blackfin® ADSP-BF53x or ADSP-219x). This interface can be either
3-wire or 4-wire. A 3-wire interface using the CNV, SCK, and
SDO signals minimizes wiring connections useful, for instance,
in isolated applications. A 4-wire interface using the SDI, CNV,
SCK, and SDO signals allows CNV, which initiates conversions,
to be independent of the readback timing (SDI). This is useful
in low jitter sampling or simultaneous sampling applications.
The AD7942, when in chain mode, provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The
mode is selected if
CS
SDI is high and the chain mode is selected if SDI is low. The SDI
hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
mode, it is
CS
0.1
OPERATING CURRENT (µA)
0.001
10 100 1000 10000 100000 1000000
Figure 28. Operating Currents vs. Sampling Rate
SAMPLING RATE (SPS)
04657-028
Supplying the ADC from the Reference
For simplified applications, the AD7942, with its low operating
current, can be supplied directly using the reference circuit, as
Rev. 0 | Page 16 of 24
In either mode, the AD7942 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must time out the maximum conversion time prior
to readback.
The busy indicator feature is enabled as follows:
• In the
mode, if CNV or SDI is low when the ADC
CS
conversion ends (see Figure 33 and Figure 37).
• In the chain mode, if SCK is high during the CNV rising
edge (see Figure 41).
Page 17
AD7942
MODE 3-Wire, No Busy Indicator
CS
This mode is usually used when a single AD7942 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 30 and the corresponding timing is shown
in Figure 31.
With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the
mode, and forces SDO to high impedance.
CS
Once a conversion is initiated, it continues to completion
irrespective of the state of CNV. For instance, it could be useful
to bring CNV low to select other SPI devices, such as analog
multiplexers. However, CNV must be returned high before the
minimum conversion time and held high until the maximum
conversion time to avoid generating the busy signal indicator.
When the conversion is complete the AD7942 enters the
acquisition phase and powers down. When CNV goes low, the
MSB is output onto SDO. The remaining data bits are then
SDI = 1
t
CNVH
CNV
t
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to
capture the data, a digital host also using the SCK falling edge
allows a faster reading rate provided it has an acceptable hold
time. After the 14th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CONVERT
DIGITAL HOST
CLK
CYC
VIO
CNV
AD7942
SCK
Figure 30.
SDOSDI DATA IN
CS
Mode 3-Wire, No Busy Indicator
Connection Diagram (SDI High)
04657-030
SCK
SDO
t
CONV
CONVERSIONACQUISITION
Figure 31.
t
ACQ
ACQUISITION
t
SCK
t
SCKL
123 121314
t
HSDO
t
EN
D13 D12 D11 D1 D0
CS
Mode 3-Wire, No Busy Indicator, Serial Interface Timing (SDI High)
t
DSDO
t
SCKH
t
DIS
04657-031
Rev. 0 | Page 17 of 24
Page 18
AD7942
S
Mode 3-Wire with Busy Indicator
CS
This mode is usually used when a single AD7942 is connected
to an SPI-compatible digital host with an interrupt input. The
connection diagram is shown in Figure 32 and the corresponding timing is shown in Figure 33.
With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the
SDO is maintained in high impedance until the completion of
the conversion irrespective of the state of CNV. Prior to the
minimum conversion time, CNV can be used to select other SPI
devices, such as analog multiplexers. However, CNV must be
returned low before the minimum conversion time and held
low until the maximum conversion time to guarantee the
generation of the busy signal indicator. When the conversion is
complete, SDO goes from high impedance to low impedance.
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data reading controlled by the
digital host. The AD7942 then enters the acquisition phase and
mode, and forces SDO to high impedance.
CS
DI = 1
t
CNVH
CNV
t
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
optional 15th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CONVERT
CYC
VIO
SDOSDI
VIO
CNV
AD7942
SCK
Figure 32.
CS
Mode 3-Wire with Busy Indicator
Connection Diagram (SDI High)
47kΩ
DIGITAL HOST
DATA IN
IRQ
CLK
04657-032
ACQUISITION
SCK
SDO
t
CONV
CONVERSION
Figure 33.
t
ACQ
ACQUISITION
t
SCK
t
SCKL
123 131415
t
HSDO
t
DSDO
D13 D12 D1 D0
CS
Mode 3-Wire with Busy Indicator, Serial Interface Timing (SDI High)
t
SCKH
t
DIS
04657-033
Rev. 0 | Page 18 of 24
Page 19
AD7942
S
S
Mode 4-Wire, No Busy Indicator
CS
This mode is usually used when multiple AD7942s are connected to an SPI-compatible digital host. A connection diagram
using two AD7942s is shown in Figure 34 and the corresponding timing is given in Figure 35.
With SDI high, a rising edge on CNV initiates a conversion,
selects the
mode, and forces SDO to high impedance. In this
CS
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers.
However, SDI must be returned high before the minimum
conversion time and held high until the maximum conversion
time to avoid generating the busy signal indicator. When the
conversion is complete, the AD7942 enters the acquisition phase
and powers down. Each ADC result can be read by bringing low
CNV
its SDI input, which consequently outputs the MSB onto SDO.
The remaining data bits are then clocked by subsequent SCK
driving edges. The data is valid on both SCK edges. Although
the nondriving edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate, provided it has an acceptable hold time. After the
14th SCK falling edge or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7942
can be read.
If multiple AD7942s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
CS2
CS1
CONVERT
CNV
DIGITAL HOST
CNV
t
SSDICNV
DI (CS1)
DI (CS2)
SCK
SDO
t
HSDICNV
SCK
SDOSDI
DATA IN
CLK
04657-034
AD7942
SCK
Figure 34.
SDOSDI
CS
Mode 4-Wire, No Busy Indicator Connection Diagram
AD7942
t
CYC
t
CONV
CONVERSIONACQUISITION
t
SCK
t
SCKL
t
DSDO
12 13
t
SCKH
D1
123 262728
t
t
EN
HSDO
D13 D12 D11 D1 D0
t
ACQ
ACQUISITION
15 1614
D0 D13 D12
t
DIS
04657-035
Figure 35.
CS
Mode 4-Wire, No Busy Indicator, Serial Interface Timing
Rev. 0 | Page 19 of 24
Page 20
AD7942
A
Mode 4-Wire with Busy Indicator
CS
This mode is usually used when a single AD7942 is connected
to an SPI-compatible digital host with an interrupt input and it
is desired to keep CNV (which is used to sample the analog
input) independent of the signal used to select the data reading.
This requirement is particularly important in applications
where low jitter on CNV is desired. The connection diagram
is shown in Figure 36 and the corresponding timing is given
in Figure 37.
interrupt signal to initiate the data readback controlled by the
digital host. The AD7942 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK driving edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
optional 15th SCK falling edge or SDI going high, whichever is
earlier, the SDO returns to high impedance.
With SDI high, a rising edge on CNV initiates a conversion,
selects the
mode, and forces SDO to high impedance. In this
CS
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line this transition can be used as an
CNV
t
CONV
CQUISITION
t
SSDICNV
SDI
t
HSDICNV
SCK
SDO
CONVERSION
t
EN
Figure 37.
123 131415
t
HSDO
t
DSDO
CS
Mode 4-Wire with Busy Indicator, Serial Interface Timing
CNV
SDOSDI
SCK
Figure 36.
AD7942
CS
Mode 4-Wire with Busy Indicator Connection Diagram
t
CYC
t
ACQ
ACQUISITION
t
SCK
t
SCKL
t
SCKH
D13 D12 D1 D0
VIO
47kΩ
CS1
CONVERT
DATA IN
IRQ
CLK
t
DIS
DIGITAL HOST
04657-037
04657-036
Rev. 0 | Page 20 of 24
Page 21
AD7942
S
Chain Mode, No Busy Indicator
This mode can be used to daisy-chain multiple AD7942s on a
3-wire serial interface. This feature is useful for reducing component count and wiring connections, e.g., in isolated multiconverter applications or for systems with a limited interfacing
capacity. Data readback is analogous to clocking a shift register.
A connection diagram example using two AD7942s is shown in
Figure 38 and the corresponding timing is given in Figure 39.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode CNV is held
high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7942 enters the acquisition phase and
CNV
SDIA = 0
CNV
SCK
t
HSCKCNV
DOA = SDI
SDO
AD7942
t
CONV
CONVERSIONACQUISITION
t
SSCKCNV
t
EN
B
t
HSDO
t
DSDO
B
SDOSDI
A
SCK
Figure 38. Chain Mode, No Busy Indicator Connection Diagram
t
SCKL
1 2 3 26 27 28
t
SSDISCK
DA13 DA12 DA11
DB13 DB12 DB11 DA1DB1DB0DA13 DA12
Figure 39. Chain Mode, No Busy Indicator, Serial Interface Timing
AD7942
12 13
t
HSDISC
powers down. The remaining data bits stored in the internal
shift register are then clocked by subsequent SCK falling edges.
For each ADC, SDI feeds the input of the internal shift register
and is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first and 14 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host also using the SCK falling edge allows a faster
reading rate and consequently more AD7942s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate may be reduced due to the total
readback time. For instance, with a 5 ns digital host setup time
and 3 V interface, up to eight AD7942s running at a conversion
rate of 220 kSPS can be daisy-chained on a 3-wire port.
CONVERT
CNV
B
SCK
SDOSDI
t
CYC
ACQUISITION
t
SCK
DA1
t
t
SCKH
DA0
ACQ
15 1614
DIGITAL HOST
DATA IN
CLK
04657-038
DA0
04657-039
Rev. 0 | Page 21 of 24
Page 22
AD7942
A
Chain Mode with Busy Indicator
This mode can also be used to daisy-chain multiple AD7942s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, e.g., in isolated multiconverter applications or for
systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register. A connection diagram
example using three AD7942s is shown in Figure 40 and the
corresponding timing is given in Figure 41.
When SDI and CNV are low, SDO is driven low. With SCK high,
a rising edge on CNV initiates a conversion, selects the chain
mode, and enables the busy indicator feature. In this mode,
CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the near end ADC (ADC C in
CNV = SDI
CQUISITION
SCK
t
HSCKCNV
SDOA = SDI
SDO
= SDI
B
SDO
A
B
C
C
CNV
AD7942
A
SCK
t
CONV
CONVERSION
t
SSCKCNV
t
EN
t
DSDOSDI
SDOSDI
Figure 40. Chain Mode with Busy Indicator Connection Diagram
123 35 41 42
t
SSDISCK
DA13 DA12 DA11
t
HSDO
t
DSDO
DB13 DB12 DB11 DA1DB1DB0DA13 DA12
DC13 DC12 DC11 DA1DA0DC1DC0D
Figure 41. Chain Mode with Busy Indicator, Serial Interface Timing
CNV
AD7942
B
SCK
t
t
SCKH
SCK
413
t
HSDISC
SDOSDI
DA1
t
SCKL
15 3114
DA0
Figure 40) SDO is driven high. This transition on SDO can be
used as a busy indicator to trigger the data readback controlled
by the digital host. The AD7942 then enters the acquisition
phase and powers down. The data bits stored in the internal
shift register are then clocked out, MSB first, by subsequent SCK
falling edges. For each ADC, SDI feeds the input of the internal
shift register and is clocked by the SCK falling edge. Each ADC
in the chain outputs its data MSB first, and 14 × N + 1 clocks are
required to readback the N ADCs. Although the rising edge can
be used to capture the data, a digital host also using the SCK
falling edge allows a faster reading rate and consequently more
AD7942s in the chain, provided the digital host has an
acceptable hold time. For instance, with a 5 ns digital host setup time and a 3 V interface, up to eight AD7942s running at a
conversion rate of 220 kSPS can be daisy-chained to a single 3wire port.
CONVERT
t
CYC
ACQUISITION
17 27 2816
t
ACQ
CNV
AD7942
C
SCK
SDOSDI
29
DA0
D
1DB0DA13DB13 DB12
B
DIGITAL HOST
DATA IN
IRQ
CLK
12
A
43
04657-040
04657-041
Rev. 0 | Page 22 of 24
Page 23
AD7942
APPLICATION HINTS
LAYOUT
The printed circuit board that houses the AD7942 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7942 with all its analog signals on the left side and all its
digital signals on the right side eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7942 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Avoid
crossover of digital and analog signals.
04657-042
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In such a case, it
should be joined underneath the AD7942.
The AD7942 voltage reference input, REF, has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. That is done by placing the reference decoupling
ceramic capacitor close to and ideally right up against the
REF and GND pins. Connect these pins with wide, low
impedance traces.
Figure 42. Example of Layout of the AD7942 ( Top Layer)
Finally, the power supply, VDD, and VIO of the AD7942 should
be decoupled with ceramic capacitors, typically 100 nF, placed
close to the AD7942. Connect them using short and large traces
to provide low impedance paths and reduce the effect of glitches
on the power supply lines. An example of layout following these
rules is shown in Figure 42 and Figure 43.
EVALUATING THE AD7942’S PERFORMANCE
Other recommended layouts for the AD7942 are outlined in the
evaluation board for the AD7942 (
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the
EVAL-AD7942CB). The
EVAL-CONTROL BRD3.
Figure 43. Example of Layout of the AD7942 (Bottom Layer)
04657-043
Rev. 0 | Page 23 of 24
Page 24
AD7942
OUTLINE DIMENSIONS
1.50
BCS SQ
0.80
0.75
0.70
SEATING
PLANE
3.00 BSC
6
10
3.00 BSC
PIN 1
0.95
0.85
0.75
0.15
0.00
0.50 BSC
0.27
0.17
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
4.90 BSC
1
5
1.10 MAX
SEATING
PLANE
0.23
0.08
Figure 44.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
INDEX
AREA
3.00
BSC SQ
TOP VIEW
SIDE VIEW
0.30
0.23
0.18
0.80 MAX
0.55 TYP
0.50
BSC
0.50
0.40
0.30
0.05 MAX
0.02 NOM
0.20 REF
10
6
EXPOSED
PAD
(BOTTOM VIEW)
1.74
1.64
1.49
PIN 1
INDICATOR
Figure 45. 10-Lead Lead Frame Chip Scale Package [QFN
3 mm × 3 mm Body
(CP-10)
Dimensions shown in millimeters
8°
0°
0.80
0.60
0.40
1
2.48
2.38
2.23
5
PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES
1
(LFCSP)]
ORDERING GUIDE
Models Temperature Range Package Option Transport Media, Quantity Brand
AD7942BRM –40°C to +85°C MSOP (RM-10) Tube, 50 C1N
AD7942BRMRL7 –40°C to +85°C MSOP (RM-10) Reel, 1,000 C1N
EVAL-AD7942CB2 Evaluation Board
EVAL-CONTROL BRD2
EVAL-CONTROL BRD33 Controller Board
1
QFN package in development. Contact sales for samples and availability.
2
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes.
3
These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered
trademarks are the property of their respective owners.
D04657-0-3/05(0)
3
Controller Board
Rev. 0 | Page 24 of 24
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