Datasheet AD7934 Datasheet (Analog Devices)

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Page 1

4-Channel, 625 kSPS, 12-Bit

FEATURES

Fast throughput rate: 625 kSPS Specified for V Low power

3.6 mW max at 625 kSPS with 3 V supplies

7.5 mW max at 625 kSPS with 5 V supplies 4 analog input channels with a sequencer Software configurable analog inputs

4-channel single-ended inputs 2-channel fully differential inputs

2-channel pseudo-differential inputs Accurate on-chip 2.5 V reference ±0.2% max @ 25°C, 25 ppm/°C max 70 dB SINAD at 50 kHz input frequency No pipeline delays High speed parallel interface—word/byte modes Full shutdown mode: 2 µA max 28-lead TSSOP package

GENERAL DESCRIPTION

The AD7934-6 is a 12-bit, high speed, low power, successive approximation (SAR) ADC. The part operates from a single

2.7 V to 5.25 V power supply and features throughput rates to 625 kSPS. The part contains a low noise, wide bandwidth, differential track-and-hold amplifier that can handle input frequencies up to 50 MHz.

The AD7934-6 features four analog input channels with a channel sequencer to allow a consecutive sequence of channels to be converted. This part can accept either single-ended, fully differential, or pseudo-differential analog inputs.

The conversion process and data acquisition are controlled using standard control inputs, which allow for easy interfacing to microprocessors and DSPs. The input signal is sampled on the falling edge of

at this point.

The AD7934-6 has an accurate on-chip 2.5 V reference that can be used as the reference source for the analog-to-digital conversion. Alternatively, this pin can be overdriven to provide an external reference.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

of 2.7 V to 5.25 V

CONVST

, and the conversion is also initiated

Parallel ADC with a Sequencer

AD7934-6

FUNCTIONAL BLOCK DIAGRAM

AGND

12-BIT

SAR ADC

AND

CONTROL

AD7934-6

CONVST

REFIN/

REFOUT

VIN0

VIN3

SEQUENCER

PARALLEL INTERFACE/CONTROL REGISTER

DB0 DB11

I/P

MUX

2.5V

VREF

T/H

CS DGNDRD WR W/B

Figure 1.

The AD7934-6 uses advanced design techniques to achieve very low power dissipation at high throughput rates. The part also features flexible power management options. An on-chip control register allows the user to set up different operating conditions, including analog input range and configuration, output coding, power management, and channel sequencing.

PRODUCT HIGHLIGHTS

1. High throughput with low power consumption.

2. Four analog inputs with a channel sequencer.

3. Accurate on-chip 2.5 V reference.

4. Software configurable analog inputs. Single-ended,

pseudo-differential, or fully differential analog inputs that are software selectable.

5. Single-supply operation with VDRIVE function. The

VDRIVE function allows the parallel interface to connect directly to 3 V or 5 V processor systems independent of VDD.

6. No pipeline delay.

7. Accurate control of the sampling instant via a

input and once off conversion control.

www.analog.com

CLKIN CONVST BUSY

DRIVE

04752-001

Page 2

AD7934-6

Specifications..................................................................................... 3

Analog Input Structure.............................................................. 16

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Te r m in o l o g y ...................................................................................... 9

Typical Performance Characteristics........................................... 11

Control Register.......................................................................... 13

Sequencer Operation .................................................................14

Circuit Information........................................................................ 15

Converter Operation.................................................................. 15

ADC Transfer Function............................................................. 15

Typical C o n nect i o n D iagram ................................................... 16

REVISION HISTORY

1/05—Revision 0: Initial Version

Analog Inputs.............................................................................. 17

Analog Input Selection.............................................................. 19

Reference Section ....................................................................... 20

Parallel Interface ......................................................................... 21

Power Modes of Operation ....................................................... 24

Power vs. Throughput Rate ....................................................... 25

Microprocessor Interfacing....................................................... 25

Application Hints ........................................................................... 27

Grounding and Layout .............................................................. 27

Evaluating the AD7934-6 Performance................................... 27

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 28

Page 3

AD7934-6

SPECIFICATIONS

VDD = V

= T

Table 1.

Parameter B Version

DYNAMIC PERFORMANCE FIN = 50 kHz sine wave

Signal-to-Noise + Distortion (SINAD) 68 dB min Single-ended mode Signal-to-Noise Ratio (SNR)2 71 dB min Differential mode 69 dB min Single-ended mode Total Harmonic Distortion (THD)2 −73 dB max −85 dB typ, differential mode

−70 dB max −80 dB typ, single-ended mode Peak Harmonic or Spurious Noise (SFDR)2 −73 dB max −82 dB typ Intermodulation Distortion (IMD)2 fa = 30 kHz, fb = 50 kHz

Channel-to-Channel Isolation −85 dB typ FIN = 50 kHz, F Aperture Delay2 5 ns typ Aperture Jitter2 72 ps typ

Full Power Bandwidth2 50 MHz typ @ 3 dB 10 MHz typ @ 0.1 dB DC ACCURACY

Resolution 12 Bits

Integral Nonlinearity2 ±1 LSB max Differential mode

±1.5 LSB max Single-ended mode

Differential Nonlinearity2

Single-Ended and Pseudo-Differential Input Straight binary output coding

Fully Differential Input

ANALOG INPUT

Single-Ended Input Range 0 to V

Pseudo-Differential Input Range: V

Fully Differential Input Range: V

DC Leakage Current

Input Capacitance 45 pF typ When in track

10 pF typ When in hold

= 2.7 V to 5.25 V, internal/external V

DRIVE

to T

MIN

, unless otherwise noted.

MAX

= 2.5 V, unless otherwise noted, F

REF

Unit Test Conditions/Comments

= 10 MHz, F

CLKIN

SAMPLE

70 dB min Differential mode

= 625 kSPS;

Second-Order Terms −86 dB typ Third-Order Terms −90 dB typ

= 300 kHz

NOISE

Differential Mode ±0.95 LSB max Guaranteed no missed codes to 12 bits Single-Ended Mode −0.95/+1.5 LSB max Guaranteed no missed codes to 12 bits

Offset Error2 ±6 LSB max Offset Error Match2 ±1 LSB max Gain Error2 ±3 LSB max Gain Error Match2 ±1 LSB max Twos complement output coding

Positive Gain Error2 ±3 LSB max Positive Gain Error Match2 ±1 LSB max Zero-Code Error2 ±6 LSB max Zero-Code Error Match2 ±1 LSB max Negative Gain Error2 ±3 LSB max Negative Gain Error Match2 ±1 LSB max

or 0 to 2 × V

REF

0 to V

IN+

IN−

or 2 × V

REF

−0.3 to +0.7 V typ VDD = 3 V

V RANGE bit = 0, or RANGE bit = 1, respectively

REF

V RANGE bit = 0, or RANGE bit = 1, respectively

−0.3 to +1.8 V typ VDD = 5 V and V

IN+

and V

IN+

IN−

VCM ± V VCM ± V

/2 V VCM = common-mode voltage3 = V

REF

V VCM = V

±1 µA max

REF

, V

IN+

or V

must remain within GND/V

IN−

REF

Rev. 0 | Page 3 of 28

Page 4

AD7934-6

Parameter B Version

Unit Test Conditions/Comments

REFERENCE INPUT/OUTPUT

Input Voltage5 2.5 V ±1% specified performance

REF

DC Leakage Current ±1 µA max V

Output Voltage 2.5 V ±0.2% max @ 25°C

REFOUT

Temperature Coefficient 25 ppm/°C max 5 ppm/°C typ

REFOUT

Noise 10 µV typ 0.1 Hz to 10 Hz bandwidth

REF

130 µV typ 0.1 Hz to 1 MHz bandwidth V

Output Impedance 10 Ω typ

REF

Input Capacitance 15 pF typ When in track-and-hold

REF

25 pF typ When in track-and-hold

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V

INH

INL

2.4 V min

0.8 V max Input Current, IIN ±5 µA max Typically 10 nA, VIN = 0 V or V Input Capacitance, C

10 pF max

LOGIC OUTPUTS

Output High Voltage, V

Output Low Voltage, VOL 0.4 V max I

2.4 V min I

SOURCE

= 200 µA

SINK

= 200 µA

Floating-State Leakage Current ±3 µA max Floating-State Output Capacitance4 10 pF max Output Coding CODING bit = 0

Straight (Natural) Binary

Twos Complement

CODING bit = 1

CONVERSION RATE

Conversion Time t2 + 13 t

CLK

Track-and-Hold Acquisition Time 125 ns max Full-scale step input Throughput Rate 625 kSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 V min/max V

2.7/5.25 V min/max

DRIVE

Digital I/PS = 0 V or V

DRIVE

Normal Mode (Static) 0.8 mA typ VDD = 2.7 V to 5.25 V, SCLK on or off Normal Mode (Operational) 1.5 mA max VDD = 4.75 V to 5.25 V

1.2 mA max VDD = 2.7 V to 3.6 V Autostandby Mode 0.3 mA typ F

= 100 kSPS, VDD = 5 V

SAMPLE

160 µA typ (Static) Full/Autoshutdown Mode (Static) 2 µA max SCLK on or off

Power Dissipation

Normal Mode (Operational) 7.5 mW max VDD = 5 V

3.6 mW max VDD = 3 V Autostandby Mode (Static) 800 µW typ VDD = 5 V 480 µW typ VDD = 3 V Full/Autoshutdown Mode 10/6 µW max VDD = 5 V/3 V

Temperature ranges is as follows: B Versions: −40°C to +85°C.

See the section. Terminology

For full common-mode range see Fig and . ure 25 Figure 26

Sample tested during initial release to ensure compliance.

This device is operational with an external reference in the range 0.1 V to VDD. See the Reference Section for more information.

Measured with a midscale dc analog input.

DRIVE

Rev. 0 | Page 4 of 28

Page 5

AD7934-6

TIMING SPECIFICATIONS

VDD = V

= T

Table 2.

Limit at T Parameter AD7934-6 Unit Description

CLKIN

10 MHz max t

QUIET

50 ns max t

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

All timing specifications given above are with a 25 pF load capacitance. See , , , and .

The time required for the output to cross 0.4 V or 2.4 V.

t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or

discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.

= 2.7 V to 5.25 V, internal/external V

DRIVE

to T

MIN

, unless otherwise noted.

MAX

, T

MIN

MAX

50 kHz min

30 ns min

10 ns min 15 ns min 50 ns min CLKIN Falling Edge to BUSY Rising Edge.

0 ns min 0 ns min 10 ns min 10 ns min 10 ns min 10 ns min New Data Valid before Falling Edge of BUSY. 0 ns min 0 ns min 30 ns min 30 ns max 3 ns min

0 ns min 0 ns min 10 ns min Minimum Time between Reads/Writes. 0 ns min 10 ns min 40 ns max CLKIN Falling Edge to BUSY Falling Edge.

15.7 ns min CLKIN Low Pulse Width

7.8 ns min CLKIN High Pulse Width.

= 2.5 V, unless otherwise noted, F

REF

Minimum time between end of read and start of next conversion, i.e., time from when the data bus goes into three-state until the next falling edge of

CONVST Pulse Width. CONVST Falling Edge to CLKIN Falling Edge Setup Time.

CS to WR Setup Time. CS to WR Hold Time. WR Pulse Width. Data Setup Time before Data Hold after

CS to RD Setup Time. CS to RD Hold Time. RD Pulse Width. Data Access Time after Bus Relinquish Time after Bus Relinquish Time after HBEN to HBEN to

HBEN to HBEN to

RD Setup Time. RD Hold Time.

WR Setup Time. WR Hold Time.

= 10 MHz, F

CLKIN

WR.

RD.

RD. RD.

Figure 34 Figure 35 Figure 36 Figure 37

= 625 kSPS;

SAMPLE

CONVST.

Rev. 0 | Page 5 of 28

Page 6

AD7934-6

ABSOLUTE MAXIMUM RATINGS

= 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to AGND/DGND −0.3 V to +7 V V

to AGND/DGND −0.3 V to VDD +0.3 V

DRIVE

Analog Input Voltage to AGND −0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to +7 V V

to V

DRIVE

Digital Output Voltage to AGND −0.3 V to V V

to AGND −0.3 V to VDD + 0.3 V

REFIN

−0.3 V to VDD + 0.3 V + 0.3 V

DRIVE

AGND to DGND −0.3 V to +0.3 V Input Current to Any Pin Except Supplies

±10 mA

Operating Temperature Range

Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θJA Thermal Impedance 97.9°C/W (TSSOP) θJC Thermal Impedance 14°C/W (TSSOP) Lead Temperature, Soldering

Reflow Temperature (10 sec to 30 sec) 255°C ESD 1.5 kV

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 6 of 28

Page 7

AD7934-6

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 4. Pin Function Description

Pin No. Mnemonic Description

1 VDD

Power Supply Input. The V to AGND with a 0.1 µF capacitor and a 10 µF tantalum capacitor.

B Word/Byte Input. When this input is logic high, word transfer mode is enabled and data is transferred to and

from the AD7934-6 in 12-bit words on Pins DB0/DB2 to DB11. When this pin is logic low, byte transfer mode is enabled. Data and the channel ID are transferred on Pins DB0 to DB7, and Pin DB8/HBEN assumes its HBEN functionality. Unused data lines when operating in byte transfer mode should be tied off to DGND.

3 to 10 DB0 to DB7

Data Bits 0 to 7. Three-state parallel digital I/O pins that provide the conversion result and also allow the control register to be programmed. These pins are controlled by levels for these pins are determined by the V

11 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of the AD7934-6 operates. This pin should be decoupled to DGND. The voltage at this pin may be different to

but should never exceed VDD by more than 0.3 V.

12 DGND

that at V Digital Ground. This is the ground reference point for all digital circuitry on the AD7934-6. This pin should

connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

13 DB8/HBEN

Data Bit 8/High Byte Enable. When W/ controlled by the low byte of data written to or read from the AD7934-6 is on DB0 to DB7. When HBEN is high, the top four

bits of the data being written to or read from the AD7934-6 are on DB0 to DB3. When reading from the device, DB4 of the high byte is always 0, and DB5 and DB6 contain the ID of the channel to which the conversion result corresponds (see Channel Address Bits in Table 8). When writing to the device, DB4 to DB7 of the high byte must be all 0s.

14 to 16 DB9 to DB11

Data Bits 9 to 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the control register to be programmed in word mode. These pins are controlled by high/low voltage levels for these pins are determined by the V

17 BUSY

Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the falling edge of and the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track mode just prior to the falling edge of BUSY, on the 13

18 CLKIN

Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7934-6 takes 13 clock cycles + t conversion time and achievable throughput rate.

CONVST Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes

from track to hold mode on the falling edge of Following power-down, when operating in the autoshutdown or autostandby mode, a rising edge on

CONVST is used to power up the device. The CLKIN signal may be a continuous or burst clock.

W/B

DB0

DB1 DB2 DB3 DB4 DB5 DB6 DB7

DRIVE

DGND

DB8/HBEN DB11

DB9

5 6

(Not to Scale)

7 8

9 10 11 12 13 14

AD7934-6

TOP VIEW

VIN2

REFIN/VREFOU

AGND

CONVST

CLKIN

BUSY

16 15

DB10

1 0

04752-006

Figure 2. Pin Configuration

range for the AD7934-6 is from 2.7 V to 5.25 V. The supply should be decoupled

CS, RD, and WR. The logic high/low voltage

input.

DRIVE

B is high, this pin acts as Data Bit 8, a three-state I/O pin that is

CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low,

CS, RD, and WR. The logic

input.

DRIVE

CONVST and stays high for the duration of the conversion. Once the conversion is complete

rising edge of SCLK, see Figure 34.

. The frequency of the master clock input therefore determines the

CONVST, and the conversion process is initiated at this point.

Rev. 0 | Page 7 of 28

Page 8

AD7934-6

Pin No. Mnemonic Description

20 21

23 AGND

24 V

25 to 28 VIN0 to VIN3

WR Write Input. Active low logic input used in conjunction with CS to write data to the control register. RD Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion

result is placed on the data bus following the falling edge of

CS Chip Select. Active low logic input used in conjunction with RD and WR to read conversion data or write data

to the control register. Analog Ground. This is the ground reference point for all analog circuitry on the AD7934-6. All analog

input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

REFIN/VREFOUT

Reference Input/Output. This pin is connected to the internal reference and is the reference source for the ADC. The nominal internal reference voltage is 2.5 V, and this appears at this pin. This pin can be overdriven by an external reference. The input voltage range for the external reference is 0.1 V to V be taken to ensure that the analog input range does not exceed V

Analog Input 0 to Analog Input 3. Four analog input channels that are multiplexed into the on-chip track-andhold. The analog inputs can be programmed to be four single ended inputs, two fully differential pairs or two pseudo-differential pairs by setting the MODE bits in the control register appropriately (see Table 8). The analog input channel to be converted can either be selected by writing to the address bits (ADD1 and ADD0) in the control register prior to the conversion, or the on-chip sequencer can be used. The input range for all input channels can either be 0 V to V depending on the states of the RANGE and CODING bits in the control register. Any unused input channels should be connected to AGND to avoid noise pickup.

or 0 V to 2 × V

REF

RD read while CS is low.

; however, care must

+ 0.3 V. See the Reference Section.

, and the coding can be binary or twos complement,

REF

Rev. 0 | Page 8 of 28

Page 9

AD7934-6

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (00 . . .000) to (00 . . . 001) f rom the ideal, i.e., AGND + 1 LSB.

Offset Error Match

This is the difference in offset error between any two channels.

Gain Error

This is the deviation of the last code transition (111 . . .110) to (111 . . . 111) from the ideal (i.e., V

– 1 LSB) after the offset

REF

error has been adjusted out.

Gain Error Match

This is the difference in gain error between any two channels.

Zero-Code Error

This applies when using the twos complement output coding option, in particular to the 2 × V

biased about the V

REF

REFIN

input range with −V

REF

point. It is the deviation of the midscale transition (all 0s to all 1s) from the ideal V voltage, i.e., V

REF

Zero-Code Error Match

This is the difference in zero-code error between any two channels.

Positive Gain Error

This applies when using the twos complement output coding option, in particular to the 2 × V

biased about the V

REF

point. It is the deviation of the last

REFIN

input range with −V

REF

code transition (011. . .110) to (011 .. . 111) from the ideal (i.e.,

– 1 LSB) after the zero-code error has been adjusted out.

REF

Positive Gain Error Match

This is the difference in positive gain error between any two channels.

Negative Gain Error

This applies when using the twos complement output coding option, in particular to the 2 × V

biased about the V

REF

point. It is the deviation of the first

REF

input range with −V

REF

code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e., −V

+ 1 LSB) after the zero-code error has been

REFIN

adjusted out.

Negative Gain Error Match

This is the difference in negative gain error between any two channels.

Channel-to-Channel Isolation

It is a measure of the level of crosstalk between channels. It is measured by applying a full-scale sine wave signal to the three nonselected input channels and applying a 50 kHz signal to the selected channel. The channel-to-channel isolation is defined as the ratio of the power of the 50 kHz signal on the selected channel to the power of the noise signal on the unselected channels that appears in the FFT of this channel. The noise frequency on the unselected channels varies from 40 kHz to 740 kHz. The noise amplitude is at 2 × V amplitude is at 1 × V

REF

, while the signal

REF

Power Supply Rejection Ratio (PSRR)

It is defined as the ratio of the power in the ADC output at fullscale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC V

supply of frequency fS. The frequenc y

of the input varies from 1 kHz to 1 MHz.

PSRR (dB) = 10log(Pf/Pf

Pf is the power at frequency f in the ADC output; Pf

power at frequency f

in the ADC output.

)

is the

Common-Mode Rejection Ratio (CMRR)

CMRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the common-mode voltage of V frequency f

CMRR (dB) = 10log (Pf/Pf

)

IN+

and V

Pf is the power at frequency f in the ADC output; Pf power at frequency f

in the ADC output.

IN−

is the

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode and the end of conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1/2 LSB, after the end of conversion.

Rev. 0 | Page 9 of 28

Page 10

AD7934-6

Signal-to-(Noise + Distortion) Ratio (SINAD)

This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Thus, for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7934-6, it is defined as

()

THD

where V V

is the rms amplitude of the fundamental, and V2, V3,

, V5, and V6 are the rms amplitudes of the second through the

20logdB

−=

sixth harmonics.

/2), excluding dc. The

22222

VVVVV

++++

65432

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f

/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The AD7934-6 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs.

Rev. 0 | Page 10 of 28

Page 11

AD7934-6

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise noted.

???

(dB)

–10 –20 –30 –40 –50 –60 –70 –80 –90

–100 –110

100

200

300

FREQUENCY (kHz)

Figure 6. AD7934-6 FFT @ V

4096 POINT FFT

= 5V

= 625kSPS

SAMPLE

= 49.62kHz

SINAD = 70.94dB THD = –90.09dB DIFFERENTIAL MODE

400

500

= 5 V

600

04752-009

700

–60

100mV p-p SINE WAVE ON VDD AND/OR V NO DECOUPLING DIFFERENTIAL/SINGLE-ENDED MODE

–70

–80

–90

PSSR (dB)

–100

–110

–120

10 210 610410 810 1010

INT REF

EXT REF

SUPPLY RIPPLE FREQUENCY (kHz)

DRIVE

Figure 3. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

04752-007

–70

INTERNAL/EXTERNAL REFERENCE

= 5V

–75

–80

–85

NOISE ISOLATION (dB)

–90

–195

0 100 400200 300 600500 800700

NOISE FREQUENCY (kHz)

Figure 4. Channel-to-Channel Isolation

SINAD (dB)

= 625kSPS

SAMPLE

RANGE = 0 TO V DIFFERENTIAL MODE

0 100 400200 300 600500 1000700 800 900

REF

FREQUENCY (kHz)

VDD = 5V

VDD = 3V

Figure 5. AD7934-6 SINAD vs. Analog Input

Frequency for Various Supply Voltages

04752-021

04752-008

1.0

0.8

0.6

0.4

0.2 0

–0.2

DNL ERROR (LSB)

–0.4

–0.6 –0.8 –1.0

0 500 20001000 1500 30002500 40003500

CODE

Figure 7. AD7934-6 Typical DNL @ V

1.0

0.8

0.6

0.4

0.2 0

–0.2

INL ERROR (LSB)

–0.4

–0.6 –0.8 –1.0

0 500 20001000 1500 30002500 40003500

CODE

Figure 8. AD7934-6 Typical INL @ V

VDD = 5V DIFFERENTIAL MODE

= 5 V

VDD = 5V DIFFERENTIAL MODE

= 5 V

04752-010

04752-011

Rev. 0 | Page 11 of 28

Page 12

AD7934-6

DNL (LSB)

–1

0.25 0.50 1.250.75 1.00 2.001.751.50 2.752.502.25

SINGLE-ENDED MODE

REF

Figure 9. AD7934-6 DNL vs. V

POSITIVE DNL

NEGATIVE DNL

(V)

for VDD = 3 V

REF

10000

DIFFERENTIAL MODE

9000

8000

7000

6000

5000

???

4000

3000

2000 1000

04752-012

2046 2047 2048 2049 2050

9997

CODES

CODE

3 CODES

INTERNAL

REF

04752-015

Figure 12. AD7934-6 Histogram of Codes for

10k Samples @ V

= 5 V with the Internal Reference

DIFFERENTIAL MODE

EFFECTIVE NUMBER OF BITS

0 0.5 1.51.0 2.52.0 4.03.53.0

SINGLE-ENDED MODE

VDD = 5V

VDD = 3V SINGLE-ENDED MODE

VDD = 3V DIFFERENTIAL MODE

(V)

REF

Figure 10. AD7934-6 ENOB vs. V

–0.5

–1.0

–1.5

–2.0

–2.5 –3.0

OFFSET (LSB)

–3.5

–4.0 –4.5 –5.0

0 0.5 1.51.0 2.52.0 3.53.0

VDD = 5V

VDD = 3V

(V)

REF

Figure 11. AD7934-6 Offset vs. V

REF

SINGLE-ENDED MODE

REF

04752-013

04752-014

–60

DIFFERENTIAL MODE

–70

–80

–90

CMRR (dB)

–100

–110

–120

0 200 400 800600 12001000

RIPPLE FREQUENCY (kHz)

Figure 13. CMRR vs. Input Frequency V

= 5 V and 3 V

04752-017

Rev. 0 | Page 12 of 28

Page 13

AD7934-6

CONTROL REGISTER

The control register on the AD7934-6 is a 12-bit, write-only register. Data is written to this register using the CS and WR pins. The control

register is shown below, and the functions of the bits are described in Table 6. At power-up, the default bit settings in the control register are all 0s.

Table 5. Control Register Bits

MSB LSB DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

PM1 PM0 CODING REF ZERO ADD1 ADD0 MODE1 MODE0 SEQ1 SEQ0 RANGE

Table 6. Control Register Bit Function Description

Bit No. Mnemonic Description

11, 10 PM1, PM0

9 CODING

8 REF

7 ZERO This bit is not used so it should always be set to Logic 0.

6, 5

4, 3

ADD1, ADD0

MODE1, MODE0

2 SEQ1

1 SEQ0

0 RANGE

Table 7. Power Mode Selection Using the Power Management Bits in the Control Register

PM1 PM0 Mode Description

0 0 Normal Mode When operating in normal mode, all circuitry is fully powered up at all times. 0 1 Autoshutdown

1 0 Autostandby

1 1 Full Shutdown

Power Management Bits. These two bits are used to select the power mode of operation. The user can choose between either normal mode or various power-down modes of operation as shown in Table 7.

This bit selects the output coding of the conversion result. If this bit is set to 0, the output coding is straight (natural) binary. If this bit is set to 1, the output coding is twos complement.

This bit selects whether the internal or external reference is used to perform the conversion. If this bit is Logic 0, an external reference should be applied to the V

pin, and if it is Logic 1, the internal reference is selected (see the

REF

Reference Section).

These two address bits are used to either select which analog input channel is to be converted in the next conversion, if the sequencer is not being used, or to select the final channel in a consecutive sequence when the sequencer is being used as described in Table 9. The selected input channel is decoded as shown in Table 8.

The two mode pins select the type of analog input on the four V

pins. The AD7934-6 has either four single-ended

inputs, two fully differential inputs, or two pseudo-differential inputs (see Table 8). The SEQ1 bit in the control register is used in conjunction with the SEQ0 bit to control the sequencer function

(see Table 9). The SEQ0 bit in the control register is used in conjunction with the SEQ1 bit to control the sequencer function

(see Table 9). This bit selects the analog input range of the AD7934-6. If it is set to 0, the analog input range extends from 0 V to

. If it is set to 1, the analog input range extends from 0 V to 2 × V

REF

. When this range is selected, AVDD must be

REF

4.75 V to 5.25 V if a 2.5 V reference is used; otherwise, care must be taken to ensure that the analog input remains within the supply rails. See the Analog Inputs section for more information.

When operating in autoshutdown mode, the AD7934-6 enters full shutdown mode at the end of each conversion. In this mode, all circuitry is powered down.

When the AD7934-6 enters this mode, the reference remains fully powered, the reference buffer is partially powered down, and all other circuitry is fully powered down. This mode is similar to autoshutdown mode, but it allows the part to power-up in 7 µs (or 600 ns if an external reference is used). See the Power Modes of Operation section for more information.

When the AD7934-6 enters this mode, all circuitry is powered down. The information in the control register is retained.

Rev. 0 | Page 13 of 28

Page 14

AD7934-6

Table 8. Analog Input Type Selection

Channel Address MODE0 = 0, MODE1 = 0 MODE0 = 0, MODE1 = 1 MODE0 = 1, MODE1 = 0 MODE0 = 1, MODE1 = 1 Four Single-Ended I/P

Channels

ADD1 ADD0 V

IN+

IN−

0 0 VIN0 AGND VIN0 VIN1 VIN0 VIN1 0 1 VIN1 AGND VIN1 VIN0 VIN1 VIN0 1 0 VIN2 AGND VIN2 VIN3 VIN2 VIN3 1 1 VIN3 AGND VIN3 VIN2 VIN3 VIN2

SEQUENCER OPERATION

The configuration of the SEQ0 and SEQ1 bits in the control register allow the user to use the sequencer function. Table 9 outlines the two sequencer modes of operation.

Table 9. Sequence Selection Modes

SEQ0 SEQ1 Sequence Type

0 0

0 1 Not Used. 1 0 Not Used. 1 1

This configuration is selected when the sequence function is not used. The analog input channel selected on each individual conversion is determined by the contents of the channel address bits, ADD1 and ADD0, in each prior write operation. This mode of operation reflects the normal operation of a multichannel ADC, without the sequencer function being used, where each write to the AD7934-6 selects the next channel for conversion.

This configuration is used in conjunction with the channel address bits, ADD1 and ADD0, to program continuous conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by the channel address bits in the control register. When in differential or pseudo-differential mode, inverse channels (e.g., VIN1, VIN0) are not converted in this mode.

Two Fully Differential I/P Channels

IN+

IN−

Two Pseudo-Differential I/P Channels

IN+

IN−

Not Used

Rev. 0 | Page 14 of 28

Page 15

AD7934-6

CIRCUIT INFORMATION

The AD7934-6 is a fast, 4-channel, 12-bit, single-supply, successive approximation analog-to-digital converter. The part operates from a 2.7 V to 5.25 V power supply and features throughput rates up to 625 kSPS.

The AD7934-6 provides the user with an on-chip track-andhold, an internal accurate reference, an analog-to-digital converter, and a parallel interface housed in a 28-lead TSSOP package.

The AD7934-6 has four analog input channels that can be configured to be four single-ended inputs, two fully differential pairs, or two pseudo-differential pairs. There is an on-chip channel sequencer that allows the user to select a consecutive sequence of channels through which the ADC can cycle with each falling edge of

CONVST

The analog input range for the AD7934-6 is 0 to V V

, depending on the status of the RANGE bit in the control

REF

or 0 to 2 ×

REF

register. The output coding of the ADC can be either binary or twos complement, depending on the status of the CODING bit in the control register.

The AD7934-6 provides flexible power management options to allow users to achieve the best power performance for a given throughput rate. These options are selected by programming the power management bits, PM1 and PM0, in the control register.

CONVERTER OPERATION

The AD7934-6 is a successive approximation ADC based on two capacitive DACs. Figure 14 and Figure 15 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC is comprised of control logic, a SAR, and two capacitive DACs. Both figures show the operation of the ADC in differential/pseudo-differential mode. Single-ended mode operation is similar but V In the acquisition phase, SW3 is closed, SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input.

IN+

IN–

SW1

SW2

REF

Figure 14. ADC Acquisition Phase

is internally tied to AGND.

IN−

CAPACITIVE

COMPARATOR

SW3

CAPACITIVE

DAC

CONTROL

LOGIC

DAC

04752-023

When the ADC starts a conversion (Figure 15), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC’s output code. The output impedances of the sources driving the V

and the V

IN+

pins must match;

IN−

otherwise, the two inputs have different settling times, resulting in errors.

CAPACITIVE

IN+

IN–

SW1

SW2

REF

COMPARATOR

SW3

DAC

CONTROL

LOGIC

CAPACITIVE

DAC

04752-024

Figure 15. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding for the AD7934-6 is either straight binary or twos complement, depending on the status of the CODING bit in the control register. The designed code transitions occur at successive LSB values (i.e., 1 LSB, 2 LSBs, and so on), and the LSB size is V AD7934-6 for both straight binary and twos complement output coding are shown in Figure 16 and Figure 17, respectively.

111...111

111...110

111...000

011...111

ADC CODE

000...010

000...001

000...000

/4096. The ideal transfer characteristics of the

REF

1 LSB = V

1 LSB +V

NOTE: V

IS EITHER V

REF

ANALOG INPUT

REF

OR 2 × V

/4096

REF

–1 LSB

Figure 16. AD7934-6 Ideal Transfer Characteristic

with Straight Binary Output Coding

04752-025

Rev. 0 | Page 15 of 28

Page 16

AD7934-6

1 LSB = 2 × V

011...111

011...110

000...001

000...000

111...111

ADC CODE

100...010

100...001

100...000 –V

REF

+ 1 LSB V

Figure 17. AD7934-6 Ideal Transfer Characteristic

with Twos Complement Output Coding and 2 x V

TYPICAL CONNECTION DIAGRAM

Figure 18 shows a typical connection diagram for the AD7934-

6. The AGND and DGND pins are connected together at the device for good noise suppression. The V decoupled to AGND with a 0.47 µF capacitor to avoid noise pickup, if the internal reference is used. Alternatively, V V

can be connected to a external reference source, and in

REFOUT

this case, the reference pin should be decoupled with a 0.1 µF capacitor. In both cases, the analog input range can either be 0 V to V

(RANGE bit = 0) or 0 V to 2 × V

REF

The analog input configuration is either four single-ended inputs, two differential pairs or two pseudo-differential pairs (see Table 8). The V The voltage applied to the V the digital interface, and here it is connected to the same 3 V supply of the microprocessor to allow a 3 V logic interface (see the Digital Inputs section).

0 TO V

REF

0 TO 2 × V

REF

2.5V

REF

pin connects to either a 3 V or 5 V supply.

0.1µF10µF

AD7934-6

VIN0

VIN3

AGND DGND

REFIN/VREFOUT

0.1µF EXTERNAL V

0.47µF INTERNAL V

Figure 18. Typical Connection Diagram

/4096

REF

REFIN/VREFOUT

REF

input controls the voltage of

DRIVE

3V/5V SUPPLY

W/B

CLKIN

CS RD

BUSY

CONVST

DB0

DB11/DB9

DRIVE

0.1µF

REF

– 1 LSB

REF

Range

REF

(RANGE bit = 1).

10µF

pin is

REFIN

µC/µP

SUPPLY

04752-026

04752-027

ANALOG INPUT STRUCTURE

Figure 19 shows the equivalent circuit of the analog input structure of the AD7934-6 in differential/pseudo-differential mode. In single-ended mode, V The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This causes these diodes to become forward-biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part.

The C1 capacitors, in Figure 19, are typically 4 pF and can primarily be attributed to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 Ω. The C2 capacitors, in Figure 19, are the ADC’s sampling capacitors and have a typical capacitance of 45 pF.

For ac applications, removing high frequency components from the analog input signal is recommended by using an RC low-pass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application.

–

Figure 19. Equivalent Analog Input Circuit,

Conversion Phase—Switches Open, Track Phase—Switches Closed

When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of THD that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 20 and Figure 21 show a graph of the THD vs. source impedance with a 50 kHz input tone for both V differential mode, respectively.

= 5 V and 3 V in single-ended mode and

is internally tied to AGND.

IN−

R1 C2

04752-028

Rev. 0 | Page 16 of 28

Page 17

AD7934-6

–40

FIN = 50kHz

–45 –50

–55

–60

–65

THD (dB)

–70

–75 –80

–85 –90

10 100 1k 10k

SOURCE

VDD = 3V

VDD = 5V

(Ω)

Figure 20. THD vs. Source Impedance in Single-Ended Mode

–60

FIN = 50kHz

–65

–70

–75

–80

THD (dB)

–85

VDD = 3V

–90

–95

–100

10 100 1k 10k

VDD = 5V

SOURCE

(Ω)

Figure 21. THD vs. Source Impedance in Differential Mode

04752-018

04752-019

ANALOG INPUTS

The AD7934-6 has software selectable analog input configurations. Users can choose either four single-ended inputs, two fully differential pairs, or two pseudo-differential pairs. The analog input configuration is chosen by setting the MODE0/MODE1 bits in the internal control register (see Table 8).

Single-Ended Mode

The AD7934-6 can have four single-ended analog input channels by setting the MODE0 and MODE1 bits in the control register to 0. In applications where the signal source has a high impedance, it is recommended to buffer the analog input before applying it to the ADC. The analog input range is either 0 to V

or 0 to 2 × V

REF

If the analog input signal to be sampled is bipolar, the internal reference of the ADC can be used to externally bias up this signal to make it the correct format for the ADC.

Figure 23 shows a typical connection diagram when operating the ADC in single-ended mode.

+1.25V

–1.25V

REF

+2.5V

IN0

AD7934-6*

IN3

REFOUT

0.47µF

Figure 22 shows a graph of the THD vs. the analog input frequency for various supplies, while sampling at 625 kHz with an SCLK of 10 MHz. In this case, the source impedance is 10 Ω.

–50

VDD = 3V

–60

–70

–80

–90

THD (dB)

–100

–110

–120

0 100 400200 300 600500 700

SINGLE-ENDED MODE

VDD = 5V/3V DIFFERENTIAL MODE

= 625kSPS

SAMPLE

RANGE = 0 TO V

VDD = 5V SINGLE-ENDED MODE

REF

INPUT FREQUENCY (kHz)

04752-020

Figure 22. THD vs. Analog Input Frequency for Various Supply Voltages

Rev. 0 | Page 17 of 28

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 23. Single-Ended Mode Connection Diagram

Differential Mode

The AD7934-6 can have two differential analog input pairs by setting the MODE0 and MODE1 bits in the control register to 0 and 1, respectively.

Differential signals have some benefits over single-ended signals, including noise immunity based on the device’s common-mode rejection and improvements in distortion performance. Figure 24 defines the fully differential analog input of the AD7934-6.

COMMON-MODE

VOLTAGE

Figure 24. Differential Input Definition

REF

p-p

REF

p-p

*ADDITIONAL PINS OMITTED FOR CLARITY

IN+

AD7934-6*

IN–

04752-032

04752-031

Page 18

AD7934-6

The amplitude of the differential signal is the difference between the signals applied to the V differential pair (i.e., V

IN+

− V

IN−

simultaneously driven by two signals, each of amplitude V (or 2 × V

depending on the range chosen) that are 180° out

REF

). V

IN+

and V

pins in each

IN−

should be

IN−

REF

of phase. The amplitude of the differential signal is therefore

−V

REF

to +V

peak-to-peak (i.e., 2 × V

REF

). This is regardless of

REF

the common mode (CM). The common mode is the average of the two signals, i.e. (V

IN+

+ V

)/2, and is therefore the voltage

IN−

on which the two inputs are centered. This results in the span of each input being CM ± V externally and its range varies with the reference value V As the value of V

increases, the common-mode range

REF

/2. This voltage has to be set up

REF

decreases. When driving the inputs with an amplifier, the actual common-mode range is determined by the amplifier’s output voltage swing.

Figure 25 and Figure 26 show how the common-mode range typically varies with V V

range or 2 × V

REF

for a 5 V power supply using the 0 to

REF

range, respectively. The common mode

REF

must be in this range to guarantee the functionality of the AD7934-6.

When a conversion takes place, the common mode is rejected resulting in a virtually noise free signal of amplitude −V +V

corresponding to the digital codes of 0 to 4096. If the 2 ×

REF

range is used then the input signal amplitude would extend

REF

from −2 V

3.5

3.0

2.5

2.0

1.5

1.0

COMMON-MODE RANGE (V)

0.5

to +2 V

REF

TA = 25°C

0 0.5 1.51.0 2.0 2.5 3.0

Figure 25. Input Common-Mode Range vs.

after conversion.

REF

(0 to V

REF

Range, VDD = 5 V)

REF

(V)

REF

04752-033

4.5 TA = 25°C

4.0

3.5

3.0

2.5

2.0

1.5

COMMON-MODE RANGE (V)

1.0

0.5

0.1 0.6 1.61.1 2.1 2.6 V

(V)

REF

04752-034

Figure 26. Input Common-Mode Range vs.

(2 × V

REF

Range, VDD = 5 V)

REF

Driving Differential Inputs

Differential operation requires that V

IN+

and V

IN−

be simultaneously driven with two equal signals that are 180° out of phase. The common mode must be set up externally and have a range that is determined by V

, the power supply,

REF

and the particular amplifier used to drive the analog inputs. Differential modes of operation with either an ac or dc input provide the best THD performance over a wide frequency range. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform single-ended-to-differential conversion.

Using an Op Amp Pair

An op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the AD7934-6. The circuit configurations shown in Figure 27 and Figure 28 show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively.

The voltage applied to Point A sets up the common-mode voltage. In both diagrams, it is connected in some way to the reference, but any value in the common-mode range can be input here to set up the common mode. A suitable dual op amp, such as the AD8022, could be used in this configuration to provide differential drive to the AD7934-6.

Take care when choosing the op amp; the selection depends on the required power supply and system performance objectives. The driver circuits in Figure 27 and Figure 28 are optimized for dc coupling applications requiring best distortion performance.

The circuit configuration shown in Figure 27 converts a unipolar, single-ended signal into a differential signal.

Rev. 0 | Page 18 of 28

Page 19

AD7934-6

The circuit configuration in Figure 28 converts and level shifts a single-ended, ground-referenced (bipolar) signal to a differential signal centered at the V

220Ω

390Ω

20kΩ

V+

V–

220Ω 220Ω

V+

V–

10kΩ

Figure 27. Dual Op Amp Circuit to Convert a

220Ω

390Ω

220Ω

20kΩ

V+

V–

220Ω 220Ω

V+

V–

10kΩ

Figure 28. Dual Op Amp Circuit to Convert a

REF

GND

REF

GND

2× V

p-p

REF

Single-Ended Unipolar Signal into a Differential Signal

2× V

p-p

REF

Single-Ended Bipolar Signal into a Differential Signal

level of the ADC.

REF

27Ω

3.75V

2.5V

1.25V

3.75V

2.5V

1.25V

3.75V

2.5V

1.25V

3.75V

2.5V

1.25V

IN+

AD7934-6

IN–

0.47µF

IN+

AD7934-6

IN–

0.47µF

REF

Pseudo-Differential Mode

The AD7934-6 can have two pseudo-differential pairs by setting the MODE0 and MODE1 bits in the control register to 1, 0, respectively. V have an amplitude of V

+ is connected to the signal source that must

(or 2 × V

REF

depending on the range

REF

chosen) to make use of the full dynamic range of the part. A dc input is applied to the V

pin. The voltage applied to this

IN−

input provides an offset from ground or a pseudo ground for the V

+ input. The benefit of pseudo-differential inputs is that

they separate the analog input signal ground from the ADC’s ground, allowing dc common-mode voltages to be cancelled. The specified voltage range for the V

pin while in pseudo-

IN−

differential mode is −0.1 V to +0.4 V; however, typically this range can extend to −0.3 V to +0.7 V when V to +1.8V when V

= 5V. Figure 29 shows a connection diagram

= 3 V or −0.3 V

for the pseudo-differential mode.

04752-035

04752-036

ANALOG INPUT SELECTION

As shown in Table 8, users can set up their analog input configuration by setting the values in the MODE0 and MODE1 bits in the control register. Assuming the configuration has been chosen, there are two different ways of selecting the analog input to be converted depending on the state of the SEQ0 and SEQ1 bits in the control register.

Traditional Multichannel Operation (SEQ0 = SEQ1 = 0)

Any one of four analog input channels or two pairs of channels may be selected for conversion in any order by setting the SEQ0 and SEQ1 bits in the control register both to 0. The channel to be converted is selected by writing to the address bits, ADD1 and ADD0, in the control register to program the multiplexer prior to the conversion. This mode of operation is that of a traditional multichannel ADC, where each data write selects the next channel for conversion. Figure 30 shows a flow chart of this mode of operation. The channel configurations are shown in Table 8.

Using the Sequencer: Consecutive Sequence (SEQ0 = 1, SEQ1 = 1)

A sequence of consecutive channels can be converted beginning with Channel 0 and ending with a final channel selected by writing to the ADD1 and ADD0 bits in the control register. This is done by setting the SEQ0 and SEQ1 bits in the control register both to 1. Once the control register is written to, to set this mode up, the next conversion is on Channel 0, then Channel 1, and so on until the channel selected by the address

p-p

REF

IN+

AD7934-6*

IN–

DC INPUT VOLTAGE

*ADDITIONAL PINS OMITTED FOR CLARITY

REF

0.47µF

Figure 29. Pseudo-Differential Mode Connection Diagram

POWER ON

WRITE TO THE CONTROL REGISTER TO

SET UP OPERATING MODE, ANALOG INPUT

AND OUTPUT CONFIGURATION

SET SEQ0 = SEQ1 = 0. SELECT THE DESIRED

CHANNEL TO CONVERT ON (ADD1 TO ADD0).

ISSUE CONVST PULSE TO INITIATE A CONVERSION

ON THE SELECTED CHANNEL.

INITIATE A READ CYCLE TO READ THE DATA

FROM THE SELECTED CHANNEL.

INITIATE A WRITE CYCLE TO SELECT THE NEXT

CHANNEL TO BE CONVERTED ON BY

CHANGING THE VALUES OF BITS ADD2 TO ADD0

IN THE CONTROL REGISTER. SEQ0 = SEQ1 = 0.

Figure 30. Traditional Multichannel Operation Flow Chart

04752-037

04752-038

Rev. 0 | Page 19 of 28

Page 20

AD7934-6

bits, ADD1 and ADD0, is reached. The ADC then returns to Channel 0 and starts the sequence again. The

kept high to ensure that the control register is not accidentally overwritten and the sequence interrupted. This pattern continues until such time as the AD7934-6 is written to. Figure 31 shows the flowchart of the consecutive sequence mode.

POWER ON

WRITE TO THE CONTROL REGISTER TO

SET UP OPERATING MODE, ANALOG INPUT

AND OUTPUT CONFIGURATION SELECT

FINAL CHANNEL (ADD1 AND ADD0) IN

CONSECUTIVE SEQUENCE.

SET SEQ0 = 1 SEQ1 = 1.

CONTINUOUSLY CONVERT ON A CONSECUTIVE

SEQUENCE OF CHANNELS FROM CHANNEL 0

UP TO AND INCLUDING THE PREVIOUSLY

SELECTED FINAL CHANNEL ON ADD1 AND ADD0

WITH EACH CONVST PULSE.

Figure 31. Consecutive Sequence Mode Flow Chart

REFERENCE SECTION

The AD7934-6 can operate with either the on-chip reference or an external reference. The internal reference is selected by setting the REF bit in the internal control register to 1. A block diagram of the internal reference circuitry is shown in Figure 32. The internal reference circuitry includes an on-chip 2.5 V band gap reference and a reference buffer. When using the internal reference, the V

REFIN/VREFOUT

with a 0.47 µF capacitor. This internal reference not only provides the reference for the analog-to-digital conversion, but it also is used externally in the system. It is recommended that the reference output is buffered using an external precision op amp before applying it anywhere in the system.

REFIN

REFOUT

Figure 32. Internal Reference Circuit Block Diagram

Alternatively, an external reference can be applied to the V

REFIN/VREFOUT

pin of the AD7934-6. An external reference input is selected by setting the REF bit in the internal control register to 0. The external reference input range is 0.1 V to V important to ensure that, when choosing the reference value, the maximum analog input range (V

+ 0.3 V to comply with the maximum ratings of the device.

For example, if operating in differential mode and the reference is sourced from V

used. This is because the analog input signal range would now extend to 2 × V

, which would exceed maximum rating

conditions. In the pseudo-differential modes, the user must ensure that V

REF

+ (V

or when using the 2 × V

pin should be decoupled to AGND

BUFFER

REFERENCE

ADC

AD7934-6

) is never greater than

IN MAX

, then the 0 to 2 × V

) ≤ VDD when using the 0 to V

IN−

range that 2 × V

REF

input must be

04752-039

04752-040

. It is

range cannot be

range,

REF

+(V

REF

) ≤ VDD.

IN−

In all cases, the specified reference is 2.5 V.

The performance of the part with different reference values is shown in Figure 9 to Figure 11. The value of the reference sets the analog input span and the common-mode voltage range. Errors in the reference source result in gain errors in the AD7934-6 transfer function and add to the specified full-scale errors on the part. Table 10 lists suitable voltage references available from ADI that could be used, and Figure 33 shows a typical connection diagram for an external reference.

Table 10. Examples of Suitable Voltage References

Reference

Output Voltage

Initial Accuracy (% max)

Operating Current (µA)

AD780 2.5/3 0.04 1000 ADR421 2.5 0.04 500 ADR420 2.048 0.05 500

AD780

O/PSELECT

10nF 0.1µF

0.1µF

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 33. Typical V

TEMP

GND

NC = NO CONNECT

REF

2.5V

OUT

TRIM

Connection Diagram

AD7934-6*

REF

0.1µF

Digital Inputs

The digital inputs applied to the AD7934-6 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the AV

+ 0.3 V limit that is on the analog inputs.

Another advantage of the digital inputs not being restricted by the AV issues are avoided. If any of these inputs are applied before AV

+ 0.3 V limit is the fact that power supply sequencing

then there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V was applied prior to AV

Input

DRIVE

The AD7934-6 has a V which the parallel interface operates. V

DRIVE

feature. V

controls the voltage at

DRIVE

allows the ADC to

DRIVE

easily interface to 3 V, and 5 V processors. For example, if the AD7934-6 is operated with an AV

of 5 V, and the V

DRIVE

pin is powered from a 3 V supply, the AD7934-6 has better dynamic performance with an AV

of 5 V while still being able to

interface to 3 V processors. Care should be taken to ensure V

does not exceed AVDD by more than 0.3 V (see the

DRIVE

Absolute Maximum Ratings section).

04752-041

Rev. 0 | Page 20 of 28

Page 21

AD7934-6

PARALLEL INTERFACE

The AD7934-6 has a flexible, high speed, parallel interface. This interface is 12-bits wide and is capable of operating in either word (W/

The

CONVST

operating in autoshutdown or autostandby mode, it is used to initiate power up.

A falling edge on the conversions, and it also puts the ADC track-and-hold into track.

Once the

CONVST for the duration of the conversion. In between conversions, CONVST This must happen after the 14

otherwise, the conversion is aborted and the track-and-hold goes back into track.

tied high) or byte (W/B tied low) mode.

signal is used to initiate conversions, and when

CONVST

signal is used to initiate

signal goes low, the BUSY signal goes high

must be brought high for a minimum time of t1.

falling edge of CLKIN;

At the end of the conversion, BUSY goes low and can be used to activate an interrupt service routine. The

and RD lines are

then activated in parallel to read the 12 bits of conversion data. When power supplies are first applied to the device, a rising edge on

CONVST

is necessary to put the track-and-hold into

track. The acquisition time of 125 ns minimum must be allowed before

CONVST ADC then goes into hold on the falling edge of

back into track on the 13

is brought low to initiate a conversion. The

CONVST

rising edge of CLKIN after this (see

and

Figure 34). When operating the device in autoshutdown or autostandby mode, where the ADC powers down at the end of each conversion, a rising edge on the

CONVST

signal is used to

power up the device.

CONVST

CLKIN

BUSY

INTERNAL

TRACK/HOLD

DB0 TO DB11

12345 121314

WITH CS AND RD TIED LOW

THREE-STATE

CONVERT

Figure 34. AD7934-6 Parallel Interface—Conversion and Read Cycle in Word Mode (W/

AQUISITION

DATA

DATAOLD DATADB0 TO DB11

THREE-STATE

= 1)

QUIET

04752-004

Rev. 0 | Page 21 of 28

Page 22

AD7934-6

Reading Data from the AD7934-6

With the W/B pin tied logic high, the AD7934-6 interface

operates in word mode. In this case, a single read operation from the device accesses the conversion data-word on Pins DB0 to DB11. The DB8/HBEN pin assumes its DB8 function. With the W/

pin tied to logic low, the AD7934-6 interface operates

in byte mode. In this case, the DB8/HBEN pin assumes its HBEN function.

Conversion data from the AD7934-6 must be accessed in two read operations with 8 bits of data provided on DB0 to DB7 for each of the read operations. The HBEN pin determines whether the read operation accesses the high byte or the low byte of the12-bit word. For a low byte read, DB0 to DB7 provide the eight LSBs of the 12-bit word. For a high byte read, DB0 to DB3 provide the 4 MSBs of the 12-bit word. DB4 of the high byte is always 0 and DB5 and DB6 of the high byte provide the Channel ID.

Figure 34 shows the read cycle timing diagram for a 12-bit transfer. When operated in word mode, the HBEN input does not exist and only the first read operation is required to access data from the device. When operated in byte mode, the two read cycles shown in Figure 35 are required to access the full dataword from the device.

and RD signals are gated internally and level triggered

The

CS active low. In either word mode or byte mode,

may be tied together as the timing specification t

and RD

and t11

are 0 ns minimum. This means the bus is constantly driven by the AD7934-6.

The data is placed onto the data bus a time, t

go low. The RD rising edge can be used to latch

and

data out of the device. After a time, t

, the data lines b ecome

, after both CS

three-stated.

Alternatively,

conversion data is valid and placed onto the data bus a time, t

and RD can be tied permanently low, and the

before the falling edge of BUSY.

Note that if

is pulsed during the conversion time then this

causes a degradation in linearity performance of approximately

0.25 LSB. Reading during conversion by way of tying

low does not cause any degradation.

and

HBEN/DB8

DB0 TO DB7

Figure 35. AD7934-6 Parallel Interface—Read Cycle Timing for Byte Mode Operation (W/

LOW BYTE HIGH BYTE

04752-005

= 0)

Rev. 0 | Page 22 of 28

Page 23

AD7934-6

Writing Data to the AD7934-6

With W/B tied logic high, a single write operation transfers the full data-word on DB0 to DB11 to the control register on the

AD7934-6. The DB8/HBEN pin assumes its DB8 function. Data written to the AD7934-6 should be provided on the DB0 to DB11 inputs, with DB0 being the LSB of the data-word. With

tied logic low, the AD7934-6 requires two write operations

to transfer a full 12-bit word. DB8/HBEN assumes its HBEN function. Data written to the AD7934-6 should be provided on the DB0 to DB7 inputs. HBEN determines whether the byte written is high byte or low byte data. The low byte of the dataword has DB0 being the LSB of the full data-word. For the high byte write, HBEN should be high, and the data on the DB0 input should be data Bit 8 of the 12 bit word.

Figure 36 shows the write cycle timing diagram of the AD7934-

6. When operated in word mode, the HBEN input does not exist, and only one write operation is required to write the word of data to the device. Data should be provided on DB0 to DB11. When operated in byte mode, the two write cycles shown in Figure 37 are required to write the full data-word to the AD7934-6. In Figure 37, the first write transfers the lower 8 bits of the data-word from DB0 to DB7, and the second write transfers the upper 4 bits of the data-word.

When writing to the AD7934-6, the top 4 bits in the high byte must be 0s.

The data is latched into the device on the rising edge of The data needs to be setup a time, t and held for a time, t signals are gated internally.

, after the WR rising edge. The CS and WR

the timing specification for t

and RD have not already been tied together).

, before the WR rising edge

and WR may be tied together as

and t5 is 0 ns minimum (assuming

DB0 TO DB11

DATA

Figure 36. AD7934-6 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/

04752-002

= 1)

HBEN/DB8

DB0 TO DB7

LOW BYTE HIGH BYTE

Figure 37. AD7934-6 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/

04752-003

= 0)

Rev. 0 | Page 23 of 28

Page 24

AD7934-6

POWER MODES OF OPERATION

The AD7934-6 has four different power modes of operation. These modes are designed to provide flexible power management options. Different options can be chosen to optimize the power dissipation/throughput rate ratio for differing applications. The mode of operation is selected by the power management bits, PM1 and PM0, in the control register, as detailed in Table 7. When power is first applied to the AD7934-6, an on-chip, power-on reset circuit ensures the default power-up condition is normal mode.

Note that, after power-on, the track-and-hold is in hold mo de, and the first rising edge of

CONVST

into track mode.

Normal Mode (PM1 = PM0 = 0)

This mode is intended for the fastest throughput rate performance because the user does not have to worry about any power-up times because the AD7934-6 remains fully powered up at all times. At power-on reset, this mode is the default setting in the control register.

Autoshutdown (PM1 = 0; PM0 = 1)

In this mode of operation, the AD7934-6 automatically enters full shutdown at the end of each conversion, which is shown at Point A in Figure 34 or Figure 38. In shutdown mode, all internal circuitry on the device is powered down. The part retains information in the control register during shutdown. The track-and-hold also goes into hold at this point and remains in hold as long as the device is in shutdown. The AD7934-6 remains in shutdown mode until the next rising edge of

CONVST

(see Point B in Figure 34 or Figure 38). In order to keep the device in shutdown for as long as possible, should idle low between conversions as shown in Figure 38.

On this rising edge, the part begins to power-up and the trackand-hold returns to track mode. The power-up time required is 10 ms minimum regardless of whether the user is operating with the internal or external reference. The user should ensure that the power-up time has elapsed before initiating a conversion.

places the track-and-hold

CONVST

Autostandby (PM1 = 1; PM0 = 0)

In this mode of operation, the AD7934-6 automatically enters standby mode at the end of each conversion, which is shown as Point A in Figure 34. When this mode is entered, all circuitry on the AD7934-6 is powered down except for the reference and reference buffer. The track-and-hold also goes into hold at this point and remains in hold as long as the device is in standby. The part remains in standby until the next rising edge of CONVST

powers up the device. The power-up time required

depends on whether the internal or external reference is used. With an external reference, the power-up time required is a minimum of 600 ns, while when using the internal reference, the power-up time required is a minimum of 7 µs. The user should ensure this power-up time has elapsed before initiating another conversion as shown in Figure 38. This rising edge of CONVST

also places the track-and-hold back into track mode.

Full Shutdown Mode (PM1 = 1; PM0 = 1)

When this mode is entered, all circuitry on the AD7934-6 is powered down upon completion of the write operation, i.e., on rising edge of

. The track-and-hold enters hold mode at this

point. The part retains the information in the control register while the part is in shutdown. The AD7934-6 remains in full shutdown mode, and the track-and-hold in hold mode, until the power management bits (PM1 and PM0) in the control register are changed. If a write to the control register occurs while the part is in full shutdown mode, and the power management bits are changed to PM0 = PM1 = 0, i.e., normal mode, the part begins to power up on the

rising edge, and the track-and-

hold returns to track. To ensure the part is fully powered up before a conversion is initiated, the power-up time of 10 ms minimum should be allowed before the

CONVST

falling edge;

otherwise, invalid data is read.

Note that all power-up times quoted apply with a 470 nF capacitor on the V

REFIN

pin.

POWER-UP

CONVST

1 114 14

CLKIN

BUSY

Figure 38. Autoshutdown/Autostandby Mode

04752-048

Rev. 0 | Page 24 of 28

Page 25

AD7934-6

POWER VS. THROUGHPUT RATE

A big advantage of powering the ADC down after a conversion is that the power consumption of the part is significantly reduced at lower throughput rates. When using the different power modes, the AD7934-6 is only powered up for the duration of the conversion. Therefore, the average power consumption per cycle is significantly reduced. Figure 39 shows a plot of the power vs. the throughput rate when operating in autostandby mode for both V

= 5 V and 3 V.

For example, if the maximum CLKIN frequency of 10 MHz is used to minimize the conversion time, this accounts for only

1.315 µs of the overall cycle time while the AD7934-6 remains in standby mode for the remainder of the cycle. If the device runs at a throughput rate of 10 kSPS, for example, then the overall cycle time would be 100 µs.

Figure 40 shows a plot of the power vs. the throughput rate when operating in normal mode for both V

= 5 V and

3 V. In both plots, the figures apply when using the internal reference. If an external reference is used, the power-up time reduces to 600 ns; therefore, the AD7934-6 remains in standby for a greater time in every cycle. Additionally, the current consumption when converting should be lower than the specified maximum of 1.5 mA or 1.2 mA with V

= 5 V

or 3 V, respectively.

2.0 TA = 25°C

1.8

1.6

1.4

1.2

1.0

0.8

POWER (mW)

0.6

0.4

0.2

0 20 40 60 80 120100

THROUGHPUT (kSPS)

Figure 39. Power vs. Throughput in

Autostandby Mode Using Internal Reference

VDD = 5V

VDD = 3V

04752-029

MICROPROCESSOR INTERFACING

AD7934-6 to ADSP-21xx Interface

Figure 41 shows the AD7934-6 interfaced to the ADSP-21xx series of DSPs as a memory-mapped device. A single wait state may be necessary to interface the AD7934-6 to the ADSP-21xx, depending on the clock speed of the DSP. The wait state can be programmed via the data memory wait state control register of the ADSP-21xx (see the ADSP-21xx family User’s Manual for details). The following instruction reads from the AD7934-6:

where ADC is the address of the AD7934-6.

*ADDITIONAL PINS OMITTED FOR CLARITY

TA = 25°C

POWER (mW)

0 100 200 300 400 500 700600

THROUGHPUT (kSPS)

VDD = 5V

VDD = 3V

04752-030

Figure 40. Power vs. Throughput in Normal Mode Using Internal Reference

MR = DM (ADC)

OPTIONAL

A0 TO A15

ADSP-21xx*

D0 TO D23

ADDRESS BUS

DMS

IRQ2

ADDRESS DECODER

DATA BUS

Figure 41. Interfacing to the ADSP-21xx

CONVST

AD7934-6*

BUSY WR

DB0 TO DB11

04752-044

Rev. 0 | Page 25 of 28

Page 26

AD7934-6

AD7934-6 to ADSP-21065L Interface

Figure 42 shows a typical interface between the AD7934-6 and the ADSP-21065L SHARC processor. This interface is an example of one of three DMA handshake modes. The

control line is actually three memory select lines. Internal ADDR

are decoded into

25–24

as chip selects. The

DMAR

, these lines are then asserted

3-0

(DMA request 1) is used in this

setup as the interrupt to signal the end of the conversion. The rest of the interface is standard handshaking operation.

OPTIONAL

TO ADDR

ADDR

ADSP-21065L*

DMAR

D0 TO D31

ADDITIONAL PINS OMITTED FOR CLARIT

ADDRESS BUS

ADDRESS

LATCH

ADDRESS BUS

ADDRESS DECODER

DATA BUS

CONVST

AD7934-6*

BUSY RDRD

DB0 TO DB11

Figure 42. Interfacing to the ADSP-21065L

AD7934-6 to TMS32020, TMS320C25, and TMS320C5x Interface

Parallel interfaces between the AD7934-6 and the TMS32020, TMS320C25 and TMS320C5x family of DSPs are shown in Figure 43. The memory-mapped address chosen for the AD7934-6 should be chosen to fall in the I/O memory space of the DSPs. The parallel interface on the AD7934-6 is fast enough to interface to the TMS32020 with no extra wait states. If high speed glue logic, such as 74AS devices, are used to drive the

and the

lines when interfacing to the TMS320C25, then

again, no wait states are necessary. However, if slower logic is used, data accesses may be slowed sufficiently when reading from, and writing to, the part to require the insertion of one wait state. Extra wait states are necessary when using the TMS320C5x at their fastest clock speeds (see the TMS320C5x User’s Guide for details).

Data is read from the ADC using the following instruction:

IN D, ADC

where D is the data memory address, and ADC is the AD7934-6 address.

OPTIONAL

A0 TO A15

TMS32020/

TMS320C25/

TMS320C50*

READY

MSC

STRB

INT

*ADDITIONAL PINS OMITTED FOR CLARITY

R/W

ADDRESS BUS

ADDRESS DECODER

DATA BUS

TMS320C25

ONLY

CONVST

AD7934-6*

CSEN

BUSY DB11 TO DB0DMD0 TO DMD15

04752-046

Figure 43. Interfacing to the TMS32020/C25/C5x

AD7934-6 to 80C186 Interface

Figure 44 shows the AD7934-6 interfaced to the 80C186 microprocessor. The 80C186 DMA controller provides two independent high speed DMA channels where data transfer can occur between memory and I/O spaces. Each data transfer consumes two bus cycles, one cycle to fetch data and the other to store data. After the AD7934-6 has finished a conversion, the

04752-045

BUSY line generates a DMA request to Channel 1 (DRQ1). As a result of the interrupt, the processor performs a DMA READ operation which also resets the interrupt latch. Sufficient priority must be assigned to the DMA channel to ensure that the DMA request is serviced before the completion of the next conversion.

OPTIONAL

AD0 TO AD15

A16 TO A19

80C186*

ADDITIONAL PINS OMITTED FOR CLARIT

ADDRESS/DATA BUS

ALE

DRQ1

ADDRESS

LATCH

ADDRESS

DECODER

ADDRESS BUS

DATA BUS

CONVST

AD7934-6*

BUSY RDRD

WR DB0 TO DB11

04752-047

Figure 44. Interfacing to the 80C186

Rev. 0 | Page 26 of 28

Page 27

AD7934-6

APPLICATION HINTS

GROUNDING AND LAYOUT

The printed circuit board that houses the AD7934-6 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined in only one place, and the connection should be a star ground point established as close to the ground pins on the AD7934-6 as possible. Avoid running digital lines under the device as this couples noise onto the die. The analog ground plane should be allowed to run under the AD7934-6 to avoid noise coupling. The power supply lines to the AD7934-6 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line.

Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board.

In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should be decoupled with 10 µF tantalum capacitors in parallel with

0.1 µF capacitors to GND. To achieve the best from these decoupling components, they must be placed as close as possible to the device.

EVALUATING THE AD7934-6 PERFORMANCE

The recommended layout for the AD7934-6 is outlined in the evaluation board documentation. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the evaluation board controller. The evaluation board controller can be used in conjunction with the AD7934-6 evaluation board, as well as many other ADI evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7934-6.

The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7934-6. The software and documentation are on the CD that ships with the evaluation board.

Rev. 0 | Page 27 of 28

Page 28

AD7934-6

OUTLINE DIMENSIONS

9.80

9.70

9.60

PIN 1

0.15

0.05

COPLANARITY

0.10

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AE

1.20 MAX

SEATING

PLANE

4.50

4.40

4.30

0.20

0.09

6.40 BSC

8° 0°

0.75

0.60

0.45

141

Figure 45. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Linearity Error (LSB)

AD7934BRU-6 −40°C to +85°C ±1 28-Lead TSSOP RU-28 AD7934BRU-6REEL7 −40°C to +85°C ±1 28-Lead TSSOP RU-28 AD7934BRUZ-6

−40°C to +85°C ±1 28-Lead TSSOP RU-28 AD7934BRUZ-6REEL72 −40°C to +85°C ±1 28-Lead TSSOP RU-28 EVAL-AD7934-6CB EVAL-CONTROL BRD2

Evaluation Board Controller Board

Linearity error here refers to integral linearity error.

Z = Pb-free part.

This can be used as a standalone evaluation board or in conjunction with the Evaluation Board Controller for evaluation/demonstration purposes.

The Evaluation Board Controller is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB

designators. The following needs to be ordered to obtain a complete evaluation kit: the ADC Evaluation Board (e.g. EVAL-AD7934CB), the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the relevant evaluation board technical note for more details.

Package Descriptions Package Option

D04752–0–1/05(0)

Rev. 0 | Page 28 of 28

Datasheet AD7934 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

CONTROL REGISTER

SEQUENCER OPERATION

CIRCUIT INFORMATION

CONVERTER OPERATION

ADC TRANSFER FUNCTION

TYPICAL CONNECTION DIAGRAM

ANALOG INPUT STRUCTURE

ANALOG INPUTS

Single-Ended Mode

Differential Mode

Driving Differential Inputs

Using an Op Amp Pair

Pseudo-Differential Mode

ANALOG INPUT SELECTION

Traditional Multichannel Operation (SEQ0 = SEQ1 = 0)

REFERENCE SECTION

Digital Inputs

PARALLEL INTERFACE

Reading Data from the AD7934-6

Writing Data to the AD7934-6

POWER MODES OF OPERATION

Normal Mode (PM1 = PM0 = 0)

Autoshutdown (PM1 = 0; PM0 = 1)

Autostandby (PM1 = 1; PM0 = 0)

Full Shutdown Mode (PM1 = 1; PM0 = 1)

POWER VS. THROUGHPUT RATE

MICROPROCESSOR INTERFACING

AD7934-6 to ADSP-21xx Interface

AD7934-6 to ADSP-21065L Interface

AD7934-6 to TMS32020, TMS320C25, and TMS320C5x Interface

AD7934-6 to 80C186 Interface

APPLICATION HINTS

GROUNDING AND LAYOUT

EVALUATING THE AD7934-6 PERFORMANCE

OUTLINE DIMENSIONS

ORDERING GUIDE