Datasheet AD7927 Datasheet (Analog Devices)

8-Channel, 200 kSPS, 12-Bit ADC

with Sequencer in 20-Lead TSSOP

AD7927

FEATURES
Fast Throughput Rate: 200 kSPS
Specified for AV

of 2.7 V to 5.25 V

DD

Low Power:

3.6 mW Max at 200 kSPS with 3 V Supply

7.5 mW Max at 200 kSPS with 5 V Supply
8 (Single-Ended) Inputs with Sequencer
Wide Input Bandwidth:

70 dB Min SINAD at 50 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface SPI™/QSPI™/

MICROWIRE™/DSP Compatible
Shutdown Mode: 0.5

␮A Max

20-Lead TSSOP Package

GENERAL DESCRIPTION

The AD7927 is a 12-bit, high speed, low power, 8-channel,
successive-approximation ADC. The part operates from a single

2.7 V to 5.25 V power supply and features throughput rates up
to 200 kSPS. The part contains a low noise, wide bandwidth
track-and-hold amplifier that can handle input frequencies in
excess of 8 MHz.

The conversion process and data acquisition are controlled
using CS and the serial clock signal, allowing the device to
easily interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS and the conversion is also
initiated at this point. There are no pipeline delays associated
with the part.

The AD7927 uses advanced design techniques to achieve very low
power dissipation at maximum throughput rates. At maximum
throughput rates, the AD7927 consumes 1.2 mA maximum
with 3 V supplies; with 5 V supplies, the current consumption is

1.5 mA maximum.

Through the configuration of the Control Register, the analog
input range for the part can be selected as 0 V to REF
2 ¥ REF

, with either straight binary or twos complement output

IN

or 0 V to

IN

coding. The AD7927 features eight single-ended analog inputs
with a channel sequencer to allow a preprogrammed selection of
channels to be converted sequentially.

The conversion time for the AD7927 is determined by the SCLK
frequency, as this is also used as the master clock to control the
conversion. The conversion time may be as short as 800 ns with
a 20 MHz SCLK.

FUNCTIONAL BLOCK DIAGRAM

AV

DD

REF

IN

VIN0

V

IN

•

•

•

•

•

•

•

•

•

•

•

•

•
7

I/P

MUX

AD7927

T/H

SEQUENCER

APPROXIMATION

CONTROL LOGIC

GND

12-BIT

SUCCESSIVE

ADC

SCLK

DOUT

DIN

CS

V

DRIVE

PRODUCT HIGHLIGHTS

1. High Throughput with Low Power Consumption.
The AD7927 offers up to 200 kSPS throughput rates. At the
maximum throughput rate with 3 V supplies, the AD7927
dissipates 3.6 mW of power maximum.

2. Eight Single-Ended Inputs with a Channel Sequencer.
A consecutive sequence of channels, through which the ADC
will cycle and convert on, can be selected.

3. Single-Supply Operation with V

DRIVE

Function.

The AD7927 operates from a single 2.7 V to 5.25 V supply. The

function allows the serial interface to connect directly

V

DRIVE

to either 3 V or 5 V processor systems independent of AV

DD

4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. The part also features various shutdown modes
to maximize power efficiency at lower throughput rates. Current
consumption is 0.5 mA maximum when in full shutdown.

5. No Pipeline Delay.
The part features a standard successive-approximation ADC
with accurate control of the sampling instant via a CS input
and once off conversion control.

.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD7927–SPECIFICATIONS

(AVDD = V

= 2.7 V to 5.25 V, REFIN = 2.5 V, f

DRIVE

otherwise noted.)

= 20 MHz, TA = T

SCLK

MIN

to T

, unless

MAX

Parameter B Version

DYNAMIC PERFORMANCE f

Signal-to-(Noise + Distortion) (SINAD)

Signal-to-Noise Ratio (SNR)

2

Total Harmonic Distortion (THD)

2

70 dB min @ 5 V
69 dB min @ 3 V Typically 70 dB

2

70 dB min
–77 dB max @ 5 V Typically –84 dB

1

Unit Test Conditions/Comments

= 50 kHz Sine Wave, f

IN

SCLK

= 20 MHz

–73 dB max @ 3 V Typically –77 dB

Peak Harmonic or Spurious Noise –78 dB max @ 5 V Typically –86 dB

(SFDR)

Intermodulation Distortion (IMD)

2

2

–76 dB max @ 3 V Typically –80 dB

fa = 40.1 kHz, fb = 41.5 kHz
Second Order Terms –90 dB typ
Third Order Terms –90 dB typ

Aperture Delay 10 ns typ
Aperture Jitter 50 ps typ
Channel-to-Channel Isolation

2

–82 dB typ fIN = 400 kHz

Full Power Bandwidth 8.2 MHz typ @ 3 dB

1.6 MHz typ @ 0.1 dB

DC ACCURACY

2

Resolution 12 Bits
Integral Nonlinearity ± 1 LSB max
Differential Nonlinearity –0.9/+1.5 LSB max Guaranteed No Missed Codes to 12 Bits
0 V to REF

Input Range Straight Binary Output Coding

IN

Offset Error ± 8 LSB max Typically ± 0.5 LSB
Offset Error Match ± 0.5 LSB max
Gain Error ± 1.5 LSB max
Gain Error Match ± 0.5 LSB max

0 V to 2 ¥ REF

Input Range –REFIN to +REFIN Biased about REFIN with

IN

Positive Gain Error ± 1.5 LSB max Twos Complement Output Coding
Positive Gain Error Match ± 0.5 LSB max
Zero Code Error ± 8 LSB max Typically ± 0.8 LSB
Zero Code Error Match ± 0.5 LSB max
Negative Gain Error ± 1 LSB max
Negative Gain Error Match ± 0.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to REF

0 to 2 ¥ REF

V RANGE Bit Set to 1

IN

V RANGE Bit Set to 0, AVDD/V

IN

= 4.75 V to 5.25 V

DRIVE

DC Leakage Current ± 1 mA max
Input Capacitance 20 pF typ f

SAMPLE

= 200 kSPS

REFERENCE INPUT

REFIN Input Voltage 2.5 V ± 1% Specified Performance
DC Leakage Current ± 1 mA max
REFIN Input Impedance 36 kW typ

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

3

0.7 ¥ V

DRIVE

0.3 ¥ V

DRIVE

± 1 mA max Typically 10 nA, V
10 pF max

V min
V max

= 0 V or V

IN

DRIVE

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ± 1 mA max
Floating-State Output Capacitance

OH

OL

3

V

– 0.2 V min I

DRIVE

0.4 V max I

10 pF max

= 200 mA, AVDD = 2.7 V to 5.25 V

SOURCE

= 200 mA

SINK

Output Coding Straight (Natural) Binary Coding Bit Set to 1

Twos Complement Coding Bit Set to 0

REV. 0–2–

Parameter B Version1Unit Test Conditions/Comments

CONVERSION RATE

Conversion Time 800 ns max 16 SCLK Cycles with SCLK at 20 MHz
Track-and-Hold Acquisition Time 300 ns max Sine Wave Input

300 ns max Full-Scale Step Input

Throughput Rate 200 kSPS max See Serial Interface Section

POWER REQUIREMENTS

AV

DD

V

DRIVE

4

I

DD

During Conversion 2.7 mA max AVDD = 4.75 V to 5.25 V, f

Normal Mode (Static) 600 mA typ AV
Normal Mode (Operational) f

Using Auto Shutdown Mode f

= 200 kSPS 1.5 mA max AVDD = 4.75 V to 5.25 V, f

SAMPLE

= 200 kSPS 900 mA typ AVDD = 4.75 V to 5.25 V, f

SAMPLE

2.7/5.25 V min/max

2.7/5.25 V min/max
Digital I/Ps = 0 V or V

2 mA max AV

1.2 mA max AV

650 mA typ AV

DRIVE

= 2.7 V to 3.6 V, f

DD

= 2.7 V to 5.25 V, SCLK On or Off

DD

= 2.7 V to 3.6 V, f

DD

= 2.7 V to 3.6 V, f

DD

SCLK

= 20 MHz

SCLK

= 20 MHz

SCLK

= 20 MHz

SCLK

= 20 MHz

SCLK

= 20 MHz

SCLK

= 20 MHz

Auto Shutdown (Static) 0.5 mA max SCLK On or Off (20 nA typ)
Full Shutdown Mode 0.5 mA max SCLK On or Off (20 nA typ)

Power Dissipation

Normal Mode (Operational) 7.5 mW max AVDD = 5 V, f

Auto Shutdown (Static) 2.5 mW max AV

Full Shutdown Mode 2.5 mW max AV

4

= 20 MHz

3.6 mW max AV

1.5 mW max AV

= 3 V, f

DD

= 5 V

DD

= 3 V

DD

= 5 V

DD

SCLK

= 20 MHz

SCLK

1.5 mW max AVDD = 3 V

NOTES

1

Temperature ranges as follows: B Version: –40∞ C to +85∞C.

2

See Terminology section.

3

Sample tested @ 25∞C to ensure compliance.

4

See Power versus Throughput Rate section.

Specifications subject to change without notice.

AD7927

REV. 0

–3–

AD7927

TIMING SPECIFICATIONS

Limit at T

1

(AVDD = 2.7 V to 5.25 V, V

, T

MAX

AD7927

MIN

ⱕ AVDD, REFIN = 2.5 V, TA = T

DRIVE

MIN

to T

, unless otherwise noted.)

MAX

Parameter AVDD = 3 V AVDD = 5 V Unit Description

2

f

SCLK

10 10 kHz min
20 20 MHz max

t

CONVERT

t

QUIET

16 ¥ t

SCLK

50 50 ns minMinimum Quiet Time Required between CS Rising Edge

16 ¥ t

SCLK

and Start of Next Conversion

t

2

3

t

3

3

t

4

t

5

t

6

t

7

4

t

8

t

9

t

10

t

11

t

12

10 10 ns min CS to SCLK Setup Time
35 30 ns max Delay from CS until DOUT Three-State Disabled
40 40 ns max Data Access Time after SCLK Falling Edge

0.4 ¥ t

0.4 ¥ t

SCLK

SCLK

0.4 ¥ t

0.4 ¥ t

SCLK

SCLK

ns min SCLK Low Pulsewidth

ns min SCLK High Pulsewidth
10 10 ns min SCLK to DOUT Valid Hold Time
15/45 15/35 ns min/max SCLK Falling Edge to DOUT High Impedance
10 10 ns min DIN Setup Time Prior to SCLK Falling Edge
55 ns min DIN Hold Time after SCLK Falling Edge
20 20 ns min Sixteenth SCLK Falling Edge to CS High
11 ms max Power-Up Time from Full Power-Down/Auto

Shutdown Mode

NOTES

1

Sample tested at 25∞C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V.
See Figure 1. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.

2

Mark/Space ratio for the SCLK input is 40/60 to 60/40.

3

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 ¥ V

4

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means the time, quoted in the timing characteristics t8, is the true bus relinquish time
of the part and is independent of the bus loading.

Specifications subject to change without notice.

DRIVE

.

I

OL

1.6V

I

OH

OUTPUT

PIN

200␮A

TO

C

L

50pF

200␮A

Figure 1. Load Circuit for Digital Output Timing Specifications

REV. 0–4–

AD7927

ABSOLUTE MAXIMUM RATINGS

(TA = 25∞C, unless otherwise noted.)

1

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

V

DRIVE

Analog Input Voltage to AGND . . . . –0.3 V to AV

+ 0.3 V

DD

Digital Input Voltage to AGND . . . . . . . . . . . . –0.3 V to +7 V

Digital Output Voltage to AGND . . . . . –0.3 V to AV

to AGND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

REF

IN

+ 0.3 V

DD

Input Current to Any Pin Except Supplies2 . . . . . . . . ± 10 mA

Operating Temperature Range

Commercial (B Version) . . . . . . . . . . . . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . –65∞C to +150∞C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C

ORDERING GUIDE

Temperature Linearity Package Package

Model Range Error (LSB)

AD7927BRU –40∞C to +85∞C ± 1 RU-20 TSSOP
EVAL-AD7927CB
EVAL-CONTROL BRD2

NOTES

1

Linearity error here refers to integral linearity error.

2

This can be used as a standalone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/demonstration purposes.

3

This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
To order a complete evaluation kit, you will need to order the particular ADC evaluation board, e.g., EVAL-AD7927CB, the EVAL-CONTROL
BRD2, and a 12 V ac transformer. See the relevant Evaluation Board Application Note for more information.

2

3

TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . 143∞C/W (TSSOP)

q

JA

Thermal Impedance . . . . . . . . . . . . . . . 45∞C/W (TSSOP)

q

JC

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215∞C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

1

Option Description

Evaluation Board
Controller Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7927 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0

–5–

AD7927

PIN CONFIGURATION

20-Lead TSSOP

1

SCLK AGND

2

DIN V

3

CS

AD7927

4

AGND AGND

AV

AV

REF

AGND VIN3

TOP VIEW

(Not to Scale)

5

DD

6

DD

7

IN

8

9

VIN7V

10

VIN6V

20

19

18

17

16

15

14

13

12

11

DRIVE

DOUT

VIN0

VIN1

VIN2

IN

IN

4

5

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock

input is also used as the clock source for the AD7927s conversion process.

2DIN Data In. Logic input. Data to be written to the AD7927s Control Register is provided on this input

and is clocked into the register on the falling edge of SCLK (see the Control Register section).

3 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on

the AD7927 and framing the serial data transfer.

4, 8, 17, 20 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7927. All analog input

signals and any external reference signal should be referred to this AGND voltage. All AGND pins
should be connected together.

5, 6 AV

7 REF

DD

IN

Analog Power Supply Input. The AVDD range for the AD7927 is from 2.7 V to 5.25 V. For the
0V to 2 ¥ REF

range, AVDD should be from 4.75 V to 5.25 V.

IN

Reference Input for the AD7927. An external reference must be applied to this input. The voltage
range for the external reference is 2.5 V ± 1% for specified performance.

16–9V

0–VIN7Analog Input 0 through Analog Input 7. Eight single-ended analog input channels that are multiplexed

IN

into the on-chip track-and-hold. The analog input channel to be converted is selected by using the
address bits ADD2 through ADD0 of the Control Register. The address bits in conjunction with the
SEQ and SHADOW bits allow the sequencer to be programmed. The input range for all input channels
can extend from 0 V to REF

or 0 V to 2 ¥ REFIN, as selected via the RANGE bit in the Control Register.

IN

Any unused input channels should be connected to AGND to avoid noise pickup.

18 DOUT Data Out. Logic output. The conversion result from the AD7927 is provided on this output as a serial

data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the
AD7927 consists of two leading zeros, two address bits indicating which channel the conversion result
corresponds to, followed by the 12 bits of conversion data, MSB first. The output coding may be
selected as straight binary or twos complement via the CODING bit in the Control Register.

19 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface
of the AD7927 will operate.

REV. 0–6–

AD7927

TERMINOLOGY
Integral Nonlinearity

This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end­points of the transfer function are zero-scale, a point 1 LSB
below the first code transition, and full-scale, a point 1 LSB
above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.

Offset Error Match

This is the difference in offset error between any two channels.

Gain Error

This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., REFIN – 1 LSB) after the
offset error has been adjusted out.

Gain Error Match

This is the difference in gain error between any two channels.

Zero Code Error

This applies when using the twos complement output coding
option, in particular to the 2 ¥ REF
to +REFIN biased about the REF
the midscale transition (all 0s to all 1s) from the ideal V
age, i.e., REF

Zero Code Error Match

– 1 LSB.

IN

input range with –REF

IN

point. It is the deviation of

IN

IN

IN

volt-

This is the difference in Zero Code Error between any two
channels.

Positive Gain Error

This applies when using the twos complement output coding
option, in particular to the 2 ¥ REF
to +REFIN biased about the REF

input range with –REF

IN

point. It is the deviation of

IN

IN

the last code transition (011. . .110) to (011 . . . 111) from the
ideal (i.e., +REF

– 1 LSB) after the Zero Code Error has been

IN

adjusted out.

Positive Gain Error Match

This is the difference in Positive Gain Error between any two
channels.

Negative Gain Error

This applies when using the twos complement output coding
option, in particular to the 2 ¥ REF
to +REFIN biased about the REF

input range with –REF

IN

point. It is the deviation of

IN

IN

the first code transition (100 . . . 000) to (100 . . . 001) from the
ideal (i.e., –REF

+ 1 LSB) after the Zero Code Error has

IN

been adjusted out.

Negative Gain Error Match

This is the difference in Negative Gain Error between any two
channels.

Channel-to-Channel Isolation

Channel-to-Channel Isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale 400 kHz
sine wave signal to all seven nonselected input channels and deter­mining how much that signal is attenuated in the selected channel
with a 50 kHz signal. The figure is given worst case across all
eight channels for the AD7927.

PSR (Power Supply Rejection)

Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power supply rejection is the
maximum change in full-scale transition point due to a change
in power supply voltage from the nominal value. See Typical
Performance Characteristics.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns into track mode at the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ± 1 LSB, after the end of conversion.

Signal-to-(Noise + Distortion) Ratio

This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (f

/2), excluding dc. The ratio

S

is dependent on the number of quantization levels in the digiti­zation process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:

Signal to Noise Distortion N dB--()(..)+=+602 176

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7927, it is defined as:

2

() log=

THD dB

20

++++

VVVVV

223242526

V

1

where V1 is the rms amplitude of the fundamental and V2, V3,

, V5, and V6 are the rms amplitudes of the second through the

V

4

sixth harmonics.

REV. 0

–7–

AD7927–Typical Performance Characteristics

PERFORMANCE CURVES

TPC 1 shows a typical FFT plot for the AD7927 at 200 kSPS
sample rate and 50 kHz input frequency. TPC 2 shows the
signal-to-(noise + distortion) ratio performance versus input
frequency for various supply voltages while sampling at 200 kSPS
with an SCLK of 20 MHz.

TPC 3 shows the power supply rejection ratio versus supply
ripple frequency for the AD7927 with no decoupling. The power
supply rejection ratio is defined as the ratio of the power in the
ADC output at full-scale frequency f, to the power of a 200 mV
p-p sine wave applied to the ADC AVDD supply of frequency fS:

PSRR dB Pf Pf

() log( / )= 10

s

Pf is equal to the power at frequency f in ADC output; PfS is equal
to the power at frequency fS coupled onto the ADC AVDD supply.
Here a 200 mV p-p sine wave is coupled onto the AVDD supply.

4096 POINT FFT

= 4.75V

AV

DD

f

–10

–30

–50

SNR – dB

–70

–90

–110

0

10 30 50 70 90

FREQUENCY – kHz

= 200kSPS

SAMPLE

f

= 50kHz

IN

SINAD = 70.714dB
THD = ⴚ82.853dB
SFDR = ⴚ84.815dB

80604020

100

TPC 1. Dynamic Performance at 200 kSPS

75

TPC 4 shows a graph of total harmonic distortion versus analog
input frequency for various supply voltages, while TPC 5 shows
a graph of total harmonic distortion versus analog input frequency
for various source impedances. See the Analog Input section.

TPC 6 and TPC 7 show typical INL and DNL plots for the
AD7927.

0

AVDD = 5V
200mV p-p SINE WAVE ON AV

–10

REFIN = 2.5V, 1␮F CAPACITOR

= 25ⴗC

T

A

–20

–30

–40

–50

PSRR – dB

–60

–70

–80

–90

0 200

SUPPLY RIPPLE FREQUENCY – kHz

100

DD

18016014012080604020

TPC 3. PSRR vs. Supply Ripple Frequency

–50

f

= 200kSPS

SAMPLE

= 25ⴗC

T

A

–55

RANGE = 0 TO REF

–60

–65

–70

THD – dB

–75

–80

IN

AV

AVDD = V

= V

DD

DRIVE

DRIVE

= 3.6V

= 2.7V

AVDD = V

AV

DD

70

AV

DD

AV

DD

SINAD – dB

65

f

= 200kSPS

SAMPLE

= 25ⴗC

T

A

RANGE = 0 TO REF

60

0 100

IN

INPUT FREQUENCY – kHz

= V

= V

= V

DRIVE

DRIVE

DRIVE

DRIVE

= 5.25V

= 4.75V

= 3.6V

= 2.7V

TPC 2. SINAD vs. Analog Input Frequency for Various
Supply Voltages at 200 kSPS

–85

–90

10 100

INPUT FREQUENCY – kHz

AV

= V

DRIVE

AV

DD

= 4.75V
= V

DRIVE

= 5.25V

DD

TPC 4. THD vs. Analog Input Frequency for Various
Supply Voltages at 200 kSPS

–55

f

= 200kSPS

SAMPLE

= 25ⴗC

T

A

–60

–65

–70

–75

THD – dB

–80

–85

–90

–95

= 5.25V

AV

DD

RANGE = 0 TO REF

10 100

IN

RIN = 1000⍀

R

= 100⍀

IN

RIN = 50⍀

INPUT FREQUENCY – kHz

R

= 10⍀

IN

TPC 5. THD vs. Analog Input Frequency for Various
Source Impedances

REV. 0–8–

AD7927

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR – LSB

–0.4

–0.6

–0.8

–1.0

= V

DRIVE

= 5V

2048

CODE

2560 3072 3584512 1024 1536

AV

DD

TEMP = 25ⴗC

0

0 4096

TPC 6. Typical INL

1.0
AVDD = V

0.8

TEMP = 25ⴗC

0.6

0.4

0.2

0

–0.2

DNL ERROR – LSB

–0.4

–0.6

–0.8

–1.0

0 4096

DRIVE

= 5V

2048

CODE

2560 3072 3584512 1024 1536

TPC 7. Typical DNL

CONTROL REGISTER

The Control Register on the AD7927 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7927 on the falling
edge of SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data
transferred on the DIN line corresponds to the AD7927 configuration for the next conversion. This requires 16 serial clocks for every
data transfer. Only the information provided on the first 12 falling clock edges (after CS falling edge) is loaded to the Control Register.
MSB denotes the first bit in the data stream. The bit functions are outlined in Table I.

Table I. Control Register Bit Functions

MSB LSB

WRITE SEQ DONTC ADD2 ADD1 ADD0 PM1 PM0 SHADOW DONTC RANGE CODING

Bit Mnemonic Comment

11 WRITE The value written to this bit of the Control Register determines whether the following 11 bits will be loaded

to the Control Register. If this bit is a 1, the following 11 bits will be written to the Control Register; if it is
a 0, then the remaining 11 bits are not loaded to the Control Register and it remains unchanged.

10 SEQ The SEQ bit in the Control Register is used in conjunction with the SHADOW bit to control the use of the

sequencer function and access the Shadow Register. (See Table IV.)

9 DONTC Don’t Care

8–6 ADD2–ADD0 These three address bits are loaded at the end of the present conversion and select which analog input channel

is to be converted in the next serial transfer, or they may select the final channel in a consecutive sequence
as described in Table IV. The selected input channel is decoded as shown in Table II. The address bits
corresponding to the conversion result are also output on DOUT prior to the 12 bits of data. (See the Serial
Interface section.) The next channel to be converted on will be selected by the mux on the 14th SCLK
falling edge.

5, 4 PM1, PM0 Power Management Bits. These two bits decode the mode of operation of the AD7927 as shown in Table III.

3 SHADOW The SHADOW bit in the Control Register is used in conjunction with the SEQ bit to control the use of the

sequencer function and access the Shadow Register. (See Table IV.)

2 DONTC Don’t Care

1 RANGE This bit selects the analog input range to be used on the AD7927. If it is set to 0, the analog input range

will extend from 0 V to 2 ¥ REF

. If it is set to 1, the analog input range will extend from 0 V to REF

IN

IN

(for the next conversion). For the 0 V to 2 ¥ REFIN range, AVDD = 4.75 V to 5.25 V.

0 CODING This bit selects the type of output coding the AD7927 will use for the conversion result. If this bit is set to

0, the output coding for the part will be twos complement. If this bit is set to 1, the output coding from the
part will be straight binary (for the next conversion).

REV. 0

–9–

AD7927

Table II. Channel Selection

ADD2 ADD1 ADD0 Analog Input Channel

00 0 V
00 1 V
01 0 V
01 1 V
10 0 V
10 1 V
11 0 V
11 1 V

PM1 PM0 Mode

11Normal Operation. In this mode, the AD7927 remains in full power mode, regardless of the status of any of the logic

inputs. This mode allows the fastest possible throughput rate from the AD7927.

10Full Shutdown. In this mode, the AD7927 is in full shutdown mode with all circuitry on the AD7927 powering down.

The AD7927 retains the information in the Control Register while in full shutdown. The part remains in full shutdown
until these bits are changed.

01Auto Shutdown. In this mode, the AD7927 automatically enters full shutdown mode at the end of each conversion

when the Control Register is updated. Wake-up time from full shutdown is 1 ms and the user should ensure that 1 ms
has elapsed before attempting to perform a valid conversion on the part in this mode.

00Invalid Selection. This configuration is not allowed.

0

IN

1

IN

2

IN

3

IN

4

IN

5

IN

6

IN

7

IN

Table III. Power Mode Selection

SEQUENCER OPERATION

The configuration of the SEQ and SHADOW bits in the
Control Register allows the user to select a particular mode of
operation of the sequencer function. Table IV outlines the four
modes of operation of the sequencer.

Table IV. Sequence Selection

SEQ SHADOW Sequence Type

00 This configuration means that the sequence function is not used. The analog input channel selected for each

individual conversion is determined by the contents of the channel address bits ADD0 through ADD2 in each
prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without
the sequencer function being used, where each write to the AD7927 selects the next channel for conversion. (See
Figure 2.)

01 This configuration selects the Shadow Register for programming. The following write operation will load the

contents of the Shadow Register. This will program the sequence of channels to be converted on continuously with
each successive valid CS falling edge. (See Shadow Register, Table V, and Figure 3.) The channels selected need
not be consecutive.

10 If the SEQ and SHADOW bits are set in this way, the sequence function will not be interrupted upon completion

of the WRITE operation. This allows other bits in the Control Register to be altered between conversions while
in a sequence, without terminating the cycle.

11 This configuration is used in conjunction with the channel address bits ADD2 to ADD0 to program continuous

conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the
channel address bits in the Control Register. (See Figure 4.)

REV. 0–10–

AD7927

SHADOW REGISTER

The Shadow Register on the AD7927 is a 16-bit, write-only
register. Data is loaded from the DIN pin of the AD7927 on the
falling edge of SCLK. The data is transferred on the DIN line at
the same time that a conversion result is read from the part. This
requires 16 serial clock falling edges for the data transfer. The
information is clocked into the Shadow Register, provided that the
SEQ and SHADOW bits were set to 0,1, respectively, in the
previous write to the Control Register. MSB denotes the first bit
in the data stream. Each bit represents an analog input from
Channel 0 to Channel 7. Through programming the Shadow
Register, two sequences of channels may be selected, through

which the AD7927 will cycle with each consecutive conversion
after the write to the Shadow Register. Sequence One will be
performed first and then Sequence Two. If the user does not
wish to preform a second sequence option, then all 0s must be
written to the last eight LSBs of the Shadow Register. To select
a sequence of channels, the associated channel bit must be set for
each analog input. The AD7927 will continuously cycle through
the selected channels in ascending order, beginning with the
lowest channel, until a write operation occurs (i.e., the WRITE bit
is set to 1) with the SEQ and SHADOW bits configured in any
way except 1,0. (See Table IV.) The bit functions are outlined
in Table V.

Table V. Shadow Register Bit Functions

MSB LSB
VIN0VIN1VIN2VIN3VIN4VIN5VIN6VIN7VIN0VIN1VIN2VIN3VIN4VIN5VIN6VIN7

------------------SEQUENCE ONE-------------------------------------------------------SEQUENCE TWO-----------------------

CS

POWER-ON

DUMMY CONVERSION
DIN = ALL 1s

DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A2–A0 FOR CONVERSION.
SEQ = SHADOW = 0

CS

DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A2–A0 FOR CONVERSION.
SEQ = 0 SHADOW = 1

POWER-ON

DUMMY CONVERSION
DIN = ALL 1s

DOUT: CONVERSION RESULT FROM PREVIOUSLY
SELECTED CHANNEL A2–A0.

CS

DIN: WRITE TO CONTROL REGISTER,
WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT A2–A0 FOR CONVERSION.
SEQ = SHADOW = 0

WRITE BIT = 1,
SEQ = SHADOW = 0

Figure 2. SEQ Bit = 0, SHADOW Bit = 0 Flowchart

Figure 2 reflects the traditional operation of a multichannel ADC,
where each serial transfer selects the next channel for conversion.
In this mode of operation, the sequencer function is not used.

Figure 3 shows how to program the AD7927 to continuously
convert on a particular sequence of channels. To exit this mode
of operation and revert back to the traditional mode of operation
of a multichannel ADC (as outlined in Figure 2), ensure that the
WRITE bit = 1 and the SEQ = SHADOW = 0 on the next serial
transfer. Figure 4 shows how a sequence of consecutive chan­nels can be converted on without having to program the Shadow
Register or write to the part on each serial transfer. Again, to exit
this mode of operation and revert back to the traditional mode
of operation of a multichannel ADC (as outlined in Figure 2),
ensure the WRITE bit = 1 and the SEQ = SHADOW = 0 on
the next serial transfer.

DOUT: CONVERSION RESULT FROM PREVIOUSLY

CS

CS

SELECTED CHANNEL A2–A0.
DIN: WRITE TO SHADOW REGISTER, SELECTING
WHICH CHANNELS TO CONVERT ON; CHANNELS
SELECTED NEED NOT BE CONSECUTIVE CHANNELS

WRITE BIT = 0 WRITE BIT = 1

CONTINUOUSLY
CONVERTS ON THE
SELECTED
SEQUENCE OF
CHANNELS

WRITE BIT = 0

WRITE BIT = 0

CONTINUOUSLY
CONVERTS ON THE
SELECTED
SEQUENCE OF
CHANNELS BUT
WILL ALLOW RANGE,
CODING, AND SO ON,
TO CHANGE IN THE
CONTROL REGISTER
WITHOUT INTERRUPT­ING THE SEQUENCE,
PROVIDED SEQ = 1
SHADOW = 0

WRITE BIT = 1,
SEQ = 1,
SHADOW = 0

SEQ = 1 SHADOW = 0

Figure 3. SEQ Bit = 0, SHADOW Bit = 1 Flowchart

REV. 0

–11–

AD7927

POWER-ON

DUMMY CONVERSION
DIN = ALL 1s

DIN: WRITE TO CONTROL REGISTER,

CS

CS

CS

WRITE BIT = 1,
SELECT CODING, RANGE, AND POWER MODE.
SELECT CHANNEL A2–A0 FOR CONVERSION.
SEQ = 1 SHADOW = 1

DOUT: CONVERSION RESULT FROM CHANNEL 0

CONTINUOUSLY CONVERTS ON A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0 UP
TO AND INCLUDING THE PREVIOUSLY SELECTED
A2–A0 IN THE CONTROL REGISTER

CONTINUOUSLY CONVERTS ON THE SELECTED
SEQUENCE OF CHANNELS BUT WILL ALLOW
RANGE, CODING AND SO ON, TO CHANGE IN THE
CONTROL REGISTER WITHOUT INTERRUPTING
THE SEQUENCE, PROVIDED SEQ = 1 SHADOW = 0

WRITE BIT = 0

WRITE BIT = 1,
SEQ = 1,
SHADOW = 0

Figure 4. SEQ Bit = 1, SHADOW Bit = 1 Flowchart

CIRCUIT INFORMATION

The AD7927 is a high speed, 8-channel, 12-bit, single supply,
A/D converter. The part can be operated from a 2.7 V to 5.25 V
supply. When operated from either a 5 V or 3 V supply, the AD7927
is capable of throughput rates of 200 kSPS. The conversion time
may be as short as 800 ns when provided with a 20 MHz clock.

The AD7927 provides the user with an on-chip track-and-hold,
A/D converter, and a serial interface housed in a 20-lead TSSOP
package. The AD7927 has eight single-ended input channels
with a channel sequencer, allowing the user to select a channel
sequence through which the ADC can cycle with each consecu­tive CS falling edge. The serial clock input accesses data from
the part, controls the transfer of data written to the ADC, and
provides the clock source for the successive-approximation A/D
converter. The analog input range for the AD7927 is 0 V to

or 0 V to 2 ¥ REFIN, depending on the status of Bit 1 in

REF

IN

the Control Register. For the 0 to 2 ¥ REF

range, the part

IN

must be operated from a 4.75 V to 5.25 V supply.

The AD7927 provides flexible power management options to
allow the user to achieve the best power performance for a given
throughput rate. These options are selected by programming the
Power Management bits, PM1 and PM0, in the Control Register.

CONVERTER OPERATION

The AD7927 is a 12-bit successive approximation analog-to­digital converter based around a capacitive DAC. The AD7927
can convert analog input signals in the range 0 V to REF
to 2 ¥ REF

. Figures 5 and 6 show simplified schematics of the

IN

or 0 V

IN

ADC. The ADC is comprised of Control Logic, SAR, and a
Capacitive DAC that are used to add and subtract fixed amounts
of charge from the sampling capacitor to bring the comparator
back into a balanced condition. Figure 5 shows the ADC during
its acquisition phase. SW2 is closed and SW1 is in position A.
The comparator is held in a balanced condition and the sampling
capacitor acquires the signal on the selected V

channel.

IN

CAPACITIVE

DAC

VIN0

V

7

IN

AGND

A

SW1

4k⍀

B

SW2

COMPARATOR

CONTROL

LOGIC

Figure 5. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 6), SW2 will
open and SW1 will move to position B, causing the comparator
to become unbalanced. The Control Logic and the Capacitive
DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the ADC
output code. Figures 8 and 9 show the ADC transfer functions.

CAPACITIVE

DAC

VIN0

V

IN

.
.

7

AGND

A

SW1

B

4k⍀

SW2

COMPARATOR

CONTROL

LOGIC

Figure 6. ADC Conversion Phase

Analog Input

Figure 7 shows an equivalent circuit of the analog input structure
of the AD7927. The two diodes D1 and D2 provide ESD pro­tection for the analog inputs. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 300 mV. This will cause these diodes to become forward
biased and start conducting current into the substrate. 10 mA is
the maximum current these diodes can conduct without causing
irreversible damage to the part. The capacitor C1 in Figure 7 is
typically about 4 pF and can primarily be attributed to pin capaci­tance. The resistor R1 is a lumped component made up of the on
resistance of a switch (track-and-hold switch) and also includes
the on resistance of the input multiplexer. The total resistance is
typically about 400 W. The capacitor C2 is the ADC sampling
capacitor and has a capacitance of 30 pF typically. For ac appli­cations, removing high frequency components from the analog
input signal is recommended by use of an RC low-pass filter on
the relevant analog input pin. In applications where harmonic
distortion and signal to noise ratio are critical, the analog input
should be driven from a low impedance source. Large source
impedances will significantly affect the ac performance of the ADC.
This may necessitate the use of an input buffer amplifier. The
choice of the op amp will be a function of the particular application.

When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance will depend on the amount of total harmonic distortion
(THD) that can be tolerated. The THD will increase as the source
impedance increases, and performance will degrade. (See TPC 5.)

AV

DD

V

IN

C1

4pF

D1

D2

CONVERSION PHASE: SWITCH OPEN
TRACK PHASE: SWITCH CLOSED

C2

30pF

R1

Figure 7. Equivalent Analog Input Circuit

REV. 0–12–

AD7927

SERIAL

INTERFACE

AD780

2.5V

AD7927

0.1␮F

␮C/␮P

0.1␮F

10␮F

3V

SUPPLY

5V

SUPPLY

0.1␮F

10␮F

AGND

AV

DD

V

IN

0

•

•

V

IN

7

0V TO REF

IN

SCLK

DOUT

CS

DIN

V

DRIVE

REF

IN

NOTE: ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTED TO AGND

ADC TRANSFER FUNCTION

The output coding of the AD7927 is either straight binary or
twos complement, depending on the status of the LSB in the
Control Register. The designed code transitions occur at suc­cessive LSB values (i.e., 1 LSB, 2 LSBs, and so forth). The LSB

111…111
111…110

•

•

111…000

•

011…111

•

•
000…010
000…001
000…000

NOTE: V

1 LSB

0V

REF

1LSB ⴝ V

ANALOG INPUT

IS EITHER REF

REF

+V

OR 2 ⴛ REF

IN

/4096

REF

ⴚ 1 LSB

IN

Figure 8. Straight Binary Transfer Characteristic

V

REF

0.1␮F

REF

size is REFIN/4096 for the AD7927. The ideal transfer charac­teristic for the AD7927 when straight binary coding is selected
is shown in Figure 8, and the ideal transfer characteristic for the
AD7927 when twos complement coding is selected is shown in
Figure 9.

011…111
011…110

•

•
000…001
000…000
111…111

•

ADC CODE

•
100…010
100…001
100…000

1LSB ⴝ 2 ⴛ V

ⴙ 1LSB

–V

REF

V

+V

ⴚ 1LSB

REF

ANALOG INPUT

REF

REF

ⴚ 1LSB

Ⲑ4096

Figure 9. Twos Complement Transfer Characteristic with
REF

± REFIN Input Range

IN

V

DD

AV

DD

IN

V

DRIVE

V

DD

V

0V

Handling Bipolar Input Signals

Figure 10 shows how useful the combination of the 2 ¥ REF
input range and the twos complement output coding scheme is
for handling bipolar input signals. If the bipolar input signal is
biased about REF
selected, then REF
negative full scale and +REF
a dynamic range of 2 ¥ REF

and twos complement output coding is

IN

becomes the zero code point, –REFIN is

IN

becomes positive full scale, with

IN

.

IN

TYPICAL CONNECTION DIAGRAM

Figure 11 shows a typical connection diagram for the AD7927.
In this setup, the AGND pin is connected to the analog ground
plane of the system. In Figure 11, REF
decoupled 2.5 V supply from a reference source, the AD780, to
provide an analog input range of 0 V to 2.5 V (if RANGE bit is 1)
or 0 V to 5 V (if RANGE bit is 0). Although the AD7927 is con­nected to a AV
microprocessor. The V
the same 3 V supply of the microprocessor to allow a 3 V logic
interface (see the Digital Inputs section). The conversion result is

of 5 V, the serial interface is connected to a 3 V

DD

pin of the AD7927 is connected to

DRIVE

output in a 16-bit word. This 16-bit data stream consists of one

REV. 0

R3

R2

V

R1 ⴝ R2 ⴝ R3 ⴝ R4

Figure 10. Handling Bipolar Signals

is connected to a

IN

R4

R1

AD7927

VIN0

V

7

IN

DOUT

TWOS

COMPLEMENT

+REF

IN

REF

IN

–REF

IN

DSP/␮P

(= 2 ⴛ REF

(= 0V)

011…111

)

IN

000…000

100…000

leading zero, three address bits indicating which channel the

IN

conversion result corresponds to, followed by the 12 bits of
conversion data. For applications where power consumption is
of concern, the power-down modes should be used between
conversions or bursts of several conversions to improve power
performance. (See the Modes of Operation section.)

Figure 11. Typical Connection Diagram

–13–

AD7927

Analog Input Selection

Any one of eight analog input channels may be selected for
conversion by programming the multiplexer with the address bits
ADD2 though ADD0 in the Control Register. The channel con­figurations are shown in Table II.

The AD7927 may also be configured to automatically cycle through
a number of channels as selected. The sequencer feature is
accessed via the SEQ and SHADOW bits in the Control Register
(see Table IV). The AD7927 can be programmed to continuously
convert on a selection of channels in ascending order. The analog
input channels to be converted on are selected through program­ming the relevant bits in the Shadow Register (see Table V).
The next serial transfer will then act on the sequence programmed
by executing a conversion on the lowest channel in the selection.
The next serial transfer will result in the conversion on the next
highest channel in the sequence, and so on.

It is not necessary to write to the Control Register once a sequencer
operation has been initiated. The WRITE bit must be set to
zero or the DIN line tied low to ensure that the Control Register
is not accidently overwritten, or the sequence operation inter­rupted. If the Control Register is written to at any time during
the sequence, the user must ensure that the SEQ and SHADOW
bits are set to 1,0 to avoid interrupting the automatic conversion
sequence. This pattern will continue until such time as the AD7927
is written to and the SEQ and SHADOW bits are configured with
any bit combination except 1,0. On completion of the sequence,
the AD7927 sequencer will return to the first selected channel
in the Shadow Register and commence the sequence again.

Rather than selecting a particular sequence of channels, a number
of consecutive channels beginning with Channel 0 may also be
programmed via the Control Register alone without needing to
write to the Shadow Register. This is possible if the SEQ and
SHADOW bits are set to 1,1. The channel address bits ADD2
through ADD0 will then determine the final channel in the con­secutive sequence. The next conversion will be on Channel 0,
then Channel 1, and so on until the channel selected via the ad­dress bits ADD2 through ADD0 is reached. The cycle will begin
again on the next serial transfer provided the WRITE bit is set
to low, or if high, that the SEQ and SHADOW bits are set to
1,0; then the ADC will continue its preprogrammed automatic
sequence uninterrupted.

Regardless of which channel selection method is used, the 16-bit
word output from the AD7927 during each conversion will
always contain one leading zero, three channel address bits
that the conversion result corresponds to, followed by the 12-bit
conversion result. (See the Serial Interface section.)

Digital Inputs

The digital inputs applied to the AD7927 are not limited by the
maximum ratings that limit the analog inputs. Instead, the digital
inputs applied can go to 7 V and are not restricted by the AV

DD

+ 0.3 V limit as on the analog inputs.
Another advantage of SCLK, DIN, and CS not being restricted

by the AV

+ 0.3 V limit is that possible power supply sequencing

DD

issues are avoided. If CS, DIN, or SCLK are applied before

there is no risk of latch-up as there would be on the analog

AV

DD,

inputs if a signal greater than 0.3 V was applied prior to AV

V

DRIVE

The AD7927 also has the V
at which the serial interface operates. V

DRIVE

feature. V

controls the voltage

DRIVE

allows the ADC

DRIVE

DD

.

to easily interface to both 3 V and 5 V processors. For example,
if the AD7927 were operated with an AV

of 5 V, the V

DD

DRIVE

pin could be powered from a 3 V supply. The AD7927 has a
larger dynamic range with an AV

of 5 V while still being

DD

able to interface to 3 V processors. Care should be taken to
ensure V

does not exceed AVDD by more than 0.3 V. (See

DRIVE

Absolute Maximum Ratings.)

The Reference

An external reference source should be used to supply the 2.5 V
reference to the AD7927. Errors in the reference source will result
in gain errors in the AD7927 transfer function and will add to the
specified full-scale errors of the part. A capacitor of at least 0.1 mF
should be placed on the REF

pin. Suitable reference sources for

IN

the AD7927 include the AD780, REF 193, and the AD1582.

If 2.5 V is applied to the REF

pin, the analog input range can

IN

be either 0 V to 2.5 V or 0 V to 5 V, depending on the setting of
the RANGE bit in the Control Register.

MODES OF OPERATION

The AD7927 has a number of different modes of operation,
which are designed to provide flexible power management options.
These options can be chosen to optimize the power dissipation/
throughput rate ratio for differing application requirements. The
mode of operation of the AD7927 is controlled by the power
management bits, PM1 and PM0, in the Control Register, as
detailed in Table III. When power supplies are first applied to
the AD7927, care should be taken to ensure that the part is
placed in the required mode of operation. (See the Powering
Up the AD7927 section.)

Normal Mode (PM1 = PM0 = 1)

This mode is intended for the fastest throughput rate perfor­mance as the user does not have to worry about any power-up
times with the AD7927 remaining fully powered at all times.
Figure 12 shows the general diagram of the operation of the
AD7927 in this mode.

The conversion is initiated on the falling edge of CS and the track
and hold will enter hold mode as described in the Serial Interface
section. The data presented to the AD7927 on the DIN line during
the first 12 clock cycles of the data transfer are loaded into the
Control Register (provided WRITE bit is 1). If data is to be
written to the Shadow Register (SEQ = 0, SHADOW = 1 on
previous write), data presented on the DIN line during the first
16 SCLK cycles is loaded into the Shadow Register. The part
will remain fully powered up in Normal mode at the end of the
conversion as long as PM1 and PM0 are set to 1 in the write
transfer during that conversion. To ensure continued operation
in Normal mode, PM1 and PM0 are both loaded with 1 on every
data transfer. Sixteen serial clock cycles are required to complete
the conversion and access the conversion result. The track and
hold will go back into track on the 14th SCLK falling edge. CS
may then idle high until the next conversion or may idle low until
sometime prior to the next conversion (effectively idling CS low).

For specified performance, the throughput rate should not exceed
200 kSPS, which means there should be no less than 5 ms between
consecutive falling edges of CS when converting. The actual
frequency of SCLK used will determine the duration of the
conversion within this 5 ms cycle; however, once a conversion is
complete and CS has returned high, a minimum of the quiet
time, t

, must elapse before bringing CS low again to initiate

quiet

another conversion.

REV. 0–14–

AD7927

CS

SCLK

DOUT

DIN

NOTES

1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES

2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES

1

1 LEADING ZERO + 3 CHANNEL IDENTIFIER BITS

+ CONVERSION RESULT

DATA IN TO CONTROL REGISTER/

SHADOW REGISTER

12

16

Figure 12. Normal Mode Operation

Full Shutdown (PM1 = 1, PM0 = 0)

In this mode, all internal circuitry on the AD7927 is powered down.
The part retains information in the Control Register during full
shutdown. The AD7927 remains in full shutdown until the power
management bits in the Control Register, PM1 and PM0, are
changed.

If a write to the Control Register occurs while the part is in full
shutdown, with the power management bits changed to PM0 =
PM1 = 1, Normal Mode, the part will begin to power up on the
CS rising edge. The track and hold that was in hold while the
part was in full shutdown will return to track on the 14th SCLK
falling edge. A full 16 SCLK transfer must occur to ensure the
Control Register contents are updated; however, the DOUT
line will not be driven during this wake-up transfer.

To ensure that the part is fully powered up, t

POWER UP

should have

elapsed before the next CS falling edge; otherwise, invalid data

will be read if a conversion is initiated before this time. Figure 13
shows the general diagram for this sequence.

Auto Shutdown (PM1 = 0, PM0 = 1)

In this mode, the AD7927 automatically enters shutdown at the
end of each conversion when the Control Register is updated. When
the part is in shutdown, the track and hold is in Hold Mode.
Figure 14 shows the general diagram of the operation of the
AD7927 in this mode. In Shutdown Mode all internal circuitry on
the AD7927 is powered down. The part retains information in
the Control Register during shutdown. The AD7927 remains in
shutdown until the next CS falling edge it receives. On this CS
falling edge, the track and hold that was in hold while the part
was in shutdown will return to track. Wake-up time from auto
shutdown is 1 ms maximum, and the user should ensure that
1 ms has elapsed before attempting a valid conversion. When
running the AD7927 with a 20 MHz clock, one dummy 16 SCLK
transfer should be sufficient to ensure the part is fully powered
up. During this dummy transfer the contents of the Control
Register should remain unchanged; therefore the WRITE bit
should be 0 on the DIN line.

Depending on the SCLK frequency used, this dummy transfer
may affect the achievable throughput rate of the part, with every
other data transfer being a valid conversion result. If, for example,
the maximum SCLK frequency of 20 MHz was used, the auto
shutdown mode could be used at the full throughput rate of
200 kSPS without affecting the throughput rate at all. Only a
portion of the cycle time is taken up by the conversion time and the
dummy transfer for wake-up.

PA R T IS IN FULL
SHUTDOWN

CS

SCLK

DOUT

DIN

CS

SCLK

DOUT

PA RT BEGINS TO POWER UP ON
CS RISING EDGE AS PM1 = PM0 = 1

1141611416

DATA IN TO CONTROL REGISTER

CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS. PM1 = 1, PM0 = 1

THE PART IS FULLY POWERED UP
ONCE

t

POWER UP

t

12

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

DATA IN TO CONTROL REGISTER/SHADOW REGISTER

TO KEEP THE PART IN NORMAL MODE, LOAD
PM1 = PM0 = 1 IN CONTROL REGISTER

HAS ELAPSED

Figure 13. Full Shutdown Mode Operation

PA R T ENTERS
SHUTDOWN ON CS
RISING EDGE AS
PM1 ⴝ 0, PM0 ⴝ 1

1

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

16

12

PA RT BEGINS
TO POWER
UP ON CS
FA LLING EDGE

DUMMY CONVERSION

1161

INVALID DATA

PA R T IS FULLY
POWERED UP

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

PA R T ENTERS
SHUTDOWN ON CS
RISING EDGE AS
PM1 ⴝ 0, PM0 ⴝ 1

16

1212

DIN

REV. 0

DATA IN TO CONTROL/SHADOW REGISTER

CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS, PM1 ⴝ 0, PM0 ⴝ 1

CONTROL REGISTER SHOULD NOT
CHANGE, WRITE BIT ⴝ 0

Figure 14. Auto Shutdown Mode Operation

–15–

DATA IN TO CONTROL/SHADOW REGISTER

TO KEEP PART IN THIS MODE, LOAD PM1 ⴝ 0, PM0 ⴝ 1
IN CONTROL REGISTER OR SET WRITE BIT = 0

AD7927

CS

SCLK

DUMMY CONVERSION

1

CORRECT VALUE IN CONTROL
REGISTER, VALID DATA FROM
NEXT CONVERSION, USER CAN
WRITE TO SHADOW REGISTER
IN NEXT CONVERSION

DUMMY CONVERSION

12

16

1161

16

1212

DOUT

DIN

KEEP DIN LINE TIED HIGH FOR FIRST TWO DUMMY CONVERSIONS

INVALID DATA INVALID DATA

INVALID DATA

Figure 15. To Place AD7927 into the Required Operating Mode after Supplies Are Applied

In this mode the power consumption of the part is greatly reduced
with the part entering shutdown at the end of each conversion.
When the Control Register is programmed to move into Auto
Shutdown, it does so at the end of the conversion. The user can
move the ADC in and out of the low power state by controlling
the CS signal.

Powering Up the AD7927

When supplies are first applied to the AD7927, the ADC may
power up in any of the operating modes of the part. To ensure that
the part is placed into the required operating mode, the user
should perform a dummy cycle operation as outlined in Figure 15.

The three dummy conversion operation outlined in Figure 15
must be performed to place the part into the Auto Shutdown
Mode. The first two conversions of this dummy cycle operation
are performed with the DIN line tied high, and for the third con­version of the dummy cycle operation, the user should write the
desired Control Register configuration to the AD7927 in order to
place the part into the Auto Shutdown mode. On the third CS
rising edge after the supplies are applied, the Control Register
will contain the correct information and valid data will result from
the next conversion.

Therefore, to ensure the part is placed into the correct operating
mode, when supplies are first applied to the AD7927, the user
must first issue two serial write operations with the DIN line tied
high, and on the third conversion cycle the user can then write
to the Control Register to place to part into any of the operating
modes. The user should not write to the Shadow Register until
the fourth conversion cycle after the supplies are applied to the
ADC, in order to guarantee the Control Register contains the
correct data.

If the user wishes to place the part into either the Normal or
Full Shutdown Mode, the second dummy cycle with DIN tied
high can be omitted from the three dummy conversion operation
outlined in Figure 15.

POWER VERSUS THROUGHPUT RATE

In Auto Shutdown Mode, the average power consumption of the
ADC may be reduced at any given throughput rate. The power
saving will depend on the SCLK frequency used, i.e., conversion
time. In some cases where the conversion time is quite a propor­tion of the cycle time, the throughput rate would need to be
reduced in order to take advantage of the power-down modes.
Assuming a 20 MHz SCLK is used, the conversion time is

DATA IN TO CONTROL REGISTER

CONTROL REGISTER IS LOADED ON THE FIRST
12 CLOCK EDGES

800 ns but the cycle time is 5 ms when the sampling rate is at a
maximum of 200 kSPS. If the AD7927 is placed into shutdown
for the remainder of the cycle time, then on average far less
power will be consumed in every cycle compared to leaving the
device in Normal Mode. Furthermore, Figure 16 shows how as
the throughput rate is reduced, the part remains in its shutdown
longer and the average power consumption drops accordingly
over time.

For example, if the AD7927 is operated in a continuous sampling
mode, with a throughput rate of 200 kSPS and an SCLK of
20 MHz (AV

= 5 V), and the device is placed in Auto Shutdown

DD

Mode i.e., if PM1 = 0 and PM0 = 1, then the power consumption
is calculated as follows:

The maximum power dissipation during the conversion time is

13.5 mW (I

= 2.7 mA max, AVDD = 5 V). If the power-up time

DD

from Auto Shutdown is 1 ms and the remaining conversion time
is another cycle, i.e., 800 ns, the AD7927 can be said to dissipate

13.5 mW for 1.8 ms during each conversion cycle. For the remain-
der of the conversion cycle, 3.2 ms, the part remains in Shutdown.
The AD7927 can be said to dissipate 2.5 mW for the remaining

3.2 ms of the conversion cycle. If the throughput rate is 200 kSPS,
the cycle time is 5 ms and the average power dissipated during each
cycle is (1.8/5) ¥ (13.5 mW) + (3.2/5) ¥ (2.5 mW) = 4.8616 mW.

Figure 16 shows the maximum power versus throughput rate
when using the Auto Shutdown mode with 3 V and 5 V supplies.

10

AVDD = 5V

POWER – mW

0.1

0.01
0 200

801100 140 18020 40 60 120 160

THROUGHPUT – kSPS

AV

= 3V

DD

Figure 16. Power vs. Throughput Rate

REV. 0–16–

AD7927

SERIAL INTERFACE

Figure 17 shows the detailed timing diagram for serial interfacing
to the AD7927. The serial clock provides the conversion clock
and also controls the transfer of information to and from the
AD7927 during each conversion.

The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track and hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. The conversion is also initiated at this point and will
require 16 SCLK cycles to complete. The track and hold will
go back into track on the 14th SCLK falling edge as shown in
Figure 17 at point B, except when the write is to the Shadow
Register, in which case the track and hold will not return to
track until the rising edge of CS, i.e., point C in Figure 18. On
the 16th SCLK falling edge the DOUT line will go back into
three-state. If the rising edge of CS occurs before 16 SCLKs have
elapsed, the conversion will be terminated and the DOUT line
will go back into three-state and the Control Register will not be
updated; otherwise DOUT returns to three-state on the 16th
SCLK falling edge, as shown in Figure 17. Sixteen serial clock
cycles are required to perform the conversion process and to
access data from the AD7927. For the AD7927, the 12 bits of
data are preceded by a leading zero and the three channel address
bits ADD2 to ADD0, identifying which channel the result corre­sponds to. CS going low provides the leading zero to be read in by
the microcontroller or DSP. The three remaining address bits and
data bits are then clocked out by subsequent SCLK falling edges
beginning with the first address bit ADD2, thus the first falling
clock edge on the serial clock has a leading zero provided and
also clocks out address bit ADD2. The final bit in the data
transfer is valid on the 16th falling edge, having been clocked
out on the previous (15th) falling edge.

Writing of information to the Control Register takes place on the
first 12 falling edges of SCLK in a data transfer, assuming the MSB,
i.e., the WRITE bit, has been set to 1. If the Control Register is
programmed to use the Shadow Register, then the writing of
information to the Shadow Register will take place on all 16 SCLK
falling edges in the next serial transfer as shown for example on the
AD7927 in Figure 18. Two sequence options can be programmed
in the Shadow Register. If the user does not want to program a
second sequence, then the eight LSBs should be filled with zeros.
The Shadow Register will be updated upon the rising edge of
CS and the track and hold will begin to track the first channel
selected in the sequence.

The 16-bit word read from the AD7927 will always contain a
leading zero, three channel address bits that the conversion
result corresponds to, followed by the 12-bit conversion result.

Writing Between Conversions

As outlined in the Operating Modes section, not less than 5 ms
should be left between consecutive valid conversions. However,
there is one case where this does not necessarily mean that at least
5 ms should always be left between CS falling edges. Consider the
case when writing to the AD7927 to power it up from shutdown
prior to a valid conversion. The user must write to the part to tell
it to power up before it can convert successfully. Once the serial
write to power up has finished, one may wish to perform the con­version as soon as possible and not have to wait a further 5 ms
before bringing CS low for the conversion. In this case, as long
as there is a minimum of 5 ms between each valid conversion, then
only the quiet time between the CS rising edge at the end of the
write to power up and the next CS falling edge for a valid con­version needs to be met. Figure 19 illustrates this point. Note

SCLK

DOUT

DIN

SCLK

DOUT

DIN

CS

CS

t

t

2

12345 13141516

t

3

THREE­STATE

ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0

3 IDENTIFICATION BITS

ZERO

t

9

WRITE SEQ DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC

CONVERT

t

6

t

4

t

7

t

10

B

t

5

Figure 17. Serial Interface Timing Diagram

t

t

2

12345 13141516

t

3

THREE­STATE

ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0

3 IDENTIFICATION BITS

t

ZERO

9

VIN0VIN1VIN2VIN3VIN4VIN5V

SEQUENCE 1 SEQUENCE 2

CONVERT

t

6

t

4

t

t

7

t

10

5

5VIN6VIN7

IN

Figure 18. Writing to Shadow Register Timing Diagram

t

QUIET

t

11

t

8

THREE­STATE

C

t

11

t

8

THREE­STATE

REV. 0

–17–

AD7927

CS

SCLK

t

5␮s MIN

CYCLE

116 116 116

t

QUIET

MIN

DOUT

DIN

VA LID DATA

Figure 19. General Timing Diagram

that when writing to the AD7927 between these valid conversions,
the DOUT line will not be driven during the extra write operation,
as shown in Figure 19.

It is critical that an extra write operation as outlined above is
never issued between valid conversions when the AD7927 is
executing through a sequence function, as the falling edge of CS
in the extra write would move the mux on to the next channel in
the sequence. This means when the next valid conversion takes
place, a channel result would have been missed.

MICROPROCESSOR INTERFACING

The serial interface on the AD7927 allows the part to be directly
connected to a range of many different microprocessors. This
section explains how to interface the AD7927 with some of the
more common microcontroller and DSP serial interface protocols.

AD7927 to TMS320C541

The serial interface on the TMS320C541 uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices like the AD7927. The
CS input allows easy interfacing between the TMS320C541 and
the AD7927 without any glue logic required. The serial port of
the TMS320C541 is set up to operate in burst mode with internal
CLKX0 (TX serial clock on serial port 0) and FSX0 (TX frame
sync from serial port 0). The serial port control register (SPC)
must have the following setup: FO = 0, FSM = 1, MCM = 1, and
TXM = 1. The connection diagram is shown in Figure 20. It
should be noted that for signal processing applications, it is impera­tive that the frame synchronization signal from the TMS320C541
provides equidistant sampling. The V

pin of the AD7927

DRIVE

takes the same supply voltage as that of the TMS320C541. This
allows the ADC to operate at a higher voltage than the serial
interface, i.e., TMS320C541, if necessary.

AD7927

*

SCLK

DOUT

DIN

CS

V

DRIVE

TMS320C541*

CLKX

CLKR
DR

DT

FSX

FSR

VA LID DATA

POWER-UP

AD7927 to ADSP-21xx

The ADSP-21xx family of DSPs are interfaced directly to the
AD7927 without any glue logic required. The V

DRIVE

pin of
the AD7927 takes the same supply voltage as that of the
ADSP-218x. This allows the ADC to operate at a higher voltage
than the serial interface, i.e., ADSP-218x, if necessary.

The SPORT0 Control Register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data-Words
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0
ITFS = 1

The connection diagram is shown in Figure 21. The ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in Alter­nate Framing Mode and the SPORT Control Register is set up as
described. The frame synchronization signal generated on the TFS
is tied to CS, and as with all signal processing applications equi­distant sampling is necessary. However, in this example the timer
interrupt is used to control the sampling rate of the ADC, and
under certain conditions equidistant sampling may not be achieved.

AD7927

*

SCLK

DOUT

CS

DIN

V

DRIVE

*ADDITIONAL PINS REMOVED FOR CLARITY

ADSP-218x*

SCLK

DR

RFS

TFS

DT

V

DD

Figure 21. Interfacing to the ADSP-218x

*ADDITIONAL PINS REMOVED FOR CLARITY

Figure 20. Interfacing to the TMS320C541

V

DD

REV. 0–18–

AD7927

The Timer register, for instance, is loaded with a value that will
provide an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and therefore
the reading of data. The frequency of the serial clock is set in the
SCLKDIV Register. When the instruction to transmit with TFS
is given (i.e., AX0 = TX0), the state of the SCLK is checked.
The DSP will wait until the SCLK has gone High, Low, and
High before transmission will start. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or
near the rising edge of SCLK, then the data may be transmitted
or it may wait until the next clock edge.

For example, if the ADSP-2189 had a 20 MHz crystal such that
it had a master clock frequency of 40 MHz, then the master cycle
time would be 25 ns. If the SCLKDIV Register is loaded with the
value 3, then an SCLK of 5 MHz is obtained and eight master
clock periods will elapse for every one SCLK period. Depending
on the throughput rate selected, if the Timer Registers are loaded
with the value, say 803, 100.5 SCLKs will occur between inter­rupts and subsequently between transmit instructions. This
situation will result in non-equidistant sampling as the transmit
instruction is occurring on a SCLK edge. If the number of
SCLKs between interrupts is a whole integer figure of N, then
equidistant sampling will be implemented by the DSP.

AD7927 to DSP563xx

The connection diagram in Figure 22 shows how the AD7927
can be connected to the ESSI (Synchronous Serial Interface) of
the DSP563xx family of DSPs from Motorola. Each ESSI (two on
board) is operated in Synchronous mode (SYN bit in CRB = 1)
with internally generated word length frame sync for both Tx
and Rx (bits FSL1 = 0 and FSL0 = 0 in CRB). Normal operation
of the ESSI is selected by making MOD = 0 in the CRB. Set the
word length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA.
The FSP bit in the CRB should be set to 1 so the frame sync is
negative. It should be noted that for signal processing applica­tions, it is imperative that the frame synchronization signal from
the DSP563xx provides equidistant sampling.

In the example shown in Figure 22, the serial clock is taken from
the ESSI so the SCK0 pin must be set as an output, SCKD = 1.
The V

pin of the AD7927 takes the same supply voltage as

DRIVE

that of the DSP563xx. This allows the ADC to operate at a higher
voltage than the serial interface, i.e., DSP563xx, if necessary.

AD7927

*

SCLK

DOUT

CS

DIN

V

DRIVE

*ADDITIONAL PINS REMOVED FOR CLARITY

DSP563xx*

SCK

SRD

STD

SC2

V

DD

Figure 22. Interfacing to the DSP563xx

APPLICATION HINTS
Grounding and Layout

The AD7927 has very good immunity to noise on the power
supplies as can be seen by the PSRR vs. Supply Ripple Frequency
plot, TPC 3. However, care should still be taken with regard to
grounding and layout.

The printed circuit board that houses the AD7927 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the use
of ground planes that can be separated easily. A minimum etch
technique is generally best for ground planes as it gives the best
shielding. All three AGND pins of the AD7927 should be sunk
in the AGND plane. Digital and analog ground planes should be
joined at only one place. If the AD7927 is in a system where
multiple devices require an AGND to DGND connection, the
connection should still be made at one point only, a star ground
point that should be established as close as possible to the AD7927.

Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed to
run under the AD7927 to avoid noise coupling. The power supply
lines to the AD7927 should use as large a trace as possible to
provide low impedance paths and reduce the effects of glitches
on the power supply line. Fast switching signals, like clocks,
should be shielded with digital ground to avoid radiating noise
to other sections of the board, and clock signals should never be
run near the analog inputs. Avoid crossover of digital and analog
signals. Traces on opposite sides of the board should run at right
angles to each other. This will reduce the effects of feedthrough
through the board. A microstrip technique is by far the best but
is not always possible with a double-sided board. In this technique,
the component side of the board is dedicated to ground planes
while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should be
decoupled with 10 mF tantalum in parallel with 0.1 mF capacitors
to AGND. To achieve the best from these decoupling components,
they must be placed as close as possible to the device, ideally
right up against the device. The 0.1 mF capacitors should have
low Effective Series Resistance (ESR) and Effective Series Induc­tance (ESI), such as the common ceramic types or surface mount
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.

Evaluating the AD7927 Performance

The recommended layout for the AD7927 is outlined in the
evaluation board for the AD7927. The evaluation board package
includes a fully assembled and tested evaluation board, docu­mentation, and software for controlling the board from the
PC via the Eval-Board Controller. The Eval-Board Controller
can be used in conjunction with the AD7927 Evaluation board
as well as many other Analog Devices evaluation boards ending
in the CB designator to demonstrate/evaluate the ac and dc
performance of the AD7927.

The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the AD7927.
The software and documentation are on a CD shipped with the
evaluation board.

REV. 0

–19–

AD7927

OUTLINE DIMENSIONS

20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

6.60

6.50

6.40

PIN 1

0.15

0.05

COPLANARITY

0.10

20

1

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AC

0.65

BSC

11

10

1.20
MAX

SEATING

PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09

C03088–0–1/03(0)

8ⴗ
0ⴗ

0.75

0.60

0.45

–20–

PRINTED IN U.S.A.

REV. 0