Datasheet AD7918 Datasheet (ANALOG DEVICES)

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8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs

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FEATURES

Fast throughput rate: 1 MSPS Specified for AV Low power

6.0 mW max at 1 MSPS with 3 V supply

13.5 mW max at 1 MSPS with 5 V supply Eight (single-ended) inputs with sequencer Wide input bandwidth

AD7928, 70 dB min SINAD at 50 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI®/QSPI™/

MICROWIRE™/DSP compatible Shutdown mode: 0.5 μA max 20-lead TSSOP package

GENERAL DESCRIPTION

The AD7908/AD7918/AD7928 are, respectively, 8-bit, 10-bit, and 12-bit, high speed, low power, 8-channel, successive approximation ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 8 MHz.

The conversion process and data acquisition are controlled using CS

and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of There are no pipeline delays associated with the part.

of 2.7 V to 5.25 V

and conversion is also initiated at this point.

with Sequencer in 20-Lead TSSOP

AD7908/AD7918/AD7928

FUNCTIONAL BLOCK DIAGRAM

REF

VIN0

•

• 7

I/P

MUX

AD7908/AD7918/AD7928

PRODUCT HIGHLIGHTS

1. High Throughput with Low Power Consumption. The AD7908/

AD7918/AD7928 offer up to 1 MSPS throughput rates. At the maximum throughput rate with 3 V supplies, the AD7908/ AD7918/AD7928 dissipate just 6 mW of power maximum.

2. Eight Single-Ended Inputs with a Channel Sequencer.

A sequence of channels can be selected, through which the ADC cycles and converts on.

T/H

SEQUENCER

APPROXIMATI ON

CONTROL LO GIC

GND

Figure 1.

8-/10-/12-BI T

SUCCESSIVE

ADC

SCLK

DOUT

DIN

DRIVE

03089-001

The AD7908/AD7918/AD7928 use advanced design techniques to achieve very low power dissipation at maximum throughput rates. At maximum throughput rates, the AD7908/AD7918/AD7928 consume 2 mA maximum with 3 V supplies; with 5 V supplies, the

3. Single-Supply Operation with V

AD7918/AD7928 operate from a single 2.7 V to 5.25 V supply. The V

function allows the serial interface to connect directly

DRIVE

to either 3 V or 5 V processor systems independent of AV

current consumption is 2.7 mA maximum.

4. Flexible Power/Serial Clock Speed Management. The conversion

Through the configuration of the control register, the analog input range for the part can be selected as 0 V to REF REF

, with either straight binary or twos complement output

or 0 V to 2 ×

coding. The AD7908/AD7918/AD7928 each feature eight singleended analog inputs with a channel sequencer to allow a

rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. The parts also feature various shutdown modes to maximize power efficiency at lower throughput rates. Current consumption is

0.5 μA max when in full shutdown.

preprogrammed selection of channels to be converted sequentially.

5. No Pipeline Delay. The parts feature a standard successive

The conversion time for the AD7908/AD7918/AD7928 is determined by the SCLK frequency, which is also used as the

approximation ADC with accurate control of the sampling instant via a

input and once off conversion control.

master clock to control the conversion.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Function. The AD7908/

DRIVE

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AD7908/AD7918/AD7928

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Features .............................................................................................. 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AD7908 Specifications ................................................................. 3

AD7918 Specifications ................................................................. 5

AD7928 Specifications ................................................................. 7

Timing Specifications .................................................................. 9

Absolute Maximum Ratings .......................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Terminology .................................................................................... 12

Typical Performance Characteristics ........................................... 13

Performance Curves ................................................................... 13

Control Register .............................................................................. 15

Sequencer Operation ................................................................. 16

SHADOW Register .................................................................... 17

Circuit Information .................................................................... 18

Converter Operation .................................................................. 18

ADC Transfer Function ............................................................. 19

Handling Bipolar Input Signals ................................................ 19

Typical Connection Diagram ................................................... 19

Modes of Operation ................................................................... 21

Power vs. Throughput Rate ....................................................... 23

Serial Interface ............................................................................ 23

Microprocessor Interfacing ....................................................... 24

Application Hints ....................................................................... 27

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 28

REVISION HISTORY

11/08—Rev. B to Rev. C

Changes to ESD Parameter, Table 5 ............................................. 10

6/06—Rev. A to Rev. B

Updated Format .................................................................. Universal

Changes to Reference Section ....................................................... 21

9/03—Rev. 0 to Rev. A

Changes to Figure 3 ........................................................................ 15

Changes to Reference section ....................................................... 18

Rev. C | Page 2 of 28

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AD7908/AD7918/AD7928

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SPECIFICATIONS

AD7908 SPECIFICATIONS

AVDD = V

Table 1.

Parameter B Version1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, f

Signal-to-(Noise + Distortion) (SINAD)2 49 dB min Signal-to-Noise Ratio (SNR)2 49 dB min Total Harmonic Distortion (THD)2 −66 dB max Peak Harmonic or Spurious Noise (SFDR)2 −64 dB max Intermodulation Distortion (IMD)2 fa = 40.1 kHz, fb = 41.5 kHz

Second-Order Terms −90 dB typ

Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation2 −85 dB typ fIN = 400 kHz Full Power Bandwidth 8.2 MHz typ @ 3 dB

1.6 MHz typ @ 0.1 dB DC ACCURACY2

Resolution 8 Bits Integral Nonlinearity ±0.2 LSB max Differential Nonlinearity ±0.2 LSB max Guaranteed no missed codes to 8 bits 0 V to REFIN Input Range Straight binary output coding

Offset Error ±0.5 LSB max

Offset Error Match ±0.05 LSB max

Gain Error ±0.2 LSB max

Gain Error Match ±0.05 LSB max 0 V to 2 × REFIN Input Range

Positive Gain Error ±0.2 LSB max

Positive Gain Error Match ±0.05 LSB max

Zero Code Error ±0.5 LSB max

Zero Code Error Match ±0.1 LSB max

Negative Gain Error ±0.2 LSB max

Negative Gain Error Match ±0.05 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to REFIN V RANGE bit set to 1 0 to 2 × REFIN V

DC Leakage Current ±1 μA max Input Capacitance 20 pF typ

REFERENCE INPUT

REFIN Input Voltage 2.5 V ±1% specified performance DC Leakage Current ±1 μA max REFIN Input Impedance 36 kΩ typ f

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V or V Input Capacitance, C

= 2.7 V to 5.25 V, REFIN = 2.5 V, f

DRIVE

0.7 × V

INH

0.3 × V

INL

10 pF max

= 20 MHz, TA = T

SCLK

V min

DRIVE

V max

DRIVE

Rev. C | Page 3 of 28

MIN

to T

, unless otherwise noted.

MAX

−REF twos complement output coding

RANGE bit set to 0, AV

5.25 V

SAMPLE

= 20 MHz

SCLK

to +REFIN biased about REFIN with

= 4.75 V to

DD/VDRIVE

= 1 MSPS

DRIVE

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AD7908/AD7918/AD7928

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Parameter B Version1 Unit Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, VOH V Output Low Voltage, VOL 0.4 V max I Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance3 10 pF max

Output Coding Straight (natural) binary Coding bit set to 1 Twos complement Coding bit set to 0 CONVERSION RATE

Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz

Track-and-Hold Acquisition Time 300 ns max Sine wave input

300 ns max Full-scale step input

Throughput Rate 1 MSPS max See Serial Interface section POWER REQUIREMENTS

AVDD 2.7/5.25 V min/max

2.7/5.25 V min/max

DRIVE

Digital inputs = 0 V or V

Normal Mode (Static) 600 μA typ AVDD = 2.7 V to 5.25 V, SCLK On or Off Normal Mode (Operational) 2.7 mA max AVDD = 4.75 V to 5.25 V, f 2 mA max AVDD = 2.7 V to 3.6 V, f Using Auto Shutdown Mode 960 μA typ f

0.5 μA max (Static) Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ)

Power Dissipation4

Normal Mode (Operational) 13.5 mW max AVDD = 5 V, f 6 mW max AVDD = 3 V, f Auto Shutdown Mode (Static) 2.5 μW max AVDD = 5 V

1.5 μW max AVDD = 3 V Full Shutdown Mode 2.5 μW max AVDD = 5 V

1.5 μW max AVDD = 3 V

Temperature ranges as follows: B version: −40°C to +85°C.

See Terminology section.

Sample tested @ 25°C to ensure compliance.

See Power vs. Throughput Rate section.

− 0.2 V min I

DRIVE

= 200 μA, AVDD = 2.7 V to 5.25 V

SOURCE

= 200 μA

SINK

DRIVE

SCLK

= 20 MHz

SCLK

= 250 kSPS

SAMPLE

= 20 MHz

SCLK

= 20 MHz

SCLK

= 20 MHz

Rev. C | Page 4 of 28

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AD7908/AD7918/AD7928

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AD7918 SPECIFICATIONS

AVDD = V

Table 2.

Parameter B Version1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, f

Signal-to-(Noise + Distortion) (SINAD)2 61 dB min Signal-to-Noise Ratio (SNR)2 61 dB min Total Harmonic Distortion (THD)2 −72 dB max Peak Harmonic or Spurious Noise (SFDR)2 −74 dB max Intermodulation Distortion (IMD)2 fa = 40.1 kHz, fb = 41.5 kHz

Second-Order Terms −90 dB typ

Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation2 −85 dB typ fIN = 400 kHz Full Power Bandwidth 8.2 MHz typ @ 3 dB

1.6 MHz typ @ 0.1 dB DC ACCURACY2

Resolution 10 Bits Integral Nonlinearity ±0.5 LSB max Differential Nonlinearity ±0.5 LSB max Guaranteed no missed codes to 10 bits 0 V to REFIN Input Range Straight binary output coding

Offset Error ±2 LSB max

Offset Error Match ±0.2 LSB max

Gain Error ±0.5 LSB max

Gain Error Match ±0.2 LSB max 0 V to 2 × REFIN Input Range

Positive Gain Error ±0.5 LSB max

Positive Gain Error Match ±0.2 LSB max

Zero Code Error ±2 LSB max

Zero Code Error Match ±0.2 LSB max

Negative Gain Error ±0.5 LSB max

Negative Gain Error Match ±0.2 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to REFIN V RANGE bit set to 1 0 to 2 × REFIN V RANGE bit set to 0, AVDD/V DC Leakage Current ±1 μA max Input Capacitance 20 pF typ

REFERENCE INPUT

REFIN Input Voltage 2.5 V ±1% specified performance DC Leakage Current ±1 μA max REFIN Input Impedance 36 kΩ typ f

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V or V Input Capacitance, C

= 2.7 V to 5.25 V, REFIN = 2.5 V, f

DRIVE

0.7 × V

INH

0.3 × V

INL

10 pF max

= 20 MHz, TA = T

SCLK

V min

DRIVE

V max

DRIVE

MIN

to T

, unless otherwise noted.

MAX

to +REFIN biased about REFIN with twos

−REF

complement output coding

= 1 MSPS

SAMPLE

= 20 MHz

SCLK

= 4.75 V to 5.25 V

DRIVE

Rev. C | Page 5 of 28

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AD7908/AD7918/AD7928

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Parameter B Version1 Unit Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, VOH V Output Low Voltage, VOL 0.4 V max I Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance3 10 pF max

Output Coding Straight (natural) binary Coding bit set to 1 Twos complement Coding bit set to 0 CONVERSION RATE

Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz

Track-and-Hold Acquisition Time 300 ns max Sine wave input

300 ns max Full-scale step input

Throughput Rate 1 MSPS max See Serial Interface section POWER REQUIREMENTS

AVDD 2.7/5.25 V min/max

2.7/5.25 V min/max

DRIVE

Digital inputs = 0 V or V

Normal Mode (Static) 600 μA typ AVDD = 2.7 V to 5.25 V, SCLK on or off Normal Mode (Operational) 2.7 mA max AVDD = 4.75 V to 5.25 V, f 2 mA max AVDD = 2.7 V to 3.6 V, f Using Auto Shutdown Mode 960 μA typ f

0.5 μA max (Static) Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ)

Power Dissipation4

Normal Mode (Operational) 13.5 mW max AVDD = 5 V, f 6 mW max AVDD = 3 V, f Auto Shutdown Mode (Static) 2.5 μW max AVDD = 5 V

1.5 μW max AVDD = 3 V Full Shutdown Mode 2.5 μW max AVDD = 5 V

1.5 μW max AVDD = 3 V

Temperature ranges as follows: B version: –40°C to +85°C.

See Terminology section.

Sample tested @ 25°C to ensure compliance.

See Power vs. Throughput Rate section.

− 0.2 V min I

DRIVE

= 200 μA, AVDD = 2.7 V to 5.25 V

SOURCE

= 200 μA

SINK

DRIVE

SCLK

= 20 MHz

SCLK

= 250 kSPS

SAMPLE

= 20 MHz

SCLK

= 20 MHz

SCLK

= 20 MHz

Rev. C | Page 6 of 28

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AD7908/AD7918/AD7928

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AD7928 SPECIFICATIONS

= V

VDD

Table 3.

Parameter B Version1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, f

Signal-to-(Noise + Distortion) (SINAD)2 70 dB min @ 5 V 69 dB min @ 3 V typically 70 dB Signal-to-Noise Ratio (SNR)2 70 dB min Total Harmonic Distortion (THD)2 −77 dB max @ 5 V typically −84 dB

−73 dB max @ 3 V typically −77 dB Peak Harmonic or Spurious Noise −78 dB max @ 5 V typically −86 dB

(SFDR)2 −76 dB max @ 3 V typically −80 dB

Intermodulation Distortion (IMD)2 fa = 40.1 kHz, fb = 41.5 kHz

Second-Order Terms −90 dB typ

Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation2 −85 dB typ fIN = 400 kHz Full Power Bandwidth 8.2 MHz typ @ 3 dB

1.6 MHz typ @ 0.1 dB DC ACCURACY2

Resolution 12 Bits Integral Nonlinearity ±1 LSB max Differential Nonlinearity −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits 0 V to REFIN Input Range Straight binary output coding

Offset Error ±8 LSB max Typically ±0.5 LSB

Offset Error Match ±0.5 LSB max

Gain Error ±1.5 LSB max

Gain Error Match ±0.5 LSB max 0 V to 2 × REFIN Input Range

Positive Gain Error ±1.5 LSB max

Positive Gain Error Match ±0.5 LSB max

Zero Code Error ±8 LSB max Typically ±0.8 LSB

Zero Code Error Match ±0.5 LSB max

Negative Gain Error ±1 LSB max

Negative Gain Error Match ±0.5 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to REFIN V RANGE bit set to 1 0 to 2 × REFIN V RANGE bit set to 0, AVDD/V DC Leakage Current ±1 μA max Input Capacitance 20 pF typ

REFERENCE INPUT

REFIN Input Voltage 2.5 V ±1% specified performance DC Leakage Current ±1 μA max REFIN Input Impedance 36 kΩ typ f

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V or V Input Capacitance, C

= 2.7 V to 5.25 V, REFIN = 2.5 V, f

DRIVE

0.7 × V

INH

0.3 × V

INL

10 pF max

= 20 MHz, TA = T

SCLK

V min

DRIVE

V max

DRIVE

MIN

to T

, unless otherwise noted.

MAX

to +REFIN biased about REFIN with twos

−REF

complement output coding

= 1 MSPS

SAMPLE

= 20 MHz

SCLK

= 4.75 V to 5.25 V

DRIVE

Rev. C | Page 7 of 28

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Parameter B Version1 Unit Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, VOH V Output Low Voltage, VOL 0.4 V max I Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance3 10 pF max

Output Coding Straight (natural) binary Coding bit set to 1 Twos complement Coding bit set to 0 CONVERSION RATE

Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz

Track-and-Hold Acquisition Time 300 ns max Sine wave input

300 ns max Full-scale step input

Throughput Rate 1 MSPS max See Serial Interface section POWER REQUIREMENTS

AVDD 2.7/5.25 V min/max

2.7/5.25 V min/max

DRIVE

Digital inputs = 0 V or V

0.5 μA max (Static) Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ)

Power Dissipation4

Normal Mode (Operational) 13.5 mW max AVDD = 5 V, f 6 mW max AVDD = 3 V, f Auto Shutdown Mode (Static) 2.5 μW max AVDD = 5 V

1.5 μW max AVDD = 3 V Full Shutdown Mode 2.5 μW max AVDD = 5 V

1.5 μW max AVDD = 3 V

Temperature ranges as follows: B Version: −40°C to +85°C.

See Terminology section.

Sample tested @ 25°C to ensure compliance.

See Power vs. Throughput Rate section.

− 0.2 V min I

DRIVE

= 200 μA, AVDD = 2.7 V to 5.25 V

SOURCE

= 200 μA

SINK

DRIVE

SCLK

= 20 MHz

SCLK

= 250 kSPS

SAMPLE

= 20 MHz

SCLK

= 20 MHz

SCLK

= 20 MHz

Rev. C | Page 8 of 28

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TIMING SPECIFICATIONS

AVDD = 2.7 V to 5.25 V, V

Table 4.

Limit at T

Parameter AVDD = 3 V AVDD = 5 V Unit Description

10 10 kHz min

SCLK

20 20 MHz max t

16 × t

CONVER T

50 50 ns min

QUIET

40 40 ns max Data access time after SCLK falling edge

t5 0.4 × t t6 0.4 × t

SCLK

10 10 ns min 35 30 ns max

SCLK

t7 10 10 ns min SCLK to DOUT valid hold time

15/45 15/35 ns min/max SCLK falling edge to DOUT high impedance

t9 10 10 ns min DIN setup time prior to SCLK falling edge t

5 5 ns min DIN hold time after SCLK falling edge

t11

20 20 ns min

t12 1 1 μs max Power-up time from full power-down/auto shutdown mode

Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 2.

The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.

Mark/space ratio for the SCLK input is 40/60 to 60/40.

Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × V

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.

≤ AVDD, REFIN = 2.5 V, TA = T

DRIVE

, T

MIN

16 × t

0.4 × t

AD7908/AD7918/AD7928

MAX

SCLK

ns min SCLK low pulse width

SCLK

ns min SCLK high pulse width

SCLK

MIN

to T

, unless otherwise noted.1

MAX

Minimum quiet time required between CS

next conversion

to SCLK setup time

Delay from CS

SCLK falling edge to CS high

until DOUT three-state disabled

DRIVE

rising edge and start of

200µA

OUTPUT

Figure 2. Load Circuit for Digital Output Timing Specifications

50pF

200µA

1.6V

3089-002

Rev. C | Page 9 of 28

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

AVDD to AGND −0.3 V to +7 V V

to AGND −0.3 V to AVDD + 0.3 V

DRIVE

Analog Input Voltage to AGND −0.3 V to AVDD + 0.3 V Digital Input Voltage to AGND −0.3 V to +7 V Digital Output Voltage to AGND −0.3 V to AVDD + 0.3 V REFIN to AGND −0.3 V to AVDD + 0.3 V Input Current to Any Pin Except

Supplies Operating Temperature Range

Commercial (B Version) −40°C to +85°C

Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package, Power Dissipation 450 mW

θJA Thermal Impedance 143°C/W (TSSOP)

θJC Thermal Impedance 45°C/W (TSSOP) Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C ESD 1.5 kV

Transient currents of up to 100 mA do not cause SCR latch-up.

±10 mA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. C | Page 10 of 28

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 SCLK

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process of the AD7908/AD7918/AD7928.

2 DIN

Data In. Logic input. Data to be written to the control register of the AD7908/AD7918/AD7928 is provided on this input and is clocked into the register on the falling edge of SCLK (see the Control Register section).

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the

AD7908/AD7918/AD7928, and also frames the serial data transfer.

4, 8, 17, 20 AGND

Analog Ground. This is the ground reference point for all analog circuitry on the AD7908/AD7918/AD7928. All analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected together.

5, 6 AVDD

7 REFIN

Analog Power Supply Input. The AV to 2 × REF

Reference Input for the AD7908/AD7918/AD7928. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance.

16 to 9 VIN0 to VIN7

Analog Input 0 through Analog Input 7. These are eight single-ended analog input channels that are multiplexed into the on-chip track-and-hold. The analog input channel to be converted is selected by using Address Bit ADD2 through Address Bit ADD0 of the control register. The address bits, in conjunction with the SEQ and SHADOW bits, allow the sequencer to be programmed. The input range for all input channels can extend from 0 V to REF input channels must be connected to AGND to avoid noise pickup.

18 DOUT

Data Out. Logic output. The conversion result from the AD7908/AD7918/AD7928 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7908 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the eight bits of conversion data, followed by four trailing zeros, provided MSB first; the data stream from the AD7918 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of conversion data, followed by two trailing zeros, also provided MSB first; the data stream from the AD7928 consists of one leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, provided MSB first. The output coding can be selected as straight binary or twos complement via the CODING bit in the control register.

19 V

DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of the AD7908/AD7918/AD7928 operates.

SCLK

DIN

AGND

REF

AGND

VIN7

AD7908/

AD7918/

AD7928

615

TOP VIEW

(Not to Scal e)

714

813

10 11

AGND

DRIVE

DOUT

AGND

Figure 3. Pin Configuration

range for the AD7908/AD7918/AD7928 is from 2.7 V to 5.25 V. For the 0 V

range, AVDD should be from 4.75 V to 5.25 V.

or 0 V to 2 × REFIN as selected via the RANGE bit in the control register. Any unused

03089-003

Rev. C | Page 11 of 28

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TERMINOLOGY

Integral Nonlinearity Negative Gain Error Match

This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a position 1 LSB below the first code transition, and full scale, a position 1 LSB above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, AGND + 1 LSB.

Offset Error Match

This is the difference in offset error between any two channels.

Gain Error

This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (that is, REF offset error has been adjusted out.

Gain Error Match

This is the difference in gain error between any two channels.

Zero Code Error

This applies when using the twos complement output coding option, in particular to the 2 × REF to +REF midscale transition (all 0s to all 1s) from the ideal V that is, REF

Zero Code Error Match

This is the difference in zero code error between any two channels.

Positive Gain Error

This applies when using the twos complement output coding option, in particular to the 2 × REF to +REF last code transition (011. . .110) to (011 . . . 111) from the ideal (that is, +REF adjusted out.

Positive Gain Error Match

This is the difference in positive gain error between any two channels.

Negative Gain Error

This applies when using the twos complement output coding option, in particular to the 2 × REF to +REF first code transition (100 . . . 000) to (100 . . . 001) from the ideal (that is, −REF adjusted out.

biased about the REFIN point. It is the deviation of the

− 1 LSB.

biased about the REFIN point. It is the deviation of the

− 1 LSB) after the zero code error has been

biased about the REFIN point. It is the deviation of the

+ 1 LSB) after the zero code error has been

– 1 LSB) after the

input range with −REFIN

voltage,

input range with −REFIN

Rev. C | Page 12 of 28

This is the difference in negative gain error between any two channels.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale 400 kHz sine wave signal to all seven nonselected input channels and determining how much that signal is attenuated in the selected channel with a 50 kHz signal. The figure is given worst case across all eight channels for the AD7908/AD7918/ AD7928.

Power Supply Rejection (PSR)

Variations in power supply affect the full-scale transition, but not the converter’s linearity. Power supply rejection is the maximum change in full-scale transition point due to a change in power-supply voltage from the nominal value (see the Performance Curves section).

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode at the end of conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1 LSB, after the end of conversion.

Signal-to-(Noise + Distortion) Ratio

This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02N + 1.76)dB

Thus for a 12-bit converter, this is 74 dB; for a 10-bit converter, this is 62 dB; and for an 8-bit converter, this is 50 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7908/AD7918/ AD7928, it is defined as:

()

dBTHD

log20

where V V

sixth harmonics.

is the rms amplitude of the fundamental and V2, V3,

, V5, and V6 are the rms amplitudes of the second through the

/2), excluding dc. The ratio is

VVVVV

++++

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AD7908/AD7918/AD7928

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TYPICAL PERFORMANCE CHARACTERISTICS

PERFORMANCE CURVES

Figure 4 shows a typical FFT plot for the AD7928 at 1 MSPS sample rate and 50 kHz input frequency. Figure 5 shows the signal-to-(noise + distortion) ratio performance vs. input frequency for various supply voltages while sampling at 1 MSPS with an SCLK of 20 MHz.

Figure 6 shows the power supply rejection ratio vs. supply ripple frequency for the AD7928 when no decoupling is used. The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency f, to the power of a 200 mV p-p sine wave applied to the ADC AV frequency f

PSRR(dB) = 10 log(Pf/Pfs)

Pf is equal to the power at frequency f in ADC output; Pf equal to the power at frequency f

coupled onto the ADC AVDD

supply. Here a 200 mV p-p sine wave is coupled onto the AV supply.

–10

–30

–50

SNR (dB)

–70

–90

–110

0 50 100 150 200 250 300 350 40 0 450 500

Figure 4. AD7928 Dynamic Performance at 1 MSPS

FREQUENCY (kHz)

supply of

4096 POINT FFT AV

= 5V

= 1MSPS

SAMPLE

= 50kHz

SINAD = 71.147dB THD = –87.229dB SFDR = –90.744d B

= V

DRIVE

= 5.25V

= 4.75V

03089-004

Figure 7 shows a graph of total harmonic distortion vs. analog input frequency for various supply voltages, and Figure 8 shows a graph of total harmonic distortion vs. analog input frequency for various source impedances. See the Analog Input section.

Figure 9 and Figure 10 show typical INL and DNL plots for the AD7928.

AVDD = 5V 200mV p-p SINEWAVE O N AV

–10

REFIN = 2.5V, 1µ F CAPACITO R

= 25°C

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

0 1000500 900800700600400300200100

SUPPLY RIPPLE FREQUENCY (kHz)

Figure 6. AD7928 PSRR vs. Supply Ripple Frequency

= 1MSPS

SAMPLE

= 25°C

–55

RANGE = 0V TO REF

–60

–65

–70

THD (dB)

–75

–80

–85

–90

10 100 1000

INPUT FREQ UENCY (kHz)

Figure 7. AD7928 THD vs. Analog Input Frequency for

Various Supply Voltages at 1 MSPS

AVDD = V

DRIVE

= 2.70V

= V

AVDD = V

= 5.25V

DRIVE

= 3.60V

= 4.75V

03089-006

03089-007

= V

DRIVE

= 3.60V

= 2.70V

03089-005

SINAD (dB)

= 1MSPS

SAMPLE

= 25°C

RANGE = 0V TO REF

10 100 1000

INPUT FREQ UENCY (kHz)

AVDD = V

Figure 5. AD7928 SINAD vs. Analog Input Frequency for

Various Supply Voltages at 1 MSPS

Rev. C | Page 13 of 28

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= 1MSPS

SAMPLE

= 25°C

–55

RANGE = 0V TO RE F AVDD = 5.25V

–60

–65

–70

THD (dB)

–75

–80

–85

–90

10 100 1000

= 1000Ω

= 100Ω

= 50Ω

RIN= 10Ω

INPUT FREQUENCY (kHz)

Figure 8. AD7928 THD vs. Analog Input Frequency for

Various Source Impedances

1.0

AVDD = V

0.8 TEMPERATURE = 25°C

0.6

0.4

0.2

–0.2

INL ERRO R (LS B)

–0.4

–0.6

–0.8

–1.0

0 1024 2048 30721536512 2560 3584 4096

DRIVE

= 5V

CODE

Figure 9. AD7928 Typical INL

03089-008

03089-009

1.0

AVDD = V

0.8 TEMPERATURE = 25°C

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 1024 2048 30721536512 2560 3584 4096

DRIVE

= 5V

CODE

03089-010

Figure 10. AD7928 Typical DNL

Rev. C | Page 14 of 28

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CONTROL REGISTER

The control register on the AD7908/AD7918/AD7928 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7908/AD7918/AD7928 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conversion result is read from the part. The data transferred on the DIN line corresponds to the AD7908/AD7918/AD7928 configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling clock edges (after CS

falling edge) is loaded to the control register. MSB denotes the first bit in the data stream. The bit functions are outlined in . Ta ble 7

MSB LSB

WRITE SEQ DON’TCARE ADD2 ADD1 ADD0 PM1 PM0 SHADOW DON’TCARE RANGE CODING

Table 7. Control Register Bit Functions

Bit Mnemonic Comment

11 WRITE

10 SEQ

9 DON’TCARE 8 to 6

5, 4 PM1, PM0

3 SHADOW

2 DON’TCARE 1 RANGE

0 CODING

ADD2 to ADD0

The value written to this bit of the control register determines whether or not the following 11 bits are loaded to the control register. If this bit is a 1, the following 11 bits are written to the control register; if it is a 0, the remaining 11 bits are not loaded to the control register, and it remains unchanged.

The SEQ bit in the control register is used in conjunction with the SHADOW bit to control the use of the sequencer function and access the SHADOW register (see the SHADOW register bit map).

These three address bits are loaded at the end of the present conversion sequence and select which analog input channel is to be converted in the next serial transfer, or they can select the final channel in a consecutive sequence as described in Table 10. The selected input channel is decoded as shown in Table 8. The address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of data, see the Serial Interface section. The next channel to be converted on is selected by the mux on the 14th SCLK falling edge.

Power Management Bits. These two bits decode the mode of operation of the AD7908/AD7918/AD7928 as shown in Table 9.

The SHADOW bit in the control register is used in conjunction with the SEQ bit to control the use of the sequencer function and access the SHADOW register (see Table 10).

This bit selects the analog input range to be used on the AD7908/AD7918/AD7928. If it is set to 0, the analog input range extends from 0 V to 2 × REF conversion). For 0 V to 2 × REF

This bit selects the type of output coding the AD7908/AD7918/AD7928 uses for the conversion result. If this bit is set to 0, the output coding for the part is twos complement. If this bit is set to 1, the output coding from the part is straight binary (for the next conversion).

. If it is set to 1, the analog input range extends from 0 V to REFIN (for the next

, AVDD = 4.75 V to 5.25 V.

Table 8. Channel Selection

ADD2 ADD1 ADD0 Analog Input Channel

0 0 0 VIN0 0 0 1 VIN1 0 1 0 VIN2 0 1 1 VIN3 1 0 0 VIN4 1 0 1 VIN5 1 1 0 VIN6 1 1 1 VIN7

Rev. C | Page 15 of 28

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Table 9. Power Mode Selection

PM1 PM0 Mode

1 1

1 0

0 1

0 0 Invalid Selection. This configuration is not allowed.

SEQUENCER OPERATION

The configuration of the SEQ and SHADOW bits in the control register allows the user to select a particular mode of operation of the sequencer function. Tabl e 10 outlines the four modes of operation of the sequencer.

Table 10. Sequence Selection

SEQ SHADOW Sequence Type

0 0

0 1

1 0

1 1

Normal Operation. In this mode, the AD7908/AD7918/AD7928 remain in full power mode regardless of the status of any of the logic inputs. This mode allows the fastest possible throughput rate from the AD7908/AD7918/AD7928.

Full Shutdown. In this mode, the AD7908/ AD7918/AD7928 is in full shutdown mode with all circuitry powering down. The AD7908/AD7918/AD7928 retains the information in the control register while in full shutdown. The part remains in full shutdown until these bits are changed.

Auto Shutdown. In this mode, the AD7908/AD7918/AD7928 automatically enters full shutdown mode at the end of each conversion when the control register is updated. Wake-up time from full shutdown is 1 μs and the user should ensure that 1 μs has elapsed before attempting to perform a valid conversion on the part in this mode.

This configuration means that the sequence function is not used. The analog input channel selected for each individual conversion is determined by the contents of the ADD0 through ADD2 channel address bits in each prior write operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer function being used, where each write to the AD7908/AD7918/AD7928 selects the next channel for conversion (see Figure 11).

This configuration selects the SHADOW register for programming. The following write operation loads the contents of the SHADOW register. This programs the sequence of channels to be converted on continuously with each successive

falling edge (see the section, SHADOW register bit map, and ). The channels

valid CS selected need not be consecutive.

If the SEQ and SHADOW bits are set in this way, then the sequence functions are not interrupted upon completion of the write operation. This allows other bits in the control register to be altered between conversions while in a sequence, without terminating the cycle.

This configuration is used in conjunction with the ADD2 to ADD0 channel address bits to program continuous conversions on a consecutive sequence of channels from Channel 0 to a selected final channel as determined by the channel address bits in the control register (see Figure 13).

SHADOW Register Figure 12

Rev. C | Page 16 of 28

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SHADOW REGISTER

MSB LSB

VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7

Sequence One Sequence Two

The SHADOW register on the AD7908/AD7918/AD7928 is a 16-bit, write-only register. Data is loaded from the DIN pin of the AD7908/AD7918/AD7928 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that a conversion result is read from the part. This requires 16 serial clock falling edges for the data transfer. The information is clocked into the SHADOW register, provided that the SEQ and SHADOW bits were set to 0,1, respectively, in the previous write to the control register. MSB denotes the first bit in the data stream. Each bit represents an analog input from Channel 0 to Channel 7. Through programming the SHADOW register, two sequences of channels can be selected, through which the AD7908/AD7918/AD7928 cycle with each consecutive conversion after the write to the SHADOW register.

Sequence One is performed first and then Sequence Two. If the user does not wish to perform a second sequence option, then all 0s must be written to the last 8 LSBs of the SHADOW register. To select a sequence of channels, the associated channel bit must be set for each analog input. The AD7908/AD7918/ AD7928 continuously cycle through the selected channels in ascending order beginning with the lowest channel, until a write operation occurs (that is, the WRITE bit is set to 1) with the SEQ and SHADOW bits configured in any way except 1, 0, (see Tabl e 10 ). The bit functions are outlined in the SHADOW register bit map.

Figure 11 reflects the traditional operation of a multichannel ADC, where each serial transfer selects the next channel for conversion. In this mode of operation the sequencer function is not used.

Figure 12 shows how to program the AD7908/AD7918/AD7928 to continuously convert on a particular sequence of channels. To exit this mode of operation and revert back to the traditional mode of operation of a multichannel ADC (as outlined in Figure 11), ensure that the WRITE bit = 1 and the SEQ = SHADOW = 0 on the next serial transfer. Figure 13 shows how a sequence of consecutive channels can be converted on without having to program the SHADOW register or write to the part on each serial transfer. Again, to exit this mode of operation and revert back to the traditional mode of operation of a multichannel ADC (as outlined in Figure 11), ensure the WRITE bit = 1 and the SEQ = SHADOW = 0 on the next serial transfer.

POWER-ON

DUMMY CONVERSION

DIN = ALL 1s

DIN: WRITE TO CONTRO L REGISTER, WRITE BIT = 1, SEL ECT CODING , RANGE, AND POWER MODE . SELECT A2 TO A0 FOR CONV ERSION. SEQ = SHADOW = 0

DOUT: CONVERSION RESULT FROM PREVIOUSLY SEL ECTED CHANNEL A2 TO A0.

DIN: WRITE TO CONTRO L REGISTER, WRITE BIT = 1, SEL ECT CODING , RANGE, AND POWER MODE . SELECT A2 TO A0 FOR CONV ERSION. SEQ = SHADOW = 0

Figure 11. SEQ Bit = 0, SHADOW Bit = 0 Flowchart

POWER-ON

DUMMY CONVERSION

DIN = ALL 1s

DIN: WRITE TO CONTROL REGISTER,

WRITE BIT = 0

WRITE BIT = 1, SEL ECT CODING , RANGE, AND POWER MODE. SELECT CHANNEL A2 TO A0 FOR CONVERSI ON. SEQ = 0 SHADOW = 1

DOUT: CONVERS ION RESULT FROM PREVIOUSL Y SELECTE D CHANNEL A2 TO A0.

DIN: WRITE TO SHADOW REGISTER, SELECTING WHICH CHANNELS TO CONVERT ON; CHANNELS SELECT ED NEED NOT BE CONSECUTIVE CHANNELS

WRITE BIT = 0

CONTINUOUSL Y CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS

WRITE BIT = 0

WRITE BIT = 1 SEQ = 1, SHADOW = 0

CONTINUOUSL Y CONVERTS ON THE SELECTED SEQUENCE OF CHANNELS BUT WILL ALLOW RANG E, CODING , AND SO ON, T O CHANGE IN THE CO NTROL REGISTER WITHOUT INTERRUPTI NG THE SEQUENCE, PROVIDED SEQ = 1 SHADOW = 0

WRITE BIT = 1

SEQ = 1, SHADOW = 0

Figure 12. SEQ Bit = 0, SHADOW Bit = 1 Flowchart

WRITE BIT = 1, SEQ = SHADOW = 0

3089-011

03089-012

Rev. C | Page 17 of 28

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AD7908/AD7918/AD7928

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or 0 V to 2 × REFIN. Figure 14 and Figure 15 show

POWER-ON

DUMMY CO NVERSI ON

DIN = ALL 1s

DIN: WRITE TO CONTRO L REGISTER,

WRITE BI T = 1, SEL ECT CODING , RANGE, AND POWER MODE. SELECT CHANNEL A2 TO A0 FOR CONVERSI ON. SEQ = 1 SHADOW = 1

DOUT: CONVERSION RESULT FROM CHANNEL 0.

CONTINUOUSL Y CONVERTS O N A CONSECUTIVE S EQUENCE OF CHANNELS FROM CHANNEL 0 UP TO, AND INCLUDING, THE PREVIO USLY SELECTED A2 T O A0 IN THE CO NTROL REGISTER.

CONTINUOUSL Y CONVERTS O N THE SELECTED SEQUENCE OF CHANNEL S BUT WILL ALLOW RANGE, CODING , AND SO ON, TO CHANGE IN THE CONTROL REGISTER W ITHOUT INTERRUPTI NG THE SEQUENCE, PROVIDED SEQ = 1 SHADOW = 0

Figure 13. SEQ Bit = 1, SHADOW Bit = 1 Flowchart

WRITE BIT = 0

WRITE BIT = 1 SEQ = 1, SHADO W = 0

CIRCUIT INFORMATION

The AD7908/AD7918/AD7928 are high speed, 8-channel, 8-bit, 10-bit, and 12-bit, single-supply ADCs, respectively. The parts can be operated from a 2.7 V to 5.25 V supply. When operated from either a 5 V or 3 V supply, the AD7908/AD7918/AD7928 are capable of throughput rates of 1 MSPS when provided with a 20 MHz clock.

03089-013

REF

simplified schematics of the ADC. The ADC is comprised of control logic, SAR, and a capacitive DAC, which are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. Figure 14 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on the selected V

VIN7

AGND

SW1

Figure 14. ADC Acquisition Phase

4kΩ

SW2

channel.

COMPARATOR

CAPACITIVE DAC

CONTROL

LOGIC

03089-014

When the ADC starts a conversion (see Figure 15), SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 17 and Figure 18 show the ADC transfer functions.

CAPACIT IVE DACCAPACITIV E DAC

The AD7908/AD7918/AD7928 provide the user with an onchip, track-and-hold ADC, and a serial interface housed in a 20-lead TSSOP package. The AD7908/AD7918/ AD7928 each have eight single-ended input channels with a channel sequencer, allowing the user to select a channel sequence that the ADC can cycle through with each consecutive

falling edge. The serial clock input accesses data from the part, controls the transfer of data written to the ADC, and provides the clock source for the successive approximation ADC. The analog input range for the AD7908/AD7918/ AD7928 is 0 V to REF to 2 × REF register. For the 0 to 2 × REF

, depending on the status of Bit 1 in the control

range, the part must be operated

or 0 V

from a 4.75 V to 5.25 V supply.

The AD7908/AD7918/AD7928 provide flexible power management options to allow the user to achieve the best power performance for a given throughput rate. These options are selected by programming the PM1 and PM0 power management bits in the control register.

CONVERTER OPERATION

The AD7908/AD7918/AD7928 are 8-, 10-, and 12-bit successive approximation analog-to-digital converters based around a capacitive DAC, respectively. The AD7908/AD7918/ AD7928 can convert analog input signals in the range 0 V to

Rev. C | Page 18 of 28

VIN7

AGND

SW1

Figure 15. ADC Conversion Phase

4kΩ

SW2

COMPARATOR

CONTRO L

LOGIC

03089-015

Analog Input

Figure 16 shows an equivalent circuit of the analog input structure of the AD7908/AD7918/AD7928. The two diodes (D1 and D2) provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mV. This causes these diodes to become forward biased and start conducting current into the substrate. 10 mA is the maximum current these diodes can conduct without causing irreversible damage to the part. The Capacitor C1 in Figure 16 is typically about 4 pF and can primarily be attributed to pin capacitance. The Resistor R1 is a lumped component made up of the on resistance of the trackand-hold switch and also includes the on resistance of the input multiplexer. The total resistance is typically about 400 Ω. The Capacitor C2 is the ADC sampling capacitor and has a capacitance of 30 pF typically. For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC lowpass filter on the relevant analog input pin. In applications where harmonic distortion

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and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This can necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application.

When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases, and performance degrades (see Figure 8).

011…111 011…110

•

• 000…001 000…000 111…111

•

ADC CODE

• 100…010 100…001 100…000

–V

REF

+ 1 LSB

1LSB = 2 × V 1LSB = 2 × V 1LSB = 2 × V

– 1 LSB

REF

ANALOG INPUT

REF REF REF

REF

/256 AD7908 /1024 AD7918 /4096 AD7928

– 1 LSB

Figure 18. Twos Complement Transfer Characteristic

with REF

± REFIN Input Range

03089-018

4pF

CONVERSION PHASE: SWITCH OPEN TRACK PHASE: SWI TCH CLOSED

30pF

03089-016

Figure 16. Equivalent Analog Input Circuit

ADC TRANSFER FUNCTION

The output coding of the AD7908/AD7918/AD7928 is either straight binary or twos complement, depending on the status of the LSB in the control register. The designed code transitions occur at successive LSB values (that is, 1 LSB, 2 LSBs, and so on). The LSB size is REF the AD7918, and REF characteristic for the AD7908/AD7918/AD7928 when straight binary coding is selected is shown in Figure 17, and the ideal transfer characteristic for the AD7908/AD7918/AD7928 when twos complement coding is selected is shown in Figure 18.

111…111 111…110

•

111…000

•

011…111

ADC CODE

•

• 000…010 000…001 000…000

Figure 17. Straight Binary Transfer Characteristic

/256 for the AD7908, REFIN/1024 for

/4096 for the AD7928. The ideal transfer

1LSB = V 1LSB = V 1LSB = V

1 LSB

NOTE

1. V

ANALOG INPUT

IS EITHER REFIN OR 2 × REF

REF

/256 AD7908

REF

/1024 AD7918

REF

/4096 AD7928

REF

– 1 LSB

IN.

03089-017

HANDLING BIPOLAR INPUT SIGNALS

Figure 19 shows how useful the combination of the 2 × REFIN input range and the twos complement output coding scheme is for handling bipolar input signals. If the bipolar input signal is biased about REF selected, then REF negative full scale and +REF a dynamic range of 2 × REF

and twos complement output coding is

becomes the zero code point, −REFIN is

becomes positive full scale, with

TYPICAL CONNECTION DIAGRAM

Figure 20 shows a typical connection diagram for the AD7908/AD7918/AD7928. In this setup, the AGND pin is connected to the analog ground plane of the system. In Figure 20, REF

is connected to a decoupled 2.5 V supply from a reference

source, the AD780, to provide an analog input range of 0 V to

2.5 V (if RANGE bit is 1) or 0 V to 5 V (if RANGE bit is 0). Although the AD7908/AD7918/AD7928 is connected to a V of 5 V, the serial interface is connected to a 3 V microprocessor. The V

pin of the AD7908/AD7918/ AD7928 is connected

DRIVE

to the same 3 V supply of the microprocessor to allow a 3 V logic interface (see the Digital Inputs section). The conversion result is output in a 16-bit word. This 16-bit data stream consists of a leading zero, three address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data for the AD7928 (10 bits of data for the AD7918 and 8 bits of data for the AD7908, each followed by two and four trailing zeros, respectively). For applications where power consumption is of concern, the power-down modes should be used between conversions or bursts of several conversions to improve power performance (see the Modes of Operation section).

Rev. C | Page 19 of 28

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AD7908/AD7918/AD7928

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DSP/µP

IN)

011…111

000…000

100…000

03089-019

0V TO REF

REF

0.1µF

REF

DRIVE

R1 = R2 = R3 = R4

AD7908/ AD7918/

AD7928

VIN0

•

• 7

TWOS COMPLEMENT

DOUT

+REFIN(= 2 × REF

REF

(= 0V)

–REF

Figure 19. Handling Bipolar Signals

during the sequence, then it must be ensured that the SEQ and

DRIVE

SUPPLY

SCLK

DOUT

DIN

0.1µF 10µF

VIN0

AGND

AD7908/

•

AD7918/

•

AD7928

REF

SERIAL

INTERFACE

µC/µP

SHADOW bits are set to 1, 0 to avoid interrupting the automatic conversion sequence. This pattern continues until such time as the AD7908/AD7918/AD7928 is written to and the SEQ and SHADOW bits are configured with any bit combination except 1, 0. On completion of the sequence, the AD7908/ AD7918/AD7928 sequencer returns to the first selected channel in the SHADOW register and commence the sequence again.

0.1µF

NOTE

1. ALL UNUSED INPUT CHANNELS SHO ULD BE CO NNECTED TO AGND.

2.5V

AD780

0.1µF 10µF 3V

SUPPLY

Figure 20. Typical Connection Diagram

Analog Input Selection

Any one of eight analog input channels can be selected for conversion by programming the multiplexer with the Address Bit ADD2 to Address Bit ADD0 in the control register. The channel configurations are shown in Tab le 8 . The AD7908/ AD7918/AD7928 can also be configured to automatically cycle through a number of channels as selected. The sequencer feature is accessed via the SEQ and SHADOW bits in the control register (see Ta ble 1 0).

The AD7908/AD7918/AD7928 can be programmed to continuously convert on a selection of channels in ascending order. The analog input channels to be converted on are selected through programming the relevant bits in the SHADOW register (see the SHADOW Register section). The next serial transfer then acts on the sequence programmed by executing a conversion on the lowest channel in the selection. The next serial transfer results in a conversion on the next highest channel in the sequence, and so on.

It is not necessary to write to the control register once a sequencer operation has been initiated. The WRITE bit must be set to zero or the DIN line tied low to ensure the control register is not accidentally overwritten, or the sequence operation interrupted. If the control register is written to at any time

Rev. C | Page 20 of 28

Rather than selecting a particular sequence of channels, a number of consecutive channels beginning with Channel 0 can

03089-020

also be programmed via the control register alone, without needing to write to the SHADOW register. This is possible if the SEQ and SHADOW bits are set to 1,1. The channel address bits ADD2 through ADD0 then determine the final channel in the consecutive sequence. The next conversion is on Channel 0, then Channel 1, and so on until the channel selected via the address bits ADD2 through ADD0 is reached. The cycle begins again on the next serial transfer, provided the WRITE bit is set to low, or if high, that the SEQ and SHADOW bits are set to 1, 0; then the ADC continues its preprogrammed automatic sequence uninterrupted.

Regardless of which channel selection method is used, the 16-bit word output from the AD7928 during each conversion always contains a leading zero, three channel address bits that the conversion result corresponds to, followed by the 12-bit conversion result. The AD7918 outputs a leading zero, three channel address bits that the conversion result corresponds to, followed by the 10-bit conversion result and two trailing zeros; the AD7908 outputs a leading zero, three channel address bits that the conversion result corresponds to, followed by the 8-bit conversion result and four trailing zeros. (See the

Serial

Interface section.)

Digital Inputs

The digital inputs applied to the AD7908/AD7918/AD7928 are not limited by the maximum ratings that limit the analog

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AD7908/AD7918/AD7928

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inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the AV

Another advantage of SCLK, DIN, and by the AV

+ 0.3 V limit is the fact that power supply

sequencing issues are avoided. If before AV

, there is no risk of latch-up as there would be on

+ 0.3 V limit as on the analog inputs.

not being restricted

, DIN, or SCLK are applied

the analog inputs if a signal greater than 0.3 V was applied prior to AV

The AD7908/AD7918/AD7928 also have the V V V

DRIVE

feature.

DRIVE

controls the voltage at which the serial interface operates.

DRIVE

allows the ADC to easily interface to both 3 V and 5 V

DRIVE

processors. For example, if the AD7908/AD7918/AD7928 were operated with an AV

of 5 V, the V

pin could be powered

DRIVE

from a 3 V supply. The AD7908/AD7918/AD7928 have better dynamic performance with an AV

of 5 V while still being able

to interface to 3 V processors. Care should be taken to ensure V

does not exceed AVDD by more than 0.3 V. See the

DRIVE

Absolute Maximum Ratings section.

Reference

An external reference source should be used to supply the 2.5 V reference to the AD7908/AD7918/AD7928. Errors in the reference source results in gain errors in the AD7908/ AD7918/AD7928 transfer function and adds to the specified full-scale errors of the part. A capacitor of at least 0.1 μF should be placed on the REF

pin. Suitable reference sources for the

AD7908/AD7918/AD7928 include the AD780, REF192, AD1582, ADR03, ADR381, ADR391, and ADR421.

If 2.5 V is applied to the REF

pin, the analog input range can

either be 0 V to 2.5 V or 0 V to 5 V, depending on the setting of the RANGE bit in the control register.

MODES OF OPERATION

The AD7908/AD7918/AD7928 have a number of different modes of operation. These modes are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. The mode of operation of the AD7908/AD7918/AD7928 is controlled by the power management bits, PM1 and PM0, in the control register, as detailed in Tab le 9 . When power supplies are first applied to the AD7908/AD7918/AD7928, care should be taken to ensure that the part is placed in the required mode of operation (see Powering Up the AD7908/AD7918/AD7928 section).

Normal Mode (PM1 = PM0 = 1)

This mode is intended for the fastest throughput rate performance, as the user does not have to worry about any power-up times with the AD7908/AD7918/AD7928 remaining fully powered at all times. Figure 21 shows the general diagram of the operation of the AD7908/AD7918/AD7928 in this mode.

Rev. C | Page 21 of 28

The conversion is initiated on the falling edge of track-and-hold enters hold mode as described in the Interface

section. The data presented to the AD7908/AD7918/ AD7928 on the DIN line during the first 12 clock cycles of the data transfer are loaded into the control register (provided WRITE bit is set to 1). If data is to be written to the SHADOW register (SEQ = 0, SHADOW = 1 on previous write), data presented on the DIN line during the first 16 SCLK cycles is loaded into the SHADOW register. The part remains fully powered up in normal mode at the end of the conversion as long as PM1 and PM0 are both loaded with 1 on every data transfer.

Sixteen serial clock cycles are required to complete the conversion and access the conversion result. The track-andhold goes back into track on the 14th SCLK falling edge. then idle high until the next conversion or can idle low until sometime prior to the next conversion, effectively idling

Once a data transfer is complete (DOUT has returned to threestate), another conversion can be initiated after the quiet time, t

, has elapsed by bringing CS low again.

QUIET

SCLK

DOUT

DIN

NOTES

1. CONTROL REGIST ER DATA IS L OADED ON FI RST 12 SCLK CYCL ES.

2. SHADOW REG ISTER DATA IS LOADED O N FIRST 16 SCLK CYCLES.

1 LEADING Z ERO + 3 CHANNEL

IDENTIFIER BITS + CO NVERSION RES ULT

DATA IN TO CO NTROL/S HADOW REGISTER

Figure 21. Normal Mode Operation

Full Shutdown Mode (PM1 = 1, PM0 = 0)

In this mode, all internal circuitry on the AD7908/AD7918/ AD7928 is powered down. The part retains information in the control register during full shutdown. The AD7908/AD7918/ AD7928 remains in full shutdown until the power management bits in the control register, PM1 and PM0, are changed.

If a write to the control register occurs while the part is in full shutdown, with the power management bits changed to PM0 = PM1 = 1, normal mode, the part begins to power up on the rising edge. The track-and-hold that was in hold while the part was in full shutdown returns to track on the 14th SCLK falling edge.

To ensure that the part is fully powered up, t

have elapsed before the next

falling edge. shows

the general diagram for this sequence.

Auto Shutdown Mode (PM1 = 0, PM0 = 1)

In this mode, the AD7908/AD7918/AD7928 automatically enters shutdown at the end of each conversion when the control register is updated. When the part is in shutdown, the track and hold is in hold mode. Figure 23 shows the general diagram of

POWER UP

Figure 22

and the

Serial

, should

can

low.

03089-021

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AD7908/AD7918/AD7928

www.BDTIC.com/ADI

the operation of the AD7908/AD7918/AD7928 in this mode. In shutdown mode, all internal circuitry on the AD7908/AD7918/ AD7928 is powered down. The part retains information in the control register during shutdown. The AD7908/AD7918/ AD7928 remains in shutdown until the next

receives. On this

falling edge, the track-and-hold that was in

falling edge it

hold while the part was in shutdown returns to track. Wakeup time from auto shutdown is 1 μs, and the user should ensure that 1 μs has elapsed before attempting a valid conversion. When running the AD7908/AD7918/AD7928 with a 20 MHz clock, one dummy cycle should be sufficient to ensure the part is fully powered up. During this dummy cycle the contents of the control register should remain unchanged; therefore the WRITE bit should be 0 on the DIN line. This dummy cycle effectively halves the throughput rate of the part, with every

other conversion result being valid. In this mode, the power consumption of the part is greatly reduced with the part entering shutdown at the end of each conversion. When the control register is programmed to move into auto shutdown, it does so at the end of the conversion. The user can move the ADC in and out of the low power state by controlling the

signal.

Powering Up the AD7908/AD7918/AD7928

When supplies are first applied to the AD7908/AD7918/ AD7928, the ADC can power up in any of the operating modes of the part. To ensure the part is placed into the required operating mode, the user should perform a dummy cycle operation as outlined in Figure 24.

PART IS IN FULL SHUTDOWN

SCLK

DOUT

DIN

SCLK

DOUT

DIN

PA R T BE GI N CS RISING EDGE AS PM1 = PM0 = 1

DATA IN TO CONTROL REGISTER

CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS. PM1 = 1, PM0 = 1

Figure 22. Full Shutdown Mode Operation

PART ENTERS SHUTDOW N ON CS

RISING EDGE AS PM1 = 0, PM0 = 1

CHANNEL IDENTIFIER

BITS + CONVERSION RESULT

DATA IN TO CONTROL /SHADOW REGIST ER

CONTROL REGISTER IS LOADED ON THE FIRST 12 CLOCKS, PM1 = 0, PM0 = 1

PART BEGI NS TO PO WER UP ON CS FALLING EDGE

Figure 23. Auto Shutdown Mode Operation

TO POWER UP ON

1614

DUMMY CONVER SION

INVALID DATA

CONTROL REGIST ER CONTENTS SHOUL D NOT CHANGE. WRITE BIT = 0

THE PART IS FULLY POWERED UP

ONCE

TO KEEP THE PART IN NORMAL MO DE, LOAD PM1 = PM0 = 1 IN CONTROL REGISTER

HAS ELAPSED

POWER UP

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

DATA IN TO CONTROL /SHADOW REGIST ER

PART ENTERS SHUTDOWN PART IS FULLY POWERED UP

1611

CHANNEL IDENTIFIER

BITS + CONVERSION RESULT

DATA IN TO CONTRO L/SHADO W REGI STER

TO KEEP PART IN THIS MODE, LOAD PM1 = 0, PM0 = 1 IN CONTROL REGISTER OR SET WRITE BIT = 0

ON CS RISING EDGE

AS PM1 = 0, PM0 = 1

1212

1614

3089-022

03089-023

Rev. C | Page 22 of 28

Page 23

AD7908/AD7918/AD7928

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SCLK

DOUT

DIN

DUMMY CONVERSIO N

INVALID DATA INVALID DATA

KEEP DIN LINE TIED HIG H FOR FIRST TWO DUMMY CONVERSIONS

Figure 24. Placing AD7928 into the Required Operating Mode After Supplies are Applied

16 1161 16

DUMMY CONVERSION

POWER VS. THROUGHPUT RATE

By operating in auto shutdown mode on the AD7908/AD7918/ AD7928, the average power consumption of the ADC decreases at lower throughput rates. Figure 25 shows how as the throughput rate is reduced, the part remains in its shutdown state longer and the average power consumption over time drops accordingly.

For example, if the AD7928 is operated in a continuous sampling mode with a throughput rate of 100 kSPS and an SCLK of 20 MHz (AV shutdown mode, that is, if PM1 = 0 and PM0 = 1, then the power consumption is calculated as follows:

The maximum power dissipation during normal operation is

13.5 mW (AV

shutdown is one dummy cycle, that is, 1 μs, and the remaining conversion time is another cycle, that is, 1 μs, then the AD7928 can be said to dissipate 13.5 mW for 2 μs during each conversion cycle. For the remainder of the conversion cycle, 8 μs, the part remains in auto shutdown mode. The AD7928 can be said to dissipate 2.5 μW for the remaining 8 μs of the conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 μs and the average power dissipated during each cycle is

(2/10) × (13.5 mW) + (8 / 10) × (2.5 μW) = 2.702 mW

Figure 25 shows the maximum power vs. throughput rate when using the auto shutdown mode with 3 V and 5 V supplies.

= 5 V), and the device is placed in auto

= 5 V). If the power-up time from auto

INVALID DATA

CORRECT VALUE I N CONTROL

NEXT CONVERSION, USER CAN

WRITE TO SHADOW REGISTER

IN NEXT CONVERSION

121212

DATA IN TO CO NTROL REG ISTER

CONTROL REGISTER I S LOADED ON T HE FIRST 12 CLOCK EDGES

AVDD = 5V

POWER (mW)

0.1

0.01 0 50 100 15 0 200 250 300 350

Figure 25. AD7928 Power vs. Throughput Rate

THROUGHPUT (kSPS)

= 3V

03089-025

SERIAL INTERFACE

Figure 26, Figure 27, and Figure 28 show the detailed timing diagrams for serial interfacing to the AD7908, AD7918, and AD7928, respectively. The serial clock provides the conversion clock and also controls the transfer of information to and from the AD7908/AD7918/AD7928 during each conversion.

The

signal initiates the data transfer and conversion process. The falling edge of takes the bus out of three-state; the analog input is sampled at

this point. The conversion is also initiated at this point and requires 16 SCLK cycles to complete. The track-and-hold goes back into track on the 14th SCLK falling edge as shown in Figure 26 Figure 27 Figure 28

, , and at Point B, except when the write is to the SHADOW register, in which case the track-andhold does not return to track until the rising edge of Point C in . On the 16th SCLK falling edge, the DOUT

Figure 29 line goes back into three-state. If the rising edge of before 16 SCLKs have elapsed, the conversion is terminated, the DOUT line goes back into three-state, and the control register is not updated; otherwise DOUT returns to three-state on the 16th SCLK falling edge as shown in , , and Figure 28

. Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7908/ AD7918/AD7928. For the AD7908/AD7918/AD7928, the

puts the track-and-hold into hold mode,

occurs

Figure 26 Figure 27

, that is,

3089-024

Rev. C | Page 23 of 28

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AD7908/AD7918/AD7928

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8/10/12 bits of data are preceded by a leading zero and the 3-channel address bits (ADD2 to ADD0) identify which channel the result corresponds to. leading zero to be read in by the microcontroller or DSP. The three remaining address bits and data bits are then clocked out by subsequent SCLK falling edges beginning with the first address bit (ADD2). Thus the first falling clock edge on the serial clock has a leading zero provided and also clocks out Address Bit ADD2. The final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge.

Writing of information to the control register takes place on the first 12 falling edges of SCLK in a data transfer, assuming the MSB, that is, the WRITE bit, has been set to 1. If the control register is programmed to use the SHADOW register, then writing of information to the SHADOW register takes place on all 16 SCLK falling edges in the next serial transfer, as shown for example on the AD7928 in Figure 29. Two sequence options can be programmed in the SHADOW register. If the user does not want to program a second sequence, then the eight LSBs should be filled with zeros. The SHADOW register is updated upon the rising edge of track the first channel selected in the sequence.

The AD7908 outputs a leading zero and three channel address bits that the conversion result corresponds to, followed by the 8-bit conversion result and four trailing zeros. The AD7918 outputs a leading zero and three channel address bits that the conversion result corresponds to, followed by the 10-bit conversion result and two trailing zeros. The 16-bit word read from the AD7928 always contains a leading zero and three channel address bits that the conversion result corresponds to, followed by the 12-bit conversion result.

going low provides the

and the track-and-hold begins to

MICROPROCESSOR INTERFACING

The serial interface on the AD7908/AD7918/AD7928 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7908/AD7918/AD7928 with some of the more common microcontroller and DSP serial interface protocols.

AD7908/AD7918/AD7928 to TMS320C541

The serial interface on the TMS320C541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7908/AD7918/AD7928. The interfacing between the TMS320C541 and the AD7908/ AD7918/AD7928 without any glue logic required. The serial port of the TMS320C541 is set up to operate in burst mode with internal CLKX0 (Tx serial clock on Serial Port 0) and FSX0 (Tx frame sync from Serial Port 0). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The connection diagram is shown in . It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the TMS320C541 provides equidistant sampling. The V the AD7908/AD7918/AD7928 takes the same supply voltage as that of the TMS320C541. This allows the ADC to operate at a higher voltage than the serial interface, that is, TMS320C541, if necessary.

input allows easy

Figure 30

pin of

DRIVE

Rev. C | Page 24 of 28

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AD7908/AD7918/AD7928

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SCLK

DOUT

THREE-STATE THREE-STATE

DIN

123456

ADD2 ADD1 ADD0 DB7 DB6 DB0 ZERO ZERO ZERO ZERO

THREE IDENTI FICATION BITS

ZERO

WRITE SEQ1 DO NTC ADD2 ADD1 ADD0

CONVERT

11 12 13 14 15 16

CODING

DONTC DON TC DO NTC DONTC

FOUR TRAIL ING ZERO S

Figure 26. AD7908 Serial Interface Timing Diagram

SCLK

DOUT

THREE-STATE THREE-STATE

DIN

123456

ADD2 ADD1 ADD0 DB7 DB6 DB2 DB1 DB0 ZERO Z ERO

THREE IDENTIFICATION BITS

ZERO

WRITE SEQ DONTC ADD2 ADD1 ADD0

CONVERT

11 12 13 14 15 16

CODING

DONTC DONTC DONT C DONT C

TWO TRAI LING ZEROS

Figure 27. AD7918 Serial Interface Timing Diagram

SCLK

DOUT

THREE-STATE

DIN

123456

ADD2 ADD1 ADD0 DB11 DB10

THREE IDENTIFICATION BITS

ZERO

WRITE SEQ DONTC ADD2 ADD1 ADD0

CONVERT

14 15

DB2 DB1 DB0

DONTCDONTC DONTC

THREE-STATE

QUIET

Figure 28. AD7928 Serial Interface Timing Diagram

SCLK

DOUT

THREE-STATE

DIN

123456

ADD2 ADD1 ADD0 DB11 DB10 DB2 DB1 DB0

THREE IDENTIFICATION BITS

ZERO

0VIN1VIN2VIN3VIN4VIN5V

SEQUENCE 1 SEQUENCE 2

CONVERT

14 15

6VIN7

THREE-STATE

Figure 29. AD7928 Writing to SHADOW Register Timing Diagram

QUIET

3089-028

3089-029

3089-026

03089-027

Rev. C | Page 25 of 28

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AD7908/AD7918/AD7928

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AD7908/ AD7918/

AD7928

SCLK

DOUT

DIN

DRIVE

ADDITIONAL PINS REMOVED FOR CLARIT Y.

Figure 30. Interfacing to the TMS320C541

TMS320C541

CLKX

CLKR

FSX

FSR

AD7908/AD7918/AD7928 to ADSP-21xx

The ADSP-21xx family of DSPs are interfaced directly to the AD7908/AD7918/AD7928 without any glue logic required. The V

pin of the AD7908/AD7918/AD7928 takes the same

DRIVE

supply voltage as that of the ADSP-21xx. This allows the ADC to operate at a higher voltage than the serial interface, that is, ADSP-21xx, if necessary.

The SPORT0 control register should be set up as follows:

TFSW = RFSW = 1, alternate framing INVRFS = INVTFS = 1, active low frame signal DTYPE = 00, right justify data SLEN = 1111, 16-bit data-words ISCLK = 1, internal serial clock TFSR = RFSR = 1, frame every word IRFS = 0 ITFS = 1

The connection diagram is shown in Figure 31. The ADSP-21xx has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode and the SPORT control register is set up as described. The frame synchronization signal generated on the TFS is tied to

, as with all signal processing applications where equidistant sampling is necessary. However, in this example the timer interrupt is used to control the sampling rate of the ADC, and under certain conditions equidistant sampling cannot be achieved.

The timer register, for example, is loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and thus the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given (that is, AX0 = TX0), the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high before transmission can start. If the timer and SCLK values are chosen, such that the instruction to transmit occurs on or near

03089-030

the rising edge of SCLK, then the data can be transmitted or it can wait until the next clock edge.

For example, if the ADSP-2189 had a 20 MHz crystal such that it had a master clock frequency of 40 MHz, then the master cycle time would be 25 ns. If the SCLKDIV register was loaded with the value 3, then an SCLK of 5 MHz is obtained, and eight master clock periods elapse for every one SCLK period. Depending on the throughput rate selected, if the timer register is loaded with the value, say 803 (803 + 1 = 804), 100.5 SCLKs occur between interrupts and subsequently between transmit instructions. This situation results in nonequidistant sampling as the transmit instruction is occurring on a SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, then equidistant sampling is implemented by the DSP.

AD7908/AD7918/AD7928 to DSP563xx

The connection diagram in Figure 32 shows how the AD7908/AD7918/AD7928 can be connected to the synchronous serial interface (ESSI) of the DSP563xx family of DSPs from Motorola. Each ESSI (two on board) is operated in synchronous mode (SYN bit in CRB = 1) with internally generated word length frame sync for both Tx and Rx (Bit FSL1 = 0 and Bit FSL0 = 0 in CRB). Normal operation of the ESSI is selected by making MOD = 0 in the CRB. Set the word length to 16 by setting Bit WL1 = 1 and Bit WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1 so the frame sync is negative. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the DSP563xx provides equidistant sampling.

AD7908/ AD7918/

AD7928

SCLK

DOUT

DIN

DRIVE

ADDITIONAL PINS REMOVED FOR CLARIT Y.

Figure 31. Interfacing to the ADSP-21xx

ADSP-21xx

SCLK

RFS

TFS

03089-031

Rev. C | Page 26 of 28

In the example shown in Figure 32, the serial clock is taken from the ESSI so the SCK0 pin must be set as an output, SCKD = 1. The V

pin of the AD7908/AD7918/AD7928 takes the

DRIVE

same supply voltage as that of the DSP563xx. This allows the ADC to operate at a higher voltage than the serial interface, that is, DSP563xx, if necessary.

Page 27

AD7908/AD7918/AD7928

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AD7908/ AD7918/

AD7928

SCLK

DOUT

DIN

DRIVE

ADDITIONAL PINS REMOVE D FOR CLARIT Y.

Figure 32. Interfacing to the DSP563xx

DSP563xx

SCK

SRD

STD

SC2

APPLICATION HINTS

Grounding and Layout

The AD7908/AD7918/AD7928 have very good immunity to noise on the power supplies, as can be seen by the PSRR vs. Supply Ripple Frequency plot, Figure 6. However, care should still be taken with regard to grounding and layout.

The printed circuit board that houses the AD7908/AD7918/ AD7928 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding.

All four AGND pins of the AD7908/AD7918/AD7928 should be sunk in the AGND plane. If the AD7908/AD7918/AD7928 is in a system where multiple devices require an AGND to DGND connection, the connection should be made at only one point in the plane. Using a star ground point, the connection should be established as close as possible to the AD7908/ AD7918/AD7928.

Avoid running digital lines under the device, as these couple noise onto the die. The analog ground plane should be allowed to run under the AD7908/AD7918/AD7928 to avoid noise coupling. The power supply lines to the AD7908/AD7918/ AD7928 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power

supply line. Fast switching signals, like clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double sided board. In this technique, the component side of the board is dedicated to

03089-032

ground planes while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should be decoupled with 10 μF tantalum in parallel with 0.1 μF capacitors to AGND. To achieve the best performance from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The

0.1 μF capacitors should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types or surface mount types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.

Evaluating the AD7908/AD7918/AD7928 Performance

The recommended layout for the AD7908/AD7918/AD7928 is outlined in the AD7908/AD7918/AD7928 evaluation board. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the PC via the eval-board controller.

The eval-board controller can be used in conjunction with the AD7908/AD7918/AD7928 evaluation board, as well as many other Analog Devices evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7908/AD7918/AD7928.

The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7908/AD7918/AD7928. The software and documentation are on a CD shipped with the evaluation board.

Rev. C | Page 27 of 28

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AD7908/AD7918/AD7928

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OUTLINE DIMENSIONS

6.60

6.50

6.40

PIN 1

0.15

0.05

COPLANARIT

0.65

BSC

0.30

0.19

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AC

1.20 MAX

SEATING PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09 8°

0°

0.75

0.60

0.45

Figure 33. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Linearity Error (LSB)1 Package Description Package Option

AD7908BRU −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7908BRU-REEL −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7908BRU-REEL7 −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7908BRUZ2 −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7908BRUZ-REEL2 −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7908BRUZ-REEL72 −40°C to +85°C ±0.2 20-Lead TSSOP RU-20 AD7918BRU −40°C to +85°C ±0.5 20-Lead TSSOP RU-20 AD7918BRU-REEL −40°C to +85°C ±0.5 20-Lead TSSOP RU-20 AD7918BRU-REEL7 −40°C to +85°C ±0.5 20-Lead TSSOP RU-20 AD7918BRUZ2 −40°C to +85°C ±0.5 20-Lead TSSOP RU-20 AD7918BRUZ-REEL2 −40°C to +85°C ±0.5 20-Lead TSSOP RU-20 AD7918BRUZ-REEL72 −40°C to +85°C ±0.5 20-Lead TSSOP RU-20 AD7928BRU −40°C to +85°C ±1 20-Lead TSSOP RU-20 AD7928BRU-REEL −40°C to +85°C ±1 20-Lead TSSOP RU-20 AD7928BRU-REEL7 −40°C to +85°C ±1 20-Lead TSSOP RU-20 AD7928BRUZ2 −40°C to +85°C ±1 20-Lead TSSOP RU-20 AD7928BRUZ-REEL2 −40°C to +85°C ±1 20-Lead TSSOP RU-20 AD7928BRUZ-REEL72 −40°C to +85°C ±1 20-Lead TSSOP RU-20 EVAL-AD79x8CBZ EVAL-CONTROL BRD4 Controller Board

Linearity error here refers to integral linearity error.

Z = RoHS Compliant Part.

This can be used as a standalone evaluation board or in conjunction with the evaluation controller board for evaluation/demonstration purposes. The board comes

with one chip of each the AD7908, AD7918, and AD7928.

This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete

evaluation kit, order the particular ADC evaluation board, such as the EVAL-AD79x8CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the relevant evaluation board technical note for more information.

2, 3

Evaluation Board

Rev. C | Page 28 of 28

Datasheet AD7918 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AD7908 SPECIFICATIONS

AD7918 SPECIFICATIONS

AD7928 SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

PERFORMANCE CURVES

CONTROL REGISTER

SEQUENCER OPERATION

SHADOW REGISTER

CIRCUIT INFORMATION

CONVERTER OPERATION

Analog Input

ADC TRANSFER FUNCTION

HANDLING BIPOLAR INPUT SIGNALS

TYPICAL CONNECTION DIAGRAM

Analog Input Selection

Digital Inputs

Reference

MODES OF OPERATION

Normal Mode (PM1 = PM0 = 1)

Full Shutdown Mode (PM1 = 1, PM0 = 0)

Auto Shutdown Mode (PM1 = 0, PM0 = 1)

Powering Up the AD7908/AD7918/AD7928

POWER VS. THROUGHPUT RATE

SERIAL INTERFACE

MICROPROCESSOR INTERFACING

AD7908/AD7918/AD7928 to TMS320C541

AD7908/AD7918/AD7928 to ADSP-21xx

AD7908/AD7918/AD7928 to DSP563xx

APPLICATION HINTS

Grounding and Layout

Evaluating the AD7908/AD7918/AD7928 Performance

OUTLINE DIMENSIONS

ORDERING GUIDE