Datasheet AD7910 Datasheet (Analog Devices)

250 kSPS,

10-/12-Bit ADCs in 6-Lead SC70

FEATURES
Throughput Rate: 250 kSPS
Specified for V

of 2.35 V to 5.25 V

DD

Low Power:

3.6 mW Typ at 250 kSPS with 3 V Supplies

12.5 mW Typ at 250 kSPS with 5 V Supplies

Wide Input Bandwidth:

71 dB SNR at 100 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface

®

/QSPI™/MICROWIRE™/DSP Compatible

SPI
Standby Mode: 1 ␮A Max
6-Lead SC70 Package
8-Lead MSOP Package

APPLICATIONS
Battery-Powered Systems

Personal Digital Assistants

Medical Instruments

Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High Speed Modems
Optical Sensors

GENERAL DESCRIPTION

The AD7910/AD7920 are, respectively, 10-bit and 12-bit, high
speed, low power, successive-approximation ADCs. The parts
operate from a single 2.35 V to 5.25 V power supply and feature
throughput rates up to 250 kSPS. The parts contain a low noise,
wide bandwidth track-and-hold amplifier that can handle input
frequencies in excess of 13 MHz.

The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.

The AD7910/AD7920 use advanced design techniques to achieve
very low power dissipation at high throughput rates.

AD7910/AD7920

*

FUNCTIONAL BLOCK DIAGRAM

V

DD

10-/12-BIT

V

T/H

IN

The reference for the part is taken internally from V

SUCCESSIVE-

APPROXIMATION

ADC

CONTROL

LOGIC

AD7910/AD7920

GND

SCLK

SDATA

CS

DD.

This
allows the widest dynamic input range to the ADC. Thus the
analog input range for the part is 0 to V

. The conversion rate

DD

is determined by the SCLK.

PRODUCT HIGHLIGHTS

1. 10-/12-Bit ADCs in SC70 and MSOP Packages.

2. Low Power Consumption.

3. Flexible Power/Serial Clock Speed Management.

The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption to
be reduced when power-down mode is used while not convert­ing. The part also features a power-down mode to maximize
power efficiency at lower throughput rates. Current consumption
is 1 A max and 50 nA typically when in power-down mode.

4. Reference Derived from the Power Supply.

5. No Pipeline Delay.

The parts feature a standard successive-approximation ADC
with accurate control of the sampling instant via a CS input
and once-off conversion control.

*Protected by U.S.Patent No. 6,681,332.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD7910–SPECIFICATIONS

(V

= 2.35 V to 5.25 V, f

1

DD

otherwise noted.)

= 5 MHz, f

SCLK

= 250 kSPS, TA = T

SAMPLE

MIN

to T

MAX

, unless

Parameter A Grade

DYNAMIC PERFORMANCE f

Signal-to-Noise + Distortion (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)

3

3

3

61 dB min
–72 dB max

3

–73 dB max

1, 2

Unit Test Conditions/Comments

= 100 kHz Sine Wave

IN

Second-Order Terms –82 dB typ fa = 100.73 kHz, fb = 90.7 kHz

Third-Order Terms –82 dB typ fa = 100.73 kHz, fb = 90.7 kHz
Aperture Delay 10 ns typ
Aperture Jitter 30 ps typ
Full Power Bandwidth 13.5 MHz typ @ 3 dB

2 MHz typ @ 0.1 dB

DC ACCURACY

Resolution 10 Bits
Integral Nonlinearity ± 0.5 LSB max
Differential Nonlinearity ± 0.5 LSB max Guaranteed No Missed Codes to 10 Bits
Offset Error
Gain Error
Total Unadjusted Error (TUE)

3, 4

3, 4

3, 4

± 1LSB max
± 1LSB max
± 1.2 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

DD

V
DC Leakage Current ± 0.5 mA max
Input Capacitance 20 pF typ

Track-and-Hold in Track, 6 pF Typ when in Hold

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V

Input Current, I
Input Current, IIN, CS Pin ± 10 nA typ
Input Capacitance, C

INH

INL

, SCLK Pin ± 0.5 mA max Typically 10 nA, V

IN

5

IN

2.4 V min

0.8 V max V

0.4 V max V

5 pF max

DD

DD

= 5 V
= 3 V

= 0 V or V

IN

DD

LOGIC OUTPUTS

V

Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ± 1 mA max
Floating-State Output Capacitance

OH

OL

5

– 0.2 V min I

DD

0.4 V max I

5 pF max

SOURCE

= 200 mA

SINK

= 200 mA, V

= 2.35 V to 5.25 V

DD

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 2.8 ms max 14 SCLK Cycles with SCLK at 5 MHz
Track-and-Hold Acquisition Time

3

250 ns max

Throughput Rate 250 kSPS max

POWER REQUIREMENTS

V

DD

I

DD

Normal Mode(Static) 2.5 mA typ V

Normal Mode (Operational) 3 mA max V

Full Power-Down Mode 1 mA max Typically 50 nA

Power Dissipation

6

Normal Mode (Operational) 15 mW max V

Full Power-Down 5 mW max V

NOTES

1

Temperature range from –40∞C to +85∞C.

2

Operational from V

3

See Terminology section.

4

SC70 values guaranteed by characterization.

5

Guaranteed by characterization.

6

See Power Vs. Throughput Rate section.

Specifications subject to change without notice.

= 2.0 V, with input high voltage (V

DD

2.35/5.25 V min/max

1.2 mA typ V

1.4 mA max V

4.2 mW max V

3 mW max V

) 1.8 V min.

INH

Digital I/Ps = 0 V or V

= 4.75 V to 5.25 V, SCLK On or Off

DD

= 2.35 V to 3.6 V, SCLK On or Off

DD

= 4.75 V to 5.25 V, f

DD

= 2.35 V to 3.6 V, f

DD

= 5 V, f

DD

= 3 V, f

DD

= 5 V

DD

= 3 V

DD

SAMPLE

SAMPLE

DD

SAMPLE

SAMPLE

= 250 kSPS
= 250 kSPS

= 250 kSPS

= 250 kSPS

–2–

REV. B

AD7920–SPECIFICATIONS

(V

= 2.35 V to 5.25 V, f

1

DD

otherwise noted.)

= 5 MHz, f

SCLK

= 250 kSPS, TA = T

SAMPLE

AD7910/AD7920

to T

MAX

, unless

MIN

Parameter A Grade

DYNAMIC PERFORMANCE f

Signal-to-Noise + Distortion (SINAD)

3

70 70 dB min VDD = 2.35 V to 3.6 V, TA = 25∞C

1, 2

B Grade

69 69 dB min V

71.5 71.5 dB typ V
69 69 dB min V

Signal-to-Noise Ratio (SNR)

3

68 68 dB min V
71 71 dB min VDD = 2.35 V to 3.6 V, TA = 25∞C
70 70 dB min V
70 70 dB min V

Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)

3

3

69 69 dB min V
–80 –80 dB typ

3

–82 –82 dB typ

1, 2

Unit Test Conditions/Comments

= 100 kHz Sine Wave

IN

= 2.4 V to 3.6 V

DD

= 2.35 V to 3.6 V

DD

= 4.75 V to 5.25 V, TA = 25∞C

DD

= 4.75 V to 5.25 V

DD

= 2.4 V to 3.6 V

DD

= 4.75 V to 5.25 V, TA = 25∞C

DD

= 4.75 V to 5.25 V

DD

Second-Order Terms –84 –84 dB typ fa = 100.73 kHz, fb = 90.72 kHz

Third-Order Terms –84 –84 dB typ fa = 100.73 kHz, fb = 90.72 kHz
Aperture Delay 10 10 ns typ
Aperture Jitter 30 30 ps typ
Full Power Bandwidth 13.5 13.5 MHz typ @ 3 dB

22MHz typ @ 0.1 dB

DC ACCURACY B Grade

Resolution 12 12 Bits
Integral Nonlinearity

3

± 1.5 LSB max

4

± 0.75 LSB typ

Differential Nonlinearity –0.9/+1.5 LSB max Guaranteed No Missed Codes to 12 Bits

Offset Error

Gain Error

Total Unadjusted Error (TUE)

3, 5

3, 5

3,5

± 0.75 LSB typ

± 1.5 LSB max

± 1.5 ±0.2 LSB typ

± 1.5 LSB max

± 1.5 ±0.5 LSB typ

± 2 LSB max

ANALOG INPUT

Input Voltage Ranges 0 to V

DD

0 to V

DD

V
DC Leakage Current ± 0.5 ±0.5 mA max
Input Capacitance 20 20 pF typ

Track-and-Hold in Track, 6 pF Typ when in Hold

LOGIC INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I
Input Current, IIN, CS Pin ± 10 ± 10 nA typ
Input Capacitance, C

INH

INL

, SCLK Pin ± 0.5 ± 0.5 mA max Typically 10 nA, V

IN

6

IN

2.4 2.4 V min

1.8 1.8 V min V

0.8 0.8 V max V

0.4 0.4 V max V

5 5pF max

= 2.35 V

DD

= 3.6 V to 5.25 V

DD

= 2.35 V to 3.6 V

DD

= 0 V or V

IN

DD

LOGIC OUTPUTS

V

Output High Voltage, V
Output Low Voltage, V
Floating-State Leakage Current ± 1 ± 1 mA max
Floating-State Output Capacitance

OH

OL

6

– 0.2 V

DD

0.4 0.4 V max I

55pF max

– 0.2 V min I

DD

SOURCE

= 200 mA

SINK

= 200 mA, V

= 2.35 V to 5.25 V

DD

Output Coding Straight (Natural) Binary

CONVERSION RATE

Conversion Time 3.2 3.2 ms max 16 SCLK Cycles with SCLK at 5 MHz
Track-and-Hold Acquisition Time

3

250 250 ns max

Throughput Rate 250 250 kSPS max See Serial Interface Section

REV. B

–3–

AD7910/AD7920

AD7920–SPECIFICATIONS

Parameter A Grade

1

(continued)

1, 2

B Grade

1, 2

Unit Test Conditions/Comments

POWER REQUIREMENTS

V

DD

I

DD

Normal Mode (Static) 2.5 2.5 mA typ V

Normal Mode (Operational) 3 3 mA max V

Full Power-Down Mode 1 1 mA max Typically 50 nA

Power Dissipation

7

Normal Mode (Operational) 15 15 mW max V

Full Power-Down 5 5 mW max V

NOTES

1

Temperature range from –40∞C to +85∞C.

2

Operational from V

3

See Terminology section.

4

B Grade, maximum specs apply as typical figures when VDD = 4.75 V to 5.25 V.

5

SC70 values guaranteed by characterization.

6

Guaranteed by characterization.

7

See Power vs. Throughput Rate section.

Specifications subject to change without notice.

= 2.0 V, with input low voltage (V

DD

TIMING SPECIFICATIONS

2.35/5.25 2.35/5.25 V min/max

1.2 1.2 mA typ V

1.4 1.4 mA max V

4.2 4.2 mW max V

33mW max V

) 0.35 V max.

INL

1

(V

= 2.35 V to 5.25 V, TA = T

DD

MIN

to T

Digital I/Ps = 0 V or V

= 4.75 V to 5.25 V, SCLK On or Off

DD

= 2.35 V to 3.6 V, SCLK On or Off

DD

= 4.75 V to 5.25 V, f

DD

= 2.35 V to 3.6 V, f

DD

= 5 V, f

DD

= 3 V, f

DD

= 5 V

DD

= 3 V

DD

, unless otherwise noted.)

MAX

SAMPLE

SAMPLE

DD

SAMPLE

SAMPLE

= 250 kSPS
= 250 kSPS

= 250 kSPS

= 250 kSPS

AD7910/AD7920

Parameter Limit at T

f

SCLK

2

10 kHz min

MIN, TMAX

Unit Description

3

5 MHz max

t

CONVERT

t

QUIET

14  t
16  t

SCLK

SCLK

AD7910
AD7920

50 ns minMinimum Quiet Time Required between Bus Relinquish and

Start of Next Conversion

t

1

t

2

4

t

3

4

t

4

t

5

t

6

5

t

7

6

t

8

t

POWER-UP

NOTES

1

Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2

Mark/Space ratio for the SCLK input is 40/60 to 60/40.

3

Minimum f

4

Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 1.8 V when V

5

Measured with a 50 pF load capacitor.

6

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the Timing Characteristics is the true bus relinquish
time of the part and is independent of the bus loading.

7

t7 values apply to t8 minimum values also.

8

See Power-Up Time section.

Specifications subject to change without notice.

8

at which specifications are guaranteed.

SCLK

10 ns min Minimum CS Pulse Width
10 ns min CS to SCLK Setup Time
22 ns max Delay from CS until SDATA Three-State Disabled
40 ns max Data Access Time after SCLK Falling Edge

0.4  t

0.4  t

SCLK

SCLK

ns min SCLK Low Pulse Width
ns min SCLK High Pulse Width

SCLK to Data Valid Hold Time

10 ns min V

9.5 ns min 3.3 V < V
7 ns min V

£ 3.3 V

DD

> 3.6 V

DD

£ 3.6 V

DD

36 ns max SCLK Falling Edge to SDATA Three-State
See Note 7 ns min SCLK Falling Edge to SDATA Three-State
1 ms max Power-Up Time from Full Power-Down

= 2.35 V and 0.8 V or 2.0 V for V

DD

> 2.35 V.

DD

–4–

REV. B

AD7910/AD7920

I

OL

1.6V

I

OH

TO OUTPUT

PIN

50pF

200␮A

C

L

200␮A

Figure 1. Load Circuit for Digital Output Timing
Specifications

CS

t

CONVERT

t

6

t

7

SCLK

SDATA

STATE

t

2

12 345 1314 15 16

t

3

ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0

Z

4 LEADING ZEROS

t

4

Figure 2. AD7920 Serial Interface Timing Diagram

TIMING EXAMPLES

Figures 2 and 3 show some of the timing parameters from the
Timing Specifications table.

Timing Example 1

From Figure 3, having f
250 kSPS gives a cycle time of t

= 10 ns min, this leaves t

With t

2

satisfies the requirement of 250 ns for t
comprises 2.5(1/f

SCLK

allows a value of 954 ns for t

= 5 MHz and a throughput rate of

SCLK

) + t8 + t

+ 12.5(1/f

2

to be 1.49 ms. This 1.49 ms

ACQ

ACQ

, where t8 = 36 ns max. This

QUIET

satisfying the minimum re-

QUIET,

) + t

SCLK

. From Figure 3, t

ACQ

= 4 ms.

ACQ

quirement of 50 ns.

t

1

B

t

5

t

8

t

QUIET

THREE-STATETHREE-

CS

t

SCLK

CONVERT

)

1/THROUGHPUT

SCLK

t

2

1 2345 13141516

12.5(1/f

Figure 3. Serial Interface Timing Example

Timing Example 2

The AD7920 can also operate with slower clock frequencies.
From Figure 3, having f
of 150 kSPS gives a cycle time of t

6.66 ms. With t

= 10 ns min, this leaves t

2

2.97 ms satisfies the requirement of 250 ns for t
Figure 3, t

comprises 2.5(1/f

ACQ

= 3.4 MHz and a throughput rate

SCLK

2

SCLK

+ 12.5(1/f

ACQ

) + t8 + t

) + t

SCLK

to be 2.97 ms. This

. From

ACQ

, t8 = 36 ns

QUIET

ACQ

=

B

max. This allows a value of 2.19 ms for t

C

t

8

t

ACQ

t

QUIET

, satisfying the

QUIET

minimum requirement of 50 ns. As in this example and with
other slower clock values, the signal may already be acquired
before the conversion is complete, but it is still necessary to leave
50 ns minimum t

between conversions. In this example, the

QUIET

signal should be fully acquired at approximately point C in
Figure 3.

REV. B

–5–

AD7910/AD7920

ABSOLUTE MAXIMUM RATINGS

(TA = 25∞C, unless otherwise noted.)

1

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Analog Input Voltage to GND . . . . . . . –0.3 V to V

+ 0.3 V

DD

Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V

Digital Output Voltage to GND . . . . . –0.3 V to V

Input Current to Any Pin Except Supplies

2

. . . . . . . . ± 10 mA

+ 0.3 V

DD

Operating Temperature Range

Commercial (A, B Grade) . . . . . . . . . . . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . –65∞C to +150∞C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C

MSOP Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 205.9∞C/W

q

JA

SC70 Package

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 340.2∞C/W

q

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 228.9∞C/W

q

JC

Lead Temperature, Soldering

Reflow (10 sec to 30 sec) . . . . . . . . . . . . . . . 235 (0/+5)∞C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.5 kV

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

qJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 43.74∞C/W

ORDERING GUIDE

Temperature Linearity Package

Model Range Error (LSB)

1

Option

2

Branding

AD7910AKS-500RL7 –40∞C to +85∞C ± 0.5 max KS-6 CVA
AD7910AKS-REEL –40∞C to +85∞C ± 0.5 max KS-6 CVA
AD7910AKS-REEL7 –40∞C to +85∞C ± 0.5 max KS-6 CVA
AD7910ARM –40∞C to +85∞C ± 0.5 max RM-8 CVA
AD7910ARM-REEL –40∞C to +85∞C ± 0.5 max RM-8 CVA
AD7910ARM-REEL7 –40∞C to +85∞C ± 0.5 max RM-8 CVA
AD7920AKS-500RL7 –40∞C to +85∞C ± 0.75 typ KS-6 CUA
AD7920AKS-REEL –40∞C to +85∞C ± 0.75 typ KS-6 CUA
AD7920AKS-REEL7 –40∞C to +85∞C ± 0.75 typ KS-6 CUA
AD7920BKS –40∞C to +85∞C ± 1.5 max KS-6 CUB
AD7920BKS-REEL –40∞C to +85∞C ± 1.5 max KS-6 CUB
AD7920BKS-REEL7 –40∞C to +85∞C ± 1.5 max KS-6 CUB
AD7920BRM –40∞C to +85∞C ± 1.5 max RM-8 CUB
AD7920BRM-REEL –40∞C to +85∞C ± 1.5 max RM-8 CUB
AD7920BRM-REEL7 –40∞C to +85∞C ± 1.5 max RM-8 CUB
EVAL-AD7910CB
EVAL-AD7920CB
EVAL-CONTROL BRD2

NOTES

1

Linearity error refers to integral nonlinearity.

2

KS = SC70, RM = MSOP.

3

This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.

4

This board is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order a
complete evaluation kit, a particular ADC evaluation board must be ordered, e.g., EVAL-AD7920CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer.
See relevant evaluation board technical note for more information.

3

3

4

Evaluation Board
Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7910/AD7920 feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–6–

REV. B

PIN CONFIGURATIONS

AD7910/AD7920

6-Lead SC70

1

V

DD

2

GND

3

V

IN

(Not to Scale)

AD7910/

AD7920

TOP VIEW

6

5

4

CS

SDATA

SCLK

8-Lead MSOP

1

V

DD

AD7910/

2

SDATA

3

CS

TOP VIEW

4

(Not to Scale)

NC = NO CONNECT

AD7920

8

7

6

5

V

IN

GND

SCLK

NCNC

PIN FUNCTION DESCRIPTIONS

Mnemonic Function

CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7910/

AD7920 and framing the serial data transfer.

V

DD

Power Supply Input. The VDD range for the AD7910/AD7920 is from 2.35 V to 5.25 V.

GND Analog Ground. Ground reference point for all circuitry on the AD7910/AD7920. All analog input signals should be

referred to this GND voltage.

V

IN

Analog Input. Single-ended analog input channel. The input range is 0 to VDD.

SDATA Data Out. Logic output. The conversion result from the AD7910/AD7920 is provided on this output as a serial data

stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7920 consists
of four leading zeros followed by the 12 bits of conversion data, which is provided MSB first. The data stream from
the AD7910 consists of four leading zeros followed by the 10 bits of conversion data followed by two trailing zeros,

which is also provided MSB first.

SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also

used as the clock source for the AD7910/AD7920 conversion process.

NC No Connect

REV. B

–7–

AD7910/AD7920

TERMINOLOGY
Integral Nonlinearity

The maximum deviation from a straight line passing through the
endpoints of the ADC transfer function. For the AD7920 and
AD7910, the endpoints of the transfer function are zero scale, a
point 1 LSB below the first code transition, and full scale, a point
1 LSB above the last code transition.

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB change
between any two adjacent codes in the ADC.

Offset Error

The deviation of the first code transition (00 . . . 000) to (00 . . . 001)
from the ideal, i.e., GND + 1 LSB.

Gain Error

The deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal, i.e., V

– 1 LSB after the offset

REF

error has been adjusted out.

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode at the end of
conversion. Track-and-hold acquisition time is the time required
for the output of the track-and-hold amplifier to reach its final
value, within ± 0.5 LSB, after the end of conversion. See the
Serial Interface section for more details.

Signal-to-(Noise + Distortion) Ratio

The measured ratio of signal-to-(noise + distortion) at the output
of the A/D converter. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (f

/2), excluding dc. The ratio is

S

dependent on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical signal-to-(noise + distortion) ratio for an ideal N-bit
converter with a sine wave input is given by:

Signal-to- Noise Distortion N ()(..)+=+602 176 dB

Thus, for a 12-bit converter this is 74 dB, and for a 10-bit converter
this is 62 dB.

Total Unadjusted Error

A comprehensive specification that includes gain error, linearity
error, and offset error.

Total Harmonic Distortion (THD)

Total harmonic distortion is the ratio of the rms sum of har­monics to the fundamental. It is defined as:

THD

() logdB =

20

2

VVVVV

+ +++

2

324

V

25262

1

where V1 is the rms amplitude of the fundamental and V2, V3, V4,
V5, and V6 are the rms amplitudes of the second through the

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output spec­trum (up to f

/2 and excluding dc) to the rms value of the funda-

S

mental. Normally, the value of this specification is determined by
the largest harmonic in the spectrum, but for ADCs whose har­monics are buried in the noise floor, it will be a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).

The AD7910/AD7920 are tested using the CCIF standard, where
two input frequencies are used (see fa and fb in the specification
page). In this case, the second-order terms are usually distanced in
frequency from the original sine waves while the third-order terms
are usually at a frequency close to the input frequencies. As a
result, the second- and third-order terms are specified separately.
The calculation of the intermodulation distortion is as per the
THD specification, the ratio of the rms sum of the individual
distortion products to the rms amplitude of the sum of the funda­mentals, expressed in dB.

–8–

REV. B

Typical Performance Characteristics–AD7910/AD7920

TPC 1 and TPC 2 show a typical FFT plot for the AD7920 and
AD7910, respectively, at a 250 kSPS sampling rate and a 100 kHz
input frequency.

TPC 3 shows the signal-to-(noise + distortion) ratio performance
versus input frequency for various supply voltages while sampling
at 250 kSPS with a SCLK frequency of 5 MHz for the AD7920.

TPC 4 and TPC 5 show typical INL and DNL performance for the
AD7920.

–5

8192 POINT FFT

= 2.7V

V

DD

–15

f

= 250kSPS

SAMPLE

f

= 100kHz

IN

SINAD = 72.05dB
THD = –82.87dB

–35

SFDR = –87.24dB

–55

SNR (dB)

–75

–95

–115

0 12525

50 75 100

FREQUENCY (kHz)

TPC 1. AD7920 Dynamic Performance at 250 kSPS

TPC 6 shows a graph of the total harmonic distortion versus analog
input frequency for different source impedances when using a
supply voltage of 3.6 V and sampling at a rate of 250 kSPS. See the
Analog Input section.

TPC 7 shows a graph of the total harmonic distortion versus analog
input signal frequency for various supply voltages while sampling
at 250 kSPS with an SCLK frequency of 5 MHz.

–71.0

VDD = 5.25V

–71.5

–72.0

VDD = 4.75V

–72.5

SINAD (dB)

–73.0

–73.5

10 1000

VDD = 3.6V

VDD = 2.35V

VDD = 2.7V

100

FREQUENCY (kHz)

TPC 3. AD7920 SINAD vs. Input Frequency at 250 kSPS

8192 POINT FFT

= 2.35V

V

DD

–5

f

= 250kSPS

SAMPLE

f

= 100kHz

IN

SINAD = 61.67dB

–25

THD = –79.59dB
SFDR = –82.93dB

–45

SNR (dB)

–65

–85

–105

0 12525 50 75 100

FREQUENCY (kHz)

TPC 2. AD7910 Dynamic Performance at 250 kSPS

1.0

VDD = 2.35V

0.8
TEMP = 25ⴗC

f

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 1024

= 250kSPS

SAMPLE

512

1536 2048 2560 3072 3584 4096

CODE

TPC 4. AD7920 INL Performance

REV. B

–9–

AD7910/AD7920

1.0

VDD = 2.35V

0.8
TEMP = 25ⴗC

f

= 250kSPS

SAMPLE

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 1024

512

1536 2048 2560 3072 3584 4096

CODE

TPC 5. AD7920 DNL Performance

–10

VDD = 3.6V

–20

–30

–40

RIN = 10k⍀

–50

THD (dB)

–60

RIN = 1k⍀

–70

–80

–90

10 1000

RIN = 130⍀

INPUT FREQUENCY (kHz)

RIN = 13⍀

RIN = 0⍀

100

–65

–70

–75

VDD = 2.35V

THD (dB)

–80

VDD = 4.75V

–85

VDD = 5.25V

–90

10 1000

VDD = 2.7V

INPUT FREQUENCY (kHz)

VDD = 3.6V

100

TPC 7. THD vs. Analog Input Frequency for
Various Supply Voltages

TPC 6. THD vs. Analog Input Frequency for
Various Source Impedances

CIRCUIT INFORMATION

The AD7910/AD7920 are fast, micropower, 10-bit/12-bit,
single-supply A/D converters, respectively. The parts can be
operated from a 2.35 V to 5.25 V supply. When operated from
either a 5 V supply or a 3 V supply, the AD7910/AD7920 are
capable of throughput rates of 250 kSPS when provided with a
5 MHz clock.

The AD7910/AD7920 provide the user with an on-chip track­and-hold, A/D converter, and a serial interface housed in a tiny
6-lead SC70 package or 8-lead MSOP package, which offers the
user considerable space saving advantages over alternative solu­tions. The serial clock input accesses data from the part but also
provides the clock source for the successive-approximation A/D
converter. The analog input range is 0 V to V

. An external

DD

reference is not required for the ADC and there is no reference
on-chip. The reference for the AD7910/AD7920 is derived from
the power supply and thus gives the widest dynamic input range.

The AD7910/AD7920 also feature a power-down option to
allow power saving between conversions. The power-down feature
is implemented across the standard serial interface, as described
in the Modes of Operation section.

CONVERTER OPERATION

The AD7910/AD7920 is a successive-approximation analog­to-digital converter based around a charge redistribution DAC.
Figures 4 and 5 show simplified schematics of the ADC.
Figure 4 shows the ADC during its acquisition phase. When
SW2 is closed and SW1 is in position A, the comparator is
held in a balanced condition, and the sampling capacitor

PHASE

VDD/2

IN

.

CHARGE

REDISTRIBUTION

DAC

CONTROL

SW2

COMPARATOR

LOGIC

acquires the signal on V

SAMPLING

CAPACITOR

A

V

IN

SW1

ACQUISITION

B

AGND

Figure 4. ADC Acquisition Phase

–10–

REV. B

AD7910/AD7920

AD7910/
AD7920/

SCLK

SDATA

CS

V

IN

GND

0V TO V

DD

INPUT

V

DD

␮C/␮P

SERIAL

INTERFACE

0.1␮F

1␮F

TANT

REF193

1.2mA

680nF

10␮F 0.1␮F

3V

5V
SUPPLY

When the ADC starts a conversion (see Figure 5), SW2 opens
and SW1 moves to position B, causing the comparator to become
unbalanced. The control logic and charge redistribution DAC are
used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
Figure 6 shows the ADC transfer function.

CHARGE

REDISTRIBUTION

DAC

SAMPLING

CAPACITOR

A

V

IN

SW1

B

AGND

CONVERSION

PHASE

VDD/2

SW2

COMPARATOR

CONTROL

LOGIC

Figure 5. ADC Conversion Phase

ADC Transfer Function

The output coding of the AD7910/AD7920 is straight binary.
The designed code transitions occur at the successive integer
LSB values, i.e., 1 LSB, 2 LSBs, and so on. The LSB size is

/4096 for the AD7920 and VDD/1024 for the AD7910. The

V

DD

ideal transfer characteristic for the AD7910/AD7920 is shown
in Figure 6.

Alternatively, because the supply current required by the AD7910/
AD7920 is so low, a precision reference can be used as the
supply source to the AD7910/AD7920. An REF19x voltage
reference (REF195 for 5 V or REF193 for 3 V) can be used to
supply the required voltage to the ADC (see Figure 7). This con­figuration is especially useful if the power supply is quite noisy
or if the system supply voltages are at a value other than 5 V or
3V (e.g., 15 V). The REF19x will output a steady voltage to the
AD7910/AD7920. If the low dropout REF193 is used, the current
it needs to supply to the AD7910/AD7920 is typically 1.2 mA.
When the ADC is converting at a rate of 250 kSPS the REF193
needs to supply a maximum of 1.4 mA to the AD7910/AD7920.
The load regulation of the REF193 is typically 10 ppm/mA
(REF193, V

= 5 V), which results in an error of 14 ppm (42 mV)

S

for the 1.4 mA drawn from it. This corresponds to a 0.057 LSB
error for the AD7920 with V

= 3 V from the REF193 and a

DD

0.014 LSB error for the AD7910. For applications where power
consumption is of concern, the power-down mode of the ADC
and the sleep mode of the REF19x reference should be used to
improve power performance. See the Modes of Operation section.

111...111

111...110

111...000

011...111

ADC CODE

000...010

000...001

000...000

1LSB = V
1LSB = V

1LSB

0V

ANALOG INPUT

/1024 (AD7910)

DD

/4096 (AD7920)

DD

+V

–1LSB

DD

Figure 6. Transfer Characteristic

Typical Connection Diagram

Figure 7 shows a typical connection diagram for the AD7910/
AD7920. V

is taken internally from VDD and, as such, V

REF

DD

should be well decoupled. This provides an analog input range of
0 V to V

. The conversion result is output in a 16-bit word with

DD

four leading zeros followed by the MSB of the 12-bit or 10-bit
result. The 10-bit result from the AD7910 will be followed by two
trailing zeros.

REV. B

Figure 7. REF193 as Power Supply

Table I provides typical performance data with various references
used as a V

source for a 100 kHz input tone at room temper-

DD

ature under the same setup conditions.

Table I. AD7920 Typical Performance
for Various Voltage References IC

Reference AD7920 SNR
Tied to V

DD

Performance (dB)

AD780 @ 3 V 72.65
REF193 72.35
AD780 @ 2.5 V 72.5
REF192 72.2
REF43 72.6

–11–

AD7910/AD7920

Analog Input

Figure 8 shows an equivalent circuit of the analog input structure
of the AD7910/AD7920. The two diodes D1 and D2 provide
ESD protection for the analog input. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 300 mV. This will cause these diodes to become
forward biased and start conducting current into the substrate.
10 mA is the maximum current these diodes can conduct without
causing irreversible damage to the part. The capacitor C1 in
Figure 8 is typically about 6 pF and can be attributed primarily to
pin capacitance. The resistor R1 is a lumped component made
up of the on resistance of a switch. This resistor is typically about
100 W. The capacitor C2 is the ADC sampling capacitor and has
a capacitance of 20 pF typically. For ac applications, removing
high frequency components from the analog input signal is
recommended by use of a band-pass filter on the relevant analog
input pin. In applications where harmonic distortion and signal­to-noise ratio are critical, the analog input should be driven from
a low impedance source. Large source impedances will signifi­cantly affect the ac performance of the ADC. This may necessitate
the use of an input buffer amplifier. The choice of the op amp is
a function of the particular application.

V

DD

D1

V

IN

6pF

C1

D2

CONVERSION PHASE – SWITCH OPEN
TRACK PHASE – SWITCH CLOSED

C2

20pF

R1

Figure 8. Equivalent Analog Input Circuit

Table II provides some typical performance data with various
op amps used as the input buffer for a 100 kHz input tone at room
temperature under the same setup conditions.

Table II. AD7920 Typical Performance
for Various Input Buffers, V

DD

= 3 V

Op Amp in the AD7920 SNR
Input Buffer Performance (dB)

AD711 72.3
AD797 72.5
AD845 71.4

When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of total harmonic distortion
(THD) that can be tolerated. The THD increases as the source
impedance increases, and performance degrades (see TPC 6).

Digital Inputs

The digital inputs applied to the AD7910/AD7920 are not
limited by the maximum ratings that limit the analog input. Instead,
the digital inputs applied can go to 7 V and are not restricted
by the V
the AD7910/AD7920 were operated with a V

+ 0.3 V limit as on the analog input. For example, if

DD

of 3V, then 5 V

DD

logic levels could be used on the digital inputs. However, it is
important to note that the data output on SDATA will still have 3 V
logic levels when V
CS not being restricted by the V

= 3 V. Another advantage of SCLK and

DD

+ 0.3 V limit is that power

DD

supply sequencing issues are avoided. If CS or SCLK is applied
before V
analog inputs if a signal greater than 0.3 V was applied prior to V

, there is no risk of latch-up as there would be on the

DD

DD

.

MODES OF OPERATION

The mode of operation of the AD7910/AD7920 is selected by
controlling the logic state of the CS signal during a conversion.
There are two possible modes of operation, normal mode and
power-down mode. The point at which CS is pulled high
after the conversion has been initiated determines whether the
AD7910/AD7920 enters power-down mode. Similarly, if the
device is already in power-down mode, CS can control whether
it returns to normal operation or remains in power-down mode.
These modes of operation are designed to provide flexible power
management options. These options can be chosen to optimize
the power dissipation/throughput rate ratio for different applica­tion requirements.

Normal Mode

This mode is intended for fastest throughput rate performance
because the user does not have to worry about any power-up
times; the AD7910/AD7920 remains fully powered all the time.
Figure 9 shows the general diagram of the operation of the
AD7910/AD7920 in this mode.

The conversion is initiated on the falling edge of CS as described
in the Serial Interface section. To ensure that the part remains
fully powered up at all times, CS must remain low until at least
10 SCLK falling edges have elapsed after the falling edge of CS.
If CS is brought high any time after the 10th SCLK falling edge
but before the end of the t

CONVERT

, the part will remain pow­ered up but the conversion will be terminated and SDATA will
go back into three-state.

For the AD7920, 16 serial clock cycles are required to complete
the conversion and access the complete conversion result. For the
AD7910, a minimum of 14 serial clock cycles is required to com­plete the conversion and access the complete conversion result.

CS may idle high until the next conversion or may idle low until CS
returns high sometime prior to the next conversion, effectively
idling CS low.

Once a data transfer is complete (SDATA has returned to three­state), another conversion can be initiated after the quiet time,
t

, has elapsed by bringing CS low again.

QUIET

–12–

REV. B

AD7910/AD7920

Power-Down Mode

This mode is intended for use in applications where slower through­put rates are required; either the ADC is powered down between
conversions, or a series of conversions may be performed at a
high throughput rate and the ADC is powered down for a rela­tively long duration between these bursts of several conversions.
When the AD7910/AD7920 is in power-down mode, all analog
circuitry is powered down.

To enter power-down mode, the conversion process must be
interrupted by bringing CS high anywhere after the second
falling edge of SCLK, and before the 10th falling edge of SCLK
as shown in Figure 10. Once CS has been brought high in this
window of SCLKs, the part will enter power-down mode, the
conversion that was initiated by the falling edge of CS will be
terminated, and SDATA will go back into three-state. If CS is
brought high before the second SCLK falling edge, the part will
remain in Normal mode and will not power down. This will
avoid accidental power-down due to glitches on the CS line.

To exit this mode of operation and power up the AD7910/AD7920
again, a dummy conversion is performed. On the falling edge of CS,
the device will begin to power up, and will continue to power up

CS

110121416

SCLK

as long as CS is held low until after the falling edge of the 10th
SCLK. The device will be fully powered up once 16 SCLKs
have elapsed and valid data will result from the next conversion,
as shown in Figure 11. If CS is brought high before the 10th SCLK
falling edge, the AD7910/AD7920 will go back into power-down
mode again. This avoids accidental power-up due to glitches on
the CS line or an inadvertent burst of eight SCLK cycles while
CS is low. Although the device may begin to power up on the
falling edge of CS, it will power down again on the rising edge
of CS as long as it occurs before the 10th SCLK falling edge.

Power-Up Time

The power-up time of the AD7910/AD7920 is 1 ms, which means
that one dummy cycle will always be sufficient to allow the device
to power up. Once the dummy cycle is complete, the ADC will
be fully powered up and the input signal will be acquired properly.
The quiet time, t

, must still be allowed from the point where

QUIET

the bus goes back into three-state after the dummy conversion,
to the next falling edge of CS.

When powering up from the power-down mode with a dummy
cycle, as in Figure 11, the track-and-hold that was in hold mode
while the part was powered down returns to track mode after

AD7910/AD7920

CS

SCLK

SDATA

SDATA

VA LID DATA

Figure 9. Normal Mode Operation

CS

2

110121416

SCLK

SDATA

THREE-STATE

Figure 10. Entering Power-Down Mode

THE PART
BEGINS TO
POWER UP

A

110121416

INVALID DATA

THE PART IS FULLY
POWERED UP WITH

FULLY ACQUIRED

V

IN

116

VA LID DATA

REV. B

Figure 11. Exiting Power-Down Mode

–13–

AD7910/AD7920

the first SCLK edge the part receives after the falling edge of
CS. This is shown as point A in Figure 11. Although at any
SCLK frequency one dummy cycle is sufficient to power up the
device and acquire V

, it does not necessarily mean that a full

IN

dummy cycle of 16 SCLKs must always elapse to power up the
device and fully acquire V

; 1 s will be sufficient to power the

IN

device up and acquire the input signal. So, if a 5 MHz SCLK
frequency is applied to the ADC, the cycle time will be 3.2 s.
In one dummy cycle, 3.2 s, the part will be powered up and

fully acquired. However, after 1 ms with a 5 MHz SCLK,

V

IN

only five SCLK cycles will have elapsed. At this stage, the ADC
will be fully powered up and the signal acquired. In this case, the
CS can be brought high after the 10th SCLK falling edge and
brought low again after a time, t

, to initiate the conversion.

QUIET

When power supplies are first applied to the AD7910/AD7920,
the ADC may power up in either power down mode or in normal
mode. Because of this, it is best to allow a dummy cycle to elapse
to ensure the part is fully powered up before attempting a valid
conversion. Likewise, if the intention is to keep the part in
power-down mode while not in use and the user wishes the part
to power up in power-down mode, the dummy cycle may be
used to ensure the device is in power-down by executing a cycle
such as that shown in Figure 10. Once supplies are applied to
the AD7910/AD7920, the power-up time is the same as that
when powering up from power-down mode. It takes approximately
1 s to power up fully if the part powers up in normal mode. It
is not necessary to wait 1 ms before executing a dummy cycle to
ensure the desired mode of operation. Instead, the dummy
cycle can occur directly after power is supplied to the ADC. If the
first valid conversion is performed directly after the dummy
conversion, care must be taken to ensure that adequate acquisi­tion time is allowed. As mentioned earlier, when powering up
from the power-down mode, the part will return to track upon
the first SCLK edge applied after the falling edge of CS. How­ever when the ADC powers up initially after supplies are
applied, the track-and-hold will already be in track. This means,
assuming one has the facility to monitor the ADC supply cur­rent, if the ADC powers up in the desired mode of operation and
thus a dummy cycle is not required to change mode, neither is a
dummy cycle required to place the track-and-hold into track.

POWER VS. THROUGHPUT RATE

By using the power-down mode on the AD7910/AD7920 when
not converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 12 shows how, as
the throughput rate is reduced, the device remains in its power­down state longer and the average power consumption over
time drops accordingly.

For example, if the AD7910/AD7920 is operated in a continuous
sampling mode with a throughput rate of 100 kSPS and an SCLK
of 5 MHz (V

= 5 V), and the device is placed in the power-

DD

down mode between conversions, the power consumption is
calculated as follows:

The power dissipation during normal mode is 15 mW (V

DD

= 5 V).
The power dissipation includes the power dissipated while the part
is entering power-down mode, the power dissipated during the
dummy conversion (when the part is exiting power-down mode
and powering up), and the power dissipated during conversion.

As mentioned in the power-down mode section, to enter power­down mode, CS has to be brought high anywhere between the
second and 10th SCLK falling edge. Therefore, the power con­sumption when entering power-down mode will vary depending
on the number of SCLK cycles used. In this example, five SCLK
cycles will be used to enter power-down mode. This gives a time
period of 5  (1/f

SCLK

) = 1 s.

The power-up time is 1 s, which implies that only five SCLK
cycles are required to power up the part. However, CS has to
remain low until at least the 10th SCLK falling edge when
exiting power-down mode. This means that a minimum of nine
SCLK cycles have to be used to exit power-down mode and
power up the part.

So, if nine SCLK cycles are used, the time to power up the part
and exit power-down mode is 9  (1/f

Finally, the conversion time is 16  (1/f

) = 1.8 s.

SCLK

SCLK

) = 3.2 s.

Therefore, the AD7910/AD7920 can be said to dissipate 15 mW
for 3.2 s + 1.8 s + 1 s = 6 s during each conversion cycle. If
the throughput rate is 100 kSPS, the cycle time is 10 s and the
average power dissipated during each cycle is (6/10)  (15 mW) =
9 mW. The power dissipation when the part is in power-down has
not been taken into account as the shutdown current is so low and
it does not have any effect on the overall power dissipation value.

If V

= 3 V, SCLK = 5 MHz and the device is again in power-

DD

down mode between conversions, the power dissipation during
normal operation is 4.2 mW. Assuming the same timing condi­tions as before, the AD7910/AD7920 can now be said to
dissipate 4.2 mW for 6 ms during each conversion cycle.

With a
throughput rate of 100 kSPS, the average power dissipated during
each cycle is (6/10)  (4.2 mW) = 2.52 mW. Figure 12 shows the
power versus throughput rate when using the power-down mode
between conversions with both 5 V and 3 V supplies.

Power-down mode is intended for use with throughput rates of
approximately 160 kSPS and under, because at higher sampling
rates there is no power saving made by using the power-down mode.

100

10

1

POWER (mW)

0.1

0.01
0

VDD = 5V, SCLK = 5MHz

VDD = 3V, SCLK = 5MHz

20

40 60 80 100 120 140 160 180

THROUGHPUT RATE (kSPS)

Figure 12. Power vs. Throughput Rate

–14–

REV. B

CS

SCLK

SDATA

STATE

CS

SCLK

SDATA
THREE-STATE

t

t

2

12 345 1314 15 16

t

3

Z

ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0

4 LEADING ZEROS

t

4

CONVERT

t

6

t

7

B

1/THROUGHPUT

t

5

Figure 13. AD7920 Serial Interface Timing Diagram

t

ZERO

CONVERT

t

6

t

4

DB9

5

t

7

DB8

B

13

DB0

1/THROUGHPUT

14

t

5

ZERO

2 TRAILING ZEROS

t

2

1

2

34

t

3

ZERO

Z

ZERO

4 LEADING ZEROS

15

t

8

ZERO

t

8

16

AD7910/AD7920

t

1

t

QUIET

THREE-STATETHREE-

t

1

t

QUIET

THREE-STATE

Figure 14. AD7910 Serial Interface Timing Diagram

SERIAL INTERFACE

Figures 13 and 14 show the detailed timing diagram for serial
interfacing to the AD7920 and AD7910, respectively. The serial
clock provides the conversion clock and also controls the transfer
of information from the AD7910/AD7920 during conversion.

The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at that point. The conversion is also initiated at this point.

For the AD7920, the conversion requires 16 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, track-and­hold goes back into track on the next SCLK rising edge as shown
in Figure 13 at point B. On the 16th SCLK falling edge, the
SDATA line goes back into three-state. If the rising edge of CS
occurs before 16 SCLKs have elapsed, then the conversion is
terminated and the SDATA line goes back into three-state;
otherwise, SDATA returns to three-state on the 16th SCLK
falling edge, as shown in Figure 13. Sixteen serial clock cycles
are required to perform the conversion process and to access data
from the AD7920.

For the AD7910, the conversion requires 14 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, track-and­hold goes back into track on the next SCLK rising edge, as shown
in Figure 14 at point B.

If the rising edge of CS occurs before 14 SCLKs have elapsed,
the conversion is terminated and the SDATA line goes back into
three-state. If 16 SCLKs are used in the cycle, SDATA returns to
three-state on the 16th SCLK falling edge, as shown in Figure 14.

CS going low clocks out the first leading zero to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges beginning with the sec­ond leading zero. Thus the first falling clock edge on the serial
clock has the first leading zero provided and also clocks out the
second leading zero. The final bit in the data transfer is valid on
the 16th falling edge, having being clocked out on the previous
(15th) falling edge.

In applications with a slower SCLK, it is possible to read in data on
each SCLK rising edge. In this case, the first falling edge of SCLK
will clock out the second leading zero, which could be read in the
first rising edge. However, the first leading zero that was clocked
out when CS went low will be missed unless it was not read in
the first falling edge. The 15th falling edge of SCLK will clock
out the last bit and it could be read in the 15th rising SCLK edge.

If CS goes low just after the SCLK falling edge has elapsed, CS
clocks out the first leading zero as before, and it may be read on the
SCLK rising edge. The next SCLK falling edge clocks out the second
leading zero and it could be read on the following rising edge.

REV. B

–15–

AD7910/AD7920

MICROPROCESSOR INTERFACING

The serial interface on the AD7910/AD7920 allows the part to
be directly connected to a range of different microprocessors.
This section explains how to interface the AD7910/AD7920
with some of the more common microcontroller and DSP serial
interface protocols.

AD7910/AD7920 to TMS320C541 Interface

The serial interface on the TMS320C541 uses a continuous serial
clock and frame synchronization signals to synchronize the data
transfer operations with peripheral devices like the AD7910/
AD7920. The CS input allows easy interfacing between the
TMS320C541 and the AD7910/AD7920 without any glue logic
required. The serial port of the TMS320C541 is set up to operate
in burst mode (FSM = 1 in the Serial Port Control register, SPC)
with internal serial clock CLKX (MCM = 1 in SPC register) and
internal frame signal (TXM = 1 in the SPC), so both pins are
configured as outputs. For the AD7920, the word length should
be set to 16 bits (FO = 0 in the SPC register). This DSP allows
frames with a word length of 16 or 8 bits. Therefore, in the case
of the AD7910 where just 14 bits could be required, the FO bit
would be set up to 16 bits also. This means that to obtain the
conversion result, 16 SCLKs are needed and two trailing zeros will
be clocked out in the two last clock cycles.

To summarize, the values in the SPC register are:

FO = 0
FSM = 1
MCM = 1
TXM = 1

The format bit, FO, may be set to 1 to set the word length to
eight bits, in order to implement the power-down mode on the
AD7910/AD7920.

The connection diagram is shown in Figure 15. It should be noted
that for signal processing applications, it is imperative that the
frame synchronization signal from the TMS320C541 provides
equidistant sampling.

AD7910/AD7920*

SCLK

SDATA

CS

TMS320C541*

CLKX

CLKR

DR

FSX

FSR

AD7910/AD7920 to ADSP-218x

The ADSP-218x family of DSPs is interfaced directly to the
AD7910/AD7920 without any glue logic required. The SPORT
control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0, Sets up RFS as an Input
ITFS = 1, Sets up TFS as an Output
SLEN = 1111, 16 Bits for the AD7920
SLEN = 1101, 14 Bits for the AD7910

To implement power-down mode, SLEN should be set to 0111
to issue an 8-bit SCLK burst. The connection diagram is shown
in Figure 16. The ADSP-218x has the TFS and RFS of the
SPORT tied together, with TFS set as an output and RFS set as
an input. The DSP operates in alternate framing mode and the
SPORT control register is set up as described. The frame syn­chronization signal generated on the TFS is tied to CS and, as
with all signal processing applications, equidistant sampling is
necessary. However, in this example, the timer interrupt is used
to control the sampling rate of the ADC and, under certain
conditions, equidistant sampling may not be achieved.

The timer registers are loaded with a value that provides an
interrupt at the required sample interval. When an interrupt is
received, a value is transmitted with TFS/DT (ADC control word).
The TFS is used to control the RFS and thus the reading of
data. The frequency of the serial clock is set in the SCLKDIV
register. When the instruction to transmit with TFS is given,
i.e., TX0 = AX0, the state of the SCLK is checked. The DSP
waits until the SCLK has gone high, low, and high before trans­mission starts. If the timer and SCLK values are chosen such
that the instruction to transmit occurs on or near the rising edge
of SCLK, the data may be transmitted or it may wait until the
next clock edge.

For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained and eight master clock periods will
elapse for every one SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs will occur between interrupts
and subsequently between transmit instructions. This situation
will result in nonequidistant sampling as the transmit instruction
is occurring on an SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling
will be implemented by the DSP.

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 15. Interfacing to the TMS320C541

–16–

AD7910/AD7920

SCLK

SDATA

*ADDITIONAL PINS OMITTED FOR CLARITY

*

CS

ADSP-218x*

SCLK

DR

RFS

TFS

Figure 16. Interfacing to the ADSP-218x

REV. B

AD7910/AD7920

AD7910/AD7920 to DSP563xx Interface

The diagram in Figure 17 shows how the AD7910/AD7920 can
be connected to the SSI (synchronous serial interface) of the
DSP563xx family of DSPs from Motorola. The SSI is operated
in Synchronous and Normal mode (SYN = 1 and MOD = 0 in
the Control Register B, CRB) with internally generated word
frame sync for both Tx and Rx (bits FSL1 = 0 and FSL0 = 0 in
the CRB). Set the word length in the Control Register A (CRA)
to 16 by setting bits WL2 = 0, WL1 = 1 and WL0 = 0 for the
AD7920. This DSP does not offer the option for a 14-bit word
length, so the AD7910 word length will be set to 16 bits like the
AD7920. For the AD7910, the conversion process will use 16
SCLK cycles, with the last two clock periods clocking out two
trailing zeros to fill the 16-bit word.

To implement the power-down mode on the AD7910/AD7920,
the word length can be changed to eight bits by setting bits
WL2 = 0, WL1 = 0, and WL0 = 0 in CRA. The FSP bit in the
CRB register can be set to 1, which means the frame goes low and
a conversion starts. Likewise, by means of bits SCD2, SCKD,
and SHFD in the CRB register, it will be established that pin
SC2 (the frame sync signal) and SCK in the serial port will be
configured as outputs and the MSB will be shifted first.

To summarize,

MOD = 0
SYN = 1
WL2, WL1, WL0 Depend on the Word Length
FSL1 = 0, FSL0 = 0
FSP = 1, Negative Frame Sync
SCD2 = 1
SCKD = 1
SHFD = 0

It should be noted that for signal processing applications, it is
imperative that the frame synchronization signal from the
DSP563xx provides equidistant sampling.

AD7910/AD7920*

SCLK

SDATA

CS

DSP563xx*

SCK

SRD

SC2

APPLICATION HINTS
Grounding and Layout

The printed circuit board that houses the AD7910/AD7920
should be designed such that the analog and digital sections are
separated and confined to certain areas of the board. This
facilitates the use of ground planes that can be easily separated.
A minimum etch technique is generally best for ground planes as
it gives the best shielding. Digital and analog ground planes
should be joined at only one place. If the AD7910/AD7920 is in a
system where multiple devices require an AGND to DGND
connection, the connection should still be made at one point only,
a star ground point that should be established as close to the
AD7910/AD7920 as possible.

Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7910/AD7920 to avoid noise coupling. The
power supply lines to the AD7910/AD7920 should use as large
a trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line. Fast switching
signals like clocks should be shielded with digital ground to avoid
radiating noise to other sections of the board, and clock signals
should never be run near the analog inputs. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This will reduce the
effects of feedthrough through the board. A microstrip technique
is by far the best but is not always possible with a double-sided
board. In this technique, the component side of the board is dedi­cated to ground planes while signals are placed on the solder side.

Good decoupling is also very important. The supply should be
decoupled with, for instance, a 680 nF 0805 to GND. When using
the SC70 package in applications where the size of the components
is of concern, a 220 nF 0603 capacitor, for example, could be used
instead. However, in that case, the decoupling may not be as
effective and may result in an approximate SINAD degradation of

0.3 dB. To achieve the best performance from these decoupling com­ponents, the user should endeavor to keep the distance between
the decoupling capacitor and the V

and GND pins to a minimum

DD

with short track lengths connecting the respective pins. Figures 18
and 19 show the recommended positions of the decoupling
capacitor for the MSOP and SC70 packages respectively.

REV. B

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 17. Interfacing to the DSP563xx

–17–

AD7910/AD7920

As can be seen in Figure 18, for the MSOP package the decou­pling capacitor has been placed as close as possible to the IC, with
short track lengths to V
tor could also be placed on the underside of the PCB
neath the IC, between the V
This method would not be recommended on PCBs above a standard

1.6 mm thickness. The best performance will be seen with the decou­pling capacitor on the top of the PCB next to the IC.

Figure 18. Recommended Supply Decoupling
Scheme for the AD7910/AD7920 MSOP Package

Similarly, for the SC70 package, the decoupling capacitor should
be located as close as possible to the V
of its pinout, i.e., V
tor can be placed extremely close to the IC. The decoupling
capacitor could be placed on the underside of the PCB directly
under the V

and GND pins, but, as before, the best perfor-

DD

mance will be seen with the decoupling capacitor on the same
side as the IC.

and GND pins. The decoupling capaci-

DD

and GND pins attached by vias.

DD

and GND pins. Because

being next to GND, the decoupling capaci-

DD

DD

directly

under-

Figure 19. Recommended Supply Decoupling
Scheme for the AD7910/AD7920 SC70 Package

Evaluating the AD7910/AD7920 Performance

The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for con­trolling the board from the PC via the Eval-Board Controller.
To demonstrate/evaluate the ac and dc performance of the
AD7910/AD7920, the evaluation board controller can be used
in conjunction with the AD7910/AD7920CB evaluation boards
as well as many other Analog Devices evaluation boards ending
in the CB designator.

The software allows the user to perform ac (fast Fourier transform)
and dc (histogram of codes) tests on the AD7910/AD7920. See
the evaluation board technical note for more information.

–18–

REV. B

OUTLINE DIMENSIONS

6-Lead Thin Shrink Small Outline Transistor Package [SC70]

(KS-6)

Dimensions shown in millimeters

2.00 BSC

4

5

1.25 BSC

1.00

0.90

0.70

0.10 MAX

6

1

2

PIN 1

1.30 BSC

0.30

0.15

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-203AB

3

0.65 BSC

2.10 BSC

1.10 MAX

SEATING
PLANE

0.22

0.08

0.46

8ⴗ
4ⴗ
0ⴗ

0.36

0.26

8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

AD7910/AD7920

3.00
BSC

85

3.00
BSC

1

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187AA

4

SEATING
PLANE

4.90
BSC

1.10 MAX

0.23

0.08

8ⴗ
0ⴗ

0.80

0.60

0.40

REV. B

–19–

AD7910/AD7920

Revision History

Location Page

3/04 – Data Sheet changed from REV. A to REV. B

Added U.S. Patent number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to Note 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to Note 6 of AD7920 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to Note 1 of TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

8/03 – Data Sheet changed from REV. 0 to REV. A

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Changes to Evaluating the AD7910/AD7920 Performance Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

C02976–0–3/04(B)

–20– REV. B